SWDEV-464648 - code and comment cleanups
Change-Id: I5ba3f1bff500b3cd5903c2f441017735e688f83f
[ROCm/clr commit: 8f42ad6aa3]
This commit is contained in:
@@ -246,12 +246,12 @@ void Settings::setKernelArgImpl(const amd::Isa& isa, bool isXgmi, bool hasValidH
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const uint32_t gfxipMinor = isa.versionMinor();
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const uint32_t gfxStepping = isa.versionStepping();
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const bool isMI300 = gfxipMajor == 9 && gfxipMinor == 4 &&
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const bool isGfx94x = gfxipMajor == 9 && gfxipMinor == 4 &&
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(gfxStepping == 0 || gfxStepping == 1 || gfxStepping == 2);
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const bool isMI200 = (gfxipMajor == 9 && gfxipMinor == 0 && gfxStepping == 10);
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const bool isPreMI100 =
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const bool isGfx90a = (gfxipMajor == 9 && gfxipMinor == 0 && gfxStepping == 10);
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const bool isPreGfx908 =
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(gfxipMajor < 9) || ((gfxipMajor == 9) && (gfxipMinor == 0) && (gfxStepping < 8));
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const bool isNavi10 =
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const bool isGfx101x =
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(gfxipMajor == 10) && ((gfxipMinor == 0) || (gfxipMinor == 1));
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auto kernelArgImpl = KernelArgImpl::HostKernelArgs;
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@@ -262,21 +262,18 @@ void Settings::setKernelArgImpl(const amd::Isa& isa, bool isXgmi, bool hasValidH
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kernelArgImpl = KernelArgImpl::DeviceKernelArgs;
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} else if (hasValidHDPFlush) {
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// If the HDP flush register is valid implement the HDP flush to MMIO
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// workaround. This does not work on gfx9 devices before MI100 or Navi10
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// devices
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if (!(isPreMI100 || isNavi10)) {
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// workaround.
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if (!(isPreGfx908 || isGfx101x)) {
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kernelArgImpl = KernelArgImpl::DeviceKernelArgsHDP;
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}
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} else if (isMI300 || isMI200) {
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} else if (isGfx94x || isGfx90a) {
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// Implement the kernel argument readback workaround
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// (write all args -> sfence -> write last byte -> mfence -> read last byte)
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// It works only on MI200 and MI300 because of the strict guarantee on
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// ordering of stores in those ASICS
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kernelArgImpl = KernelArgImpl::DeviceKernelArgsReadback;
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}
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// Enable device kernel args for MI300* for now
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if (isMI300) {
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// Enable device kernel args for gfx94x for now
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if (isGfx94x) {
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kernel_arg_impl_ = kernelArgImpl;
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kernel_arg_opt_ = true;
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}
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