diff --git a/projects/rocr-runtime/rocrtst/suites/test_common/CMakeLists.txt b/projects/rocr-runtime/rocrtst/suites/test_common/CMakeLists.txt index 486cc32c41..81ed2b4a6b 100755 --- a/projects/rocr-runtime/rocrtst/suites/test_common/CMakeLists.txt +++ b/projects/rocr-runtime/rocrtst/suites/test_common/CMakeLists.txt @@ -82,7 +82,10 @@ if ( PROC_RESULT EQUAL "0" AND NOT EVAL_RESULT STREQUAL "" ) endif() set (CPACK_RPM_PACKAGE_REQUIRES "rocm-core") -set(DEFAULT_TARGETS "gfx700;gfx701;gfx702;gfx801;gfx802;gfx803;gfx805;gfx810;gfx900;gfx902;gfx904;gfx906;gfx908;gfx909;gfx90a;gfx90c;gfx940;gfx941;gfx942;gfx1010;gfx1011;gfx1012;gfx1013;gfx1030;gfx1031;gfx1032;gfx1033;gfx1034;gfx1035;gfx1036;gfx1100;gfx1101;gfx1102;gfx1103") +set(DEFAULT_TARGETS "gfx700;gfx701;gfx702;gfx801;gfx802;gfx803;gfx805;gfx810" + "gfx900;gfx902;gfx904;gfx906;gfx908;gfx909;gfx90a;gfx90c;gfx940;gfx941;gfx942" + "gfx1010;gfx1011;gfx1012;gfx1013;gfx1030;gfx1031;gfx1032;gfx1033;gfx1034;gfx1035;gfx1036" + "gfx1100;gfx1101;gfx1102;gfx1103;gfx1150;gfx1151") # # Currently support for Windows platform is not present diff --git a/projects/rocr-runtime/runtime/hsa-runtime/core/runtime/isa.cpp b/projects/rocr-runtime/runtime/hsa-runtime/core/runtime/isa.cpp index 3674848a77..c87cbc71fb 100755 --- a/projects/rocr-runtime/runtime/hsa-runtime/core/runtime/isa.cpp +++ b/projects/rocr-runtime/runtime/hsa-runtime/core/runtime/isa.cpp @@ -347,6 +347,8 @@ constexpr size_t hsa_name_size = 63; ISAREG_ENTRY_GEN("gfx1101", 11, 0, 1, unsupported, unsupported, 32) ISAREG_ENTRY_GEN("gfx1102", 11, 0, 2, unsupported, unsupported, 32) ISAREG_ENTRY_GEN("gfx1103", 11, 0, 3, unsupported, unsupported, 32) + ISAREG_ENTRY_GEN("gfx1150", 11, 5, 0, unsupported, unsupported, 32) + ISAREG_ENTRY_GEN("gfx1151", 11, 5, 1, unsupported, unsupported, 32) #undef ISAREG_ENTRY_GEN return supported_isas; } diff --git a/projects/rocr-runtime/runtime/hsa-runtime/image/addrlib/src/amdgpu_asic_addr.h b/projects/rocr-runtime/runtime/hsa-runtime/image/addrlib/src/amdgpu_asic_addr.h index 28faf83e7e..c384c138cb 100644 --- a/projects/rocr-runtime/runtime/hsa-runtime/image/addrlib/src/amdgpu_asic_addr.h +++ b/projects/rocr-runtime/runtime/hsa-runtime/image/addrlib/src/amdgpu_asic_addr.h @@ -46,10 +46,12 @@ #define FAMILY_VGH 0x90 #define FAMILY_GFX1100 0x91 #define FAMILY_GFX1103 0x94 +#define FAMILY_GFX1150 0x96 #define FAMILY_RMB 0x92 #define FAMILY_GC_10_3_6 0x95 #define FAMILY_GC_10_3_7 0x97 + // AMDGPU_FAMILY_IS(familyId, familyName) #define FAMILY_IS(f, fn) (f == FAMILY_##fn) #define FAMILY_IS_TN(f) FAMILY_IS(f, TN) @@ -65,6 +67,7 @@ #define FAMILY_IS_RMB(f) FAMILY_IS(f, RMB) #define FAMILY_IS_GFX1100(f) FAMILY_IS(f, GFX1100) #define FAMILY_IS_GFX1103(f) FAMILY_IS(f, GFX1103) +#define FAMILY_IS_GFX1150(f) FAMILY_IS(f, GFX1150) #define AMDGPU_UNKNOWN 0xFF @@ -117,8 +120,8 @@ #define AMDGPU_GFX1100_RANGE 0x01, 0x10 #define AMDGPU_GFX1101_RANGE 0x20, 0xFF #define AMDGPU_GFX1102_RANGE 0x10, 0x20 - #define AMDGPU_GFX1103_RANGE 0x01, 0xFF +#define AMDGPU_GFX1150_RANGE 0x01, 0xFF #define AMDGPU_REMBRANDT_RANGE 0x01, 0xFF @@ -191,6 +194,7 @@ #define ASICREV_IS_GFX1101(r) ASICREV_IS(r, GFX1101) #define ASICREV_IS_GFX1102(r) ASICREV_IS(r, GFX1102) #define ASICREV_IS_GFX1103(r) ASICREV_IS(r, GFX1103) +#define ASICREV_IS_GFX1150(r) ASICREV_IS(r, GFX1150) #define ASICREV_IS_REMBRANDT(r) ASICREV_IS(r, REMBRANDT) diff --git a/projects/rocr-runtime/runtime/hsa-runtime/image/addrlib/src/core/addrlib.cpp b/projects/rocr-runtime/runtime/hsa-runtime/image/addrlib/src/core/addrlib.cpp index b8c16d4432..a958cd11ed 100644 --- a/projects/rocr-runtime/runtime/hsa-runtime/image/addrlib/src/core/addrlib.cpp +++ b/projects/rocr-runtime/runtime/hsa-runtime/image/addrlib/src/core/addrlib.cpp @@ -234,6 +234,7 @@ ADDR_E_RETURNCODE Lib::Create( break; case FAMILY_GFX1100: case FAMILY_GFX1103: + case FAMILY_GFX1150: pLib = Gfx11HwlInit(&client); break; default: diff --git a/projects/rocr-runtime/runtime/hsa-runtime/image/addrlib/src/gfx11/gfx11addrlib.cpp b/projects/rocr-runtime/runtime/hsa-runtime/image/addrlib/src/gfx11/gfx11addrlib.cpp index c80c6cea83..c56be1a575 100644 --- a/projects/rocr-runtime/runtime/hsa-runtime/image/addrlib/src/gfx11/gfx11addrlib.cpp +++ b/projects/rocr-runtime/runtime/hsa-runtime/image/addrlib/src/gfx11/gfx11addrlib.cpp @@ -755,6 +755,11 @@ ChipFamily Gfx11Lib::HwlConvertChipFamily( { } break; + case FAMILY_GFX1150: + if (ASICREV_IS_GFX1150(chipRevision)) + { + } + break; default: ADDR_ASSERT(!"Unknown chip family"); break; diff --git a/projects/rocr-runtime/runtime/hsa-runtime/image/blit_kernel.cpp b/projects/rocr-runtime/runtime/hsa-runtime/image/blit_kernel.cpp index 067c668f73..afbafed662 100644 --- a/projects/rocr-runtime/runtime/hsa-runtime/image/blit_kernel.cpp +++ b/projects/rocr-runtime/runtime/hsa-runtime/image/blit_kernel.cpp @@ -103,6 +103,8 @@ extern uint8_t ocl_blit_object_gfx1100[]; extern uint8_t ocl_blit_object_gfx1101[]; extern uint8_t ocl_blit_object_gfx1102[]; extern uint8_t ocl_blit_object_gfx1103[]; +extern uint8_t ocl_blit_object_gfx1150[]; +extern uint8_t ocl_blit_object_gfx1151[]; // Arguments inserted by OCL compiler, all zero here. struct OCLHiddenArgs { @@ -1046,6 +1048,10 @@ hsa_status_t BlitKernel::GetPatchedBlitObject(const char* agent_name, *blit_code_object = ocl_blit_object_gfx1102; } else if (sname == "gfx1103") { *blit_code_object = ocl_blit_object_gfx1103; + } else if (sname == "gfx1150") { + *blit_code_object = ocl_blit_object_gfx1150; + } else if (sname == "gfx1151") { + *blit_code_object = ocl_blit_object_gfx1151; } else { return HSA_STATUS_ERROR_INVALID_ISA_NAME; } diff --git a/projects/rocr-runtime/runtime/hsa-runtime/image/blit_src/CMakeLists.txt b/projects/rocr-runtime/runtime/hsa-runtime/image/blit_src/CMakeLists.txt index 1b3c7cfa3c..481adf81a8 100644 --- a/projects/rocr-runtime/runtime/hsa-runtime/image/blit_src/CMakeLists.txt +++ b/projects/rocr-runtime/runtime/hsa-runtime/image/blit_src/CMakeLists.txt @@ -47,7 +47,10 @@ find_package(Clang REQUIRED HINTS ${CMAKE_PREFIX_PATH}/llvm PATHS /opt/rocm/llvm # Determine the target devices if not specified if (NOT DEFINED TARGET_DEVICES) - set(TARGET_DEVICES "gfx700;gfx701;gfx702;gfx801;gfx802;gfx803;gfx805;gfx810;gfx900;gfx902;gfx904;gfx906;gfx908;gfx909;gfx90a;gfx90c;gfx940;gfx941;gfx942;gfx1010;gfx1011;gfx1012;gfx1013;gfx1030;gfx1031;gfx1032;gfx1033;gfx1034;gfx1035;gfx1036;gfx1100;gfx1101;gfx1102;gfx1103") + set (TARGET_DEVICES "gfx700;gfx701;gfx702;gfx801;gfx802;gfx803;gfx805;gfx810" + "gfx900;gfx902;gfx904;gfx906;gfx908;gfx909;gfx90a;gfx90c;gfx940;gfx941;gfx942" + "gfx1010;gfx1011;gfx1012;gfx1013;gfx1030;gfx1031;gfx1032;gfx1033;gfx1034;gfx1035;gfx1036" + "gfx1100;gfx1101;gfx1102;gfx1103;gfx1150;gfx1151") endif() set( TARGET_DEVICES ${TARGET_DEVICES} CACHE STRING "Build targets" FORCE ) diff --git a/projects/rocr-runtime/runtime/hsa-runtime/inc/amd_hsa_elf.h b/projects/rocr-runtime/runtime/hsa-runtime/inc/amd_hsa_elf.h index 45962b1ddd..d5359f18db 100644 --- a/projects/rocr-runtime/runtime/hsa-runtime/inc/amd_hsa_elf.h +++ b/projects/rocr-runtime/runtime/hsa-runtime/inc/amd_hsa_elf.h @@ -122,10 +122,12 @@ enum : unsigned { EF_AMDGPU_MACH_AMDGCN_GFX940 = 0x040, EF_AMDGPU_MACH_AMDGCN_GFX1100 = 0x041, EF_AMDGPU_MACH_AMDGCN_GFX1013 = 0x042, + EF_AMDGPU_MACH_AMDGCN_GFX1150 = 0x043, EF_AMDGPU_MACH_AMDGCN_GFX1103 = 0x044, EF_AMDGPU_MACH_AMDGCN_GFX1036 = 0x045, EF_AMDGPU_MACH_AMDGCN_GFX1101 = 0x046, EF_AMDGPU_MACH_AMDGCN_GFX1102 = 0x047, + EF_AMDGPU_MACH_AMDGCN_GFX1151 = 0x04a, EF_AMDGPU_MACH_AMDGCN_GFX941 = 0x04b, EF_AMDGPU_MACH_AMDGCN_GFX942 = 0x04c, diff --git a/projects/rocr-runtime/runtime/hsa-runtime/libamdhsacode/amd_hsa_code.cpp b/projects/rocr-runtime/runtime/hsa-runtime/libamdhsacode/amd_hsa_code.cpp index da0a6532e3..08836a5777 100644 --- a/projects/rocr-runtime/runtime/hsa-runtime/libamdhsacode/amd_hsa_code.cpp +++ b/projects/rocr-runtime/runtime/hsa-runtime/libamdhsacode/amd_hsa_code.cpp @@ -598,6 +598,8 @@ namespace code { case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1101: MI.Name = "gfx1101"; MI.XnackSupported = false; MI.SrameccSupported = false; break; case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1102: MI.Name = "gfx1102"; MI.XnackSupported = false; MI.SrameccSupported = false; break; case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1103: MI.Name = "gfx1103"; MI.XnackSupported = false; MI.SrameccSupported = false; break; + case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1150: MI.Name = "gfx1150"; MI.XnackSupported = false; MI.SrameccSupported = false; break; + case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1151: MI.Name = "gfx1151"; MI.XnackSupported = false; MI.SrameccSupported = false; break; default: return false; } return true;