Updated RDC to use AMD-SMI 24.6.0 structs
Signed-off-by: Maisam Arif <Maisam.Arif@amd.com> Change-Id: I9ef0f3cb786c1238e53cf21df5c6afafac829175
This commit is contained in:
Maisam Arif
committed by
Galantsev, Dmitrii
Galantsev, Dmitrii
parent
53033a5b77
commit
7c6bd4dc1c
@@ -217,27 +217,28 @@ const char* GetErrStateNameStr(amdsmi_ras_err_state_t st) { return kErrStateName
|
||||
}*/
|
||||
|
||||
const char* FreqEnumToStr(amdsmi_clk_type_t rsmi_clk) {
|
||||
static_assert(CLK_TYPE__MAX == CLK_TYPE_DCLK1, "FreqEnumToStr() needs to be updated");
|
||||
static_assert(AMDSMI_CLK_TYPE__MAX == AMDSMI_CLK_TYPE_DCLK1,
|
||||
"FreqEnumToStr() needs to be updated");
|
||||
switch (rsmi_clk) {
|
||||
case CLK_TYPE_SYS:
|
||||
case AMDSMI_CLK_TYPE_SYS:
|
||||
return "System clock";
|
||||
case CLK_TYPE_DF:
|
||||
case AMDSMI_CLK_TYPE_DF:
|
||||
return "Data Fabric clock";
|
||||
case CLK_TYPE_DCEF:
|
||||
case AMDSMI_CLK_TYPE_DCEF:
|
||||
return "Display Controller Engine clock";
|
||||
case CLK_TYPE_SOC:
|
||||
case AMDSMI_CLK_TYPE_SOC:
|
||||
return "SOC clock";
|
||||
case CLK_TYPE_MEM:
|
||||
case AMDSMI_CLK_TYPE_MEM:
|
||||
return "Memory clock";
|
||||
case CLK_TYPE_PCIE:
|
||||
case AMDSMI_CLK_TYPE_PCIE:
|
||||
return "PCIe clock";
|
||||
case CLK_TYPE_VCLK0:
|
||||
case AMDSMI_CLK_TYPE_VCLK0:
|
||||
return "VCLK0 clock";
|
||||
case CLK_TYPE_VCLK1:
|
||||
case AMDSMI_CLK_TYPE_VCLK1:
|
||||
return "VCLK1 clock";
|
||||
case CLK_TYPE_DCLK0:
|
||||
case AMDSMI_CLK_TYPE_DCLK0:
|
||||
return "DCLK0 clock";
|
||||
case CLK_TYPE_DCLK1:
|
||||
case AMDSMI_CLK_TYPE_DCLK1:
|
||||
return "DCLK1 clock";
|
||||
default:
|
||||
return "Invalid Clock ID";
|
||||
|
||||
@@ -50,85 +50,85 @@
|
||||
#include "amd_smi/amdsmi.h"
|
||||
|
||||
static const std::map<amdsmi_fw_block_t, const char*> kDevFWNameMap = {
|
||||
{FW_ID_SMU, "SMU"},
|
||||
{FW_ID_FIRST, "FIRST"},
|
||||
{FW_ID_CP_CE, "CP_CE"},
|
||||
{FW_ID_CP_PFP, "CP_PFP"},
|
||||
{FW_ID_CP_ME, "CP_ME"},
|
||||
{FW_ID_CP_MEC_JT1, "CP_MEC_JT1"},
|
||||
{FW_ID_CP_MEC_JT2, "CP_MEC_JT2"},
|
||||
{FW_ID_CP_MEC1, "CP_MEC1"},
|
||||
{FW_ID_CP_MEC2, "CP_MEC2"},
|
||||
{FW_ID_RLC, "RLC"},
|
||||
{FW_ID_SDMA0, "SDMA0"},
|
||||
{FW_ID_SDMA1, "SDMA1"},
|
||||
{FW_ID_SDMA2, "SDMA2"},
|
||||
{FW_ID_SDMA3, "SDMA3"},
|
||||
{FW_ID_SDMA4, "SDMA4"},
|
||||
{FW_ID_SDMA5, "SDMA5"},
|
||||
{FW_ID_SDMA6, "SDMA6"},
|
||||
{FW_ID_SDMA7, "SDMA7"},
|
||||
{FW_ID_VCN, "VCN"},
|
||||
{FW_ID_UVD, "UVD"},
|
||||
{FW_ID_VCE, "VCE"},
|
||||
{FW_ID_ISP, "ISP"},
|
||||
{FW_ID_DMCU_ERAM, "DMCU_ERAM"},
|
||||
{FW_ID_DMCU_ISR, "DMCU_ISR"},
|
||||
{FW_ID_RLC_RESTORE_LIST_GPM_MEM, "RLC_RESTORE_LIST_GPM_MEM"},
|
||||
{FW_ID_RLC_RESTORE_LIST_SRM_MEM, "RLC_RESTORE_LIST_SRM_MEM"},
|
||||
{FW_ID_RLC_RESTORE_LIST_CNTL, "RLC_RESTORE_LIST_CNTL"},
|
||||
{FW_ID_RLC_V, "RLC_V"},
|
||||
{FW_ID_MMSCH, "MMSCH"},
|
||||
{FW_ID_PSP_SYSDRV, "PSP_SYSDRV"},
|
||||
{FW_ID_PSP_SOSDRV, "PSP_SOSDRV"},
|
||||
{FW_ID_PSP_TOC, "PSP_TOC"},
|
||||
{FW_ID_PSP_KEYDB, "PSP_KEYDB"},
|
||||
{FW_ID_DFC, "DFC"},
|
||||
{FW_ID_PSP_SPL, "PSP_SPL"},
|
||||
{FW_ID_DRV_CAP, "DRV_CAP"},
|
||||
{FW_ID_MC, "MC"},
|
||||
{FW_ID_PSP_BL, "PSP_BL"},
|
||||
{FW_ID_CP_PM4, "CP_PM4"},
|
||||
{FW_ID_RLC_P, "RLC_P"},
|
||||
{FW_ID_SEC_POLICY_STAGE2, "SEC_POLICY_STAGE2"},
|
||||
{FW_ID_REG_ACCESS_WHITELIST, "REG_ACCESS_WHITELIST"},
|
||||
{FW_ID_IMU_DRAM, "IMU_DRAM"},
|
||||
{FW_ID_IMU_IRAM, "IMU_IRAM"},
|
||||
{FW_ID_SDMA_TH0, "SDMA_TH0"},
|
||||
{FW_ID_SDMA_TH1, "SDMA_TH1"},
|
||||
{FW_ID_CP_MES, "CP_MES"},
|
||||
{FW_ID_MES_KIQ, "MES_KIQ"},
|
||||
{FW_ID_MES_STACK, "MES_STACK"},
|
||||
{FW_ID_MES_THREAD1, "MES_THREAD1"},
|
||||
{FW_ID_MES_THREAD1_STACK, "MES_THREAD1_STACK"},
|
||||
{FW_ID_RLX6, "RLX6"},
|
||||
{FW_ID_RLX6_DRAM_BOOT, "RLX6_DRAM_BOOT"},
|
||||
{FW_ID_RS64_ME, "RS64_ME"},
|
||||
{FW_ID_RS64_ME_P0_DATA, "RS64_ME_P0_DATA"},
|
||||
{FW_ID_RS64_ME_P1_DATA, "RS64_ME_P1_DATA"},
|
||||
{FW_ID_RS64_PFP, "RS64_PFP"},
|
||||
{FW_ID_RS64_PFP_P0_DATA, "RS64_PFP_P0_DATA"},
|
||||
{FW_ID_RS64_PFP_P1_DATA, "RS64_PFP_P1_DATA"},
|
||||
{FW_ID_RS64_MEC, "RS64_MEC"},
|
||||
{FW_ID_RS64_MEC_P0_DATA, "RS64_MEC_P0_DATA"},
|
||||
{FW_ID_RS64_MEC_P1_DATA, "RS64_MEC_P1_DATA"},
|
||||
{FW_ID_RS64_MEC_P2_DATA, "RS64_MEC_P2_DATA"},
|
||||
{FW_ID_RS64_MEC_P3_DATA, "RS64_MEC_P3_DATA"},
|
||||
{FW_ID_PPTABLE, "PPTABLE"},
|
||||
{FW_ID_PSP_SOC, "PSP_SOC"},
|
||||
{FW_ID_PSP_DBG, "PSP_DBG"},
|
||||
{FW_ID_PSP_INTF, "PSP_INTF"},
|
||||
{FW_ID_RLX6_CORE1, "RLX6_CORE1"},
|
||||
{FW_ID_RLX6_DRAM_BOOT_CORE1, "RLX6_DRAM_BOOT_CORE1"},
|
||||
{FW_ID_RLCV_LX7, "RLCV_LX7"},
|
||||
{FW_ID_RLC_SAVE_RESTORE_LIST, "RLC_SAVE_RESTORE_LIST"},
|
||||
{FW_ID_ASD, "ASD"},
|
||||
{FW_ID_TA_RAS, "TA_RAS"},
|
||||
{FW_ID_TA_XGMI, "TA_XGMI"},
|
||||
{FW_ID_RLC_SRLG, "RLC_SRLG"},
|
||||
{FW_ID_RLC_SRLS, "RLC_SRLS"},
|
||||
{FW_ID_PM, "PM"},
|
||||
{FW_ID_DMCU, "DMCU"},
|
||||
{AMDSMI_FW_ID_SMU, "SMU"},
|
||||
{AMDSMI_FW_ID_FIRST, "FIRST"},
|
||||
{AMDSMI_FW_ID_CP_CE, "CP_CE"},
|
||||
{AMDSMI_FW_ID_CP_PFP, "CP_PFP"},
|
||||
{AMDSMI_FW_ID_CP_ME, "CP_ME"},
|
||||
{AMDSMI_FW_ID_CP_MEC_JT1, "CP_MEC_JT1"},
|
||||
{AMDSMI_FW_ID_CP_MEC_JT2, "CP_MEC_JT2"},
|
||||
{AMDSMI_FW_ID_CP_MEC1, "CP_MEC1"},
|
||||
{AMDSMI_FW_ID_CP_MEC2, "CP_MEC2"},
|
||||
{AMDSMI_FW_ID_RLC, "RLC"},
|
||||
{AMDSMI_FW_ID_SDMA0, "SDMA0"},
|
||||
{AMDSMI_FW_ID_SDMA1, "SDMA1"},
|
||||
{AMDSMI_FW_ID_SDMA2, "SDMA2"},
|
||||
{AMDSMI_FW_ID_SDMA3, "SDMA3"},
|
||||
{AMDSMI_FW_ID_SDMA4, "SDMA4"},
|
||||
{AMDSMI_FW_ID_SDMA5, "SDMA5"},
|
||||
{AMDSMI_FW_ID_SDMA6, "SDMA6"},
|
||||
{AMDSMI_FW_ID_SDMA7, "SDMA7"},
|
||||
{AMDSMI_FW_ID_VCN, "VCN"},
|
||||
{AMDSMI_FW_ID_UVD, "UVD"},
|
||||
{AMDSMI_FW_ID_VCE, "VCE"},
|
||||
{AMDSMI_FW_ID_ISP, "ISP"},
|
||||
{AMDSMI_FW_ID_DMCU_ERAM, "DMCU_ERAM"},
|
||||
{AMDSMI_FW_ID_DMCU_ISR, "DMCU_ISR"},
|
||||
{AMDSMI_FW_ID_RLC_RESTORE_LIST_GPM_MEM, "RLC_RESTORE_LIST_GPM_MEM"},
|
||||
{AMDSMI_FW_ID_RLC_RESTORE_LIST_SRM_MEM, "RLC_RESTORE_LIST_SRM_MEM"},
|
||||
{AMDSMI_FW_ID_RLC_RESTORE_LIST_CNTL, "RLC_RESTORE_LIST_CNTL"},
|
||||
{AMDSMI_FW_ID_RLC_V, "RLC_V"},
|
||||
{AMDSMI_FW_ID_MMSCH, "MMSCH"},
|
||||
{AMDSMI_FW_ID_PSP_SYSDRV, "PSP_SYSDRV"},
|
||||
{AMDSMI_FW_ID_PSP_SOSDRV, "PSP_SOSDRV"},
|
||||
{AMDSMI_FW_ID_PSP_TOC, "PSP_TOC"},
|
||||
{AMDSMI_FW_ID_PSP_KEYDB, "PSP_KEYDB"},
|
||||
{AMDSMI_FW_ID_DFC, "DFC"},
|
||||
{AMDSMI_FW_ID_PSP_SPL, "PSP_SPL"},
|
||||
{AMDSMI_FW_ID_DRV_CAP, "DRV_CAP"},
|
||||
{AMDSMI_FW_ID_MC, "MC"},
|
||||
{AMDSMI_FW_ID_PSP_BL, "PSP_BL"},
|
||||
{AMDSMI_FW_ID_CP_PM4, "CP_PM4"},
|
||||
{AMDSMI_FW_ID_RLC_P, "RLC_P"},
|
||||
{AMDSMI_FW_ID_SEC_POLICY_STAGE2, "SEC_POLICY_STAGE2"},
|
||||
{AMDSMI_FW_ID_REG_ACCESS_WHITELIST, "REG_ACCESS_WHITELIST"},
|
||||
{AMDSMI_FW_ID_IMU_DRAM, "IMU_DRAM"},
|
||||
{AMDSMI_FW_ID_IMU_IRAM, "IMU_IRAM"},
|
||||
{AMDSMI_FW_ID_SDMA_TH0, "SDMA_TH0"},
|
||||
{AMDSMI_FW_ID_SDMA_TH1, "SDMA_TH1"},
|
||||
{AMDSMI_FW_ID_CP_MES, "CP_MES"},
|
||||
{AMDSMI_FW_ID_MES_KIQ, "MES_KIQ"},
|
||||
{AMDSMI_FW_ID_MES_STACK, "MES_STACK"},
|
||||
{AMDSMI_FW_ID_MES_THREAD1, "MES_THREAD1"},
|
||||
{AMDSMI_FW_ID_MES_THREAD1_STACK, "MES_THREAD1_STACK"},
|
||||
{AMDSMI_FW_ID_RLX6, "RLX6"},
|
||||
{AMDSMI_FW_ID_RLX6_DRAM_BOOT, "RLX6_DRAM_BOOT"},
|
||||
{AMDSMI_FW_ID_RS64_ME, "RS64_ME"},
|
||||
{AMDSMI_FW_ID_RS64_ME_P0_DATA, "RS64_ME_P0_DATA"},
|
||||
{AMDSMI_FW_ID_RS64_ME_P1_DATA, "RS64_ME_P1_DATA"},
|
||||
{AMDSMI_FW_ID_RS64_PFP, "RS64_PFP"},
|
||||
{AMDSMI_FW_ID_RS64_PFP_P0_DATA, "RS64_PFP_P0_DATA"},
|
||||
{AMDSMI_FW_ID_RS64_PFP_P1_DATA, "RS64_PFP_P1_DATA"},
|
||||
{AMDSMI_FW_ID_RS64_MEC, "RS64_MEC"},
|
||||
{AMDSMI_FW_ID_RS64_MEC_P0_DATA, "RS64_MEC_P0_DATA"},
|
||||
{AMDSMI_FW_ID_RS64_MEC_P1_DATA, "RS64_MEC_P1_DATA"},
|
||||
{AMDSMI_FW_ID_RS64_MEC_P2_DATA, "RS64_MEC_P2_DATA"},
|
||||
{AMDSMI_FW_ID_RS64_MEC_P3_DATA, "RS64_MEC_P3_DATA"},
|
||||
{AMDSMI_FW_ID_PPTABLE, "PPTABLE"},
|
||||
{AMDSMI_FW_ID_PSP_SOC, "PSP_SOC"},
|
||||
{AMDSMI_FW_ID_PSP_DBG, "PSP_DBG"},
|
||||
{AMDSMI_FW_ID_PSP_INTF, "PSP_INTF"},
|
||||
{AMDSMI_FW_ID_RLX6_CORE1, "RLX6_CORE1"},
|
||||
{AMDSMI_FW_ID_RLX6_DRAM_BOOT_CORE1, "RLX6_DRAM_BOOT_CORE1"},
|
||||
{AMDSMI_FW_ID_RLCV_LX7, "RLCV_LX7"},
|
||||
{AMDSMI_FW_ID_RLC_SAVE_RESTORE_LIST, "RLC_SAVE_RESTORE_LIST"},
|
||||
{AMDSMI_FW_ID_ASD, "ASD"},
|
||||
{AMDSMI_FW_ID_TA_RAS, "TA_RAS"},
|
||||
{AMDSMI_FW_ID_TA_XGMI, "TA_XGMI"},
|
||||
{AMDSMI_FW_ID_RLC_SRLG, "RLC_SRLG"},
|
||||
{AMDSMI_FW_ID_RLC_SRLS, "RLC_SRLS"},
|
||||
{AMDSMI_FW_ID_PM, "PM"},
|
||||
{AMDSMI_FW_ID_DMCU, "DMCU"},
|
||||
};
|
||||
|
||||
const char* NameFromFWEnum(amdsmi_fw_block_t blk) { return kDevFWNameMap.at(blk); }
|
||||
|
||||
Reference in New Issue
Block a user