From 7f83bcdb455ed00f47dca261801dd7b519f49345 Mon Sep 17 00:00:00 2001 From: Jason Tang Date: Mon, 30 Aug 2021 11:44:24 -0400 Subject: [PATCH] SWDEV-1 - Disable OpenCL support for gfx8 in ROCm path Change-Id: Ie1e0c0d6273edf6b734909447c2a08252cba305b --- rocclr/cmake/ROCclr.cmake | 7 ------- rocclr/device/device.hpp | 3 +++ rocclr/device/rocm/rocdevice.cpp | 8 -------- rocclr/utils/flags.hpp | 4 +++- 4 files changed, 6 insertions(+), 16 deletions(-) diff --git a/rocclr/cmake/ROCclr.cmake b/rocclr/cmake/ROCclr.cmake index fd09d38b1c..e29a54cd18 100644 --- a/rocclr/cmake/ROCclr.cmake +++ b/rocclr/cmake/ROCclr.cmake @@ -93,13 +93,6 @@ if(WIN32) target_compile_definitions(rocclr PUBLIC ATI_OS_WIN) else() target_compile_definitions(rocclr PUBLIC ATI_OS_LINUX) - - # Additional settings for LinuxPro - option(BUILD_LINUXPRO "Build LinuxPro" OFF) - if(BUILD_LINUXPRO) - target_compile_definitions(rocclr PUBLIC - ROCCLR_DISABLE_PREVEGA ) - endif() endif() target_compile_definitions(rocclr PUBLIC diff --git a/rocclr/device/device.hpp b/rocclr/device/device.hpp index e8975ea929..48f98598a3 100644 --- a/rocclr/device/device.hpp +++ b/rocclr/device/device.hpp @@ -1303,6 +1303,9 @@ class Isa { /// @returns If the ROCm runtime supports the ISA. bool runtimeRocSupported() const { + if (!IS_HIP && !ROC_ENABLE_PRE_VEGA && (versionMajor_ == 8)) { + return false; + } return runtimeRocSupported_; } diff --git a/rocclr/device/rocm/rocdevice.cpp b/rocclr/device/rocm/rocdevice.cpp index 967dc313eb..f31ec77c02 100644 --- a/rocclr/device/rocm/rocdevice.cpp +++ b/rocclr/device/rocm/rocdevice.cpp @@ -606,14 +606,6 @@ bool Device::create() { return false; } -#if ROCCLR_DISABLE_PREVEGA - if (isa->versionMajor() < 9) { - LogPrintfError("Disabled HSA device %s (PCI ID %x) for ISA %s", agent_name, pciDeviceId_, - isa_name.data()); - return false; - } -#endif - if (HSA_STATUS_SUCCESS != hsa_agent_get_info(_bkendDevice, HSA_AGENT_INFO_PROFILE, &agent_profile_)) { LogPrintfError("Unable to get profile for HSA device %s (PCI ID %x)", agent_name, pciDeviceId_); diff --git a/rocclr/utils/flags.hpp b/rocclr/utils/flags.hpp index 0ceb67de39..4197d1f9e2 100644 --- a/rocclr/utils/flags.hpp +++ b/rocclr/utils/flags.hpp @@ -206,7 +206,7 @@ release(bool, GPU_IMAGE_BUFFER_WAR, true, \ release(cstring, HIP_VISIBLE_DEVICES, "", \ "Only devices whose index is present in the sequence are visible to HIP") \ release(cstring, CUDA_VISIBLE_DEVICES, "", \ - "Only devices whose index is present in the sequence are visible to HIP") \ + "Only devices whose index is present in the sequence are visible to CUDA") \ release(bool, GPU_ENABLE_WGP_MODE, true, \ "Enables WGP Mode in HW if available") \ release(bool, GPU_DUMP_CODE_OBJECT, false, \ @@ -245,6 +245,8 @@ release(bool, ROC_SYSTEM_SCOPE_SIGNAL, true, \ "Enable system scope for signals (uses interrupts).") \ release(bool, ROC_SKIP_COPY_SYNC, false, \ "Skips copy syncs if runtime can predict the same engine.") \ +release(bool, ROC_ENABLE_PRE_VEGA, false, \ + "Enable support of pre-vega ASICs in ROCm path") \ release(bool, HIP_FORCE_QUEUE_PROFILING, false, \ "Force command queue profiling by default") \ release(uint, PAL_FORCE_ASIC_REVISION, 0, \