Adding rocprofilerv2
Change-Id: Ic0cc280ba207d2b8f6ccae1cd4ac3184152fc1ad
Этот коммит содержится в:
Ammar ELWazir committed
1 родитель
e0e5f7336b
Коммит
8032adb64f
263 files changed
+607729
-307
No files matched your search
@@ -0,0 +1,86 @@
|
||||
/* Copyright (c) 2022 Advanced Micro Devices, Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE. */
|
||||
|
||||
#ifndef SRC_CORE_COUNTERS_BASIC_BASIC_COUNTER_H_
|
||||
#define SRC_CORE_COUNTERS_BASIC_BASIC_COUNTER_H_
|
||||
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include <unistd.h>
|
||||
|
||||
#include <algorithm>
|
||||
#include <cassert>
|
||||
#include <cstdint>
|
||||
#include <map>
|
||||
#include <unordered_map>
|
||||
#include <vector>
|
||||
|
||||
#include "src/core/counters/counter.h"
|
||||
|
||||
#define ASSERTM(exp, msg) assert(((void)msg, exp))
|
||||
|
||||
namespace Counter {
|
||||
|
||||
class BasicCounter : Counter {
|
||||
public:
|
||||
BasicCounter(uint64_t event_id, std::string block_id, std::string name, std::string description,
|
||||
std::string gpu_name);
|
||||
~BasicCounter();
|
||||
|
||||
uint64_t GetEventId();
|
||||
std::string GetBlockId();
|
||||
std::string GetName();
|
||||
uint64_t GetBasicCounterID();
|
||||
bool GetValue(uint64_t* value, int64_t instance_id);
|
||||
uint64_t GetValue(int64_t instance_id = -1);
|
||||
|
||||
uint64_t avr(int64_t instances_count);
|
||||
uint64_t max(int64_t instances_count);
|
||||
uint64_t min(int64_t instances_count);
|
||||
uint64_t sum(int64_t instances_count);
|
||||
|
||||
private:
|
||||
void* counter_hw_info;
|
||||
std::unordered_map<int64_t, uint64_t> instances_values_;
|
||||
uint64_t event_id_;
|
||||
std::string block_id_;
|
||||
};
|
||||
|
||||
uint64_t operator+(BasicCounter counter, const uint64_t number);
|
||||
uint64_t operator*(BasicCounter counter, const uint64_t number);
|
||||
uint64_t operator/(BasicCounter counter, const uint64_t number);
|
||||
uint64_t operator-(BasicCounter counter, const uint64_t number);
|
||||
uint64_t operator^(BasicCounter counter, const uint64_t number);
|
||||
|
||||
uint64_t operator+(BasicCounter counter1, BasicCounter counter2);
|
||||
uint64_t operator*(BasicCounter counter1, BasicCounter counter2);
|
||||
uint64_t operator/(BasicCounter counter1, BasicCounter counter2);
|
||||
uint64_t operator-(BasicCounter counter1, BasicCounter counter2);
|
||||
uint64_t operator^(BasicCounter counter1, BasicCounter counter2);
|
||||
|
||||
BasicCounter* GetGeneratedBasicCounter(uint64_t id);
|
||||
void ClearBasicCounters();
|
||||
|
||||
uint64_t GetBasicCounter(const char* name, const char* gpu_name);
|
||||
|
||||
} // namespace Counter
|
||||
|
||||
#endif // SRC_CORE_COUNTERS_BASIC_BASIC_COUNTER_H_
|
||||
Executable
+696
@@ -0,0 +1,696 @@
|
||||
<counters>
|
||||
<gfx8>
|
||||
<metric name="GRBM_COUNT" block="GRBM" event="0" descr="Tie High - Count Number of Clocks"></metric>
|
||||
<metric name="GRBM_GUI_ACTIVE" block="GRBM" event="2" descr="The GUI is Active"></metric>
|
||||
<metric name="SQ_WAVES" block="SQ" event="4" descr="Count number of waves sent to SQs. (per-simd, emulated, global)"></metric>
|
||||
<metric name="SQ_INSTS_VALU" block="SQ" event="26" descr="Number of VALU instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VMEM_WR" block="SQ" event="27" descr="Number of VMEM write instructions issued (including FLAT). (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VMEM_RD" block="SQ" event="28" descr="Number of VMEM read instructions issued (including FLAT). (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_SALU" block="SQ" event="30" descr="Number of SALU instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_SMEM" block="SQ" event="31" descr="Number of SMEM instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_FLAT" block="SQ" event="32" descr="Number of FLAT instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_FLAT_LDS_ONLY" block="SQ" event="33" descr="Number of FLAT instructions issued that read/wrote only from/to LDS (only works if EARLY_TA_DONE is enabled). (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_LDS" block="SQ" event="34" descr="Number of LDS instructions issued (including FLAT). (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_GDS" block="SQ" event="35" descr="Number of GDS instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_WAIT_INST_LDS" block="SQ" event="61" descr="Number of wave-cycles spent waiting for LDS instruction issue. In units of 4 cycles. (per-simd, nondeterministic)"></metric>
|
||||
<metric name="SQ_ACTIVE_INST_VALU" block="SQ" event="69" descr="Number of cycles the SQ instruction arbiter is working on a VALU instruction. (per-simd, nondeterministic). Units in quad-cycles(4 cycles)"></metric>
|
||||
<metric name="SQ_INST_CYCLES_SALU" block="SQ" event="86" descr="Number of cycles needed to execute non-memory read scalar operations. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_THREAD_CYCLES_VALU" block="SQ" event="89" descr="Number of thread-cycles used to execute VALU operations (similar to INST_CYCLES_VALU but multiplied by # of active threads). (per-simd)"></metric>
|
||||
<metric name="SQ_LDS_BANK_CONFLICT" block="SQ" event="97" descr="Number of cycles LDS is stalled by bank conflicts. (emulated)"></metric>
|
||||
<metric name="TA_TA_BUSY" block="TA" event="15" descr="TA block is busy. Perf_Windowing not supported for this counter."></metric>
|
||||
<metric name="TA_FLAT_READ_WAVEFRONTS" block="TA" event="101" descr="Number of flat opcode reads processed by the TA."></metric>
|
||||
<metric name="TA_FLAT_WRITE_WAVEFRONTS" block="TA" event="102" descr="Number of flat opcode writes processed by the TA."></metric>
|
||||
<metric name="TCC_HIT" block="TCC" event="18" descr="Number of cache hits."></metric>
|
||||
<metric name="TCC_MISS" block="TCC" event="19" descr="Number of cache misses. UC reads count as misses."></metric>
|
||||
<metric name="TCC_MC_RDREQ" block="TCC" event="35" descr="Number of 32-byte reads. The hardware actually does 64-byte reads but the number is adjusted to provide uniformity."></metric>
|
||||
<metric name="TCC_MC_WRREQ" block="TCC" event="26" descr="Number of 32-byte transactions going over the TC_MC_wrreq interface. Atomics may travel over the same interface and are generally classified as write requests."></metric>
|
||||
<metric name="TCC_MC_WRREQ_STALL" block="TCC" event="28" descr="Number of cycles a write request was stalled."></metric>
|
||||
<metric name="TCP_TCP_TA_DATA_STALL_CYCLES" block="TCP" event="3" descr="TCP stalls TA data interface. Now Windowed."></metric>
|
||||
</gfx8>
|
||||
|
||||
<gfx906>
|
||||
<metric name="GRBM_COUNT" block="GRBM" event="0" descr="Tie High - Count Number of Clocks"></metric>
|
||||
<metric name="GRBM_GUI_ACTIVE" block="GRBM" event="2" descr="The GUI is Active"></metric>
|
||||
<metric name="SQ_WAVES" block="SQ" event="4" descr="Count number of waves sent to SQs. (per-simd, emulated, global)"></metric>
|
||||
<metric name="SQ_INSTS_VALU" block="SQ" event="26" descr="Number of VALU instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VMEM_WR" block="SQ" event="27" descr="Number of VMEM write instructions issued (including FLAT). (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VMEM_RD" block="SQ" event="28" descr="Number of VMEM read instructions issued (including FLAT). (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_SALU" block="SQ" event="30" descr="Number of SALU instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_SMEM" block="SQ" event="31" descr="Number of SMEM instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_FLAT" block="SQ" event="32" descr="Number of FLAT instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_FLAT_LDS_ONLY" block="SQ" event="33" descr="Number of FLAT instructions issued that read/wrote only from/to LDS (only works if EARLY_TA_DONE is enabled). (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_LDS" block="SQ" event="34" descr="Number of LDS instructions issued (including FLAT). (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_GDS" block="SQ" event="35" descr="Number of GDS instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_WAIT_INST_LDS" block="SQ" event="63" descr="Number of wave-cycles spent waiting for LDS instruction issue. In units of 4 cycles. (per-simd, nondeterministic)"></metric>
|
||||
<metric name="SQ_ACTIVE_INST_VALU" block="SQ" event="71" descr="regspec 71? Number of cycles the SQ instruction arbiter is working on a VALU instruction. (per-simd, nondeterministic). Units in quad-cycles(4 cycles)"></metric>
|
||||
<metric name="SQ_INST_CYCLES_SALU" block="SQ" event="84" descr="Number of cycles needed to execute non-memory read scalar operations. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_THREAD_CYCLES_VALU" block="SQ" event="85" descr="Number of thread-cycles used to execute VALU operations (similar to INST_CYCLES_VALU but multiplied by # of active threads). (per-simd)"></metric>
|
||||
<metric name="SQ_LDS_BANK_CONFLICT" block="SQ" event="93" descr="Number of cycles LDS is stalled by bank conflicts. (emulated)"></metric>
|
||||
<metric name="TA_TA_BUSY" block="TA" event="15" descr="TA block is busy. Perf_Windowing not supported for this counter."></metric>
|
||||
<metric name="TA_FLAT_READ_WAVEFRONTS" block="TA" event="101" descr="Number of flat opcode reads processed by the TA."></metric>
|
||||
<metric name="TA_FLAT_WRITE_WAVEFRONTS" block="TA" event="102" descr="Number of flat opcode writes processed by the TA."></metric>
|
||||
<metric name="TCC_HIT" block="TCC" event="20" descr="Number of cache hits."></metric>
|
||||
<metric name="TCC_MISS" block="TCC" event="22" descr="Number of cache misses. UC reads count as misses."></metric>
|
||||
<metric name="TCC_EA_WRREQ" block="TCC" event="29" descr="Number of transactions (either 32-byte or 64-byte) going over the TC_EA_wrreq interface. Atomics may travel over the same interface and are generally classified as write requests. This does not include probe commands."></metric>
|
||||
<metric name="TCC_EA_WRREQ_64B" block="TCC" event="30" descr="Number of 64-byte transactions going (64-byte write or CMPSWAP) over the TC_EA_wrreq interface."></metric>
|
||||
<metric name="TCC_EA_WRREQ_STALL" block="TCC" event="33" descr="Number of cycles a write request was stalled."></metric>
|
||||
<metric name="TCC_EA_RDREQ" block="TCC" event="41" descr="Number of TCC/EA read requests (either 32-byte or 64-byte)"></metric>
|
||||
<metric name="TCC_EA_RDREQ_32B" block="TCC" event="42" descr="Number of 32-byte TCC/EA read requests"></metric>
|
||||
<metric name="TCP_TCP_TA_DATA_STALL_CYCLES" block="TCP" event="6" descr="TCP stalls TA data interface. Now Windowed."></metric>
|
||||
<metric name="TCC_EA1_WRREQ" block="TCC" event="256" descr="Number of transactions (either 32-byte or 64-byte) going over the TC_EA_wrreq interface. Atomics may travel over the same interface and are generally classified as write requests. This does not include probe commands."></metric>
|
||||
<metric name="TCC_EA1_WRREQ_64B" block="TCC" event="257" descr="Number of 64-byte transactions going (64-byte write or CMPSWAP) over the TC_EA_wrreq interface."></metric>
|
||||
<metric name="TCC_EA1_WRREQ_STALL" block="TCC" event="260" descr="Number of cycles a write request was stalled."></metric>
|
||||
<metric name="TCC_EA1_RDREQ" block="TCC" event="267" descr="Number of TCC/EA read requests (either 32-byte or 64-byte)"></metric>
|
||||
<metric name="TCC_EA1_RDREQ_32B" block="TCC" event="268" descr="Number of 32-byte TCC/EA read requests"></metric>
|
||||
</gfx906>
|
||||
|
||||
<gfx908>
|
||||
<metric name="GRBM_COUNT" block="GRBM" event="0" descr="Tie High - Count Number of Clocks"></metric>
|
||||
<metric name="GRBM_GUI_ACTIVE" block="GRBM" event="2" descr="The GUI is Active"></metric>
|
||||
<metric name="SQ_WAVES" block="SQ" event="4" descr="Count number of waves sent to SQs. (per-simd, emulated, global)"></metric>
|
||||
<metric name="SQ_INSTS_VALU" block="SQ" event="26" descr="Number of VALU instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="TA_TA_BUSY" block="TA" event="15" descr="TA block is busy. Perf_Windowing not supported for this counter."></metric>
|
||||
<metric name="TA_FLAT_READ_WAVEFRONTS" block="TA" event="101" descr="Number of flat opcode reads processed by the TA."></metric>
|
||||
<metric name="TA_FLAT_WRITE_WAVEFRONTS" block="TA" event="102" descr="Number of flat opcode writes processed by the TA."></metric>
|
||||
<metric name="TCP_TCP_TA_DATA_STALL_CYCLES" block="TCP" event="6" descr="TCP stalls TA data interface. Now Windowed."></metric>
|
||||
<metric name="SQ_INSTS_VMEM_WR" block="SQ" event="28" descr="Number of VMEM write instructions issued (including FLAT). (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VMEM_RD" block="SQ" event="29" descr="Number of VMEM read instructions issued (including FLAT). (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_SALU" block="SQ" event="31" descr="Number of SALU instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_SMEM" block="SQ" event="32" descr="Number of SMEM instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_FLAT" block="SQ" event="33" descr="Number of FLAT instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_FLAT_LDS_ONLY" block="SQ" event="34" descr="Number of FLAT instructions issued that read/wrote only from/to LDS (only works if EARLY_TA_DONE is enabled). (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_LDS" block="SQ" event="35" descr="Number of LDS instructions issued (including FLAT). (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_GDS" block="SQ" event="36" descr="Number of GDS instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_WAIT_INST_LDS" block="SQ" event="64" descr="Number of wave-cycles spent waiting for LDS instruction issue. In units of 4 cycles. (per-simd, nondeterministic)"></metric>
|
||||
<metric name="SQ_ACTIVE_INST_VALU" block="SQ" event="72" descr="regspec 71? Number of cycles the SQ instruction arbiter is working on a VALU instruction. (per-simd, nondeterministic). Units in quad-cycles(4 cycles)"></metric>
|
||||
<metric name="SQ_INST_CYCLES_SALU" block="SQ" event="85" descr="Number of cycles needed to execute non-memory read scalar operations. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_THREAD_CYCLES_VALU" block="SQ" event="86" descr="Number of thread-cycles used to execute VALU operations (similar to INST_CYCLES_VALU but multiplied by # of active threads). (per-simd)"></metric>
|
||||
<metric name="SQ_LDS_BANK_CONFLICT" block="SQ" event="94" descr="Number of cycles LDS is stalled by bank conflicts. (emulated)"></metric>
|
||||
<metric name="TCC_HIT" block="TCC" event="17" descr="Number of cache hits."></metric>
|
||||
<metric name="TCC_MISS" block="TCC" event="19" descr="Number of cache misses. UC reads count as misses."></metric>
|
||||
<metric name="TCC_EA_WRREQ" block="TCC" event="26" descr="Number of transactions (either 32-byte or 64-byte) going over the TC_EA_wrreq interface. Atomics may travel over the same interface and are generally classified as write requests. This does not include probe commands."></metric>
|
||||
<metric name="TCC_EA_WRREQ_64B" block="TCC" event="27" descr="Number of 64-byte transactions going (64-byte write or CMPSWAP) over the TC_EA_wrreq interface."></metric>
|
||||
<metric name="TCC_EA_WRREQ_STALL" block="TCC" event="30" descr="Number of cycles a write request was stalled."></metric>
|
||||
<metric name="TCC_EA_RDREQ" block="TCC" event="38" descr="Number of TCC/EA read requests (either 32-byte or 64-byte)"></metric>
|
||||
<metric name="TCC_EA_RDREQ_32B" block="TCC" event="39" descr="Number of 32-byte TCC/EA read requests"></metric>
|
||||
</gfx908>
|
||||
|
||||
<gfx90a>
|
||||
<metric name="SQ_WAIT_INST_LDS" block="SQ" event="91" descr="Number of wave-cycles spent waiting for LDS instruction issue. In units of 4 cycles. (per-simd, nondeterministic)"></metric>
|
||||
<metric name="TCP_TCP_TA_DATA_STALL_CYCLES" block="TCP" event="6" descr="TCP stalls TA data interface. Now Windowed."></metric>
|
||||
<metric name="GRBM_COUNT" block="GRBM" event="0" descr="Tie High - Count Number of Clocks"></metric>
|
||||
<metric name="GRBM_GUI_ACTIVE" block="GRBM" event="2" descr="The GUI is Active"></metric>
|
||||
<metric name="GRBM_CP_BUSY" block="GRBM" event="3" descr="Any of the Command Processor (CPG/CPC/CPF) blocks are busy."></metric>
|
||||
<metric name="GRBM_SPI_BUSY" block="GRBM" event="11" descr="Any of the Shader Pipe Interpolators (SPI) are busy in the shader engine(s)."></metric>
|
||||
<metric name="GRBM_TA_BUSY" block="GRBM" event="13" descr="Any of the Texture Pipes (TA) are busy in the shader engine(s)."></metric>
|
||||
<metric name="GRBM_TC_BUSY" block="GRBM" event="28" descr="Any of the Texture Cache Blocks (TCP/TCI/TCA/TCC) are busy."></metric>
|
||||
<metric name="GRBM_CPC_BUSY" block="GRBM" event="30" descr="The Command Processor Compute (CPC) is busy."></metric>
|
||||
<metric name="GRBM_CPF_BUSY" block="GRBM" event="31" descr="The Command Processor Fetchers (CPF) is busy."></metric>
|
||||
<metric name="GRBM_UTCL2_BUSY" block="GRBM" event="34" descr="The Unified Translation Cache Level-2 (UTCL2) block is busy."></metric>
|
||||
<metric name="GRBM_EA_BUSY" block="GRBM" event="35" descr="The Efficiency Arbiter (EA) block is busy."></metric>
|
||||
<metric name="CPC_ME1_BUSY_FOR_PACKET_DECODE" block="CPC" event="13" descr="Me1 busy for packet decode."></metric>
|
||||
<metric name="CPC_UTCL1_STALL_ON_TRANSLATION" block="CPC" event="24" descr="One of the UTCL1s is stalled waiting on translation, XNACK or PENDING response."></metric>
|
||||
<metric name="CPC_CPC_STAT_BUSY" block="CPC" event="25" descr="CPC Busy."></metric>
|
||||
<metric name="CPC_CPC_STAT_IDLE" block="CPC" event="26" descr="CPC Idle."></metric>
|
||||
<metric name="CPC_CPC_STAT_STALL" block="CPC" event="27" descr="CPC Stalled."></metric>
|
||||
<metric name="CPC_CPC_TCIU_BUSY" block="CPC" event="28" descr="CPC TCIU interface Busy."></metric>
|
||||
<metric name="CPC_CPC_TCIU_IDLE" block="CPC" event="29" descr="CPC TCIU interface Idle."></metric>
|
||||
<metric name="CPC_CPC_UTCL2IU_BUSY" block="CPC" event="30" descr="CPC UTCL2 interface Busy."></metric>
|
||||
<metric name="CPC_CPC_UTCL2IU_IDLE" block="CPC" event="31" descr="CPC UTCL2 interface Idle."></metric>
|
||||
<metric name="CPC_CPC_UTCL2IU_STALL" block="CPC" event="32" descr="CPC UTCL2 interface Stalled waiting on Free, Tags or Translation."></metric>
|
||||
<metric name="CPC_ME1_DC0_SPI_BUSY" block="CPC" event="33" descr="CPC Me1 Processor Busy."></metric>
|
||||
<metric name="CPF_CMP_UTCL1_STALL_ON_TRANSLATION" block="CPF" event="20" descr="One of the Compute UTCL1s is stalled waiting on translation, XNACK or PENDING response."></metric>
|
||||
<metric name="CPF_CPF_STAT_BUSY" block="CPF" event="23" descr="CPF Busy."></metric>
|
||||
<metric name="CPF_CPF_STAT_IDLE" block="CPF" event="24" descr="CPF Idle."></metric>
|
||||
<metric name="CPF_CPF_STAT_STALL" block="CPF" event="25" descr="CPF Stalled."></metric>
|
||||
<metric name="CPF_CPF_TCIU_BUSY" block="CPF" event="26" descr="CPF TCIU interface Busy."></metric>
|
||||
<metric name="CPF_CPF_TCIU_IDLE" block="CPF" event="27" descr="CPF TCIU interface Idle."></metric>
|
||||
<metric name="CPF_CPF_TCIU_STALL" block="CPF" event="28" descr="CPF TCIU interface Stalled waiting on Free, Tags."></metric>
|
||||
<metric name="SPI_CSN_WINDOW_VALID" block="SPI" event="47" descr="Clock count enabled by perfcounter_start event. Requires SPI_DEBUG_CNTL.DEBUG_PIPE_SEL to select source, DEBUG_PIPE_SEL = 1, source is CS1; DEBUG_PIPE_SEL = 2, source is CS2; DEBUG_PIPE_SEL = 3, source is CS3; default, source is CS0;"></metric>
|
||||
<metric name="SPI_CSN_BUSY" block="SPI" event="48" descr="Number of clocks with outstanding waves (SPI or SH). Requires SPI_DEBUG_CNTL.DEBUG_PIPE_SEL to select source, DEBUG_PIPE_SEL = 1, source is CS1; DEBUG_PIPE_SEL = 2, source is CS2; DEBUG_PIPE_SEL = 3, source is CS3; default, source is CS0;"></metric>
|
||||
<metric name="SPI_CSN_NUM_THREADGROUPS" block="SPI" event="49" descr="Number of threadgroups launched. Requires SPI_DEBUG_CNTL.DEBUG_PIPE_SEL to select source, DEBUG_PIPE_SEL = 1, source is CS1; DEBUG_PIPE_SEL = 2, source is CS2; DEBUG_PIPE_SEL = 3, source is CS3; default, source is CS0;"></metric>
|
||||
<metric name="SPI_CSN_WAVE" block="SPI" event="52" descr="Number of waves. Requires SPI_DEBUG_CNTL.DEBUG_PIPE_SEL to select source, DEBUG_PIPE_SEL = 1, source is CS1; DEBUG_PIPE_SEL = 2, source is CS2; DEBUG_PIPE_SEL = 3, source is CS3; default, source is CS0;"></metric>
|
||||
<metric name="SPI_RA_REQ_NO_ALLOC" block="SPI" event="79" descr="Arb cycles with requests but no allocation. Source is RA0"></metric>
|
||||
<metric name="SPI_RA_REQ_NO_ALLOC_CSN" block="SPI" event="85" descr="Arb cycles with CSn req and no CSn alloc. Source is RA0"></metric>
|
||||
<metric name="SPI_RA_RES_STALL_CSN" block="SPI" event="91" descr="Arb cycles with CSn req and no CSn fits. Source is RA0"></metric>
|
||||
<metric name="SPI_RA_TMP_STALL_CSN" block="SPI" event="97" descr="Cycles where csn wants to req but does not fit in temp space."></metric>
|
||||
<metric name="SPI_RA_WAVE_SIMD_FULL_CSN" block="SPI" event="103" descr="Sum of SIMD where WAVE can't take csn wave when !fits. Source is RA0"></metric>
|
||||
<metric name="SPI_RA_VGPR_SIMD_FULL_CSN" block="SPI" event="109" descr="Sum of SIMD where VGPR can't take csn wave when !fits. Source is RA0"></metric>
|
||||
<metric name="SPI_RA_SGPR_SIMD_FULL_CSN" block="SPI" event="115" descr="Sum of SIMD where SGPR can't take csn wave when !fits. Source is RA0"></metric>
|
||||
<metric name="SPI_RA_LDS_CU_FULL_CSN" block="SPI" event="120" descr="Sum of CU where LDS can't take csn wave when !fits. Source is RA0"></metric>
|
||||
<metric name="SPI_RA_BAR_CU_FULL_CSN" block="SPI" event="123" descr="Sum of CU where BARRIER can't take csn wave when !fits. Source is RA0"></metric>
|
||||
<metric name="SPI_RA_BULKY_CU_FULL_CSN" block="SPI" event="125" descr="Sum of CU where BULKY can't take csn wave when !fits. Source is RA0"></metric>
|
||||
<metric name="SPI_RA_TGLIM_CU_FULL_CSN" block="SPI" event="127" descr="Cycles where csn wants to req but all CU are at tg_limit"></metric>
|
||||
<metric name="SPI_RA_WVLIM_STALL_CSN" block="SPI" event="133" descr="Number of clocks csn is stalled due to WAVE LIMIT."></metric>
|
||||
<metric name="SPI_SWC_CSC_WR" block="SPI" event="189" descr="Number of clocks to write CSC waves to SGPRs (need to multiply this value by 4) Requires SPI_DEBUG_CNTL.DEBUG_PIPE_SEL to select source, DEBUG_PIPE_SEL = 1, source is CS1; DEBUG_PIPE_SEL = 2, source is CS2; DEBUG_PIPE_SEL = 3, source is CS3; default, source is CS0;"></metric>
|
||||
<metric name="SPI_VWC_CSC_WR" block="SPI" event="195" descr="Number of clocks to write CSC waves to VGPRs (need to multiply this value by 4) Requires SPI_DEBUG_CNTL.DEBUG_PIPE_SEL to select source, DEBUG_PIPE_SEL = 1, source is CS1; DEBUG_PIPE_SEL = 2, source is CS2; DEBUG_PIPE_SEL = 3, source is CS3; default, source is CS0;"></metric>
|
||||
<metric name="SQ_ACCUM_PREV" block="SQ" event="1" descr="For counter N, increment by the value of counter N-1. Only accumulates once every 4 cycles."></metric>
|
||||
<metric name="SQ_CYCLES" block="SQ" event="2" descr="Clock cycles. (nondeterministic, per-simd, global)"></metric>
|
||||
<metric name="SQ_BUSY_CYCLES" block="SQ" event="3" descr="Clock cycles while SQ is reporting that it is busy. (nondeterministic, per-simd, global)"></metric>
|
||||
<metric name="SQ_WAVES" block="SQ" event="4" descr="Count number of waves sent to SQs. (per-simd, emulated, global)"></metric>
|
||||
<metric name="SQ_LEVEL_WAVES" block="SQ" event="5" descr="Track the number of waves. Set ACCUM_PREV for the next counter to use this. (level, per-simd, global)"></metric>
|
||||
<metric name="SQ_WAVES_EQ_64" block="SQ" event="6" descr="Count number of waves with exactly 64 active threads sent to SQs. (per-simd, emulated, global)"></metric>
|
||||
<metric name="SQ_WAVES_LT_64" block="SQ" event="7" descr="Count number of waves with smaller than 64 active threads sent to SQs. (per-simd, emulated, global)"></metric>
|
||||
<metric name="SQ_WAVES_LT_48" block="SQ" event="8" descr="Count number of waves with smaller than 48 active threads sent to SQs. (per-simd, emulated, global)"></metric>
|
||||
<metric name="SQ_WAVES_LT_32" block="SQ" event="9" descr="Count number of waves sent smaller than 32 active threads sent to SQs. (per-simd, emulated, global)"></metric>
|
||||
<metric name="SQ_WAVES_LT_16" block="SQ" event="10" descr="Count number of waves sent smaller than 16 active threads sent to SQs. (per-simd, emulated, global)"></metric>
|
||||
<metric name="SQ_BUSY_CU_CYCLES" block="SQ" event="13" descr="Count quad-cycles each CU is busy. (nondeterministic, per-simd)"></metric>
|
||||
<metric name="SQ_ITEMS" block="SQ" event="14" descr="Number of valid items per wave. (per-simd, global)"></metric>
|
||||
<metric name="SQ_INSTS" block="SQ" event="25" descr="Number of instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU" block="SQ" event="26" descr="Number of VALU instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_ADD_F16" block="SQ" event="27" descr="Number of VALU ADD/SUB instructions on float16. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_MUL_F16" block="SQ" event="28" descr="Number of VALU MUL instructions on float16. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_FMA_F16" block="SQ" event="29" descr="Number of VALU FMA/MAD instructions on float16. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_TRANS_F16" block="SQ" event="30" descr="Number of VALU transcendental instructions on float16. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_ADD_F32" block="SQ" event="31" descr="Number of VALU ADD/SUB instructions on float32. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_MUL_F32" block="SQ" event="32" descr="Number of VALU MUL instructions on float32. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_FMA_F32" block="SQ" event="33" descr="Number of VALU FMA/MAD instructions on float32. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_TRANS_F32" block="SQ" event="34" descr="Number of VALU transcendental instructions on float32. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_ADD_F64" block="SQ" event="35" descr="Number of VALU ADD/SUB instructions on float64. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_MUL_F64" block="SQ" event="36" descr="Number of VALU MUL instructions on float64. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_FMA_F64" block="SQ" event="37" descr="Number of VALU FMA/MAD instructions on float64. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_TRANS_F64" block="SQ" event="38" descr="Number of VALU transcendental instructions on float64. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_INT32" block="SQ" event="39" descr="Number of VALU 32-bit integer (signed or unsigned) instructions. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_INT64" block="SQ" event="40" descr="Number of VALU 64-bit integer (signed or unsigned) instructions. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_CVT" block="SQ" event="41" descr="Number of VALU data conversion instructions. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_MFMA_I8" block="SQ" event="42" descr="Number of VALU V_MFMA_*_I8 instructions. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_MFMA_F16" block="SQ" event="43" descr="Number of VALU V_MFMA_*_F16 instructions. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_MFMA_BF16" block="SQ" event="44" descr="Number of VALU V_MFMA_*_BF16 instructions. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_MFMA_F32" block="SQ" event="45" descr="Number of VALU V_MFMA_*_F32 instructions. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_MFMA_F64" block="SQ" event="46" descr="Number of VALU V_MFMA_*_F64 instructions. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_MFMA_MOPS_I8" block="SQ" event="47" descr="Number of VALU matrix math operations (add or mul) performed dividied by 512, assuming a full EXEC mask, of data type I8. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_MFMA_MOPS_F16" block="SQ" event="48" descr="Number of VALU matrix math operations (add or mul) performed dividied by 512, assuming a full EXEC mask, of data type F16. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_MFMA_MOPS_BF16" block="SQ" event="49" descr="Number of VALU matrix math operations (add or mul) performed dividied by 512, assuming a full EXEC mask, of data type BF16. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_MFMA_MOPS_F32" block="SQ" event="50" descr="Number of VALU matrix math operations (add or mul) performed dividied by 512, assuming a full EXEC mask, of data type F32. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_MFMA_MOPS_F64" block="SQ" event="51" descr="Number of VALU matrix math operations (add or mul) performed dividied by 512, assuming a full EXEC mask, of data type F64. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_MFMA" block="SQ" event="52" descr="Number of MFMA instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VMEM_WR" block="SQ" event="53" descr="Number of VMEM write instructions issued (including FLAT). (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VMEM_RD" block="SQ" event="54" descr="Number of VMEM read instructions issued (including FLAT). (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VMEM" block="SQ" event="55" descr="Number of VMEM instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_SALU" block="SQ" event="56" descr="Number of SALU instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_SMEM" block="SQ" event="57" descr="Number of SMEM instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_FLAT" block="SQ" event="58" descr="Number of FLAT instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_FLAT_LDS_ONLY" block="SQ" event="59" descr="Number of FLAT instructions issued that read/wrote only from/to LDS (only works if EARLY_TA_DONE is enabled). (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_LDS" block="SQ" event="60" descr="Number of LDS instructions issued (including FLAT). (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_GDS" block="SQ" event="61" descr="Number of GDS instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_EXP_GDS" block="SQ" event="63" descr="Number of EXP and GDS instructions issued, excluding skipped export instructions. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_BRANCH" block="SQ" event="64" descr="Number of Branch instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_SENDMSG" block="SQ" event="65" descr="Number of Sendmsg instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VSKIPPED" block="SQ" event="66" descr="Number of vector instructions skipped. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INST_LEVEL_VMEM" block="SQ" event="67" descr="Number of in-flight VMEM instructions. Set next counter to ACCUM_PREV and divide by INSTS_VMEM for average latency. Includes FLAT instructions. (per-simd, level, nondeterministic)"></metric>
|
||||
<metric name="SQ_INST_LEVEL_SMEM" block="SQ" event="68" descr="Number of in-flight SMEM instructions (*2 load/store; *2 atomic; *2 memtime; *4 wb/inv). Set next counter to ACCUM_PREV and divide by INSTS_SMEM for average latency per smem request. Falls slightly short of total request latency because some fetches are divided into two requests that may finish at different times and this counter collects the average latency of the two. (per-simd, level, nondeterministic)"></metric>
|
||||
<metric name="SQ_INST_LEVEL_LDS" block="SQ" event="69" descr="Number of in-flight LDS instructions. Set next counter to ACCUM_PREV and divide by INSTS_LDS for average latency. Includes FLAT instructions. (per-simd, level, nondeterministic)"></metric>
|
||||
<metric name="SQ_VALU_MFMA_BUSY_CYCLES" block="SQ" event="72" descr="Number of cycles the MFMA ALU is busy (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_WAVE_CYCLES" block="SQ" event="74" descr="Number of wave-cycles spent by waves in the CUs (per-simd, nondeterministic). Units in quad-cycles(4 cycles)"></metric>
|
||||
<metric name="SQ_WAIT_ANY" block="SQ" event="85" descr="Number of wave-cycles spent waiting for anything (per-simd, nondeterministic). Units in quad-cycles(4 cycles)"></metric>
|
||||
<metric name="SQ_WAIT_INST_ANY" block="SQ" event="88" descr="Number of wave-cycles spent waiting for any instruction issue. In units of 4 cycles. (per-simd, nondeterministic)"></metric>
|
||||
<metric name="SQ_ACTIVE_INST_ANY" block="SQ" event="96" descr="Number of cycles each wave is working on an instruction. (per-simd, emulated). Units in quad-cycles(4 cycles)"></metric>
|
||||
<metric name="SQ_ACTIVE_INST_VMEM" block="SQ" event="97" descr="Number of cycles the SQ instruction arbiter is working on a VMEM instruction. (per-simd, emulated). Units in quad-cycles(4 cycles)"></metric>
|
||||
<metric name="SQ_ACTIVE_INST_LDS" block="SQ" event="98" descr="Number of cycles the SQ instruction arbiter is working on a LDS instruction. (per-simd, emulated). Units in quad-cycles(4 cycles)"></metric>
|
||||
<metric name="SQ_ACTIVE_INST_VALU" block="SQ" event="99" descr="Number of cycles the SQ instruction arbiter is working on a VALU instruction. (per-simd, emulated). Units in quad-cycles(4 cycles)"></metric>
|
||||
<metric name="SQ_ACTIVE_INST_SCA" block="SQ" event="100" descr="Number of cycles the SQ instruction arbiter is working on a SALU or SMEM instruction. (per-simd, emulated). Units in quad-cycles(4 cycles)"></metric>
|
||||
<metric name="SQ_ACTIVE_INST_EXP_GDS" block="SQ" event="101" descr="Number of cycles the SQ instruction arbiter is working on an EXPORT or GDS instruction. (per-simd, emulated). Units in quad-cycles(4 cycles)"></metric>
|
||||
<metric name="SQ_ACTIVE_INST_MISC" block="SQ" event="102" descr="Number of cycles the SQ instruction aribter is working on a BRANCH or SENDMSG instruction. (per-simd, emulated). Units in quad-cycles(4 cycles)"></metric>
|
||||
<metric name="SQ_ACTIVE_INST_FLAT" block="SQ" event="103" descr="Number of cycles the SQ instruction arbiter is working on a FLAT instruction. (per-simd, emulated). Units in quad-cycles(4 cycles)"></metric>
|
||||
<metric name="SQ_INST_CYCLES_VMEM_WR" block="SQ" event="104" descr="Number of cycles needed to send addr and cmd data for VMEM write instructions. (per-simd, emulated). Units in quad-cycles(4 cycles)"></metric>
|
||||
<metric name="SQ_INST_CYCLES_VMEM_RD" block="SQ" event="105" descr="Number of cycles needed to send addr and cmd data for VMEM read instructions. (per-simd, emulated). Units in quad-cycles(4 cycles)"></metric>
|
||||
<metric name="SQ_INST_CYCLES_SMEM" block="SQ" event="111" descr="Number of cycles needed to execute scalar memory reads. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INST_CYCLES_SALU" block="SQ" event="112" descr="Number of cycles needed to execute non-memory read scalar operations. (per-simd, emulated). Units in quad-cycles(4 cycles)"></metric>
|
||||
<metric name="SQ_THREAD_CYCLES_VALU" block="SQ" event="113" descr="Number of thread-cycles used to execute VALU operations (similar to INST_CYCLES_VALU but multiplied by # of active threads). (per-simd)"></metric>
|
||||
<metric name="SQ_IFETCH" block="SQ" event="115" descr="Number of instruction fetch requests from cache. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_IFETCH_LEVEL" block="SQ" event="116" descr="Number of instruction fetch requests from cache. (per-simd, level)"></metric>
|
||||
<metric name="SQ_LDS_BANK_CONFLICT" block="SQ" event="121" descr="Number of cycles LDS is stalled by bank conflicts. (emulated)"></metric>
|
||||
<metric name="SQ_LDS_ADDR_CONFLICT" block="SQ" event="122" descr="Number of cycles LDS is stalled by address conflicts. (emulated,nondeterministic)"></metric>
|
||||
<metric name="SQ_LDS_UNALIGNED_STALL" block="SQ" event="123" descr="Number of cycles LDS is stalled processing flat unaligned load/store ops. (emulated)"></metric>
|
||||
<metric name="SQ_LDS_MEM_VIOLATIONS" block="SQ" event="124" descr="Number of threads that have a memory violation in the LDS.(emulated)"></metric>
|
||||
<metric name="SQ_LDS_ATOMIC_RETURN" block="SQ" event="125" descr="Number of atomic return cycles in LDS. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_LDS_IDX_ACTIVE" block="SQ" event="126" descr="Number of cycles LDS is used for indexed (non-direct,non-interpolation) operations. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_ACCUM_PREV_HIRES" block="SQ" event="185" descr="For counter N, increment by the value of counter N-1."></metric>
|
||||
<metric name="SQ_WAVES_RESTORED" block="SQ" event="186" descr="Count number of context-restored waves sent to SQs. (per-simd, emulated, global)"></metric>
|
||||
<metric name="SQ_WAVES_SAVED" block="SQ" event="187" descr="Count number of context-saved waves. (per-simd, emulated, global)"></metric>
|
||||
<metric name="SQ_INSTS_SMEM_NORM" block="SQ" event="188" descr="Number of SMEM instructions issued normalized to match smem_level (*2 load/store; *2 atomic; *2 memtime; *4 wb/inv). (per-simd, emulated)"></metric>
|
||||
<metric name="SQC_DCACHE_INPUT_VALID_READYB" block="SQ" event="260" descr="Input stalled by SQC (per-SQ, nondeterministic, unwindowed)"></metric>
|
||||
<metric name="SQC_TC_REQ" block="SQ" event="262" descr="Total number of TC requests that were issued by instruction and constant caches. (No-Masking, nondeterministic)"></metric>
|
||||
<metric name="SQC_TC_INST_REQ" block="SQ" event="263" descr="Number of insruction requests to the TC (No-Masking, nondeterministic)"></metric>
|
||||
<metric name="SQC_TC_DATA_READ_REQ" block="SQ" event="264" descr="Number of data read requests to the TC (No-Masking, nondeterministic)"></metric>
|
||||
<metric name="SQC_TC_DATA_WRITE_REQ" block="SQ" event="265" descr="Number of data write requests to the TC (No-Masking, nondeterministic)"></metric>
|
||||
<metric name="SQC_TC_DATA_ATOMIC_REQ" block="SQ" event="266" descr="Number of data atomic requests to the TC (No-Masking, nondeterministic)"></metric>
|
||||
<metric name="SQC_TC_STALL" block="SQ" event="267" descr="Valid request stalled TC request interface (no-credits). (No-Masking, nondeterministic, unwindowed)"></metric>
|
||||
<metric name="SQC_ICACHE_REQ" block="SQ" event="270" descr="Number of requests. (per-SQ, per-Bank)"></metric>
|
||||
<metric name="SQC_ICACHE_HITS" block="SQ" event="271" descr="Number of cache hits. (per-SQ, per-Bank, nondeterministic)"></metric>
|
||||
<metric name="SQC_ICACHE_MISSES" block="SQ" event="272" descr="Number of cache misses, includes uncached requests. (per-SQ, per-Bank, nondeterministic)"></metric>
|
||||
<metric name="SQC_ICACHE_MISSES_DUPLICATE" block="SQ" event="273" descr="Number of misses that were duplicates (access to a non-resident, miss pending CL). (per-SQ, per-Bank, nondeterministic)"></metric>
|
||||
<metric name="SQC_DCACHE_REQ" block="SQ" event="290" descr="Number of requests (post-bank-serialization). (per-SQ, per-Bank)"></metric>
|
||||
<metric name="SQC_DCACHE_HITS" block="SQ" event="291" descr="Number of cache hits. (per-SQ, per-Bank, nondeterministic)"></metric>
|
||||
<metric name="SQC_DCACHE_MISSES" block="SQ" event="292" descr="Number of cache misses, includes uncached requests. (per-SQ, per-Bank, nondeterministic)"></metric>
|
||||
<metric name="SQC_DCACHE_MISSES_DUPLICATE" block="SQ" event="293" descr="Number of misses that were duplicates (access to a non-resident, miss pending CL). (per-SQ, per-Bank, nondeterministic)"></metric>
|
||||
<metric name="SQC_DCACHE_ATOMIC" block="SQ" event="298" descr="Number of atomic requests. (per-SQ, per-Bank)"></metric>
|
||||
<metric name="SQC_DCACHE_REQ_READ_1" block="SQ" event="323" descr="Number of constant cache 1 dw read requests. (per-SQ)"></metric>
|
||||
<metric name="SQC_DCACHE_REQ_READ_2" block="SQ" event="324" descr="Number of constant cache 2 dw read requests. (per-SQ)"></metric>
|
||||
<metric name="SQC_DCACHE_REQ_READ_4" block="SQ" event="325" descr="Number of constant cache 4 dw read requests. (per-SQ)"></metric>
|
||||
<metric name="SQC_DCACHE_REQ_READ_8" block="SQ" event="326" descr="Number of constant cache 8 dw read requests. (per-SQ)"></metric>
|
||||
<metric name="SQC_DCACHE_REQ_READ_16" block="SQ" event="327" descr="Number of constant cache 16 dw read requests. (per-SQ)"></metric>
|
||||
<metric name="TA_TA_BUSY" block="TA" event="15" descr="TA block is busy. Perf_Windowing not supported for this counter."></metric>
|
||||
<metric name="TA_TOTAL_WAVEFRONTS" block="TA" event="32" descr="Total number of wavefronts processed by TA."></metric>
|
||||
<metric name="TA_BUFFER_WAVEFRONTS" block="TA" event="44" descr="Number of buffer wavefronts processed by TA."></metric>
|
||||
<metric name="TA_BUFFER_READ_WAVEFRONTS" block="TA" event="45" descr="Number of buffer read wavefronts processed by TA."></metric>
|
||||
<metric name="TA_BUFFER_WRITE_WAVEFRONTS" block="TA" event="46" descr="Number of buffer write wavefronts processed by TA."></metric>
|
||||
<metric name="TA_BUFFER_ATOMIC_WAVEFRONTS" block="TA" event="47" descr="Number of buffer atomic wavefronts processed by TA."></metric>
|
||||
<metric name="TA_BUFFER_TOTAL_CYCLES" block="TA" event="49" descr="Number of buffer cycles issued to TC."></metric>
|
||||
<metric name="TA_BUFFER_COALESCED_READ_CYCLES" block="TA" event="52" descr="Number of buffer coalesced read cycles issued to TC."></metric>
|
||||
<metric name="TA_BUFFER_COALESCED_WRITE_CYCLES" block="TA" event="53" descr="Number of buffer coalesced write cycles issued to TC."></metric>
|
||||
<metric name="TA_ADDR_STALLED_BY_TC_CYCLES" block="TA" event="54" descr="Number of cycles addr path stalled by TC. Perf_Windowing not supported for this counter."></metric>
|
||||
<metric name="TA_ADDR_STALLED_BY_TD_CYCLES" block="TA" event="55" descr="Number of cycles addr path stalled by TD. Perf_Windowing not supported for this counter."></metric>
|
||||
<metric name="TA_DATA_STALLED_BY_TC_CYCLES" block="TA" event="56" descr="Number of cycles data path stalled by TC. Perf_Windowing not supported for this counter."></metric>
|
||||
<metric name="TA_FLAT_WAVEFRONTS" block="TA" event="100" descr="Number of flat opcode wavfronts processed by the TA."></metric>
|
||||
<metric name="TA_FLAT_READ_WAVEFRONTS" block="TA" event="101" descr="Number of flat opcode reads processed by the TA."></metric>
|
||||
<metric name="TA_FLAT_WRITE_WAVEFRONTS" block="TA" event="102" descr="Number of flat opcode writes processed by the TA."></metric>
|
||||
<metric name="TA_FLAT_ATOMIC_WAVEFRONTS" block="TA" event="103" descr="Number of flat opcode atomics processed by the TA."></metric>
|
||||
<metric name="TD_TD_BUSY" block="TD" event="1" descr="TD is processing or waiting for data. Perf_Windowing not supported for this counter."></metric>
|
||||
<metric name="TD_TC_STALL" block="TD" event="15" descr="TD is stalled waiting for TC data."></metric>
|
||||
<metric name="TD_SPI_STALL" block="TD" event="18" descr="TD is stalled SPI vinit"></metric>
|
||||
<metric name="TD_LOAD_WAVEFRONT" block="TD" event="25" descr="Count the wavefronts with opcode = load, include atomics and store."></metric>
|
||||
<metric name="TD_ATOMIC_WAVEFRONT" block="TD" event="26" descr="Count the wavefronts with opcode = atomic."></metric>
|
||||
<metric name="TD_STORE_WAVEFRONT" block="TD" event="27" descr="Count the wavefronts with opcode = store."></metric>
|
||||
<metric name="TD_COALESCABLE_WAVEFRONT" block="TD" event="32" descr="Count wavefronts that TA finds coalescable."></metric>
|
||||
<metric name="TCP_GATE_EN1" block="TCP" event="0" descr="TCP interface clocks are turned on. Not Windowed."></metric>
|
||||
<metric name="TCP_GATE_EN2" block="TCP" event="1" descr="TCP core clocks are turned on. Not Windowed."></metric>
|
||||
<metric name="TCP_TD_TCP_STALL_CYCLES" block="TCP" event="7" descr="TD stalls TCP"></metric>
|
||||
<metric name="TCP_TCR_TCP_STALL_CYCLES" block="TCP" event="8" descr="TCR stalls TCP_TCR_req interface"></metric>
|
||||
<metric name="TCP_READ_TAGCONFLICT_STALL_CYCLES" block="TCP" event="11" descr="Tagram conflict stall on a read"></metric>
|
||||
<metric name="TCP_WRITE_TAGCONFLICT_STALL_CYCLES" block="TCP" event="12" descr="Tagram conflict stall on a write"></metric>
|
||||
<metric name="TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES" block="TCP" event="13" descr="Tagram conflict stall on an atomic"></metric>
|
||||
<metric name="TCP_PENDING_STALL_CYCLES" block="TCP" event="22" descr="Stall due to data pending from L2"></metric>
|
||||
<metric name="TCP_TA_TCP_STATE_READ" block="TCP" event="27" descr="Number of state reads"></metric>
|
||||
<metric name="TCP_VOLATILE" block="TCP" event="28" descr="Total number of L1 volatile pixels/buffers from TA"></metric>
|
||||
<metric name="TCP_TOTAL_ACCESSES" block="TCP" event="29" descr="Total number of pixels/buffers from TA. Equals TCP_PERF_SEL_TOTAL_READ+TCP_PERF_SEL_TOTAL_NONREAD"></metric>
|
||||
<metric name="TCP_TOTAL_READ" block="TCP" event="30" descr="Total number of read pixels/buffers from TA. Equals TCP_PERF_SEL_TOTAL_HIT_LRU_READ + TCP_PERF_SEL_TOTAL_MISS_LRU_READ + TCP_PERF_SEL_TOTAL_MISS_EVICT_READ"></metric>
|
||||
<metric name="TCP_TOTAL_WRITE" block="TCP" event="32" descr="Total number of local write pixels/buffers from TA. Equals TCP_PERF_SEL_TOTAL_MISS_LRU_WRITE+ TCP_PERF_SEL_TOTAL_MISS_EVICT_WRITE"></metric>
|
||||
<metric name="TCP_TOTAL_ATOMIC_WITH_RET" block="TCP" event="38" descr="Total number of atomic with return pixels/buffers from TA"></metric>
|
||||
<metric name="TCP_TOTAL_ATOMIC_WITHOUT_RET" block="TCP" event="39" descr="Total number of atomic without return pixels/buffers from TA"></metric>
|
||||
<metric name="TCP_TOTAL_WRITEBACK_INVALIDATES" block="TCP" event="45" descr="Total number of cache invalidates. Equals TCP_PERF_SEL_TOTAL_WBINVL1+ TCP_PERF_SEL_TOTAL_WBINVL1_VOL+ TCP_PERF_SEL_CP_TCP_INVALIDATE+ TCP_PERF_SEL_SQ_TCP_INVALIDATE_VOL. Not Windowed."></metric>
|
||||
<metric name="TCP_UTCL1_REQUEST" block="TCP" event="47" descr="Total CLIENT_UTCL1 NORMAL requests"></metric>
|
||||
<metric name="TCP_UTCL1_TRANSLATION_MISS" block="TCP" event="48" descr="Total utcl1 translation misses"></metric>
|
||||
<metric name="TCP_UTCL1_TRANSLATION_HIT" block="TCP" event="49" descr="Total utcl1 translation hits"></metric>
|
||||
<metric name="TCP_UTCL1_PERMISSION_MISS" block="TCP" event="50" descr="Total utcl1 permission misses"></metric>
|
||||
<metric name="TCP_TOTAL_CACHE_ACCESSES" block="TCP" event="60" descr="Count of total cache line (tag) accesses (includes hits and misses)."></metric>
|
||||
<metric name="TCP_TCP_LATENCY" block="TCP" event="65" descr="Total TCP wave latency (from first clock of wave entering to first clock of wave leaving), divide by TA_TCP_STATE_READ to avg wave latency"></metric>
|
||||
<metric name="TCP_TCC_READ_REQ_LATENCY" block="TCP" event="66" descr="Total TCP->TCC request latency for reads and atomics with return. Not Windowed."></metric>
|
||||
<metric name="TCP_TCC_WRITE_REQ_LATENCY" block="TCP" event="67" descr="Total TCP->TCC request latency for writes and atomics without return. Not Windowed."></metric>
|
||||
<metric name="TCP_TCC_READ_REQ" block="TCP" event="69" descr="Total read requests from TCP to all TCCs"></metric>
|
||||
<metric name="TCP_TCC_WRITE_REQ" block="TCP" event="70" descr="Total write requests from TCP to all TCCs"></metric>
|
||||
<metric name="TCP_TCC_ATOMIC_WITH_RET_REQ" block="TCP" event="71" descr="Total atomic with return requests from TCP to all TCCs"></metric>
|
||||
<metric name="TCP_TCC_ATOMIC_WITHOUT_RET_REQ" block="TCP" event="72" descr="Total atomic without return requests from TCP to all TCCs"></metric>
|
||||
<metric name="TCP_TCC_NC_READ_REQ" block="TCP" event="75" descr="Total read requests with NC mtype from this TCP to all TCCs"></metric>
|
||||
<metric name="TCP_TCC_NC_WRITE_REQ" block="TCP" event="76" descr="Total write requests with NC mtype from this TCP to all TCCs"></metric>
|
||||
<metric name="TCP_TCC_NC_ATOMIC_REQ" block="TCP" event="77" descr="Total atomic requests with NC mtype from this TCP to all TCCs"></metric>
|
||||
<metric name="TCP_TCC_UC_READ_REQ" block="TCP" event="78" descr="Total read requests with UC mtype from this TCP to all TCCs"></metric>
|
||||
<metric name="TCP_TCC_UC_WRITE_REQ" block="TCP" event="79" descr="Total write requests with UC mtype from this TCP to all TCCs"></metric>
|
||||
<metric name="TCP_TCC_UC_ATOMIC_REQ" block="TCP" event="80" descr="Total atomic requests with UC mtype from this TCP to all TCCs"></metric>
|
||||
<metric name="TCP_TCC_CC_READ_REQ" block="TCP" event="81" descr="Total write requests with CC mtype from this TCP to all TCCs"></metric>
|
||||
<metric name="TCP_TCC_CC_WRITE_REQ" block="TCP" event="82" descr="Total write requests with CC mtype from this TCP to all TCCs"></metric>
|
||||
<metric name="TCP_TCC_CC_ATOMIC_REQ" block="TCP" event="83" descr="Total atomic requests with CC mtype from this TCP to all TCCs"></metric>
|
||||
<metric name="TCP_TCC_RW_READ_REQ" block="TCP" event="85" descr="Total write requests with RW mtype from this TCP to all TCCs"></metric>
|
||||
<metric name="TCP_TCC_RW_WRITE_REQ" block="TCP" event="86" descr="Total write requests with RW mtype from this TCP to all TCCs"></metric>
|
||||
<metric name="TCP_TCC_RW_ATOMIC_REQ" block="TCP" event="87" descr="Total atomic requests with RW mtype from this TCP to all TCCs"></metric>
|
||||
<metric name="TCA_CYCLE" block="TCA" event="1" descr="Number of cycles. Not windowable."></metric>
|
||||
<metric name="TCA_BUSY" block="TCA" event="2" descr="Number of cycles we have a request pending. Not windowable."></metric>
|
||||
<metric name="TCC_CYCLE" block="TCC" event="1" descr="Number of cycles. Not windowable."></metric>
|
||||
<metric name="TCC_BUSY" block="TCC" event="2" descr="Number of cycles we have a request pending. Not windowable."></metric>
|
||||
<metric name="TCC_REQ" block="TCC" event="3" descr="Number of requests of all types. This is measured at the tag block. This may be more than the number of requests arriving at the TCC, but it is a good indication of the total amount of work that needs to be performed."></metric>
|
||||
<metric name="TCC_STREAMING_REQ" block="TCC" event="4" descr="Number of streaming requests. This is measured at the tag block."></metric>
|
||||
<metric name="TCC_NC_REQ" block="TCC" event="5" descr="The number of noncoherently cached requests. This is measured at the tag block."></metric>
|
||||
<metric name="TCC_UC_REQ" block="TCC" event="6" descr="The number of uncached requests. This is measured at the tag block."></metric>
|
||||
<metric name="TCC_CC_REQ" block="TCC" event="7" descr="The number of coherently cached requests. This is measured at the tag block."></metric>
|
||||
<metric name="TCC_RW_REQ" block="TCC" event="8" descr="The number of RW requests. This is measured at the tag block."></metric>
|
||||
<metric name="TCC_PROBE" block="TCC" event="9" descr="Number of probe requests. Not windowable."></metric>
|
||||
<metric name="TCC_PROBE_ALL" block="TCC" event="10" descr="Number of external probe requests with with EA_TCC_preq_all== 1. Not windowable."></metric>
|
||||
<metric name="TCC_READ" block="TCC" event="12" descr="Number of read requests. Compressed reads are included in this, but metadata reads are not included."></metric>
|
||||
<metric name="TCC_WRITE" block="TCC" event="13" descr="Number of write requests."></metric>
|
||||
<metric name="TCC_ATOMIC" block="TCC" event="14" descr="Number of atomic requests of all types."></metric>
|
||||
<metric name="TCC_HIT" block="TCC" event="17" descr="Number of cache hits."></metric>
|
||||
<metric name="TCC_MISS" block="TCC" event="19" descr="Number of cache misses. UC reads count as misses."></metric>
|
||||
<metric name="TCC_WRITEBACK" block="TCC" event="22" descr="Number of lines written back to main memory. This includes writebacks of dirty lines and uncached write/atomic requests."></metric>
|
||||
<metric name="TCC_EA_WRREQ" block="TCC" event="26" descr="Number of transactions (either 32-byte or 64-byte) going over the TC_EA_wrreq interface. Atomics may travel over the same interface and are generally classified as write requests. This does not include probe commands."></metric>
|
||||
<metric name="TCC_EA_WRREQ_64B" block="TCC" event="27" descr="Number of 64-byte transactions going (64-byte write or CMPSWAP) over the TC_EA_wrreq interface."></metric>
|
||||
<metric name="TCC_EA_WR_UNCACHED_32B" block="TCC" event="29" descr="Number of 32-byte write/atomic going over the TC_EA_wrreq interface due to uncached traffic. Note that CC mtypes can produce uncached requests, and those are included in this. A 64-byte request will be counted as 2"></metric>
|
||||
<metric name="TCC_EA_WRREQ_STALL" block="TCC" event="30" descr="Number of cycles a write request was stalled."></metric>
|
||||
<metric name="TCC_EA_WRREQ_IO_CREDIT_STALL" block="TCC" event="31" descr="Number of cycles a EA write request was stalled because the interface was out of IO credits."></metric>
|
||||
<metric name="TCC_EA_WRREQ_GMI_CREDIT_STALL" block="TCC" event="32" descr="Number of cycles a EA write request was stalled because the interface was out of GMI credits."></metric>
|
||||
<metric name="TCC_EA_WRREQ_DRAM_CREDIT_STALL" block="TCC" event="33" descr="Number of cycles a EA write request was stalled because the interface was out of DRAM credits."></metric>
|
||||
<metric name="TCC_TOO_MANY_EA_WRREQS_STALL" block="TCC" event="34" descr="Number of cycles the TCC could not send a EA write request because it already reached its maximum number of pending EA write requests."></metric>
|
||||
<metric name="TCC_EA_WRREQ_LEVEL" block="TCC" event="35" descr="The sum of the number of EA write requests in flight. This is primarily meant for measure average EA write latency. Average write latency = TCC_PERF_SEL_EA_WRREQ_LEVEL/TCC_PERF_SEL_EA_WRREQ."></metric>
|
||||
<metric name="TCC_EA_ATOMIC" block="TCC" event="36" descr="Number of transactions going over the TC_EA_wrreq interface that are actually atomic requests."></metric>
|
||||
<metric name="TCC_EA_ATOMIC_LEVEL" block="TCC" event="37" descr="The sum of the number of EA atomics in flight. This is primarily meant for measure average EA atomic latency. Average atomic latency = TCC_PERF_SEL_EA_WRREQ_ATOMIC_LEVEL/TCC_PERF_SEL_EA_WRREQ_ATOMIC."></metric>
|
||||
<metric name="TCC_EA_RDREQ" block="TCC" event="38" descr="Number of TCC/EA read requests (either 32-byte or 64-byte)"></metric>
|
||||
<metric name="TCC_EA_RDREQ_32B" block="TCC" event="39" descr="Number of 32-byte TCC/EA read requests"></metric>
|
||||
<metric name="TCC_EA_RD_UNCACHED_32B" block="TCC" event="40" descr="Number of 32-byte TCC/EA read due to uncached traffic. A 64-byte request will be counted as 2"></metric>
|
||||
<metric name="TCC_EA_RDREQ_IO_CREDIT_STALL" block="TCC" event="41" descr="Number of cycles there was a stall because the read request interface was out of IO credits. Stalls occur regardless of whether a read needed to be performed or not."></metric>
|
||||
<metric name="TCC_EA_RDREQ_GMI_CREDIT_STALL" block="TCC" event="42" descr="Number of cycles there was a stall because the read request interface was out of GMI credits. Stalls occur regardless of whether a read needed to be performed or not."></metric>
|
||||
<metric name="TCC_EA_RDREQ_DRAM_CREDIT_STALL" block="TCC" event="43" descr="Number of cycles there was a stall because the read request interface was out of DRAM credits. Stalls occur regardless of whether a read needed to be performed or not."></metric>
|
||||
<metric name="TCC_EA_RDREQ_LEVEL" block="TCC" event="44" descr="The sum of the number of TCC/EA read requests in flight. This is primarily meant for measure average EA read latency. Average read latency = TCC_PERF_SEL_EA_RDREQ_LEVEL/TCC_PERF_SEL_EA_RDREQ."></metric>
|
||||
<metric name="TCC_TAG_STALL" block="TCC" event="45" descr="Number of cycles the normal request pipeline in the tag was stalled for any reason. Normally, stalls of this nature are measured exactly from one point the pipeline, but that is not the case for this counter. Probes can stall the pipeline at a variety of places, and there is no single point that can reasonably measure the total stalls accurately."></metric>
|
||||
<metric name="TCC_NORMAL_WRITEBACK" block="TCC" event="68" descr="Number of writebacks due to requests that are not writeback requests."></metric>
|
||||
<metric name="TCC_ALL_TC_OP_WB_WRITEBACK" block="TCC" event="73" descr="Number of writebacks due to all TC_OP writeback requests."></metric>
|
||||
<metric name="TCC_NORMAL_EVICT" block="TCC" event="74" descr="Number of evictions due to requests that are not invalidate or probe requests."></metric>
|
||||
<metric name="TCC_ALL_TC_OP_INV_EVICT" block="TCC" event="80" descr="Number of evictions due to all TC_OP invalidate requests."></metric>
|
||||
<metric name="TCC_EA_RDREQ_DRAM" block="TCC" event="102" descr="Number of TCC/EA read requests (either 32-byte or 64-byte) destined for DRAM (MC)."></metric>
|
||||
<metric name="TCC_EA_WRREQ_DRAM" block="TCC" event="103" descr="Number of TCC/EA write requests (either 32-byte of 64-byte) destined for DRAM (MC)."></metric>
|
||||
</gfx90a>
|
||||
|
||||
<gfx940>
|
||||
<metric name="SQ_WAIT_INST_LDS" block="SQ" event="96" descr="Number of quad-cycles spent waiting for LDS instruction issue. (per-simd, nondeterministic)"></metric>
|
||||
<metric name="TCP_TCP_TA_DATA_STALL_CYCLES" block="TCP" event="6" descr="TCP stalls TA data interface. Not Windowed."></metric>
|
||||
<metric name="GRBM_COUNT" block="GRBM" event="0" descr="Tie High"></metric>
|
||||
<metric name="GRBM_GUI_ACTIVE" block="GRBM" event="2" descr="The GUI is Active"></metric>
|
||||
<metric name="GRBM_CP_BUSY" block="GRBM" event="3" descr="Any of the Command Processor (CPG/CPC/CPF) blocks are busy."></metric>
|
||||
<metric name="GRBM_SPI_BUSY" block="GRBM" event="11" descr="Any of the Shader Pipe Interpolators (SPI) are busy in the shader engine(s)."></metric>
|
||||
<metric name="GRBM_TA_BUSY" block="GRBM" event="13" descr="Any of the Texture Pipes (TA) are busy in the shader engine(s)."></metric>
|
||||
<metric name="GRBM_TC_BUSY" block="GRBM" event="28" descr="Any of the Texture Cache Blocks (TCP/TCI/TCA/TCC) are busy."></metric>
|
||||
<metric name="GRBM_CPC_BUSY" block="GRBM" event="30" descr="The Command Processor Compute (CPC) is busy."></metric>
|
||||
<metric name="GRBM_CPF_BUSY" block="GRBM" event="31" descr="The Command Processor Fetchers (CPF) is busy."></metric>
|
||||
<metric name="GRBM_UTCL2_BUSY" block="GRBM" event="34" descr="The Unified Translation Cache Level-2 (UTCL2) block is busy."></metric>
|
||||
<metric name="GRBM_EA_BUSY" block="GRBM" event="35" descr="The Efficiency Arbiter (EA) block is busy."></metric>
|
||||
<metric name="CPC_ME1_BUSY_FOR_PACKET_DECODE" block="CPC" event="13" descr="Me1 busy for packet decode."></metric>
|
||||
<metric name="CPC_UTCL1_STALL_ON_TRANSLATION" block="CPC" event="24" descr="One of the UTCL1s is stalled waiting on translation, XNACK or PENDING response."></metric>
|
||||
<metric name="CPC_CPC_STAT_BUSY" block="CPC" event="25" descr="CPC Busy."></metric>
|
||||
<metric name="CPC_CPC_STAT_IDLE" block="CPC" event="26" descr="CPC Idle."></metric>
|
||||
<metric name="CPC_CPC_STAT_STALL" block="CPC" event="27" descr="CPC Stalled."></metric>
|
||||
<metric name="CPC_CPC_TCIU_BUSY" block="CPC" event="28" descr="CPC TCIU interface Busy."></metric>
|
||||
<metric name="CPC_CPC_TCIU_IDLE" block="CPC" event="29" descr="CPC TCIU interface Idle."></metric>
|
||||
<metric name="CPC_CPC_UTCL2IU_BUSY" block="CPC" event="30" descr="CPC UTCL2 interface Busy."></metric>
|
||||
<metric name="CPC_CPC_UTCL2IU_IDLE" block="CPC" event="31" descr="CPC UTCL2 interface Idle."></metric>
|
||||
<metric name="CPC_CPC_UTCL2IU_STALL" block="CPC" event="32" descr="CPC UTCL2 interface Stalled waiting on Free, Tags or Translation."></metric>
|
||||
<metric name="CPC_ME1_DC0_SPI_BUSY" block="CPC" event="33" descr="CPC Me1 Processor Busy."></metric>
|
||||
<metric name="CPF_CMP_UTCL1_STALL_ON_TRANSLATION" block="CPF" event="20" descr="One of the Compute UTCL1s is stalled waiting on translation, XNACK or PENDING response."></metric>
|
||||
<metric name="CPF_CPF_STAT_BUSY" block="CPF" event="23" descr="CPF Busy."></metric>
|
||||
<metric name="CPF_CPF_STAT_IDLE" block="CPF" event="24" descr="CPF Idle."></metric>
|
||||
<metric name="CPF_CPF_STAT_STALL" block="CPF" event="25" descr="CPF Stalled."></metric>
|
||||
<metric name="CPF_CPF_TCIU_BUSY" block="CPF" event="26" descr="CPF TCIU interface Busy."></metric>
|
||||
<metric name="CPF_CPF_TCIU_IDLE" block="CPF" event="27" descr="CPF TCIU interface Idle."></metric>
|
||||
<metric name="CPF_CPF_TCIU_STALL" block="CPF" event="28" descr="CPF TCIU interface Stalled waiting on Free, Tags."></metric>
|
||||
<metric name="SPI_CSN_WINDOW_VALID" block="SPI" event="47" descr="Clock count enabled by perfcounter_start event. Requires SPI_DEBUG_CNTL.DEBUG_PIPE_SEL to select source, DEBUG_PIPE_SEL = 1, source is CS1; DEBUG_PIPE_SEL = 2, source is CS2; DEBUG_PIPE_SEL = 3, source is CS3; default, source is CS0;"></metric>
|
||||
<metric name="SPI_CSN_BUSY" block="SPI" event="48" descr="Number of clocks with outstanding waves (SPI or SH). Requires SPI_DEBUG_CNTL.DEBUG_PIPE_SEL to select source, DEBUG_PIPE_SEL = 1, source is CS1; DEBUG_PIPE_SEL = 2, source is CS2; DEBUG_PIPE_SEL = 3, source is CS3; default, source is CS0;"></metric>
|
||||
<metric name="SPI_CSN_NUM_THREADGROUPS" block="SPI" event="49" descr="Number of threadgroups launched. Requires SPI_DEBUG_CNTL.DEBUG_PIPE_SEL to select source, DEBUG_PIPE_SEL = 1, source is CS1; DEBUG_PIPE_SEL = 2, source is CS2; DEBUG_PIPE_SEL = 3, source is CS3; default, source is CS0;"></metric>
|
||||
<metric name="SPI_CSN_WAVE" block="SPI" event="52" descr="Number of waves. Requires SPI_DEBUG_CNTL.DEBUG_PIPE_SEL to select source, DEBUG_PIPE_SEL = 1, source is CS1; DEBUG_PIPE_SEL = 2, source is CS2; DEBUG_PIPE_SEL = 3, source is CS3; default, source is CS0;"></metric>
|
||||
<metric name="SPI_RA_REQ_NO_ALLOC" block="SPI" event="79" descr="Arb cycles with requests but no allocation. Source is RA0"></metric>
|
||||
<metric name="SPI_RA_REQ_NO_ALLOC_CSN" block="SPI" event="85" descr="Arb cycles with CSn req and no CSn alloc. Source is RA0"></metric>
|
||||
<metric name="SPI_RA_RES_STALL_CSN" block="SPI" event="91" descr="Arb cycles with CSn req and no CSn fits. Source is RA0"></metric>
|
||||
<metric name="SPI_RA_TMP_STALL_CSN" block="SPI" event="97" descr="Cycles where csn wants to req but does not fit in temp space."></metric>
|
||||
<metric name="SPI_RA_WAVE_SIMD_FULL_CSN" block="SPI" event="103" descr="Sum of SIMD where WAVE can't take csn wave when !fits. Source is RA0"></metric>
|
||||
<metric name="SPI_RA_VGPR_SIMD_FULL_CSN" block="SPI" event="109" descr="Sum of SIMD where VGPR can't take csn wave when !fits. Source is RA0"></metric>
|
||||
<metric name="SPI_RA_SGPR_SIMD_FULL_CSN" block="SPI" event="115" descr="Sum of SIMD where SGPR can't take csn wave when !fits. Source is RA0"></metric>
|
||||
<metric name="SPI_RA_LDS_CU_FULL_CSN" block="SPI" event="120" descr="Sum of CU where LDS can't take csn wave when !fits. Source is RA0"></metric>
|
||||
<metric name="SPI_RA_BAR_CU_FULL_CSN" block="SPI" event="123" descr="Sum of CU where BARRIER can't take csn wave when !fits. Source is RA0"></metric>
|
||||
<metric name="SPI_RA_BULKY_CU_FULL_CSN" block="SPI" event="125" descr="Sum of CU where BULKY can't take csn wave when !fits. Source is RA0"></metric>
|
||||
<metric name="SPI_RA_TGLIM_CU_FULL_CSN" block="SPI" event="127" descr="Cycles where csn wants to req but all CU are at tg_limit"></metric>
|
||||
<metric name="SPI_RA_WVLIM_STALL_CSN" block="SPI" event="133" descr="Number of clocks csn is stalled due to WAVE LIMIT."></metric>
|
||||
<metric name="SPI_SWC_CSC_WR" block="SPI" event="189" descr="Number of clocks to write CSC waves to SGPRs (need to multiply this value by 4) Requires SPI_DEBUG_CNTL.DEBUG_PIPE_SEL to select source, DEBUG_PIPE_SEL = 1, source is CS1; DEBUG_PIPE_SEL = 2, source is CS2; DEBUG_PIPE_SEL = 3, source is CS3; default, source is CS0;"></metric>
|
||||
<metric name="SPI_VWC_CSC_WR" block="SPI" event="195" descr="Number of clocks to write CSC waves to VGPRs (need to multiply this value by 4) Requires SPI_DEBUG_CNTL.DEBUG_PIPE_SEL to select source, DEBUG_PIPE_SEL = 1, source is CS1; DEBUG_PIPE_SEL = 2, source is CS2; DEBUG_PIPE_SEL = 3, source is CS3; default, source is CS0;"></metric>
|
||||
<metric name="SQ_ACCUM_PREV" block="SQ" event="1" descr="For counter N, increment by the value of counter N-1. Only accumulates once every 4 cycles."></metric>
|
||||
<metric name="SQ_CYCLES" block="SQ" event="2" descr="Clock cycles. (nondeterministic, per-simd, global)"></metric>
|
||||
<metric name="SQ_BUSY_CYCLES" block="SQ" event="3" descr="Clock cycles while SQ is reporting that it is busy. (nondeterministic, per-simd, global)"></metric>
|
||||
<metric name="SQ_WAVES" block="SQ" event="4" descr="Count number of waves sent to SQs. (per-simd, emulated, global)"></metric>
|
||||
<metric name="SQ_LEVEL_WAVES" block="SQ" event="5" descr="Track the number of waves. Set ACCUM_PREV for the next counter to use this. (level, per-simd, global)"></metric>
|
||||
<metric name="SQ_WAVES_EQ_64" block="SQ" event="6" descr="Count number of waves with exactly 64 active threads sent to SQs. (per-simd, emulated, global)"></metric>
|
||||
<metric name="SQ_WAVES_LT_64" block="SQ" event="7" descr="Count number of waves with <64 active threads sent to SQs. (per-simd, emulated, global)"></metric>
|
||||
<metric name="SQ_WAVES_LT_48" block="SQ" event="8" descr="Count number of waves with <48 active threads sent to SQs. (per-simd, emulated, global)"></metric>
|
||||
<metric name="SQ_WAVES_LT_32" block="SQ" event="9" descr="Count number of waves sent <32 active threads sent to SQs. (per-simd, emulated, global)"></metric>
|
||||
<metric name="SQ_WAVES_LT_16" block="SQ" event="10" descr="Count number of waves sent <16 active threads sent to SQs. (per-simd, emulated, global)"></metric>
|
||||
<metric name="SQ_BUSY_CU_CYCLES" block="SQ" event="13" descr="Count quad-cycles each CU is busy. (nondeterministic, per-simd)"></metric>
|
||||
<metric name="SQ_ITEMS" block="SQ" event="14" descr="Number of valid items per wave. (per-simd, global)"></metric>
|
||||
<metric name="SQ_INSTS" block="SQ" event="25" descr="Number of instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU" block="SQ" event="26" descr="Number of VALU instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_ADD_F16" block="SQ" event="27" descr="Number of VALU ADD/SUB instructions on float16. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_MUL_F16" block="SQ" event="28" descr="Number of VALU MUL instructions on float16. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_FMA_F16" block="SQ" event="29" descr="Number of VALU FMA/MAD instructions on float16. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_TRANS_F16" block="SQ" event="30" descr="Number of VALU transcendental instructions on float16. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_ADD_F32" block="SQ" event="31" descr="Number of VALU ADD/SUB instructions on float32. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_MUL_F32" block="SQ" event="32" descr="Number of VALU MUL instructions on float32. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_FMA_F32" block="SQ" event="33" descr="Number of VALU FMA/MAD instructions on float32. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_TRANS_F32" block="SQ" event="34" descr="Number of VALU transcendental instructions on float32. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_ADD_F64" block="SQ" event="35" descr="Number of VALU ADD/SUB instructions on float64. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_MUL_F64" block="SQ" event="36" descr="Number of VALU MUL instructions on float64. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_FMA_F64" block="SQ" event="37" descr="Number of VALU FMA/MAD instructions on float64. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_TRANS_F64" block="SQ" event="38" descr="Number of VALU transcendental instructions on float64. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_INT32" block="SQ" event="39" descr="Number of VALU 32-bit integer (signed or unsigned) instructions. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_INT64" block="SQ" event="40" descr="Number of VALU 64-bit integer (signed or unsigned) instructions. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_CVT" block="SQ" event="41" descr="Number of VALU data conversion instructions. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_MFMA_I8" block="SQ" event="42" descr="Number of VALU V_MFMA_*_I8 instructions. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_MFMA_F16" block="SQ" event="43" descr="Number of VALU V_MFMA_*_F16 instructions. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_MFMA_BF16" block="SQ" event="44" descr="Number of VALU V_MFMA_*_BF16 instructions. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_MFMA_F32" block="SQ" event="45" descr="Number of VALU V_MFMA_*_F32 instructions. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_MFMA_F64" block="SQ" event="46" descr="Number of VALU V_MFMA_*_F64 instructions. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_MFMA_MOPS_I8" block="SQ" event="49" descr="Number of VALU matrix math operations (add or mul) performed dividied by 512, assuming a full EXEC mask, of data type I8. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_MFMA_MOPS_F16" block="SQ" event="50" descr="Number of VALU matrix math operations (add or mul) performed dividied by 512, assuming a full EXEC mask, of data type F16. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_MFMA_MOPS_BF16" block="SQ" event="51" descr="Number of VALU matrix math operations (add or mul) performed dividied by 512, assuming a full EXEC mask, of data type BF16. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_MFMA_MOPS_F32" block="SQ" event="52" descr="Number of VALU matrix math operations (add or mul) performed dividied by 512, assuming a full EXEC mask, of data type F32. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_MFMA_MOPS_F64" block="SQ" event="53" descr="Number of VALU matrix math operations (add or mul) performed dividied by 512, assuming a full EXEC mask, of data type F64. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_MFMA" block="SQ" event="56" descr="Number of MFMA instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VMEM_WR" block="SQ" event="57" descr="Number of VMEM write instructions issued (including FLAT). (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VMEM_RD" block="SQ" event="58" descr="Number of VMEM read instructions issued (including FLAT). (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VMEM" block="SQ" event="59" descr="Number of VMEM instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_SALU" block="SQ" event="60" descr="Number of SALU instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_SMEM" block="SQ" event="61" descr="Number of SMEM instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_FLAT" block="SQ" event="62" descr="Number of FLAT instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_LDS" block="SQ" event="65" descr="Number of LDS instructions issued (not including FLAT). (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_GDS" block="SQ" event="66" descr="Number of GDS instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_EXP_GDS" block="SQ" event="68" descr="Number of EXP and GDS instructions issued, excluding skipped export instructions. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_BRANCH" block="SQ" event="69" descr="Number of Branch instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_SENDMSG" block="SQ" event="70" descr="Number of Sendmsg instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VSKIPPED" block="SQ" event="71" descr="Number of vector instructions skipped. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INST_LEVEL_VMEM" block="SQ" event="72" descr="Number of in-flight VMEM instructions. Set next counter to ACCUM_PREV and divide by INSTS_VMEM for average latency. Includes FLAT instructions. (per-simd, level, nondeterministic)"></metric>
|
||||
<metric name="SQ_INST_LEVEL_SMEM" block="SQ" event="73" descr="Number of in-flight SMEM instructions (*2 load/store; *2 atomic; *2 memtime; *4 wb/inv). Set next counter to ACCUM_PREV and divide by INSTS_SMEM for average latency per smem request. Falls slightly short of total request latency because some fetches are divided into two requests that may finish at different times and this counter collects the average latency of the two. (per-simd, level, nondeterministic)"></metric>
|
||||
<metric name="SQ_INST_LEVEL_LDS" block="SQ" event="74" descr="Number of in-flight LDS instructions. Set next counter to ACCUM_PREV and divide by INSTS_LDS for average latency. Includes FLAT instructions. (per-simd, level, nondeterministic)"></metric>
|
||||
<metric name="SQ_VALU_MFMA_BUSY_CYCLES" block="SQ" event="77" descr="Number of cycles the MFMA ALU is busy (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_WAVE_CYCLES" block="SQ" event="79" descr="Number of quad-cycles spent by waves in the CUs. (per-simd, nondeterministic)"></metric>
|
||||
<metric name="SQ_WAIT_ANY" block="SQ" event="90" descr="Number of quad-cycles spent waiting for anything. (per-simd, nondeterministic)"></metric>
|
||||
<metric name="SQ_WAIT_INST_ANY" block="SQ" event="93" descr="Number of quad-cycles spent waiting for any instruction issue. (per-simd, nondeterministic)"></metric>
|
||||
<metric name="SQ_ACTIVE_INST_ANY" block="SQ" event="101" descr="Number of quad-cycles each wave is working on an instruction. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_ACTIVE_INST_VMEM" block="SQ" event="102" descr="Number of quad-cycles the SQ instruction arbiter is working on a VMEM instruction. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_ACTIVE_INST_LDS" block="SQ" event="103" descr="Number of quad-cycles the SQ instruction arbiter is working on a LDS instruction. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_ACTIVE_INST_VALU" block="SQ" event="104" descr="Number of quad-cycles the SQ instruction arbiter is working on a VALU instruction. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_ACTIVE_INST_SCA" block="SQ" event="105" descr="Number of quad-cycles the SQ instruction arbiter is working on a SALU or SMEM instruction. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_ACTIVE_INST_EXP_GDS" block="SQ" event="106" descr="Number of quad-cycles the SQ instruction arbiter is working on an EXPORT or GDS instruction. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_ACTIVE_INST_MISC" block="SQ" event="107" descr="Number of quad-cycles the SQ instruction aribter is working on a BRANCH or SENDMSG instruction. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_ACTIVE_INST_FLAT" block="SQ" event="108" descr="Number of quad-cycles the SQ instruction arbiter is working on a FLAT instruction. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INST_CYCLES_VMEM_WR" block="SQ" event="109" descr="Number of quad-cycles needed to send addr and cmd data for VMEM write instructions. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INST_CYCLES_VMEM_RD" block="SQ" event="110" descr="Number of quad-cycles needed to send addr and cmd data for VMEM read instructions. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INST_CYCLES_SMEM" block="SQ" event="116" descr="Number of quad-cycles needed to execute scalar memory reads. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INST_CYCLES_SALU" block="SQ" event="117" descr="Number of quad-cycles needed to execute non-memory read scalar operations. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_THREAD_CYCLES_VALU" block="SQ" event="118" descr="Number of quad-cycles VALU is in used times number of active threads. (per-simd)"></metric>
|
||||
<metric name="SQ_IFETCH" block="SQ" event="120" descr="Number of instruction fetch requests from cache. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_IFETCH_LEVEL" block="SQ" event="121" descr="Number of instruction fetch requests from cache. (per-simd, level)"></metric>
|
||||
<metric name="SQ_LDS_BANK_CONFLICT" block="SQ" event="126" descr="Number of cycles LDS is stalled by bank conflicts. (emulated)"></metric>
|
||||
<metric name="SQ_LDS_ADDR_CONFLICT" block="SQ" event="127" descr="Number of cycles LDS is stalled by address conflicts. (emulated,nondeterministic)"></metric>
|
||||
<metric name="SQ_LDS_UNALIGNED_STALL" block="SQ" event="128" descr="Number of cycles LDS is stalled processing flat unaligned load/store ops. (emulated)"></metric>
|
||||
<metric name="SQ_LDS_MEM_VIOLATIONS" block="SQ" event="129" descr="Number of threads that have a memory violation in the LDS.(emulated)"></metric>
|
||||
<metric name="SQ_LDS_ATOMIC_RETURN" block="SQ" event="130" descr="Number of atomic return cycles in LDS. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_LDS_IDX_ACTIVE" block="SQ" event="131" descr="Number of cycles LDS is used for indexed (non-direct,non-interpolation) operations. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_ACCUM_PREV_HIRES" block="SQ" event="184" descr="For counter N, increment by the value of counter N-1."></metric>
|
||||
<metric name="SQ_WAVES_RESTORED" block="SQ" event="185" descr="Count number of context-restored waves sent to SQs. (per-simd, emulated, global)"></metric>
|
||||
<metric name="SQ_WAVES_SAVED" block="SQ" event="186" descr="Count number of context-saved waves. (per-simd, emulated, global)"></metric>
|
||||
<metric name="SQ_INSTS_SMEM_NORM" block="SQ" event="187" descr="Number of SMEM instructions issued normalized to match smem_level (*2 load/store; *2 atomic; *2 memtime; *4 wb/inv). (per-simd, emulated)"></metric>
|
||||
<metric name="SQC_DCACHE_INPUT_VALID_READYB" block="SQ" event="260" descr="Input stalled by SQC (per-SQ, nondeterministic, unwindowed)"></metric>
|
||||
<metric name="SQC_TC_REQ" block="SQ" event="262" descr="Total number of TC requests that were issued by instruction and constant caches. (No-Masking, nondeterministic)"></metric>
|
||||
<metric name="SQC_TC_INST_REQ" block="SQ" event="263" descr="Number of insruction requests to the TC (No-Masking, nondeterministic)"></metric>
|
||||
<metric name="SQC_TC_DATA_READ_REQ" block="SQ" event="264" descr="Number of data read requests to the TC (No-Masking, nondeterministic)"></metric>
|
||||
<metric name="SQC_TC_DATA_WRITE_REQ" block="SQ" event="265" descr="Number of data write requests to the TC (No-Masking, nondeterministic)"></metric>
|
||||
<metric name="SQC_TC_DATA_ATOMIC_REQ" block="SQ" event="266" descr="Number of data atomic requests to the TC (No-Masking, nondeterministic)"></metric>
|
||||
<metric name="SQC_TC_STALL" block="SQ" event="267" descr="Valid request stalled TC request interface (no-credits). (No-Masking, nondeterministic, unwindowed)"></metric>
|
||||
<metric name="SQC_ICACHE_REQ" block="SQ" event="270" descr="Number of requests. (per-SQ, per-Bank)"></metric>
|
||||
<metric name="SQC_ICACHE_HITS" block="SQ" event="271" descr="Number of cache hits. (per-SQ, per-Bank, nondeterministic)"></metric>
|
||||
<metric name="SQC_ICACHE_MISSES" block="SQ" event="272" descr="Number of cache misses, includes uncached requests. (per-SQ, per-Bank, nondeterministic)"></metric>
|
||||
<metric name="SQC_ICACHE_MISSES_DUPLICATE" block="SQ" event="273" descr="Number of misses that were duplicates (access to a non-resident, miss pending CL). (per-SQ, per-Bank, nondeterministic)" ></metric>
|
||||
<metric name="SQC_DCACHE_REQ" block="SQ" event="290" descr="Number of requests (post-bank-serialization). (per-SQ, per-Bank)"></metric>
|
||||
<metric name="SQC_DCACHE_HITS" block="SQ" event="291" descr="Number of cache hits. (per-SQ, per-Bank, nondeterministic)"></metric>
|
||||
<metric name="SQC_DCACHE_MISSES" block="SQ" event="292" descr="Number of cache misses, includes uncached requests. (per-SQ, per-Bank, nondeterministic)"></metric>
|
||||
<metric name="SQC_DCACHE_MISSES_DUPLICATE" block="SQ" event="293" descr="Number of misses that were duplicates (access to a non-resident, miss pending CL). (per-SQ, per-Bank, nondeterministic)" ></metric>
|
||||
<metric name="SQC_DCACHE_ATOMIC" block="SQ" event="298" descr="Number of atomic requests. (per-SQ, per-Bank)"></metric>
|
||||
<metric name="SQC_DCACHE_REQ_READ_1" block="SQ" event="323" descr="Number of constant cache 1 dw read requests. (per-SQ)"></metric>
|
||||
<metric name="SQC_DCACHE_REQ_READ_2" block="SQ" event="324" descr="Number of constant cache 2 dw read requests. (per-SQ)"></metric>
|
||||
<metric name="SQC_DCACHE_REQ_READ_4" block="SQ" event="325" descr="Number of constant cache 4 dw read requests. (per-SQ)"></metric>
|
||||
<metric name="SQC_DCACHE_REQ_READ_8" block="SQ" event="326" descr="Number of constant cache 8 dw read requests. (per-SQ)"></metric>
|
||||
<metric name="SQC_DCACHE_REQ_READ_16" block="SQ" event="327" descr="Number of constant cache 16 dw read requests. (per-SQ)"></metric>
|
||||
<metric name="TA_TA_BUSY" block="TA" event="13" descr="TA block is busy. Perf_Windowing not supported for this counter."></metric>
|
||||
<metric name="TA_TOTAL_WAVEFRONTS" block="TA" event="29" descr="Total number of wavefronts processed by TA."></metric>
|
||||
<metric name="TA_BUFFER_WAVEFRONTS" block="TA" event="32" descr="Number of buffer wavefronts processed by TA."></metric>
|
||||
<metric name="TA_BUFFER_READ_WAVEFRONTS" block="TA" event="33" descr="Number of buffer read wavefronts processed by TA."></metric>
|
||||
<metric name="TA_BUFFER_WRITE_WAVEFRONTS" block="TA" event="34" descr="Number of buffer write wavefronts processed by TA."></metric>
|
||||
<metric name="TA_BUFFER_ATOMIC_WAVEFRONTS" block="TA" event="35" descr="Number of buffer atomic wavefronts processed by TA."></metric>
|
||||
<metric name="TA_BUFFER_TOTAL_CYCLES" block="TA" event="37" descr="Number of buffer cycles issued to TC."></metric>
|
||||
<metric name="TA_BUFFER_COALESCED_READ_CYCLES" block="TA" event="40" descr="Number of buffer coalesced read cycles issued to TC."></metric>
|
||||
<metric name="TA_BUFFER_COALESCED_WRITE_CYCLES" block="TA" event="41" descr="Number of buffer coalesced write cycles issued to TC."></metric>
|
||||
<metric name="TA_ADDR_STALLED_BY_TC_CYCLES" block="TA" event="42" descr="Number of cycles addr path stalled by TC. Perf_Windowing not supported for this counter."></metric>
|
||||
<metric name="TA_ADDR_STALLED_BY_TD_CYCLES" block="TA" event="43" descr="Number of cycles addr path stalled by TD. Perf_Windowing not supported for this counter."></metric>
|
||||
<metric name="TA_DATA_STALLED_BY_TC_CYCLES" block="TA" event="44" descr="Number of cycles data path stalled by TC. Perf_Windowing not supported for this counter."></metric>
|
||||
<metric name="TA_FLAT_WAVEFRONTS" block="TA" event="51" descr="Number of flat opcode wavfronts processed by the TA."></metric>
|
||||
<metric name="TA_FLAT_READ_WAVEFRONTS" block="TA" event="52" descr="Number of flat opcode reads processed by the TA."></metric>
|
||||
<metric name="TA_FLAT_WRITE_WAVEFRONTS" block="TA" event="53" descr="Number of flat opcode writes processed by the TA."></metric>
|
||||
<metric name="TA_FLAT_ATOMIC_WAVEFRONTS" block="TA" event="54" descr="Number of flat opcode atomics processed by the TA."></metric>
|
||||
<metric name="TD_TD_BUSY" block="TD" event="1" descr="TD is processing or waiting for data. Perf_Windowing not supported for this counter."></metric>
|
||||
<metric name="TD_TC_STALL" block="TD" event="12" descr="TD is stalled waiting for TC data."></metric>
|
||||
<metric name="TD_SPI_STALL" block="TD" event="15" descr="TD is stalled SPI vinit"></metric>
|
||||
<metric name="TD_LOAD_WAVEFRONT" block="TD" event="16" descr="Count the wavefronts with opcode = load, include atomics and store."></metric>
|
||||
<metric name="TD_ATOMIC_WAVEFRONT" block="TD" event="17" descr="Count the wavefronts with opcode = atomic."></metric>
|
||||
<metric name="TD_STORE_WAVEFRONT" block="TD" event="18" descr="Count the wavefronts with opcode = store."></metric>
|
||||
<metric name="TD_COALESCABLE_WAVEFRONT" block="TD" event="21" descr="Count wavefronts that TA finds coalescable."></metric>
|
||||
<metric name="TCP_GATE_EN1" block="TCP" event="0" descr="TCP interface clocks are turned on. Not Windowed."></metric>
|
||||
<metric name="TCP_GATE_EN2" block="TCP" event="1" descr="TCP core clocks are turned on. Not Windowed."></metric>
|
||||
<metric name="TCP_TD_TCP_STALL_CYCLES" block="TCP" event="7" descr="TD stalls TCP"></metric>
|
||||
<metric name="TCP_TCR_TCP_STALL_CYCLES" block="TCP" event="8" descr="TCR stalls TCP_TCR_req interface"></metric>
|
||||
<metric name="TCP_READ_TAGCONFLICT_STALL_CYCLES" block="TCP" event="10" descr="Tagram conflict stall on a read"></metric>
|
||||
<metric name="TCP_WRITE_TAGCONFLICT_STALL_CYCLES" block="TCP" event="11" descr="Tagram conflict stall on a write"></metric>
|
||||
<metric name="TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES" block="TCP" event="12" descr="Tagram conflict stall on an atomic"></metric>
|
||||
<metric name="TCP_PENDING_STALL_CYCLES" block="TCP" event="21" descr="Stall due to data pending from L2"></metric>
|
||||
<metric name="TCP_TA_TCP_STATE_READ" block="TCP" event="25" descr="Number of state reads"></metric>
|
||||
<metric name="TCP_VOLATILE" block="TCP" event="26" descr="Total number of L1 volatile pixels/buffers from TA"></metric>
|
||||
<metric name="TCP_TOTAL_ACCESSES" block="TCP" event="27" descr="Total number of pixels/buffers from TA. Equals TCP_PERF_SEL_TOTAL_READ+TCP_PERF_SEL_TOTAL_NONREAD"></metric>
|
||||
<metric name="TCP_TOTAL_READ" block="TCP" event="28" descr="Total number of read pixels/buffers from TA. Equals TCP_PERF_SEL_TOTAL_HIT_LRU_READ + TCP_PERF_SEL_TOTAL_MISS_LRU_READ + TCP_PERF_SEL_TOTAL_MISS_EVICT_READ"></metric>
|
||||
<metric name="TCP_TOTAL_WRITE" block="TCP" event="30" descr="Total number of local write pixels/buffers from TA. Equals TCP_PERF_SEL_TOTAL_MISS_LRU_WRITE+ TCP_PERF_SEL_TOTAL_MISS_EVICT_WRITE"></metric>
|
||||
<metric name="TCP_TOTAL_ATOMIC_WITH_RET" block="TCP" event="36" descr="Total number of atomic with return pixels/buffers from TA"></metric>
|
||||
<metric name="TCP_TOTAL_ATOMIC_WITHOUT_RET" block="TCP" event="37" descr="Total number of atomic without return pixels/buffers from TA"></metric>
|
||||
<metric name="TCP_TOTAL_WRITEBACK_INVALIDATES" block="TCP" event="43" descr="Total number of cache invalidates. Equals TCP_PERF_SEL_TOTAL_WBINVL1+ TCP_PERF_SEL_TOTAL_WBINVL1_VOL+ TCP_PERF_SEL_CP_TCP_INVALIDATE+ TCP_PERF_SEL_SQ_TCP_INVALIDATE_VOL. Not Windowed."></metric>
|
||||
<metric name="TCP_UTCL1_REQUEST" block="TCP" event="45" descr="Total CLIENT_UTCL1 NORMAL requests"></metric>
|
||||
<metric name="TCP_UTCL1_TRANSLATION_MISS" block="TCP" event="47" descr="Total utcl1 translation misses"></metric>
|
||||
<metric name="TCP_UTCL1_TRANSLATION_HIT" block="TCP" event="48" descr="Total utcl1 translation hits"></metric>
|
||||
<metric name="TCP_UTCL1_PERMISSION_MISS" block="TCP" event="49" descr="Total utcl1 permission misses"></metric>
|
||||
<metric name="TCP_TOTAL_CACHE_ACCESSES" block="TCP" event="60" descr="Count of total cache line (tag) accesses (includes hits and misses)."></metric>
|
||||
<metric name="TCP_TCC_READ_REQ" block="TCP" event="65" descr="Total read requests from TCP to all TCCs"></metric>
|
||||
<metric name="TCP_TCC_WRITE_REQ" block="TCP" event="66" descr="Total write requests from TCP to all TCCs"></metric>
|
||||
<metric name="TCP_TCC_ATOMIC_WITH_RET_REQ" block="TCP" event="67" descr="Total atomic with return requests from TCP to all TCCs"></metric>
|
||||
<metric name="TCP_TCC_ATOMIC_WITHOUT_RET_REQ" block="TCP" event="68" descr="Total atomic without return requests from TCP to all TCCs"></metric>
|
||||
<metric name="TCP_TCC_NC_READ_REQ" block="TCP" event="71" descr="Total read requests with NC mtype from this TCP to all TCCs"></metric>
|
||||
<metric name="TCP_TCC_NC_WRITE_REQ" block="TCP" event="72" descr="Total write requests with NC mtype from this TCP to all TCCs"></metric>
|
||||
<metric name="TCP_TCC_NC_ATOMIC_REQ" block="TCP" event="73" descr="Total atomic requests with NC mtype from this TCP to all TCCs"></metric>
|
||||
<metric name="TCP_TCC_UC_READ_REQ" block="TCP" event="74" descr="Total read requests with UC mtype from this TCP to all TCCs"></metric>
|
||||
<metric name="TCP_TCC_UC_WRITE_REQ" block="TCP" event="75" descr="Total write requests with UC mtype from this TCP to all TCCs"></metric>
|
||||
<metric name="TCP_TCC_UC_ATOMIC_REQ" block="TCP" event="76" descr="Total atomic requests with UC mtype from this TCP to all TCCs"></metric>
|
||||
<metric name="TCP_TCC_CC_READ_REQ" block="TCP" event="77" descr="Total write requests with CC mtype from this TCP to all TCCs"></metric>
|
||||
<metric name="TCP_TCC_CC_WRITE_REQ" block="TCP" event="78" descr="Total write requests with CC mtype from this TCP to all TCCs"></metric>
|
||||
<metric name="TCP_TCC_CC_ATOMIC_REQ" block="TCP" event="79" descr="Total atomic requests with CC mtype from this TCP to all TCCs"></metric>
|
||||
<metric name="TCP_TCC_RW_READ_REQ" block="TCP" event="80" descr="Total write requests with RW mtype from this TCP to all TCCs"></metric>
|
||||
<metric name="TCP_TCC_RW_WRITE_REQ" block="TCP" event="81" descr="Total write requests with RW mtype from this TCP to all TCCs"></metric>
|
||||
<metric name="TCP_TCC_RW_ATOMIC_REQ" block="TCP" event="82" descr="Total atomic requests with RW mtype from this TCP to all TCCs"></metric>
|
||||
<metric name="TCA_CYCLE" block="TCA" event="1" descr="Number of cycles. Not windowable."></metric>
|
||||
<metric name="TCA_BUSY" block="TCA" event="2" descr="Number of cycles we have a request pending. Not windowable."></metric>
|
||||
<metric name="TCC_CYCLE" block="TCC" event="1" descr="Number of cycles. Not windowable."></metric>
|
||||
<metric name="TCC_BUSY" block="TCC" event="2" descr="Number of cycles we have a request pending. Not windowable."></metric>
|
||||
<metric name="TCC_REQ" block="TCC" event="3" descr="Number of requests of all types. This is measured at the tag block. This may be more than the number of requests arriving at the TCC, but it is a good indication of the total amount of work that needs to be performed."></metric>
|
||||
<metric name="TCC_STREAMING_REQ" block="TCC" event="4" descr="Number of streaming requests. This is measured at the tag block."></metric>
|
||||
<metric name="TCC_NC_REQ" block="TCC" event="5" descr="The number of noncoherently cached requests. This is measured at the tag block."></metric>
|
||||
<metric name="TCC_UC_REQ" block="TCC" event="6" descr="The number of uncached requests. This is measured at the tag block."></metric>
|
||||
<metric name="TCC_CC_REQ" block="TCC" event="7" descr="The number of coherently cached requests. This is measured at the tag block."></metric>
|
||||
<metric name="TCC_RW_REQ" block="TCC" event="8" descr="The number of RW requests. This is measured at the tag block."></metric>
|
||||
<metric name="TCC_PROBE" block="TCC" event="9" descr="Number of probe requests. Not windowable."></metric>
|
||||
<metric name="TCC_PROBE_ALL" block="TCC" event="10" descr="Number of external probe requests with with EA_TCC_preq_all== 1. Not windowable."></metric>
|
||||
<metric name="TCC_READ" block="TCC" event="12" descr="Number of read requests. Compressed reads are included in this, but metadata reads are not included."></metric>
|
||||
<metric name="TCC_WRITE" block="TCC" event="13" descr="Number of write requests."></metric>
|
||||
<metric name="TCC_ATOMIC" block="TCC" event="14" descr="Number of atomic requests of all types."></metric>
|
||||
<metric name="TCC_HIT" block="TCC" event="17" descr="Number of cache hits."></metric>
|
||||
<metric name="TCC_MISS" block="TCC" event="19" descr="Number of cache misses. UC reads count as misses."></metric>
|
||||
<metric name="TCC_WRITEBACK" block="TCC" event="22" descr="Number of lines written back to main memory. This includes writebacks of dirty lines and uncached write/atomic requests."></metric>
|
||||
<metric name="TCC_EA0_WRREQ" block="TCC" event="26" descr="Number of transactions (either 32-byte or 64-byte) going over the TC_EA_wrreq interface. Atomics may travel over the same interface and are generally classified as write requests. This does not include probe commands."></metric>
|
||||
<metric name="TCC_EA0_WRREQ_64B" block="TCC" event="27" descr="Number of 64-byte transactions going (64-byte write or CMPSWAP) over the TC_EA_wrreq interface."></metric>
|
||||
<metric name="TCC_EA0_WR_UNCACHED_32B" block="TCC" event="29" descr="Number of 32/64-byte write/atomic going over the TC_EA_wrreq interface due to uncached traffic. Note that CC mtypes can produce uncached requests, and those are included in this."></metric>
|
||||
<metric name="TCC_EA0_WRREQ_STALL" block="TCC" event="30" descr="Number of cycles a write request was stalled."></metric>
|
||||
<metric name="TCC_EA0_WRREQ_IO_CREDIT_STALL" block="TCC" event="31" descr="Number of cycles a EA write request was stalled because the interface was out of IO credits."></metric>
|
||||
<metric name="TCC_EA0_WRREQ_GMI_CREDIT_STALL" block="TCC" event="32" descr="Number of cycles a EA write request was stalled because the interface was out of GMI credits."></metric>
|
||||
<metric name="TCC_EA0_WRREQ_DRAM_CREDIT_STALL" block="TCC" event="33" descr="Number of cycles a EA write request was stalled because the interface was out of DRAM credits."></metric>
|
||||
<metric name="TCC_TOO_MANY_EA_WRREQS_STALL" block="TCC" event="34" descr="Number of cycles the TCC could not send a EA write request because it already reached its maximum number of pending EA write requests."></metric>
|
||||
<metric name="TCC_EA0_WRREQ_LEVEL" block="TCC" event="35" descr="The sum of the number of EA write requests in flight. This is primarily meant for measure average EA write latency. Average write latency = TCC_PERF_SEL_EA_WRREQ_LEVEL/TCC_PERF_SEL_EA_WRREQ."></metric>
|
||||
<metric name="TCC_EA0_ATOMIC" block="TCC" event="36" descr="Number of transactions going over the TC_EA_wrreq interface that are actually atomic requests."></metric>
|
||||
<metric name="TCC_EA0_ATOMIC_LEVEL" block="TCC" event="37" descr="The sum of the number of EA atomics in flight. This is primarily meant for measure average EA atomic latency. Average atomic latency = TCC_PERF_SEL_EA_WRREQ_ATOMIC_LEVEL/TCC_PERF_SEL_EA_WRREQ_ATOMIC."></metric>
|
||||
<metric name="TCC_EA0_RDREQ" block="TCC" event="38" descr="Number of TCC/EA read requests (either 32-byte or 64-byte)"></metric>
|
||||
<metric name="TCC_EA0_RDREQ_32B" block="TCC" event="39" descr="Number of 32-byte TCC/EA read requests"></metric>
|
||||
<metric name="TCC_EA0_RD_UNCACHED_32B" block="TCC" event="40" descr="Number of 32-byte TCC/EA read due to uncached traffic. A 64-byte request will be counted as 2"></metric>
|
||||
<metric name="TCC_EA0_RDREQ_IO_CREDIT_STALL" block="TCC" event="41" descr="Number of cycles there was a stall because the read request interface was out of IO credits. Stalls occur regardless of whether a read needed to be performed or not."></metric>
|
||||
<metric name="TCC_EA0_RDREQ_GMI_CREDIT_STALL" block="TCC" event="42" descr="Number of cycles there was a stall because the read request interface was out of GMI credits. Stalls occur regardless of whether a read needed to be performed or not."></metric>
|
||||
<metric name="TCC_EA0_RDREQ_DRAM_CREDIT_STALL" block="TCC" event="43" descr="Number of cycles there was a stall because the read request interface was out of DRAM credits. Stalls occur regardless of whether a read needed to be performed or not."></metric>
|
||||
<metric name="TCC_EA0_RDREQ_LEVEL" block="TCC" event="44" descr="The sum of the number of TCC/EA read requests in flight. This is primarily meant for measure average EA read latency. Average read latency = TCC_PERF_SEL_EA_RDREQ_LEVEL/TCC_PERF_SEL_EA_RDREQ."></metric>
|
||||
<metric name="TCC_TAG_STALL" block="TCC" event="45" descr="Number of cycles the normal request pipeline in the tag was stalled for any reason. Normally, stalls of this nature are measured exactly from one point the pipeline, but that is not the case for this counter. Probes can stall the pipeline at a variety of places, and there is no single point that can reasonably measure the total stalls accurately."></metric>
|
||||
<metric name="TCC_NORMAL_WRITEBACK" block="TCC" event="68" descr="Number of writebacks due to requests that are not writeback requests."></metric>
|
||||
<metric name="TCC_ALL_TC_OP_WB_WRITEBACK" block="TCC" event="73" descr="Number of writebacks due to all TC_OP writeback requests."></metric>
|
||||
<metric name="TCC_NORMAL_EVICT" block="TCC" event="74" descr="Number of evictions due to requests that are not invalidate or probe requests."></metric>
|
||||
<metric name="TCC_ALL_TC_OP_INV_EVICT" block="TCC" event="80" descr="Number of evictions due to all TC_OP invalidate requests."></metric>
|
||||
<metric name="TCC_EA0_RDREQ_DRAM" block="TCC" event="102" descr="Number of TCC/EA read requests (either 32-byte or 64-byte) destined for DRAM (MC)."></metric>
|
||||
<metric name="TCC_EA0_WRREQ_DRAM" block="TCC" event="103" descr="Number of TCC/EA write requests (either 32-byte of 64-byte) destined for DRAM (MC)."></metric>
|
||||
</gfx940>
|
||||
|
||||
<gfx9>
|
||||
<metric name="GRBM_COUNT" block="GRBM" event="0" descr="Tie High - Count Number of Clocks"></metric>
|
||||
<metric name="GRBM_GUI_ACTIVE" block="GRBM" event="2" descr="The GUI is Active"></metric>
|
||||
<metric name="SQ_WAVES" block="SQ" event="4" descr="Count number of waves sent to SQs. (per-simd, emulated, global)"></metric>
|
||||
<metric name="SQ_INSTS_VALU" block="SQ" event="26" descr="Number of VALU instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VMEM_WR" block="SQ" event="27" descr="Number of VMEM write instructions issued (including FLAT). (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VMEM_RD" block="SQ" event="28" descr="Number of VMEM read instructions issued (including FLAT). (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_SALU" block="SQ" event="30" descr="Number of SALU instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_SMEM" block="SQ" event="31" descr="Number of SMEM instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_FLAT" block="SQ" event="32" descr="Number of FLAT instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_FLAT_LDS_ONLY" block="SQ" event="33" descr="Number of FLAT instructions issued that read/wrote only from/to LDS (only works if EARLY_TA_DONE is enabled). (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_LDS" block="SQ" event="34" descr="Number of LDS instructions issued (including FLAT). (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_GDS" block="SQ" event="35" descr="Number of GDS instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_WAIT_INST_LDS" block="SQ" event="63" descr="Number of wave-cycles spent waiting for LDS instruction issue. In units of 4 cycles. (per-simd, nondeterministic)"></metric>
|
||||
<metric name="SQ_ACTIVE_INST_VALU" block="SQ" event="71" descr="regspec 71? Number of cycles the SQ instruction arbiter is working on a VALU instruction. (per-simd, nondeterministic). Units in quad-cycles(4 cycles)"></metric>
|
||||
<metric name="SQ_INST_CYCLES_SALU" block="SQ" event="84" descr="Number of cycles needed to execute non-memory read scalar operations. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_THREAD_CYCLES_VALU" block="SQ" event="85" descr="Number of thread-cycles used to execute VALU operations (similar to INST_CYCLES_VALU but multiplied by # of active threads). (per-simd)"></metric>
|
||||
<metric name="SQ_LDS_BANK_CONFLICT" block="SQ" event="93" descr="Number of cycles LDS is stalled by bank conflicts. (emulated)"></metric>
|
||||
<metric name="TA_TA_BUSY" block="TA" event="15" descr="TA block is busy. Perf_Windowing not supported for this counter."></metric>
|
||||
<metric name="TA_FLAT_READ_WAVEFRONTS" block="TA" event="101" descr="Number of flat opcode reads processed by the TA."></metric>
|
||||
<metric name="TA_FLAT_WRITE_WAVEFRONTS" block="TA" event="102" descr="Number of flat opcode writes processed by the TA."></metric>
|
||||
<metric name="TCC_HIT" block="TCC" event="20" descr="Number of cache hits."></metric>
|
||||
<metric name="TCC_MISS" block="TCC" event="22" descr="Number of cache misses. UC reads count as misses."></metric>
|
||||
<metric name="TCC_EA_WRREQ" block="TCC" event="29" descr="Number of transactions (either 32-byte or 64-byte) going over the TC_EA_wrreq interface. Atomics may travel over the same interface and are generally classified as write requests. This does not include probe commands."></metric>
|
||||
<metric name="TCC_EA_WRREQ_64B" block="TCC" event="30" descr="Number of 64-byte transactions going (64-byte write or CMPSWAP) over the TC_EA_wrreq interface."></metric>
|
||||
<metric name="TCC_EA_WRREQ_STALL" block="TCC" event="33" descr="Number of cycles a write request was stalled."></metric>
|
||||
<metric name="TCC_EA_RDREQ" block="TCC" event="41" descr="Number of TCC/EA read requests (either 32-byte or 64-byte)"></metric>
|
||||
<metric name="TCC_EA_RDREQ_32B" block="TCC" event="42" descr="Number of 32-byte TCC/EA read requests"></metric>
|
||||
<metric name="TCP_TCP_TA_DATA_STALL_CYCLES" block="TCP" event="6" descr="TCP stalls TA data interface. Now Windowed."></metric>
|
||||
</gfx9>
|
||||
|
||||
<gfx10>
|
||||
<metric name="GRBM_COUNT" block="GRBM" event="0" descr="Tie High - Count Number of Clocks"></metric>
|
||||
<metric name="GRBM_GUI_ACTIVE" block="GRBM" event="2" descr="The GUI is Active"></metric>
|
||||
<metric name="GRBM_CP_BUSY" block="GRBM" event="3" descr="Any of the Command Processor (CPG/CPC/CPF) blocks are busy."></metric>
|
||||
<metric name="GRBM_SPI_BUSY" block="GRBM" event="11" descr="Any of the Shader Pipe Interpolators (SPI) are busy in the shader engine(s)."></metric>
|
||||
<metric name="GRBM_TA_BUSY" block="GRBM" event="13" descr="Any of the Texture Pipes (TA) are busy in the shader engine(s)."></metric>
|
||||
<metric name="GRBM_GDS_BUSY" block="GRBM" event="25" descr="The Global Data Share (GDS) is busy."></metric>
|
||||
<metric name="GRBM_EA_BUSY" block="GRBM" event="35" descr="The Efficiency Arbiter (EA) block is busy."></metric>
|
||||
<metric name="GRBM_GL2CC_BUSY" block="GRBM" event="40" descr="The GL2CC block is busy."></metric>
|
||||
<metric name="GL2C_HIT" block="GL2C" event="42" descr="Number of cache hits"></metric>
|
||||
<metric name="GL2C_MISS" block="GL2C" event="43" descr="Number of cache misses. UC reads count as misses."></metric>
|
||||
<metric name="GL2C_MC_WRREQ" block="GL2C" event="83" descr="Number of transactions (either 32-byte or 64-byte) going over the GL2C_EA_wrreq interface. Atomics may travel over the same interface and are generally classified as write requests. This does not include probe commands"></metric>
|
||||
<metric name="GL2C_EA_WRREQ_64B" block="GL2C" event="85" descr="Number of 64-byte transactions going (64-byte write or CMPSWAP) over the TC_EA_wrreq interface."></metric>
|
||||
<metric name="GL2C_MC_WRREQ_STALL" block="GL2C" event="88" descr="Number of cycles a write request was stalled."></metric>
|
||||
<metric name="GL2C_MC_RDREQ" block="GL2C" event="96" descr="Number of GL2C/EA read requests (either 32-byte or 64-byte or 128-byte)."></metric>
|
||||
<metric name="GL2C_EA_RDREQ_32B" block="GL2C" event="99" descr="Number of 32-byte GL2C/EA read requests"></metric>
|
||||
<metric name="GL2C_EA_RDREQ_64B" block="GL2C" event="100" descr="Number of 64-byte GL2C/EA read requests"></metric>
|
||||
<metric name="GL2C_EA_RDREQ_96B" block="GL2C" event="101" descr="Number of 96-byte GL2C/EA read requests"></metric>
|
||||
<metric name="GL2C_EA_RDREQ_128B" block="GL2C" event="102" descr="Number of 128-byte GL2C/EA read requests"></metric>
|
||||
<metric name="SQ_WAVES" block="SQ" event="4" descr="Count number of waves sent to SQs. {emulated, global, C1}"></metric>
|
||||
<metric name="SQ_WAVE_CYCLES" block="SQ" event="26" descr="Number of clock cycles spent by waves in the SQs. Incremented by # of living (valid) waves each cycle. {nondeterministic, C1}"></metric>
|
||||
<metric name="SQ_WAIT_INST_ANY" block="SQ" event="28" descr="Number of clock cycles spent waiting for any instruction issue. In units of cycles. {nondeterministic}"></metric>
|
||||
<metric name="SQ_WAIT_ANY" block="SQ" event="37" descr="Number of clock cycles spent waiting for anything. {nondeterministic, C1}"></metric>
|
||||
<metric name="SQ_INSTS_WAVE32" block="SQ" event="71" descr="Number of wave32 instructions issued, for flat, lds, valu, tex. {emulated, C1}"></metric>
|
||||
<metric name="SQ_INSTS_WAVE32_LDS" block="SQ" event="74" descr="Number of wave32 LDS indexed instructions issued. Wave64 may count 1 or 2, depending on what gets issued. {emulated, C1}"></metric>
|
||||
<metric name="SQ_INSTS_WAVE32_VALU" block="SQ" event="75" descr="Number of wave32 valu instructions issued. Wave64 may count 1 or 2, depending on what gets issued. {emulated, C1}"></metric>
|
||||
<metric name="SQ_WAVE32_INSTS" block="SQ" event="84" descr="Number of instructions issued by wave32 waves. Skipped instructions are not counted. {emulated}"></metric>
|
||||
<metric name="SQ_WAVE64_INSTS" block="SQ" event="85" descr="Number of instructions issued by wave64 waves. Skipped instructions are not counted. {emulated}"></metric>
|
||||
<metric name="SQ_INST_LEVEL_GDS" block="SQ" event="98" descr="Number of in-flight GDS instructions. Set next counter to ACCUM_PREV and divide by INSTS_GDS for average latency. {level, nondeterministic, C1}"></metric>
|
||||
<metric name="SQ_INST_LEVEL_LDS" block="SQ" event="99" descr="Number of in-flight LDS instructions. Set next counter to ACCUM_PREV and divide by INSTS_LDS for average latency. Includes FLAT instructions. {level, nondeterministic, C1}"></metric>
|
||||
<metric name="SQ_INST_CYCLES_VMEM" block="SQ" event="120" descr="Number of cycles needed to send addr and data for VMEM (lds, buffer, image, flat, scratch, global) instructions, windowed by perf_en. {emulated, C1}"></metric>
|
||||
<metric name="SQC_LDS_BANK_CONFLICT" block="SQ" event="285" descr="Number of cycles LDS is stalled by bank conflicts. (emulated, C1)"></metric>
|
||||
<metric name="SQC_LDS_IDX_ACTIVE" block="SQ" event="290" descr="Number of cycles LDS is used for indexed (non-direct,non-interpolation) operations. {per-simd, emulated, C1}"></metric>
|
||||
<metric name="SQ_INSTS_VALU" block="SQ" event="64" descr="Number of VALU instructions issued excluding skipped instructions. {emulated, C1}"></metric>
|
||||
<metric name="SQ_INSTS_SALU" block="SQ" event="60" descr="Number of SALU instructions issued. {emulated, C1}"></metric>
|
||||
<metric name="SQ_INSTS_SMEM" block="SQ" event="61" descr="Number of SMEM instructions issued. {emulated, C1}"></metric>
|
||||
<metric name="SQ_INSTS_FLAT" block="SQ" event="57" descr="Number of FLAT instructions issued. {emulated, C2}"></metric>
|
||||
<metric name="SQ_INSTS_LDS" block="SQ" event="59" descr="Number of LDS indexed instructions issued. {emulated, C1}"></metric>
|
||||
<metric name="SQ_INSTS_GDS" block="SQ" event="55" descr="Number of GDS instructions issued. {emulated, C1}"></metric>
|
||||
<metric name="SQ_WAIT_INST_LDS" block="SQ" event="31" descr="Number of clock cycles spent waiting for LDS (indexed) instruction issue. In units of cycles. {nondeterministic, C1}"></metric>
|
||||
<metric name="TA_TA_BUSY" block="TA" event="15" descr="TA block is busy. Perf_Windowing not supported for this counter."></metric>
|
||||
<metric name="TA_FLAT_LOAD_WAVEFRONTS" block="TA" event="101" descr=" Number of flat load vec32 packets processed by TA, same as flat_read_wavefronts in earlier IP"></metric>
|
||||
<metric name="TA_FLAT_STORE_WAVEFRONTS" block="TA" event="102" descr="Number of flat store vec32 packets processed by TA, same as flat_write_wavefronts in earlier IP"></metric>
|
||||
</gfx10>
|
||||
|
||||
</counters>
|
||||
@@ -0,0 +1,233 @@
|
||||
#!/usr/bin/python3
|
||||
|
||||
from __future__ import print_function
|
||||
import os, sys, re
|
||||
import xml.etree.ElementTree as ET
|
||||
from lxml import etree
|
||||
import sys
|
||||
|
||||
CPP_OUT='basic_counter.cpp'
|
||||
|
||||
if (__name__ == "__main__"):
|
||||
cpp_content = ''
|
||||
cpp_content += '/* Copyright (c) 2022 Advanced Micro Devices, Inc.\n'
|
||||
cpp_content += '\n'
|
||||
cpp_content += ' Permission is hereby granted, free of charge, to any person obtaining a copy\n'
|
||||
cpp_content += ' of this software and associated documentation files (the \"Software\"), to deal\n'
|
||||
cpp_content += ' in the Software without restriction, including without limitation the rights\n'
|
||||
cpp_content += ' to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n'
|
||||
cpp_content += ' copies of the Software, and to permit persons to whom the Software is\n'
|
||||
cpp_content += ' furnished to do so, subject to the following conditions:\n'
|
||||
cpp_content += '\n'
|
||||
cpp_content += ' The above copyright notice and this permission notice shall be included in\n'
|
||||
cpp_content += ' all copies or substantial portions of the Software.\n'
|
||||
cpp_content += '\n'
|
||||
cpp_content += ' THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n'
|
||||
cpp_content += ' IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n'
|
||||
cpp_content += ' FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n'
|
||||
cpp_content += ' AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n'
|
||||
cpp_content += ' LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n'
|
||||
cpp_content += ' OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n'
|
||||
cpp_content += ' THE SOFTWARE. */\n'
|
||||
cpp_content += '\n'
|
||||
cpp_content += '#include <cassert>\n'
|
||||
cpp_content += '#include "src/utils/helper.h"\n'
|
||||
cpp_content += '\n'
|
||||
cpp_content += '#include \"src/core/counters/basic/basic_counter.h\"\n'
|
||||
cpp_content += '#include \"src/core/hardware/hsa_info.h\"\n'
|
||||
cpp_content += '\n'
|
||||
cpp_content += '#define ASSERTM(exp, msg) assert(((void)msg, exp))\n'
|
||||
cpp_content += '\n'
|
||||
cpp_content += '#pragma GCC diagnostic push\n'
|
||||
cpp_content += '#pragma GCC diagnostic ignored \"-Wmaybe-uninitialized\"\n'
|
||||
cpp_content += 'namespace Counter {\n'
|
||||
cpp_content += '\n'
|
||||
cpp_content += 'BasicCounter::BasicCounter(uint64_t event_id, std::string block_id,\n'
|
||||
cpp_content += ' std::string name, std::string description,\n'
|
||||
cpp_content += ' std::string gpu_name)\n'
|
||||
cpp_content += ' : Counter(name, description, gpu_name),\n'
|
||||
cpp_content += ' event_id_(event_id),\n'
|
||||
cpp_content += ' block_id_(block_id) {\n'
|
||||
cpp_content += ' AddCounterToCounterMap();\n'
|
||||
cpp_content += '}\n'
|
||||
cpp_content += '\n'
|
||||
cpp_content += 'BasicCounter::~BasicCounter() {}\n'
|
||||
cpp_content += '\n'
|
||||
cpp_content += 'uint64_t BasicCounter::GetBasicCounterID() {\n'
|
||||
cpp_content += ' return GetCounterID();\n'
|
||||
cpp_content += '}\n'
|
||||
cpp_content += '\n'
|
||||
cpp_content += 'uint64_t BasicCounter::GetEventId() { return event_id_; }\n'
|
||||
cpp_content += 'std::string BasicCounter::GetBlockId() { return block_id_; }\n'
|
||||
cpp_content += 'std::string BasicCounter::GetName() { return Counter::GetName(); }\n'
|
||||
cpp_content += '\n'
|
||||
cpp_content += 'bool BasicCounter::GetValue(uint64_t* value, int64_t instance_id = -1) {\n'
|
||||
cpp_content += ' Agent::CounterHardwareInfo* agent_info =\n'
|
||||
cpp_content += ' reinterpret_cast<Agent::CounterHardwareInfo*>(counter_hw_info);\n'
|
||||
cpp_content += ' if ((agent_info->getNumInstances() > 1 && instance_id == -1) ||\n'
|
||||
cpp_content += ' instance_id < -1 || instance_id >= agent_info->getNumInstances())\n'
|
||||
cpp_content += ' return false;\n'
|
||||
cpp_content += ' if (instance_id == -1) *value = instances_values_[0];\n'
|
||||
cpp_content += ' *value = instances_values_[instance_id];\n'
|
||||
cpp_content += ' return true;\n'
|
||||
cpp_content += '}\n'
|
||||
cpp_content += '\n'
|
||||
cpp_content += 'uint64_t BasicCounter::GetValue(int64_t instance_id) {\n'
|
||||
cpp_content += ' Agent::CounterHardwareInfo* agent_info =\n'
|
||||
cpp_content += ' reinterpret_cast<Agent::CounterHardwareInfo*>(counter_hw_info);\n'
|
||||
cpp_content += ' if ((agent_info->getNumInstances() > 1 && instance_id == -1) ||\n'
|
||||
cpp_content += ' instance_id < -1 || instance_id >= agent_info->getNumInstances())\n'
|
||||
cpp_content += ' throw(std::string(\"Error: Wrong number of instances (\") +\n'
|
||||
cpp_content += ' std::to_string(agent_info->getNumInstances()) +\n'
|
||||
cpp_content += ' \") OR Instance ID is less than 0 \");\n'
|
||||
cpp_content += ' if (instance_id == -1) return instances_values_[0];\n'
|
||||
cpp_content += ' return instances_values_[instance_id];\n'
|
||||
cpp_content += '}\n'
|
||||
cpp_content += '\n'
|
||||
cpp_content += 'uint64_t BasicCounter::avr(int64_t instances_count) {\n'
|
||||
cpp_content += ' Agent::CounterHardwareInfo* agent_info =\n'
|
||||
cpp_content += ' reinterpret_cast<Agent::CounterHardwareInfo*>(counter_hw_info);\n'
|
||||
cpp_content += ' if (agent_info->getNumInstances() > instances_count)\n'
|
||||
cpp_content += ' throw(std::string(\"Error: Number of instances (\") +\n'
|
||||
cpp_content += ' std::to_string(agent_info->getNumInstances()) +\n'
|
||||
cpp_content += ' \") is greater than the given instance count(\" +\n'
|
||||
cpp_content += ' std::to_string(instances_count) + \")\");\n'
|
||||
cpp_content += ' uint64_t result = 0;\n'
|
||||
cpp_content += ' int64_t instance_id;\n'
|
||||
cpp_content += ' for (instance_id = 0; instance_id < instances_count; instance_id++) {\n'
|
||||
cpp_content += ' uint64_t value;\n'
|
||||
cpp_content += ' if (GetValue(&value, instance_id)) result += value;\n'
|
||||
cpp_content += ' }\n'
|
||||
cpp_content += ' return result / instances_count;\n'
|
||||
cpp_content += '}\n'
|
||||
cpp_content += 'uint64_t BasicCounter::max(int64_t instances_count) {\n'
|
||||
cpp_content += ' uint64_t result = 0;\n'
|
||||
cpp_content += ' int64_t instance_id;\n'
|
||||
cpp_content += ' for (instance_id = 0; instance_id < instances_count; instance_id++) {\n'
|
||||
cpp_content += ' uint64_t value;\n'
|
||||
cpp_content += ' if (GetValue(&value, instance_id) && result < value) result = value;\n'
|
||||
cpp_content += ' }\n'
|
||||
cpp_content += ' return result;\n'
|
||||
cpp_content += '}\n'
|
||||
cpp_content += 'uint64_t BasicCounter::min(int64_t instances_count) {\n'
|
||||
cpp_content += ' int64_t instance_id;\n'
|
||||
cpp_content += ' uint64_t result = 0;\n'
|
||||
cpp_content += ' for (instance_id = 0; instance_id < instances_count; instance_id++) {\n'
|
||||
cpp_content += ' uint64_t value;\n'
|
||||
cpp_content += ' if (GetValue(&value, instance_id) && result > value) result = value;\n'
|
||||
cpp_content += ' }\n'
|
||||
cpp_content += ' return result;\n'
|
||||
cpp_content += '}\n'
|
||||
cpp_content += 'uint64_t BasicCounter::sum(int64_t instances_count) {\n'
|
||||
cpp_content += ' int64_t instance_id;\n'
|
||||
cpp_content += ' uint64_t result = 0;\n'
|
||||
cpp_content += ' for (instance_id = 0; instance_id < instances_count; instance_id++) {\n'
|
||||
cpp_content += ' uint64_t value;\n'
|
||||
cpp_content += ' if (GetValue(&value, instance_id)) result += value;\n'
|
||||
cpp_content += ' }\n'
|
||||
cpp_content += ' return result;\n'
|
||||
cpp_content += '}\n'
|
||||
cpp_content += '\n'
|
||||
cpp_content += 'uint64_t operator+(BasicCounter counter, const uint64_t number) {\n'
|
||||
cpp_content += ' [[maybe_unused]] uint64_t value = 0;\n'
|
||||
cpp_content += ' ASSERTM(counter.GetValue(&value), \"Error: Counter has no value!\");\n'
|
||||
cpp_content += ' return number + value;\n'
|
||||
cpp_content += '}\n'
|
||||
cpp_content += 'uint64_t operator-(BasicCounter counter, const uint64_t number) {\n'
|
||||
cpp_content += ' [[maybe_unused]] uint64_t value = 0;\n'
|
||||
cpp_content += ' ASSERTM(counter.GetValue(&value), \"Error: Counter has no value!\");\n'
|
||||
cpp_content += ' return number - value;\n'
|
||||
cpp_content += '}\n'
|
||||
cpp_content += 'uint64_t operator*(BasicCounter counter, const uint64_t number) {\n'
|
||||
cpp_content += ' [[maybe_unused]] uint64_t value = 0;\n'
|
||||
cpp_content += ' ASSERTM(counter.GetValue(&value), \"Error: Counter has no value!\");\n'
|
||||
cpp_content += ' return number * value;\n'
|
||||
cpp_content += '}\n'
|
||||
cpp_content += 'uint64_t operator/(BasicCounter counter, const uint64_t number) {\n'
|
||||
cpp_content += ' [[maybe_unused]] uint64_t value = 0;\n'
|
||||
cpp_content += ' ASSERTM(counter.GetValue(&value), \"Error: Counter has no value!\");\n'
|
||||
cpp_content += ' return number / value;\n'
|
||||
cpp_content += '}\n'
|
||||
cpp_content += 'uint64_t operator^(BasicCounter counter, const uint64_t number) {\n'
|
||||
cpp_content += ' [[maybe_unused]] uint64_t value = 0;\n'
|
||||
cpp_content += ' ASSERTM(counter.GetValue(&value), \"Error: Counter has no value!\");\n'
|
||||
cpp_content += ' return number ^ value;\n'
|
||||
cpp_content += '}\n'
|
||||
cpp_content += '\n'
|
||||
cpp_content += 'uint64_t operator+(BasicCounter counter1, BasicCounter counter2) {\n'
|
||||
cpp_content += ' [[maybe_unused]] uint64_t value1 = 0;\n'
|
||||
cpp_content += ' ASSERTM(counter1.GetValue(&value1), \"Error: Counter has no value!\");\n'
|
||||
cpp_content += ' [[maybe_unused]] uint64_t value2 = 0;\n'
|
||||
cpp_content += ' ASSERTM(counter2.GetValue(&value2), \"Error: Counter has no value!\");\n'
|
||||
cpp_content += ' return value1 + value2;\n'
|
||||
cpp_content += '}\n'
|
||||
cpp_content += 'uint64_t operator-(BasicCounter counter1, BasicCounter counter2) {\n'
|
||||
cpp_content += ' [[maybe_unused]] uint64_t value1 = 0;\n'
|
||||
cpp_content += ' ASSERTM(counter1.GetValue(&value1), \"Error: Counter has no value!\");\n'
|
||||
cpp_content += ' [[maybe_unused]] uint64_t value2 = 0;\n'
|
||||
cpp_content += ' ASSERTM(counter2.GetValue(&value2), \"Error: Counter has no value!\");\n'
|
||||
cpp_content += ' return value1 - value2;\n'
|
||||
cpp_content += '}\n'
|
||||
cpp_content += 'uint64_t operator*(BasicCounter counter1, BasicCounter counter2) {\n'
|
||||
cpp_content += ' [[maybe_unused]] uint64_t value1 = 0;\n'
|
||||
cpp_content += ' ASSERTM(counter1.GetValue(&value1), \"Error: Counter has no value!\");\n'
|
||||
cpp_content += ' [[maybe_unused]] uint64_t value2 = 0;\n'
|
||||
cpp_content += ' ASSERTM(counter2.GetValue(&value2), \"Error: Counter has no value!\");\n'
|
||||
cpp_content += ' return value1 * value2;\n'
|
||||
cpp_content += '}\n'
|
||||
cpp_content += 'uint64_t operator/(BasicCounter counter1, BasicCounter counter2) {\n'
|
||||
cpp_content += ' [[maybe_unused]] uint64_t value1 = 0;\n'
|
||||
cpp_content += ' ASSERTM(counter1.GetValue( & value1), \"Error: Counter has no value!\");\n'
|
||||
cpp_content += ' [[maybe_unused]] uint64_t value2 = 0;\n'
|
||||
cpp_content += ' ASSERTM(counter2.GetValue( & value2), \"Error: Counter has no value!\");\n'
|
||||
cpp_content += ' return value1 / value2;\n'
|
||||
cpp_content += '}\n'
|
||||
cpp_content += 'uint64_t operator^(BasicCounter counter1, BasicCounter counter2) {\n'
|
||||
cpp_content += ' [[maybe_unused]] uint64_t value1 = 0;\n'
|
||||
cpp_content += ' ASSERTM(counter1.GetValue(&value1), \"Error: Counter has no value!\");\n'
|
||||
cpp_content += ' [[maybe_unused]] uint64_t value2 = 0;\n'
|
||||
cpp_content += ' ASSERTM(counter2.GetValue(&value2), \"Error: Counter has no value!\");\n'
|
||||
cpp_content += ' return value1 ^ value2;\n'
|
||||
cpp_content += '}\n'
|
||||
cpp_content += '\n'
|
||||
cpp_content += 'static std::map<uint64_t, BasicCounter> basic_counters;\n'
|
||||
cpp_content += '\n'
|
||||
cpp_content += 'BasicCounter* GetGeneratedBasicCounter(uint64_t id) {\n'
|
||||
cpp_content += ' return &basic_counters.at(id);\n'
|
||||
cpp_content += '}\n'
|
||||
cpp_content += '\n'
|
||||
cpp_content += 'void ClearBasicCounters() {\n'
|
||||
cpp_content += ' basic_counters.clear();\n'
|
||||
cpp_content += '}\n'
|
||||
cpp_content += '\n'
|
||||
cpp_content += '/**\n'
|
||||
cpp_content += ' * @brief Basic Counters\n'
|
||||
cpp_content += ' *\n'
|
||||
cpp_content += ' * @{\n'
|
||||
cpp_content += ' */\n'
|
||||
cpp_content += 'uint64_t GetBasicCounter(const char* name, const char* gpu_name) {\n'
|
||||
cpp_content += ' std::string gpu;\n'
|
||||
parser=etree.XMLParser(recover=True, encoding='utf-8')
|
||||
xml_file=ET.parse(sys.argv[1] + '/gfx_metrics.xml', parser=parser)
|
||||
root=xml_file.getroot()
|
||||
for gpu in root:
|
||||
cpp_content += "\n\t/**\n\t * @brief Basic " + gpu.tag + " counters\n\t *\n\t * @{\n\t */\n"
|
||||
cpp_content += "\tgpu = \"" + gpu.tag + "\";\n\n"
|
||||
cpp_content += "\tif (strncmp(gpu_name, gpu.c_str(), gpu.length())==0) {\n"
|
||||
for child in gpu:
|
||||
cpp_content += "\t/**\n\t * Basic Counter: " + child.attrib['name'] + "\n\t *\n\t * " + child.attrib['descr'] + "\n\t */\n\tif (strcmp(name, \"" + child.attrib['name'] + "\")==0) {\n\t\tbasic_counters.emplace(" + child.attrib['event'] + ", BasicCounter{" + child.attrib['event'] + ", \"" + child.attrib['block'] + "\", \"" + child.attrib['name'] + "\", \"" + child.attrib['descr'] + "\", \"" + gpu.tag + "\"});\n\t\treturn " + child.attrib['event'] + ";\n\t}\n"
|
||||
cpp_content += "\t}\n\n\t/**\n\t * @}\n\t */\n"
|
||||
cpp_content += ' throw(\"Couldn\'t find the required Counter name for the mentioned GPU!\");\n'
|
||||
cpp_content += ' return 0;\n'
|
||||
cpp_content += '}\n'
|
||||
cpp_content += '/**\n'
|
||||
cpp_content += ' * @}\n'
|
||||
cpp_content += ' */\n'
|
||||
cpp_content += '\n'
|
||||
cpp_content += '} // namespace Counter\n'
|
||||
cpp_content += '\n'
|
||||
cpp_content += '#pragma GCC diagnostic pop\n'
|
||||
print ('Generating "' + sys.argv[2] + '"')
|
||||
f = open(sys.argv[2], 'w')
|
||||
f.write(cpp_content[:-1])
|
||||
f.close()
|
||||
@@ -0,0 +1,46 @@
|
||||
/* Copyright (c) 2022 Advanced Micro Devices, Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE. */
|
||||
|
||||
#include "counter.h"
|
||||
|
||||
#include <cassert>
|
||||
|
||||
#include "src/api/rocmtool.h"
|
||||
|
||||
namespace Counter {
|
||||
|
||||
std::atomic<uint64_t> COUNTER_COUNT{1};
|
||||
|
||||
Counter::Counter(std::string name, std::string description, std::string gpu_name)
|
||||
: name_(name), description_(description), gpu_name_(gpu_name) {}
|
||||
|
||||
Counter::~Counter() {}
|
||||
|
||||
void Counter::AddCounterToCounterMap() { GenerateCounterID(); }
|
||||
|
||||
uint64_t Counter::GetCounterID() { return counter_id_; }
|
||||
void Counter::GenerateCounterID() {
|
||||
counter_id_ = COUNTER_COUNT.fetch_add(1, std::memory_order_release);
|
||||
}
|
||||
|
||||
std::string Counter::GetName() { return name_; }
|
||||
std::string Counter::GetDescription() { return description_; }
|
||||
|
||||
} // namespace Counter
|
||||
@@ -0,0 +1,52 @@
|
||||
/* Copyright (c) 2022 Advanced Micro Devices, Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE. */
|
||||
|
||||
#ifndef SRC_CORE_COUNTERS_COUNTER_H_
|
||||
#define SRC_CORE_COUNTERS_COUNTER_H_
|
||||
|
||||
#include <atomic>
|
||||
#include <cstdint>
|
||||
#include <string>
|
||||
#include <unordered_map>
|
||||
|
||||
namespace Counter {
|
||||
|
||||
class Counter {
|
||||
public:
|
||||
Counter(std::string name, std::string description, std::string gpu_name);
|
||||
~Counter();
|
||||
void AddCounterToCounterMap();
|
||||
uint64_t GetCounterID();
|
||||
void GenerateCounterID();
|
||||
std::string GetName();
|
||||
std::string GetDescription();
|
||||
|
||||
private:
|
||||
uint64_t counter_id_;
|
||||
std::string name_;
|
||||
std::string description_;
|
||||
std::string gpu_name_;
|
||||
};
|
||||
|
||||
std::string GetCounterName(uint64_t descriptor);
|
||||
|
||||
} // namespace Counter
|
||||
|
||||
#endif // SRC_CORE_COUNTERS_COUNTER_H_
|
||||
@@ -0,0 +1,61 @@
|
||||
/* Copyright (c) 2022 Advanced Micro Devices, Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE. */
|
||||
|
||||
#include "src/core/counters/derived/derived_counter.h"
|
||||
|
||||
#pragma GCC diagnostic push
|
||||
#pragma GCC diagnostic ignored "-Wmaybe-uninitialized"
|
||||
|
||||
namespace Counter {
|
||||
|
||||
static std::atomic<uint64_t> COUNTER_COUNTER{0};
|
||||
|
||||
DerivedCounter::DerivedCounter(std::string name, std::string description,
|
||||
std::string gpu_name)
|
||||
: Counter(name, description, gpu_name) {
|
||||
metric_id_ = COUNTER_COUNTER.fetch_add(1, std::memory_order_release);
|
||||
addCounterToCounterMap();
|
||||
}
|
||||
|
||||
DerivedCounter::~DerivedCounter() {
|
||||
for (auto& it : counters_) delete it.second;
|
||||
counters_.clear();
|
||||
}
|
||||
|
||||
uint64_t DerivedCounter::getMetricId() { return metric_id_; }
|
||||
|
||||
std::map<uint64_t, BasicCounter*> *DerivedCounter::getAllCounters() {
|
||||
return &counters_;
|
||||
}
|
||||
|
||||
BasicCounter *DerivedCounter::getBasicCounterFromDerived(uint64_t counter_id) {
|
||||
return counters_[counter_id];
|
||||
}
|
||||
|
||||
void DerivedCounter::addBasicCounter(uint64_t counter_id,
|
||||
BasicCounter *counter) {
|
||||
counters_.emplace(counter_id, counter);
|
||||
}
|
||||
|
||||
@DERIVED_XML_PARSE_RESULT@
|
||||
|
||||
} // namespace Counter
|
||||
|
||||
#pragma GCC diagnostic pop
|
||||
@@ -0,0 +1,64 @@
|
||||
/* Copyright (c) 2022 Advanced Micro Devices, Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE. */
|
||||
|
||||
#ifndef SRC_CORE_COUNTERS_DERIVED_DERIVED_COUNTER_H_
|
||||
#define SRC_CORE_COUNTERS_DERIVED_DERIVED_COUNTER_H_
|
||||
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include <unistd.h>
|
||||
|
||||
#include <atomic>
|
||||
#include <cstdint>
|
||||
#include <functional>
|
||||
#include <map>
|
||||
#include <memory>
|
||||
|
||||
#include "src/core/counters/basic/basic_counter.h"
|
||||
|
||||
namespace Counter {
|
||||
|
||||
class DerivedCounter : Counter {
|
||||
public:
|
||||
std::function<uint64_t()> evaluate_metric;
|
||||
DerivedCounter(std::string name, std::string description,
|
||||
std::string gpu_name);
|
||||
~DerivedCounter();
|
||||
|
||||
uint64_t getMetricId();
|
||||
uint64_t getValue();
|
||||
std::map<uint64_t, BasicCounter*>* getAllCounters();
|
||||
void addBasicCounter(uint64_t counter_id, BasicCounter* counter);
|
||||
BasicCounter* getBasicCounterFromDerived(uint64_t counter_id);
|
||||
|
||||
private:
|
||||
uint64_t metric_id_;
|
||||
uint64_t value_;
|
||||
std::map<uint64_t, BasicCounter*> counters_;
|
||||
};
|
||||
|
||||
static std::map<uint64_t, DerivedCounter> derived_counters;
|
||||
|
||||
uint64_t getDerivedCounter(const char* name, const char* gpu_name);
|
||||
|
||||
} // namespace Counter
|
||||
|
||||
#endif // SRC_CORE_COUNTERS_DERIVED_DERIVED_COUNTER_H_
|
||||
Executable
+427
@@ -0,0 +1,427 @@
|
||||
<metrics>
|
||||
|
||||
<gfx8>
|
||||
<metric name="GPUBusy" expr="100*GRBM_GUI_ACTIVE/GRBM_COUNT" descr="The percentage of time GPU was busy."></metric>
|
||||
<metric name="Wavefronts" expr="SQ_WAVES" descr="Total wavefronts."></metric>
|
||||
<metric name="VALUInsts" expr="SQ_INSTS_VALU/SQ_WAVES" descr="The average number of vector ALU instructions executed per work-item (affected by flow control)."></metric>
|
||||
<metric name="SALUInsts" expr="SQ_INSTS_SALU/SQ_WAVES" descr="The average number of scalar ALU instructions executed per work-item (affected by flow control)."></metric>
|
||||
<metric name="SFetchInsts" expr="SQ_INSTS_SMEM/SQ_WAVES" descr="The average number of scalar fetch instructions from the video memory executed per work-item (affected by flow control)."></metric>
|
||||
<metric name="GDSInsts" expr="SQ_INSTS_GDS/SQ_WAVES" descr="The average number of GDS read or GDS write instructions executed per work item (affected by flow control)."></metric>
|
||||
<metric name="MemUnitBusy" expr="100*max(TA_TA_BUSY,16)/GRBM_GUI_ACTIVE/SE_NUM" descr="The percentage of GPUTime the memory unit is active. The result includes the stall time (MemUnitStalled). This is measured with all extra fetches and writes and any cache or memory effects taken into account. Value range: 0% to 100% (fetch-bound)."></metric>
|
||||
<metric name="ALUStalledByLDS" expr="100*SQ_WAIT_INST_LDS*4/SQ_WAVES/GRBM_GUI_ACTIVE" descr="The percentage of GPUTime ALU units are stalled by the LDS input queue being full or the output queue being not ready. If there are LDS bank conflicts, reduce them. Otherwise, try reducing the number of LDS accesses if possible. Value range: 0% (optimal) to 100% (bad)."></metric>
|
||||
<metric name="TA_BUSY_avr" expr="avr(TA_TA_BUSY,16)" descr="TA block is busy. Average over TA instances."></metric>
|
||||
<metric name="TA_BUSY_max" expr="max(TA_TA_BUSY,16)" descr="TA block is busy. Max over TA instances."></metric>
|
||||
<metric name="TA_BUSY_min" expr="min(TA_TA_BUSY,16)" descr="TA block is busy. Min over TA instances."></metric>
|
||||
<metric name="TA_FLAT_READ_WAVEFRONTS_sum" expr="sum(TA_FLAT_READ_WAVEFRONTS,16)" descr="Number of flat opcode reads processed by the TA. Sum over TA instances."></metric>
|
||||
<metric name="TA_FLAT_WRITE_WAVEFRONTS_sum" expr="sum(TA_FLAT_WRITE_WAVEFRONTS,16)" descr="Number of flat opcode writes processed by the TA. Sum over TA instances."></metric>
|
||||
<metric name="TCC_HIT_sum" expr="sum(TCC_HIT,16)" descr="Number of cache hits. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_MISS_sum" expr="sum(TCC_MISS,16)" descr="Number of cache misses. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_MC_RDREQ_sum" expr="sum(TCC_MC_RDREQ,16)" descr="Number of 32-byte reads. Sum over TCC instaces."></metric>
|
||||
<metric name="TCC_MC_WRREQ_sum" expr="sum(TCC_MC_WRREQ,16)" descr="Number of 32-byte transactions going over the TC_MC_wrreq interface. Sum over TCC instaces."></metric>
|
||||
<metric name="TCC_WRREQ_STALL_max" expr="max(TCC_MC_WRREQ_STALL,16)" descr="Number of cycles a write request was stalled. Max over TCC instances."></metric>
|
||||
<metric name="FETCH_SIZE" expr="(TCC_MC_RDREQ_sum*32)/1024" descr="The total kilobytes fetched from the video memory. This is measured with all extra fetches and any cache or memory effects taken into account."></metric>
|
||||
<metric name="WRITE_SIZE" expr="(TCC_MC_WRREQ_sum*32)/1024" descr="The total kilobytes written to the video memory. This is measured with all extra fetches and any cache or memory effects taken into account."></metric>
|
||||
<metric name="WRITE_REQ_32B" expr="TCC_MC_WRREQ_sum" descr="The total number of 32-byte effective memory writes."></metric>
|
||||
<metric name="VFetchInsts" expr="(SQ_INSTS_VMEM_RD-TA_FLAT_READ_WAVEFRONTS_sum)/SQ_WAVES" descr="The average number of vector fetch instructions from the video memory executed per work-item (affected by flow control). Excludes FLAT instructions that fetch from video memory."></metric>
|
||||
<metric name="VWriteInsts" expr="(SQ_INSTS_VMEM_WR-TA_FLAT_WRITE_WAVEFRONTS_sum)/SQ_WAVES" descr="The average number of vector write instructions to the video memory executed per work-item (affected by flow control). Excludes FLAT instructions that write to video memory."></metric>
|
||||
<metric name="FlatVMemInsts" expr="(SQ_INSTS_FLAT-SQ_INSTS_FLAT_LDS_ONLY)/SQ_WAVES" descr="The average number of FLAT instructions that read from or write to the video memory executed per work item (affected by flow control). Includes FLAT instructions that read from or write to scratch."></metric>
|
||||
<metric name="LDSInsts" expr="(SQ_INSTS_LDS-SQ_INSTS_FLAT_LDS_ONLY)/SQ_WAVES" descr="The average number of LDS read or LDS write instructions executed per work item (affected by flow control). Excludes FLAT instructions that read from or write to LDS."></metric>
|
||||
<metric name="FlatLDSInsts" expr="SQ_INSTS_FLAT_LDS_ONLY/SQ_WAVES" descr="The average number of FLAT instructions that read or write to LDS executed per work item (affected by flow control)."></metric>
|
||||
<metric name="VALUUtilization" expr="100*SQ_THREAD_CYCLES_VALU/(SQ_ACTIVE_INST_VALU*MAX_WAVE_SIZE)" descr="The percentage of active vector ALU threads in a wave. A lower number can mean either more thread divergence in a wave or that the work-group size is not a multiple of 64. Value range: 0% (bad), 100% (ideal - no thread divergence)."></metric>
|
||||
<metric name="VALUBusy" expr="100*SQ_ACTIVE_INST_VALU*4/SIMD_NUM/GRBM_GUI_ACTIVE" descr="The percentage of GPUTime vector ALU instructions are processed. Value range: 0% (bad) to 100% (optimal)."></metric>
|
||||
<metric name="SALUBusy" expr="100*SQ_INST_CYCLES_SALU*4/SIMD_NUM/GRBM_GUI_ACTIVE" descr="The percentage of GPUTime scalar ALU instructions are processed. Value range: 0% (bad) to 100% (optimal)."></metric>
|
||||
<metric name="FetchSize" expr="FETCH_SIZE" descr="The total kilobytes fetched from the video memory. This is measured with all extra fetches and any cache or memory effects taken into account."></metric>
|
||||
<metric name="WriteSize" expr="WRITE_SIZE" descr="The total kilobytes written to the video memory. This is measured with all extra fetches and any cache or memory effects taken into account."></metric>
|
||||
<metric name="MemWrites32B" expr="WRITE_REQ_32B" descr="The total number of effective 32B write transactions to the memory"></metric>
|
||||
<metric name="L2CacheHit" expr="100*sum(TCC_HIT,16)/(sum(TCC_HIT,16)+sum(TCC_MISS,16))" descr="The percentage of fetch, write, atomic, and other instructions that hit the data in L2 cache. Value range: 0% (no hit) to 100% (optimal)."></metric>
|
||||
<metric name="MemUnitStalled" expr="100*max(TCP_TCP_TA_DATA_STALL_CYCLES,16)/GRBM_GUI_ACTIVE/SE_NUM" descr="The percentage of GPUTime the memory unit is stalled. Try reducing the number or size of fetches and writes if possible. Value range: 0% (optimal) to 100% (bad)."></metric>
|
||||
<metric name="WriteUnitStalled" expr="100*TCC_WRREQ_STALL_max/GRBM_GUI_ACTIVE" descr="The percentage of GPUTime the Write unit is stalled. Value range: 0% to 100% (bad)."></metric>
|
||||
<metric name="LDSBankConflict" expr="100*SQ_LDS_BANK_CONFLICT/GRBM_GUI_ACTIVE/CU_NUM" descr="The percentage of GPUTime LDS is stalled by bank conflicts. Value range: 0% (optimal) to 100% (bad)."></metric>
|
||||
</gfx8>
|
||||
|
||||
<gfx906>
|
||||
<metric name="GPUBusy" expr="100*GRBM_GUI_ACTIVE/GRBM_COUNT" descr="The percentage of time GPU was busy."></metric>
|
||||
<metric name="Wavefronts" expr="SQ_WAVES" descr="Total wavefronts."></metric>
|
||||
<metric name="VALUInsts" expr="SQ_INSTS_VALU/SQ_WAVES" descr="The average number of vector ALU instructions executed per work-item (affected by flow control)."></metric>
|
||||
<metric name="SALUInsts" expr="SQ_INSTS_SALU/SQ_WAVES" descr="The average number of scalar ALU instructions executed per work-item (affected by flow control)."></metric>
|
||||
<metric name="SFetchInsts" expr="SQ_INSTS_SMEM/SQ_WAVES" descr="The average number of scalar fetch instructions from the video memory executed per work-item (affected by flow control)."></metric>
|
||||
<metric name="GDSInsts" expr="SQ_INSTS_GDS/SQ_WAVES" descr="The average number of GDS read or GDS write instructions executed per work item (affected by flow control)."></metric>
|
||||
<metric name="MemUnitBusy" expr="100*max(TA_TA_BUSY,16)/GRBM_GUI_ACTIVE/SE_NUM" descr="The percentage of GPUTime the memory unit is active. The result includes the stall time (MemUnitStalled). This is measured with all extra fetches and writes and any cache or memory effects taken into account. Value range: 0% to 100% (fetch-bound)."></metric>
|
||||
<metric name="ALUStalledByLDS" expr="100*SQ_WAIT_INST_LDS*4/SQ_WAVES/GRBM_GUI_ACTIVE" descr="The percentage of GPUTime ALU units are stalled by the LDS input queue being full or the output queue being not ready. If there are LDS bank conflicts, reduce them. Otherwise, try reducing the number of LDS accesses if possible. Value range: 0% (optimal) to 100% (bad)."></metric>
|
||||
<metric name="TA_BUSY_avr" expr="avr(TA_TA_BUSY,16)" descr="TA block is busy. Average over TA instances."></metric>
|
||||
<metric name="TA_BUSY_max" expr="max(TA_TA_BUSY,16)" descr="TA block is busy. Max over TA instances."></metric>
|
||||
<metric name="TA_BUSY_min" expr="min(TA_TA_BUSY,16)" descr="TA block is busy. Min over TA instances."></metric>
|
||||
<metric name="TA_FLAT_READ_WAVEFRONTS_sum" expr="sum(TA_FLAT_READ_WAVEFRONTS,16)" descr="Number of flat opcode reads processed by the TA. Sum over TA instances."></metric>
|
||||
<metric name="TA_FLAT_WRITE_WAVEFRONTS_sum" expr="sum(TA_FLAT_WRITE_WAVEFRONTS,16)" descr="Number of flat opcode writes processed by the TA. Sum over TA instances."></metric>
|
||||
<metric name="TCC_HIT_sum" expr="sum(TCC_HIT,16)" descr="Number of cache hits. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_MISS_sum" expr="sum(TCC_MISS,16)" descr="Number of cache misses. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA_RDREQ_32B_sum" expr="sum(TCC_EA_RDREQ_32B,16)" descr="Number of 32-byte TCC/EA read requests. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA_RDREQ_sum" expr="sum(TCC_EA_RDREQ,16)" descr="Number of TCC/EA read requests (either 32-byte or 64-byte). Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA_WRREQ_sum" expr="sum(TCC_EA_WRREQ,16)" descr="Number of transactions (either 32-byte or 64-byte) going over the TC_EA_wrreq interface. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA_WRREQ_64B_sum" expr="sum(TCC_EA_WRREQ_64B,16)" descr="Number of 64-byte transactions going (64-byte write or CMPSWAP) over the TC_EA_wrreq interface. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_WRREQ_STALL_max" expr="max(TCC_EA_WRREQ_STALL,16)" descr="Number of cycles a write request was stalled. Max over TCC instances."></metric>
|
||||
<metric name="VFetchInsts" expr="(SQ_INSTS_VMEM_RD-TA_FLAT_READ_WAVEFRONTS_sum)/SQ_WAVES" descr="The average number of vector fetch instructions from the video memory executed per work-item (affected by flow control). Excludes FLAT instructions that fetch from video memory."></metric>
|
||||
<metric name="VWriteInsts" expr="(SQ_INSTS_VMEM_WR-TA_FLAT_WRITE_WAVEFRONTS_sum)/SQ_WAVES" descr="The average number of vector write instructions to the video memory executed per work-item (affected by flow control). Excludes FLAT instructions that write to video memory."></metric>
|
||||
<metric name="FlatVMemInsts" expr="(SQ_INSTS_FLAT-SQ_INSTS_FLAT_LDS_ONLY)/SQ_WAVES" descr="The average number of FLAT instructions that read from or write to the video memory executed per work item (affected by flow control). Includes FLAT instructions that read from or write to scratch."></metric>
|
||||
<metric name="LDSInsts" expr="(SQ_INSTS_LDS-SQ_INSTS_FLAT_LDS_ONLY)/SQ_WAVES" descr="The average number of LDS read or LDS write instructions executed per work item (affected by flow control). Excludes FLAT instructions that read from or write to LDS."></metric>
|
||||
<metric name="FlatLDSInsts" expr="SQ_INSTS_FLAT_LDS_ONLY/SQ_WAVES" descr="The average number of FLAT instructions that read or write to LDS executed per work item (affected by flow control)."></metric>
|
||||
<metric name="VALUUtilization" expr="100*SQ_THREAD_CYCLES_VALU/(SQ_ACTIVE_INST_VALU*MAX_WAVE_SIZE)" descr="The percentage of active vector ALU threads in a wave. A lower number can mean either more thread divergence in a wave or that the work-group size is not a multiple of 64. Value range: 0% (bad), 100% (ideal - no thread divergence)."></metric>
|
||||
<metric name="VALUBusy" expr="100*SQ_ACTIVE_INST_VALU*4/SIMD_NUM/GRBM_GUI_ACTIVE" descr="The percentage of GPUTime vector ALU instructions are processed. Value range: 0% (bad) to 100% (optimal)."></metric>
|
||||
<metric name="SALUBusy" expr="100*SQ_INST_CYCLES_SALU*4/SIMD_NUM/GRBM_GUI_ACTIVE" descr="The percentage of GPUTime scalar ALU instructions are processed. Value range: 0% (bad) to 100% (optimal)."></metric>
|
||||
<metric name="FetchSize" expr="FETCH_SIZE" descr="The total kilobytes fetched from the video memory. This is measured with all extra fetches and any cache or memory effects taken into account."></metric>
|
||||
<metric name="WriteSize" expr="WRITE_SIZE" descr="The total kilobytes written to the video memory. This is measured with all extra fetches and any cache or memory effects taken into account."></metric>
|
||||
<metric name="MemWrites32B" expr="WRITE_REQ_32B" descr="The total number of effective 32B write transactions to the memory"></metric>
|
||||
<metric name="L2CacheHit" expr="100*sum(TCC_HIT,16)/(sum(TCC_HIT,16)+sum(TCC_MISS,16))" descr="The percentage of fetch, write, atomic, and other instructions that hit the data in L2 cache. Value range: 0% (no hit) to 100% (optimal)."></metric>
|
||||
<metric name="MemUnitStalled" expr="100*max(TCP_TCP_TA_DATA_STALL_CYCLES,16)/GRBM_GUI_ACTIVE/SE_NUM" descr="The percentage of GPUTime the memory unit is stalled. Try reducing the number or size of fetches and writes if possible. Value range: 0% (optimal) to 100% (bad)."></metric>
|
||||
<metric name="WriteUnitStalled" expr="100*TCC_WRREQ_STALL_max/GRBM_GUI_ACTIVE" descr="The percentage of GPUTime the Write unit is stalled. Value range: 0% to 100% (bad)."></metric>
|
||||
<metric name="LDSBankConflict" expr="100*SQ_LDS_BANK_CONFLICT/GRBM_GUI_ACTIVE/CU_NUM" descr="The percentage of GPUTime LDS is stalled by bank conflicts. Value range: 0% (optimal) to 100% (bad)."></metric>
|
||||
<metric name="TCC_EA1_RDREQ_32B_sum" expr="sum(TCC_EA1_RDREQ_32B,16)" descr="Number of 32-byte TCC/EA read requests. Sum over TCC EA1s."></metric>
|
||||
<metric name="TCC_EA1_RDREQ_sum" expr="sum(TCC_EA1_RDREQ,16)" descr="Number of TCC/EA read requests (either 32-byte or 64-byte). Sum over TCC EA1s."></metric>
|
||||
<metric name="TCC_EA1_WRREQ_sum" expr="sum(TCC_EA1_WRREQ,16)" descr="Number of transactions (either 32-byte or 64-byte) going over the TC_EA_wrreq interface. Sum over TCC EA1s."></metric>
|
||||
<metric name="TCC_EA1_WRREQ_64B_sum" expr="sum(TCC_EA1_WRREQ_64B,16)" descr="Number of 64-byte transactions going (64-byte write or CMPSWAP) over the TC_EA_wrreq interface. Sum over TCC EA1s."></metric>
|
||||
<metric name="TCC_WRREQ1_STALL_max" expr="max(TCC_EA1_WRREQ_STALL,16)" descr="Number of cycles a write request was stalled. Max over TCC instances."></metric>
|
||||
<metric name="RDATA1_SIZE" expr="(TCC_EA1_RDREQ_32B_sum*32+(TCC_EA1_RDREQ_sum-TCC_EA1_RDREQ_32B_sum)*64)" descr="The total kilobytes fetched from the video memory. This is measured on EA1s."></metric>
|
||||
<metric name="WDATA1_SIZE" expr="((TCC_EA1_WRREQ_sum-TCC_EA1_WRREQ_64B_sum)*32+TCC_EA1_WRREQ_64B_sum*64)" descr="The total kilobytes written to the video memory. This is measured on EA1s."></metric>
|
||||
<metric name="FETCH_SIZE" expr="(TCC_EA_RDREQ_32B_sum*32+(TCC_EA_RDREQ_sum-TCC_EA_RDREQ_32B_sum)*64+RDATA1_SIZE)/1024" descr="The total kilobytes fetched from the video memory. This is measured with all extra fetches and any cache or memory effects taken into account."></metric>
|
||||
<metric name="WRITE_SIZE" expr="((TCC_EA_WRREQ_sum-TCC_EA_WRREQ_64B_sum)*32+TCC_EA_WRREQ_64B_sum*64+WDATA1_SIZE)/1024" descr="The total kilobytes written to the video memory. This is measured with all extra fetches and any cache or memory effects taken into account."></metric>
|
||||
<metric name="WRITE_REQ_32B" expr="(TCC_EA_WRREQ_sum-TCC_EA_WRREQ_64B_sum)+(TCC_EA1_WRREQ_sum-TCC_EA1_WRREQ_64B_sum)+(TCC_EA_WRREQ_64B_sum+TCC_EA1_WRREQ_64B_sum)*2" descr="The total number of 32-byte effective memory writes."></metric>
|
||||
</gfx906>
|
||||
|
||||
<gfx908>
|
||||
<metric name="GPUBusy" expr="100*GRBM_GUI_ACTIVE/GRBM_COUNT" descr="The percentage of time GPU was busy."></metric>
|
||||
<metric name="Wavefronts" expr="SQ_WAVES" descr="Total wavefronts."></metric>
|
||||
<metric name="VALUInsts" expr="SQ_INSTS_VALU/SQ_WAVES" descr="The average number of vector ALU instructions executed per work-item (affected by flow control)."></metric>
|
||||
<metric name="SALUInsts" expr="SQ_INSTS_SALU/SQ_WAVES" descr="The average number of scalar ALU instructions executed per work-item (affected by flow control)."></metric>
|
||||
<metric name="SFetchInsts" expr="SQ_INSTS_SMEM/SQ_WAVES" descr="The average number of scalar fetch instructions from the video memory executed per work-item (affected by flow control)."></metric>
|
||||
<metric name="GDSInsts" expr="SQ_INSTS_GDS/SQ_WAVES" descr="The average number of GDS read or GDS write instructions executed per work item (affected by flow control)."></metric>
|
||||
<metric name="MemUnitBusy" expr="100*max(TA_TA_BUSY,16)/GRBM_GUI_ACTIVE/SE_NUM" descr="The percentage of GPUTime the memory unit is active. The result includes the stall time (MemUnitStalled). This is measured with all extra fetches and writes and any cache or memory effects taken into account. Value range: 0% to 100% (fetch-bound)."></metric>
|
||||
<metric name="ALUStalledByLDS" expr="100*SQ_WAIT_INST_LDS*4/SQ_WAVES/GRBM_GUI_ACTIVE" descr="The percentage of GPUTime ALU units are stalled by the LDS input queue being full or the output queue being not ready. If there are LDS bank conflicts, reduce them. Otherwise, try reducing the number of LDS accesses if possible. Value range: 0% (optimal) to 100% (bad)."></metric>
|
||||
<metric name="TA_BUSY_avr" expr="avr(TA_TA_BUSY,16)" descr="TA block is busy. Average over TA instances."></metric>
|
||||
<metric name="TA_BUSY_max" expr="max(TA_TA_BUSY,16)" descr="TA block is busy. Max over TA instances."></metric>
|
||||
<metric name="TA_BUSY_min" expr="min(TA_TA_BUSY,16)" descr="TA block is busy. Min over TA instances."></metric>
|
||||
<metric name="TA_FLAT_READ_WAVEFRONTS_sum" expr="sum(TA_FLAT_READ_WAVEFRONTS,16)" descr="Number of flat opcode reads processed by the TA. Sum over TA instances."></metric>
|
||||
<metric name="TA_FLAT_WRITE_WAVEFRONTS_sum" expr="sum(TA_FLAT_WRITE_WAVEFRONTS,16)" descr="Number of flat opcode writes processed by the TA. Sum over TA instances."></metric>
|
||||
<metric name="FETCH_SIZE" expr="(TCC_EA_RDREQ_32B_sum*32+(TCC_EA_RDREQ_sum-TCC_EA_RDREQ_32B_sum)*64)/1024" descr="The total kilobytes fetched from the video memory. This is measured with all extra fetches and any cache or memory effects taken into account."></metric>
|
||||
<metric name="WRITE_SIZE" expr="((TCC_EA_WRREQ_sum-TCC_EA_WRREQ_64B_sum)*32+TCC_EA_WRREQ_64B_sum*64)/1024" descr="The total kilobytes written to the video memory. This is measured with all extra fetches and any cache or memory effects taken into account."></metric>
|
||||
<metric name="WRITE_REQ_32B" expr="TCC_EA_WRREQ_64B_sum*2+(TCC_EA_WRREQ_sum-TCC_EA_WRREQ_64B_sum)" descr="The total number of 32-byte effective memory writes."></metric>
|
||||
<metric name="VFetchInsts" expr="(SQ_INSTS_VMEM_RD-TA_FLAT_READ_WAVEFRONTS_sum)/SQ_WAVES" descr="The average number of vector fetch instructions from the video memory executed per work-item (affected by flow control). Excludes FLAT instructions that fetch from video memory."></metric>
|
||||
<metric name="VWriteInsts" expr="(SQ_INSTS_VMEM_WR-TA_FLAT_WRITE_WAVEFRONTS_sum)/SQ_WAVES" descr="The average number of vector write instructions to the video memory executed per work-item (affected by flow control). Excludes FLAT instructions that write to video memory."></metric>
|
||||
<metric name="FlatVMemInsts" expr="(SQ_INSTS_FLAT-SQ_INSTS_FLAT_LDS_ONLY)/SQ_WAVES" descr="The average number of FLAT instructions that read from or write to the video memory executed per work item (affected by flow control). Includes FLAT instructions that read from or write to scratch."></metric>
|
||||
<metric name="LDSInsts" expr="(SQ_INSTS_LDS-SQ_INSTS_FLAT_LDS_ONLY)/SQ_WAVES" descr="The average number of LDS read or LDS write instructions executed per work item (affected by flow control). Excludes FLAT instructions that read from or write to LDS."></metric>
|
||||
<metric name="FlatLDSInsts" expr="SQ_INSTS_FLAT_LDS_ONLY/SQ_WAVES" descr="The average number of FLAT instructions that read or write to LDS executed per work item (affected by flow control)."></metric>
|
||||
<metric name="VALUUtilization" expr="100*SQ_THREAD_CYCLES_VALU/(SQ_ACTIVE_INST_VALU*MAX_WAVE_SIZE)" descr="The percentage of active vector ALU threads in a wave. A lower number can mean either more thread divergence in a wave or that the work-group size is not a multiple of 64. Value range: 0% (bad), 100% (ideal - no thread divergence)."></metric>
|
||||
<metric name="VALUBusy" expr="100*SQ_ACTIVE_INST_VALU*4/SIMD_NUM/GRBM_GUI_ACTIVE" descr="The percentage of GPUTime vector ALU instructions are processed. Value range: 0% (bad) to 100% (optimal)."></metric>
|
||||
<metric name="SALUBusy" expr="100*SQ_INST_CYCLES_SALU*4/SIMD_NUM/GRBM_GUI_ACTIVE" descr="The percentage of GPUTime scalar ALU instructions are processed. Value range: 0% (bad) to 100% (optimal)."></metric>
|
||||
<metric name="FetchSize" expr="FETCH_SIZE" descr="The total kilobytes fetched from the video memory. This is measured with all extra fetches and any cache or memory effects taken into account."></metric>
|
||||
<metric name="WriteSize" expr="WRITE_SIZE" descr="The total kilobytes written to the video memory. This is measured with all extra fetches and any cache or memory effects taken into account."></metric>
|
||||
<metric name="MemWrites32B" expr="WRITE_REQ_32B" descr="The total number of effective 32B write transactions to the memory"></metric>
|
||||
<metric name="L2CacheHit" expr="100*sum(TCC_HIT,16)/(sum(TCC_HIT,16)+sum(TCC_MISS,16))" descr="The percentage of fetch, write, atomic, and other instructions that hit the data in L2 cache. Value range: 0% (no hit) to 100% (optimal)."></metric>
|
||||
<metric name="MemUnitStalled" expr="100*max(TCP_TCP_TA_DATA_STALL_CYCLES,16)/GRBM_GUI_ACTIVE/SE_NUM" descr="The percentage of GPUTime the memory unit is stalled. Try reducing the number or size of fetches and writes if possible. Value range: 0% (optimal) to 100% (bad)."></metric>
|
||||
<metric name="WriteUnitStalled" expr="100*TCC_WRREQ_STALL_max/GRBM_GUI_ACTIVE" descr="The percentage of GPUTime the Write unit is stalled. Value range: 0% to 100% (bad)."></metric>
|
||||
<metric name="LDSBankConflict" expr="100*SQ_LDS_BANK_CONFLICT/GRBM_GUI_ACTIVE/CU_NUM" descr="The percentage of GPUTime LDS is stalled by bank conflicts. Value range: 0% (optimal) to 100% (bad)."></metric>
|
||||
<metric name="TCC_HIT_sum" expr="sum(TCC_HIT,32)" descr="Number of cache hits. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_MISS_sum" expr="sum(TCC_MISS,32)" descr="Number of cache misses. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA_RDREQ_32B_sum" expr="sum(TCC_EA_RDREQ_32B,32)" descr="Number of 32-byte TCC/EA read requests. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA_RDREQ_sum" expr="sum(TCC_EA_RDREQ,32)" descr="Number of TCC/EA read requests (either 32-byte or 64-byte). Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA_WRREQ_sum" expr="sum(TCC_EA_WRREQ,32)" descr="Number of transactions (either 32-byte or 64-byte) going over the TC_EA_wrreq interface. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA_WRREQ_64B_sum" expr="sum(TCC_EA_WRREQ_64B,32)" descr="Number of 64-byte transactions going (64-byte write or CMPSWAP) over the TC_EA_wrreq interface. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_WRREQ_STALL_max" expr="max(TCC_EA_WRREQ_STALL,32)" descr="Number of cycles a write request was stalled. Max over TCC instances."></metric>
|
||||
</gfx908>
|
||||
|
||||
<gfx90a>
|
||||
<metric name="GPUBusy" expr="100*GRBM_GUI_ACTIVE/GRBM_COUNT" descr="The percentage of time GPU was busy."></metric>
|
||||
<metric name="Wavefronts" expr="SQ_WAVES" descr="Total wavefronts."></metric>
|
||||
<metric name="VALUInsts" expr="SQ_INSTS_VALU/SQ_WAVES" descr="The average number of vector ALU instructions executed per work-item (affected by flow control)."></metric>
|
||||
<metric name="SALUInsts" expr="SQ_INSTS_SALU/SQ_WAVES" descr="The average number of scalar ALU instructions executed per work-item (affected by flow control)."></metric>
|
||||
<metric name="SFetchInsts" expr="SQ_INSTS_SMEM/SQ_WAVES" descr="The average number of scalar fetch instructions from the video memory executed per work-item (affected by flow control)."></metric>
|
||||
<metric name="GDSInsts" expr="SQ_INSTS_GDS/SQ_WAVES" descr="The average number of GDS read or GDS write instructions executed per work item (affected by flow control)."></metric>
|
||||
<metric name="MemUnitBusy" expr="100*max(TA_TA_BUSY,16)/GRBM_GUI_ACTIVE/SE_NUM" descr="The percentage of GPUTime the memory unit is active. The result includes the stall time (MemUnitStalled). This is measured with all extra fetches and writes and any cache or memory effects taken into account. Value range: 0% to 100% (fetch-bound)."></metric>
|
||||
<metric name="ALUStalledByLDS" expr="100*SQ_WAIT_INST_LDS*4/SQ_WAVES/GRBM_GUI_ACTIVE" descr="The percentage of GPUTime ALU units are stalled by the LDS input queue being full or the output queue being not ready. If there are LDS bank conflicts, reduce them. Otherwise, try reducing the number of LDS accesses if possible. Value range: 0% (optimal) to 100% (bad)."></metric>
|
||||
<metric name="VFetchInsts" expr="(SQ_INSTS_VMEM_RD-TA_FLAT_READ_WAVEFRONTS_sum)/SQ_WAVES" descr="The average number of vector fetch instructions from the video memory executed per work-item (affected by flow control). Excludes FLAT instructions that fetch from video memory."></metric>
|
||||
<metric name="VWriteInsts" expr="(SQ_INSTS_VMEM_WR-TA_FLAT_WRITE_WAVEFRONTS_sum)/SQ_WAVES" descr="The average number of vector write instructions to the video memory executed per work-item (affected by flow control). Excludes FLAT instructions that write to video memory."></metric>
|
||||
<metric name="FlatVMemInsts" expr="(SQ_INSTS_FLAT-SQ_INSTS_FLAT_LDS_ONLY)/SQ_WAVES" descr="The average number of FLAT instructions that read from or write to the video memory executed per work item (affected by flow control). Includes FLAT instructions that read from or write to scratch."></metric>
|
||||
<metric name="LDSInsts" expr="(SQ_INSTS_LDS-SQ_INSTS_FLAT_LDS_ONLY)/SQ_WAVES" descr="The average number of LDS read or LDS write instructions executed per work item (affected by flow control). Excludes FLAT instructions that read from or write to LDS."></metric>
|
||||
<metric name="FlatLDSInsts" expr="SQ_INSTS_FLAT_LDS_ONLY/SQ_WAVES" descr="The average number of FLAT instructions that read or write to LDS executed per work item (affected by flow control)."></metric>
|
||||
<metric name="VALUUtilization" expr="100*SQ_THREAD_CYCLES_VALU/(SQ_ACTIVE_INST_VALU*MAX_WAVE_SIZE)" descr="The percentage of active vector ALU threads in a wave. A lower number can mean either more thread divergence in a wave or that the work-group size is not a multiple of 64. Value range: 0% (bad), 100% (ideal - no thread divergence)."></metric>
|
||||
<metric name="VALUBusy" expr="100*SQ_ACTIVE_INST_VALU*4/SIMD_NUM/GRBM_GUI_ACTIVE" descr="The percentage of GPUTime vector ALU instructions are processed. Value range: 0% (bad) to 100% (optimal)."></metric>
|
||||
<metric name="SALUBusy" expr="100*SQ_INST_CYCLES_SALU*4/SIMD_NUM/GRBM_GUI_ACTIVE" descr="The percentage of GPUTime scalar ALU instructions are processed. Value range: 0% (bad) to 100% (optimal)."></metric>
|
||||
<metric name="FetchSize" expr="FETCH_SIZE" descr="The total kilobytes fetched from the video memory. This is measured with all extra fetches and any cache or memory effects taken into account."></metric>
|
||||
<metric name="WriteSize" expr="WRITE_SIZE" descr="The total kilobytes written to the video memory. This is measured with all extra fetches and any cache or memory effects taken into account."></metric>
|
||||
<metric name="MemWrites32B" expr="WRITE_REQ_32B" descr="The total number of effective 32B write transactions to the memory"></metric>
|
||||
<metric name="L2CacheHit" expr="100*sum(TCC_HIT,16)/(sum(TCC_HIT,16)+sum(TCC_MISS,16))" descr="The percentage of fetch, write, atomic, and other instructions that hit the data in L2 cache. Value range: 0% (no hit) to 100% (optimal)."></metric>
|
||||
<metric name="MemUnitStalled" expr="100*max(TCP_TCP_TA_DATA_STALL_CYCLES,16)/GRBM_GUI_ACTIVE/SE_NUM" descr="The percentage of GPUTime the memory unit is stalled. Try reducing the number or size of fetches and writes if possible. Value range: 0% (optimal) to 100% (bad)."></metric>
|
||||
<metric name="WriteUnitStalled" expr="100*TCC_WRREQ_STALL_max/GRBM_GUI_ACTIVE" descr="The percentage of GPUTime the Write unit is stalled. Value range: 0% to 100% (bad)."></metric>
|
||||
<metric name="LDSBankConflict" expr="100*SQ_LDS_BANK_CONFLICT/GRBM_GUI_ACTIVE/CU_NUM" descr="The percentage of GPUTime LDS is stalled by bank conflicts. Value range: 0% (optimal) to 100% (bad)."></metric>
|
||||
<metric name="TA_BUSY_avr" expr="avr(TA_TA_BUSY,16)" descr="TA block is busy. Average over TA instances."></metric>
|
||||
<metric name="TA_BUSY_max" expr="max(TA_TA_BUSY,16)" descr="TA block is busy. Max over TA instances."></metric>
|
||||
<metric name="TA_BUSY_min" expr="min(TA_TA_BUSY,16)" descr="TA block is busy. Min over TA instances."></metric>
|
||||
<metric name="TA_TA_BUSY_sum" expr="sum(TA_TA_BUSY,16)" descr="TA block is busy. Perf_Windowing not supported for this counter. Sum over TA instances."></metric>
|
||||
<metric name="TA_TOTAL_WAVEFRONTS_sum" expr="sum(TA_TOTAL_WAVEFRONTS,16)" descr="Total number of wavefronts processed by TA. Sum over TA instances."></metric>
|
||||
<metric name="TA_ADDR_STALLED_BY_TC_CYCLES_sum" expr="sum(TA_ADDR_STALLED_BY_TC_CYCLES,16)" descr="Number of cycles addr path stalled by TC. Perf_Windowing not supported for this counter. Sum over TA instances."></metric>
|
||||
<metric name="TA_ADDR_STALLED_BY_TD_CYCLES_sum" expr="sum(TA_ADDR_STALLED_BY_TD_CYCLES,16)" descr="Number of cycles addr path stalled by TD. Perf_Windowing not supported for this counter. Sum over TA instances."></metric>
|
||||
<metric name="TA_DATA_STALLED_BY_TC_CYCLES_sum" expr="sum(TA_DATA_STALLED_BY_TC_CYCLES,16)" descr="Number of cycles data path stalled by TC. Perf_Windowing not supported for this counter. Sum over TA instances."></metric>
|
||||
<metric name="TA_FLAT_WAVEFRONTS_sum" expr="sum(TA_FLAT_WAVEFRONTS,16)" descr="Number of flat opcode wavfronts processed by the TA. Sum over TA instances."></metric>
|
||||
<metric name="TA_FLAT_READ_WAVEFRONTS_sum" expr="sum(TA_FLAT_READ_WAVEFRONTS,16)" descr="Number of flat opcode reads processed by the TA. Sum over TA instances."></metric>
|
||||
<metric name="TA_FLAT_WRITE_WAVEFRONTS_sum" expr="sum(TA_FLAT_WRITE_WAVEFRONTS,16)" descr="Number of flat opcode writes processed by the TA. Sum over TA instances."></metric>
|
||||
<metric name="TA_FLAT_ATOMIC_WAVEFRONTS_sum" expr="sum(TA_FLAT_ATOMIC_WAVEFRONTS,16)" descr="Number of flat opcode atomics processed by the TA. Sum over TA instances."></metric>
|
||||
<metric name="TA_BUFFER_WAVEFRONTS_sum" expr="sum(TA_BUFFER_WAVEFRONTS,16)" descr="Number of buffer wavefronts processed by TA. Sum over TA instances."></metric>
|
||||
<metric name="TA_BUFFER_READ_WAVEFRONTS_sum" expr="sum(TA_BUFFER_READ_WAVEFRONTS,16)" descr="Number of buffer read wavefronts processed by TA. Sum over TA instances."></metric>
|
||||
<metric name="TA_BUFFER_WRITE_WAVEFRONTS_sum" expr="sum(TA_BUFFER_WRITE_WAVEFRONTS,16)" descr="Number of buffer write wavefronts processed by TA. Sum over TA instances."></metric>
|
||||
<metric name="TA_BUFFER_ATOMIC_WAVEFRONTS_sum" expr="sum(TA_BUFFER_ATOMIC_WAVEFRONTS,16)" descr="Number of buffer atomic wavefronts processed by TA. Sum over TA instances."></metric>
|
||||
<metric name="TA_BUFFER_TOTAL_CYCLES_sum" expr="sum(TA_BUFFER_TOTAL_CYCLES,16)" descr="Number of buffer cycles issued to TC. Sum over TA instances."></metric>
|
||||
<metric name="TA_BUFFER_COALESCED_READ_CYCLES_sum" expr="sum(TA_BUFFER_COALESCED_READ_CYCLES,16)" descr="Number of buffer coalesced read cycles issued to TC. Sum over TA instances."></metric>
|
||||
<metric name="TA_BUFFER_COALESCED_WRITE_CYCLES_sum" expr="sum(TA_BUFFER_COALESCED_WRITE_CYCLES,16)" descr="Number of buffer coalesced write cycles issued to TC. Sum over TA instances."></metric>
|
||||
<metric name="TD_TD_BUSY_sum" expr="sum(TD_TD_BUSY,16)" descr="TD is processing or waiting for data. Perf_Windowing not supported for this counter. Sum over TD instances."></metric>
|
||||
<metric name="TD_TC_STALL_sum" expr="sum(TD_TC_STALL,16)" descr="TD is stalled waiting for TC data. Sum over TD instances."></metric>
|
||||
<metric name="TD_LOAD_WAVEFRONT_sum" expr="sum(TD_LOAD_WAVEFRONT,16)" descr="Count the wavefronts with opcode = load, include atomics and store. Sum over TD instances."></metric>
|
||||
<metric name="TD_ATOMIC_WAVEFRONT_sum" expr="sum(TD_ATOMIC_WAVEFRONT,16)" descr="Count the wavefronts with opcode = atomic. Sum over TD instances."></metric>
|
||||
<metric name="TD_STORE_WAVEFRONT_sum" expr="sum(TD_STORE_WAVEFRONT,16)" descr="Count the wavefronts with opcode = store. Sum over TD instances."></metric>
|
||||
<metric name="TD_COALESCABLE_WAVEFRONT_sum" expr="sum(TD_COALESCABLE_WAVEFRONT,16)" descr="Count wavefronts that TA finds coalescable. Sum over TD instances."></metric>
|
||||
<metric name="TD_SPI_STALL_sum" expr="sum(TD_SPI_STALL,16)" descr="TD is stalled SPI vinit, sum of TCP instances"></metric>
|
||||
<metric name="TCP_GATE_EN1_sum" expr="sum(TCP_GATE_EN1,16)" descr="TCP interface clocks are turned on. Not Windowed. Sum over TCP instances."></metric>
|
||||
<metric name="TCP_GATE_EN2_sum" expr="sum(TCP_GATE_EN2,16)" descr="TCP core clocks are turned on. Not Windowed. Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TD_TCP_STALL_CYCLES_sum" expr="sum(TCP_TD_TCP_STALL_CYCLES,16)" descr="TD stalls TCP. Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TCR_TCP_STALL_CYCLES_sum" expr="sum(TCP_TCR_TCP_STALL_CYCLES,16)" descr="TCR stalls TCP_TCR_req interface. Sum over TCP instances."></metric>
|
||||
<metric name="TCP_READ_TAGCONFLICT_STALL_CYCLES_sum" expr="sum(TCP_READ_TAGCONFLICT_STALL_CYCLES,16)" descr="Tagram conflict stall on a read. Sum over TCP instances."></metric>
|
||||
<metric name="TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum" expr="sum(TCP_WRITE_TAGCONFLICT_STALL_CYCLES,16)" descr="Tagram conflict stall on a write. Sum over TCP instances."></metric>
|
||||
<metric name="TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum" expr="sum(TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES,16)" descr="Tagram conflict stall on an atomic. Sum over TCP instances."></metric>
|
||||
<metric name="TCP_VOLATILE_sum" expr="sum(TCP_VOLATILE,16)" descr="Total number of L1 volatile pixels/buffers from TA. Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TOTAL_ACCESSES_sum" expr="sum(TCP_TOTAL_ACCESSES,16)" descr="Total number of pixels/buffers from TA. Equals TCP_PERF_SEL_TOTAL_READ+TCP_PERF_SEL_TOTAL_NONREAD. Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TOTAL_READ_sum" expr="sum(TCP_TOTAL_READ,16)" descr="Total number of read pixels/buffers from TA. Equals TCP_PERF_SEL_TOTAL_HIT_LRU_READ + TCP_PERF_SEL_TOTAL_MISS_LRU_READ + TCP_PERF_SEL_TOTAL_MISS_EVICT_READ. Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TOTAL_WRITE_sum" expr="sum(TCP_TOTAL_WRITE,16)" descr="Total number of local write pixels/buffers from TA. Equals TCP_PERF_SEL_TOTAL_MISS_LRU_WRITE+ TCP_PERF_SEL_TOTAL_MISS_EVICT_WRITE. Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TOTAL_ATOMIC_WITH_RET_sum" expr="sum(TCP_TOTAL_ATOMIC_WITH_RET,16)" descr="Total number of atomic with return pixels/buffers from TA. Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TOTAL_ATOMIC_WITHOUT_RET_sum" expr="sum(TCP_TOTAL_ATOMIC_WITHOUT_RET,16)" descr="Total number of atomic without return pixels/buffers from TA Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TOTAL_WRITEBACK_INVALIDATES_sum" expr="sum(TCP_TOTAL_WRITEBACK_INVALIDATES,16)" descr="Total number of cache invalidates. Equals TCP_PERF_SEL_TOTAL_WBINVL1+ TCP_PERF_SEL_TOTAL_WBINVL1_VOL+ TCP_PERF_SEL_CP_TCP_INVALIDATE+ TCP_PERF_SEL_SQ_TCP_INVALIDATE_VOL. Not Windowed. Sum over TCP instances."></metric>
|
||||
<metric name="TCP_UTCL1_REQUEST_sum" expr="sum(TCP_UTCL1_REQUEST,16)" descr="Total CLIENT_UTCL1 NORMAL requests Sum over TCP instances."></metric>
|
||||
<metric name="TCP_UTCL1_TRANSLATION_MISS_sum" expr="sum(TCP_UTCL1_TRANSLATION_MISS,16)" descr="Total utcl1 translation misses Sum over TCP instances."></metric>
|
||||
<metric name="TCP_UTCL1_TRANSLATION_HIT_sum" expr="sum(TCP_UTCL1_TRANSLATION_HIT,16)" descr="Total utcl1 translation hits Sum over TCP instances."></metric>
|
||||
<metric name="TCP_UTCL1_PERMISSION_MISS_sum" expr="sum(TCP_UTCL1_PERMISSION_MISS,16)" descr="Total utcl1 permission misses Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TOTAL_CACHE_ACCESSES_sum" expr="sum(TCP_TOTAL_CACHE_ACCESSES,16)" descr="Count of total cache line (tag) accesses (includes hits and misses). Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TCP_LATENCY_sum" expr="sum(TCP_TCP_LATENCY,16)" descr="Total TCP wave latency (from first clock of wave entering to first clock of wave leaving), divide by TA_TCP_STATE_READ to avg wave latency Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TA_TCP_STATE_READ_sum" expr="sum(TCP_TA_TCP_STATE_READ,16)" descr="Number of state reads Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TCC_READ_REQ_LATENCY_sum" expr="sum(TCP_TCC_READ_REQ_LATENCY,16)" descr="Total TCP->TCC request latency for reads and atomics with return. Not Windowed. Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TCC_WRITE_REQ_LATENCY_sum" expr="sum(TCP_TCC_WRITE_REQ_LATENCY,16)" descr="Total TCP->TCC request latency for writes and atomics without return. Not Windowed. Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TCC_READ_REQ_sum" expr="sum(TCP_TCC_READ_REQ,16)" descr="Total read requests from TCP to all TCCs Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TCC_WRITE_REQ_sum" expr="sum(TCP_TCC_WRITE_REQ,16)" descr="Total write requests from TCP to all TCCs Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TCC_ATOMIC_WITH_RET_REQ_sum" expr="sum(TCP_TCC_ATOMIC_WITH_RET_REQ,16)" descr="Total atomic with return requests from TCP to all TCCs Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum" expr="sum(TCP_TCC_ATOMIC_WITHOUT_RET_REQ,16)" descr="Total atomic without return requests from TCP to all TCCs Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TCC_NC_READ_REQ_sum" expr="sum(TCP_TCC_NC_READ_REQ,16)" descr="Total read requests with NC mtype from this TCP to all TCCs Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TCC_NC_WRITE_RWriteUnitStalledQ_sum" expr="sum(TCP_TCC_RW_READ_REQ,16)" descr="Total write requests with RW mtype from this TCP to all TCCs. Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TCC_RW_WRITE_REQ_sum" expr="sum(TCP_TCC_RW_WRITE_REQ,16)" descr="Total write requests with RW mtype from this TCP to all TCCs. Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TCC_RW_ATOMIC_REQ_sum" expr="sum(TCP_TCC_RW_ATOMIC_REQ,16)" descr="Total atomic requests with RW mtype from this TCP to all TCCs. Sum over TCP instances."></metric>
|
||||
<metric name="TCP_PENDING_STALL_CYCLES_sum" expr="sum(TCP_PENDING_STALL_CYCLES,16)" descr="Stall due to data pending from L2. Sum over TCP instances."></metric>
|
||||
<metric name="TCA_CYCLE_sum" expr="sum(TCA_CYCLE,16)" descr="Number of cycles. Sum over all TCA instances "></metric>
|
||||
<metric name="TCA_BUSY_sum" expr="sum(TCA_BUSY,16)" descr="Number of cycles we have a request pending. Sum over all TCA instances."></metric>
|
||||
<metric name="TCC_BUSY_avr" expr="avr(TCC_BUSY,32)" descr="TCC_BUSY avr over all memory channels."></metric>
|
||||
<metric name="TCC_WRREQ_STALL_max" expr="max(TCC_EA_WRREQ_STALL,32)" descr="Number of cycles a write request was stalled. Max over TCC instances."></metric>
|
||||
<metric name="TCC_CYCLE_sum" expr="sum(TCC_CYCLE,32)" descr="Number of cycles. Not windowable. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_BUSY_sum" expr="sum(TCC_BUSY,32)" descr="Number of cycles we have a request pending. Not windowable. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_REQ_sum" expr="sum(TCC_REQ,32)" descr="Number of requests of all types. This is measured at the tag block. This may be more than the number of requests arriving at the TCC, but it is a good indication of the total amount of work that needs to be performed. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_STREAMING_REQ_sum" expr="sum(TCC_STREAMING_REQ,32)" descr="Number of streaming requests. This is measured at the tag block. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_NC_REQ_sum" expr="sum(TCC_NC_REQ,32)" descr="The number of noncoherently cached requests. This is measured at the tag block. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_UC_REQ_sum" expr="sum(TCC_UC_REQ,32)" descr="The number of uncached requests. This is measured at the tag block. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_CC_REQ_sum" expr="sum(TCC_CC_REQ,32)" descr="The number of coherently cached requests. This is measured at the tag block. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_RW_REQ_sum" expr="sum(TCC_RW_REQ,32)" descr="The number of RW requests. This is measured at the tag block. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_PROBE_sum" expr="sum(TCC_PROBE,32)" descr="Number of probe requests. Not windowable. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_PROBE_ALL_sum" expr="sum(TCC_PROBE_ALL,32)" descr="Number of external probe requests with with EA_TCC_preq_all== 1. Not windowable. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_READ_sum" expr="sum(TCC_READ,32)" descr="Number of read requests. Compressed reads are included in this, but metadata reads are not included. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_WRITE_sum" expr="sum(TCC_WRITE,32)" descr="Number of write requests. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_ATOMIC_sum" expr="sum(TCC_ATOMIC,32)" descr="Number of atomic requests of all types. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_HIT_sum" expr="sum(TCC_HIT,32)" descr="Number of cache hits. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_MISS_sum" expr="sum(TCC_MISS,32)" descr="Number of cache misses. UC reads count as misses. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_WRITEBACK_sum" expr="sum(TCC_WRITEBACK,32)" descr="Number of lines written back to main memory. This includes writebacks of dirty lines and uncached write/atomic requests. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA_WRREQ_sum" expr="sum(TCC_EA_WRREQ,32)" descr="Number of transactions (either 32-byte or 64-byte) going over the TC_EA_wrreq interface. Atomics may travel over the same interface and are generally classified as write requests. This does not include probe commands. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA_WRREQ_64B_sum" expr="sum(TCC_EA_WRREQ_64B,32)" descr="Number of 64-byte transactions going (64-byte write or CMPSWAP) over the TC_EA_wrreq interface. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA_WR_UNCACHED_32B_sum" expr="sum(TCC_EA_WR_UNCACHED_32B,32)" descr="Number of 32-byte write/atomic going over the TC_EA_wrreq interface due to uncached traffic. Note that CC mtypes can produce uncached requests, and those are included in this. A 64-byte request will be counted as 2. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA_WRREQ_STALL_sum" expr="sum(TCC_EA_WRREQ_STALL,32)" descr="Number of cycles a write request was stalled. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA_WRREQ_IO_CREDIT_STALL_sum" expr="sum(TCC_EA_WRREQ_IO_CREDIT_STALL,32)" descr="Number of cycles a EA write request was stalled because the interface was out of IO credits. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA_WRREQ_GMI_CREDIT_STALL_sum" expr="sum(TCC_EA_WRREQ_GMI_CREDIT_STALL,32)" descr="Number of cycles a EA write request was stalled because the interface was out of GMI credits. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum" expr="sum(TCC_EA_WRREQ_DRAM_CREDIT_STALL,32)" descr="Number of cycles a EA write request was stalled because the interface was out of DRAM credits. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_TOO_MANY_EA_WRREQS_STALL_sum" expr="sum(TCC_TOO_MANY_EA_WRREQS_STALL,32)" descr="Number of cycles the TCC could not send a EA write request because it already reached its maximum number of pending EA write requests. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA_WRREQ_LEVEL_sum" expr="sum(TCC_EA_WRREQ_LEVEL,32)" descr="The sum of the number of EA write requests in flight. This is primarily meant for measure average EA write latency. Average write latency = TCC_PERF_SEL_EA_WRREQ_LEVEL/TCC_PERF_SEL_EA_WRREQ. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA_RDREQ_LEVEL_sum" expr="sum(TCC_EA_RDREQ_LEVEL,32)" descr="The sum of the number of TCC/EA read requests in flight. This is primarily meant for measure average EA read latency. Average read latency = TCC_PERF_SEL_EA_RDREQ_LEVEL/TCC_PERF_SEL_EA_RDREQ. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA_ATOMIC_sum" expr="sum(TCC_EA_ATOMIC,32)" descr="Number of transactions going over the TC_EA_wrreq interface that are actually atomic requests. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA_ATOMIC_LEVEL_sum" expr="sum(TCC_EA_ATOMIC_LEVEL,32)" descr="The sum of the number of EA atomics in flight. This is primarily meant for measure average EA atomic latency. Average atomic latency = TCC_PERF_SEL_EA_WRREQ_ATOMIC_LEVEL/TCC_PERF_SEL_EA_WRREQ_ATOMIC. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA_RDREQ_sum" expr="sum(TCC_EA_RDREQ,32)" descr="Number of TCC/EA read requests (either 32-byte or 64-byte) Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA_RDREQ_32B_sum" expr="sum(TCC_EA_RDREQ_32B,32)" descr="Number of 32-byte TCC/EA read requests Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA_RD_UNCACHED_32B_sum" expr="sum(TCC_EA_RD_UNCACHED_32B,32)" descr="Number of 32-byte TCC/EA read due to uncached traffic. A 64-byte request will be counted as 2 Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA_RDREQ_IO_CREDIT_STALL_sum" expr="sum(TCC_EA_RDREQ_IO_CREDIT_STALL,32)" descr="Number of cycles there was a stall because the read request interface was out of IO credits. Stalls occur regardless of whether a read needed to be performed or not. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA_RDREQ_GMI_CREDIT_STALL_sum" expr="sum(TCC_EA_RDREQ_GMI_CREDIT_STALL,32)" descr="Number of cycles there was a stall because the read request interface was out of GMI credits. Stalls occur regardless of whether a read needed to be performed or not. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum" expr="sum(TCC_EA_RDREQ_DRAM_CREDIT_STALL,32)" descr="Number of cycles there was a stall because the read request interface was out of DRAM credits. Stalls occur regardless of whether a read needed to be performed or not. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_TAG_STALL_sum" expr="sum(TCC_TAG_STALL,32)" descr="."></metric>
|
||||
<metric name="TCC_NORMAL_WRITEBACK_sum" expr="sum(TCC_NORMAL_WRITEBACK,32)" descr="Number of writebacks due to requests that are not writeback requests. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_ALL_TC_OP_WB_WRITEBACK_sum" expr="sum(TCC_ALL_TC_OP_WB_WRITEBACK,32)" descr="Number of writebacks due to all TC_OP writeback requests. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_NORMAL_EVICT_sum" expr="sum(TCC_NORMAL_EVICT,32)" descr="Number of evictions due to requests that are not invalidate or probe requests. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_ALL_TC_OP_INV_EVICT_sum" expr="sum(TCC_ALL_TC_OP_INV_EVICT,32)" descr="Number of evictions due to all TC_OP invalidate requests. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA_RDREQ_DRAM_sum" expr="sum(TCC_EA_RDREQ_DRAM,32)" descr="Number of TCC/EA read requests (either 32-byte or 64-byte) destined for DRAM (MC). Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA_WRREQ_DRAM_sum" expr="sum(TCC_EA_WRREQ_DRAM,32)" descr="Number of TCC/EA write requests (either 32-byte of 64-byte) destined for DRAM (MC). Sum over TCC instances."></metric>
|
||||
<metric name="FETCH_SIZE" expr="(TCC_EA_RDREQ_32B_sum*32+(TCC_EA_RDREQ_sum-TCC_EA_RDREQ_32B_sum)*64)/1024" descr="The total kilobytes fetched from the video memory. This is measured with all extra fetches and any cache or memory effects taken into account."></metric>
|
||||
<metric name="WRITE_SIZE" expr="((TCC_EA_WRREQ_sum-TCC_EA_WRREQ_64B_sum)*32+TCC_EA_WRREQ_64B_sum*64)/1024" descr="The total kilobytes written to the video memory. This is measured with all extra fetches and any cache or memory effects taken into account."></metric>
|
||||
<metric name="WRITE_REQ_32B" expr="TCC_EA_WRREQ_64B_sum*2+(TCC_EA_WRREQ_sum-TCC_EA_WRREQ_64B_sum)" descr="The total number of 32-byte effective memory writes."></metric>
|
||||
</gfx90a>
|
||||
|
||||
<gfx940>
|
||||
<metric name="GPUBusy" expr="100*GRBM_GUI_ACTIVE/GRBM_COUNT" descr="The percentage of time GPU was busy."></metric>
|
||||
<metric name="Wavefronts" expr="SQ_WAVES" descr="Total wavefronts."></metric>
|
||||
<metric name="VALUInsts" expr="SQ_INSTS_VALU/SQ_WAVES" descr="The average number of vector ALU instructions executed per work-item (affected by flow control)."></metric>
|
||||
<metric name="SALUInsts" expr="SQ_INSTS_SALU/SQ_WAVES" descr="The average number of scalar ALU instructions executed per work-item (affected by flow control)."></metric>
|
||||
<metric name="SFetchInsts" expr="SQ_INSTS_SMEM/SQ_WAVES" descr="The average number of scalar fetch instructions from the video memory executed per work-item (affected by flow control)."></metric>
|
||||
<metric name="GDSInsts" expr="SQ_INSTS_GDS/SQ_WAVES" descr="The average number of GDS read or GDS write instructions executed per work item (affected by flow control)."></metric>
|
||||
<metric name="MemUnitBusy" expr="100*max(TA_TA_BUSY,16)/GRBM_GUI_ACTIVE/SE_NUM" descr="The percentage of GPUTime the memory unit is active. The result includes the stall time (MemUnitStalled). This is measured with all extra fetches and writes and any cache or memory effects taken into account. Value range: 0% to 100% (fetch-bound)."></metric>
|
||||
<metric name="ALUStalledByLDS" expr="100*SQ_WAIT_INST_LDS*4/SQ_WAVES/GRBM_GUI_ACTIVE" descr="The percentage of GPUTime ALU units are stalled by the LDS input queue being full or the output queue being not ready. If there are LDS bank conflicts, reduce them. Otherwise, try reducing the number of LDS accesses if possible. Value range: 0% (optimal) to 100% (bad)."></metric>
|
||||
<metric name="VFetchInsts" expr="(SQ_INSTS_VMEM_RD-TA_FLAT_READ_WAVEFRONTS_sum)/SQ_WAVES" descr="The average number of vector fetch instructions from the video memory executed per work-item (affected by flow control). Excludes FLAT instructions that fetch from video memory."></metric>
|
||||
<metric name="VWriteInsts" expr="(SQ_INSTS_VMEM_WR-TA_FLAT_WRITE_WAVEFRONTS_sum)/SQ_WAVES" descr="The average number of vector write instructions to the video memory executed per work-item (affected by flow control). Excludes FLAT instructions that write to video memory."></metric>
|
||||
<metric name="VALUUtilization" expr="100*SQ_THREAD_CYCLES_VALU/(SQ_ACTIVE_INST_VALU*MAX_WAVE_SIZE)" descr="The percentage of active vector ALU threads in a wave. A lower number can mean either more thread divergence in a wave or that the work-group size is not a multiple of 64. Value range: 0% (bad), 100% (ideal - no thread divergence)."></metric>
|
||||
<metric name="VALUBusy" expr="100*SQ_ACTIVE_INST_VALU*4/SIMD_NUM/GRBM_GUI_ACTIVE" descr="The percentage of GPUTime vector ALU instructions are processed. Value range: 0% (bad) to 100% (optimal)."></metric>
|
||||
<metric name="SALUBusy" expr="100*SQ_INST_CYCLES_SALU*4/SIMD_NUM/GRBM_GUI_ACTIVE" descr="The percentage of GPUTime scalar ALU instructions are processed. Value range: 0% (bad) to 100% (optimal)."></metric>
|
||||
<metric name="FetchSize" expr="FETCH_SIZE" descr="The total kilobytes fetched from the video memory. This is measured with all extra fetches and any cache or memory effects taken into account."></metric>
|
||||
<metric name="WriteSize" expr="WRITE_SIZE" descr="The total kilobytes written to the video memory. This is measured with all extra fetches and any cache or memory effects taken into account."></metric>
|
||||
<metric name="MemWrites32B" expr="WRITE_REQ_32B" descr="The total number of effective 32B write transactions to the memory"></metric>
|
||||
<metric name="L2CacheHit" expr="100*sum(TCC_HIT,16)/(sum(TCC_HIT,16)+sum(TCC_MISS,16))" descr="The percentage of fetch, write, atomic, and other instructions that hit the data in L2 cache. Value range: 0% (no hit) to 100% (optimal)."></metric>
|
||||
<metric name="MemUnitStalled" expr="100*max(TCP_TCP_TA_DATA_STALL_CYCLES,16)/GRBM_GUI_ACTIVE/SE_NUM" descr="The percentage of GPUTime the memory unit is stalled. Try reducing the number or size of fetches and writes if possible. Value range: 0% (optimal) to 100% (bad)."></metric>
|
||||
<metric name="WriteUnitStalled" expr="100*TCC_WRREQ_STALL_max/GRBM_GUI_ACTIVE" descr="The percentage of GPUTime the Write unit is stalled. Value range: 0% to 100% (bad)."></metric>
|
||||
<metric name="LDSBankConflict" expr="100*SQ_LDS_BANK_CONFLICT/GRBM_GUI_ACTIVE/CU_NUM" descr="The percentage of GPUTime LDS is stalled by bank conflicts. Value range: 0% (optimal) to 100% (bad)."></metric>
|
||||
<metric name="TA_BUSY_avr" expr="avr(TA_TA_BUSY,16)" descr="TA block is busy. Average over TA instances."></metric>
|
||||
<metric name="TA_BUSY_max" expr="max(TA_TA_BUSY,16)" descr="TA block is busy. Max over TA instances."></metric>
|
||||
<metric name="TA_BUSY_min" expr="min(TA_TA_BUSY,16)" descr="TA block is busy. Min over TA instances."></metric>
|
||||
<metric name="TA_TA_BUSY_sum" expr="sum(TA_TA_BUSY,16)" descr="TA block is busy. Perf_Windowing not supported for this counter. Sum over TA instances."></metric>
|
||||
<metric name="TA_TOTAL_WAVEFRONTS_sum" expr="sum(TA_TOTAL_WAVEFRONTS,16)" descr="Total number of wavefronts processed by TA. Sum over TA instances."></metric>
|
||||
<metric name="TA_ADDR_STALLED_BY_TC_CYCLES_sum" expr="sum(TA_ADDR_STALLED_BY_TC_CYCLES,16)" descr="Number of cycles addr path stalled by TC. Perf_Windowing not supported for this counter. Sum over TA instances."></metric>
|
||||
<metric name="TA_ADDR_STALLED_BY_TD_CYCLES_sum" expr="sum(TA_ADDR_STALLED_BY_TD_CYCLES,16)" descr="Number of cycles addr path stalled by TD. Perf_Windowing not supported for this counter. Sum over TA instances."></metric>
|
||||
<metric name="TA_DATA_STALLED_BY_TC_CYCLES_sum" expr="sum(TA_DATA_STALLED_BY_TC_CYCLES,16)" descr="Number of cycles data path stalled by TC. Perf_Windowing not supported for this counter. Sum over TA instances."></metric>
|
||||
<metric name="TA_FLAT_WAVEFRONTS_sum" expr="sum(TA_FLAT_WAVEFRONTS,16)" descr="Number of flat opcode wavfronts processed by the TA. Sum over TA instances."></metric>
|
||||
<metric name="TA_FLAT_READ_WAVEFRONTS_sum" expr="sum(TA_FLAT_READ_WAVEFRONTS,16)" descr="Number of flat opcode reads processed by the TA. Sum over TA instances."></metric>
|
||||
<metric name="TA_FLAT_WRITE_WAVEFRONTS_sum" expr="sum(TA_FLAT_WRITE_WAVEFRONTS,16)" descr="Number of flat opcode writes processed by the TA. Sum over TA instances."></metric>
|
||||
<metric name="TA_FLAT_ATOMIC_WAVEFRONTS_sum" expr="sum(TA_FLAT_ATOMIC_WAVEFRONTS,16)" descr="Number of flat opcode atomics processed by the TA. Sum over TA instances."></metric>
|
||||
<metric name="TA_BUFFER_WAVEFRONTS_sum" expr="sum(TA_BUFFER_WAVEFRONTS,16)" descr="Number of buffer wavefronts processed by TA. Sum over TA instances."></metric>
|
||||
<metric name="TA_BUFFER_READ_WAVEFRONTS_sum" expr="sum(TA_BUFFER_READ_WAVEFRONTS,16)" descr="Number of buffer read wavefronts processed by TA. Sum over TA instances."></metric>
|
||||
<metric name="TA_BUFFER_WRITE_WAVEFRONTS_sum" expr="sum(TA_BUFFER_WRITE_WAVEFRONTS,16)" descr="Number of buffer write wavefronts processed by TA. Sum over TA instances."></metric>
|
||||
<metric name="TA_BUFFER_ATOMIC_WAVEFRONTS_sum" expr="sum(TA_BUFFER_ATOMIC_WAVEFRONTS,16)" descr="Number of buffer atomic wavefronts processed by TA. Sum over TA instances."></metric>
|
||||
<metric name="TA_BUFFER_TOTAL_CYCLES_sum" expr="sum(TA_BUFFER_TOTAL_CYCLES,16)" descr="Number of buffer cycles issued to TC. Sum over TA instances."></metric>
|
||||
<metric name="TA_BUFFER_COALESCED_READ_CYCLES_sum" expr="sum(TA_BUFFER_COALESCED_READ_CYCLES,16)" descr="Number of buffer coalesced read cycles issued to TC. Sum over TA instances."></metric>
|
||||
<metric name="TA_BUFFER_COALESCED_WRITE_CYCLES_sum" expr="sum(TA_BUFFER_COALESCED_WRITE_CYCLES,16)" descr="Number of buffer coalesced write cycles issued to TC. Sum over TA instances."></metric>
|
||||
<metric name="TD_TD_BUSY_sum" expr="sum(TD_TD_BUSY,16)" descr="TD is processing or waiting for data. Perf_Windowing not supported for this counter. Sum over TD instances."></metric>
|
||||
<metric name="TD_TC_STALL_sum" expr="sum(TD_TC_STALL,16)" descr="TD is stalled waiting for TC data. Sum over TD instances."></metric>
|
||||
<metric name="TD_LOAD_WAVEFRONT_sum" expr="sum(TD_LOAD_WAVEFRONT,16)" descr="Count the wavefronts with opcode = load, include atomics and store. Sum over TD instances."></metric>
|
||||
<metric name="TD_ATOMIC_WAVEFRONT_sum" expr="sum(TD_ATOMIC_WAVEFRONT,16)" descr="Count the wavefronts with opcode = atomic. Sum over TD instances."></metric>
|
||||
<metric name="TD_STORE_WAVEFRONT_sum" expr="sum(TD_STORE_WAVEFRONT,16)" descr="Count the wavefronts with opcode = store. Sum over TD instances."></metric>
|
||||
<metric name="TD_COALESCABLE_WAVEFRONT_sum" expr="sum(TD_COALESCABLE_WAVEFRONT,16)" descr="Count wavefronts that TA finds coalescable. Sum over TD instances."></metric>
|
||||
<metric name="TD_SPI_STALL_sum" expr="sum(TD_SPI_STALL,16)" descr="TD is stalled SPI vinit, sum of TCP instances"></metric>
|
||||
<metric name="TCP_GATE_EN1_sum" expr="sum(TCP_GATE_EN1,16)" descr="TCP interface clocks are turned on. Not Windowed. Sum over TCP instances."></metric>
|
||||
<metric name="TCP_GATE_EN2_sum" expr="sum(TCP_GATE_EN2,16)" descr="TCP core clocks are turned on. Not Windowed. Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TD_TCP_STALL_CYCLES_sum" expr="sum(TCP_TD_TCP_STALL_CYCLES,16)" descr="TD stalls TCP. Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TCR_TCP_STALL_CYCLES_sum" expr="sum(TCP_TCR_TCP_STALL_CYCLES,16)" descr="TCR stalls TCP_TCR_req interface. Sum over TCP instances."></metric>
|
||||
<metric name="TCP_READ_TAGCONFLICT_STALL_CYCLES_sum" expr="sum(TCP_READ_TAGCONFLICT_STALL_CYCLES,16)" descr="Tagram conflict stall on a read. Sum over TCP instances."></metric>
|
||||
<metric name="TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum" expr="sum(TCP_WRITE_TAGCONFLICT_STALL_CYCLES,16)" descr="Tagram conflict stall on a write. Sum over TCP instances."></metric>
|
||||
<metric name="TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum" expr="sum(TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES,16)" descr="Tagram conflict stall on an atomic. Sum over TCP instances."></metric>
|
||||
<metric name="TCP_VOLATILE_sum" expr="sum(TCP_VOLATILE,16)" descr="Total number of L1 volatile pixels/buffers from TA. Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TOTAL_ACCESSES_sum" expr="sum(TCP_TOTAL_ACCESSES,16)" descr="Total number of pixels/buffers from TA. Equals TCP_PERF_SEL_TOTAL_READ+TCP_PERF_SEL_TOTAL_NONREAD. Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TOTAL_READ_sum" expr="sum(TCP_TOTAL_READ,16)" descr="Total number of read pixels/buffers from TA. Equals TCP_PERF_SEL_TOTAL_HIT_LRU_READ + TCP_PERF_SEL_TOTAL_MISS_LRU_READ + TCP_PERF_SEL_TOTAL_MISS_EVICT_READ. Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TOTAL_WRITE_sum" expr="sum(TCP_TOTAL_WRITE,16)" descr="Total number of local write pixels/buffers from TA. Equals TCP_PERF_SEL_TOTAL_MISS_LRU_WRITE+ TCP_PERF_SEL_TOTAL_MISS_EVICT_WRITE. Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TOTAL_ATOMIC_WITH_RET_sum" expr="sum(TCP_TOTAL_ATOMIC_WITH_RET,16)" descr="Total number of atomic with return pixels/buffers from TA. Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TOTAL_ATOMIC_WITHOUT_RET_sum" expr="sum(TCP_TOTAL_ATOMIC_WITHOUT_RET,16)" descr="Total number of atomic without return pixels/buffers from TA Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TOTAL_WRITEBACK_INVALIDATES_sum" expr="sum(TCP_TOTAL_WRITEBACK_INVALIDATES,16)" descr="Total number of cache invalidates. Equals TCP_PERF_SEL_TOTAL_WBINVL1+ TCP_PERF_SEL_TOTAL_WBINVL1_VOL+ TCP_PERF_SEL_CP_TCP_INVALIDATE+ TCP_PERF_SEL_SQ_TCP_INVALIDATE_VOL. Not Windowed. Sum over TCP instances."></metric>
|
||||
<metric name="TCP_UTCL1_REQUEST_sum" expr="sum(TCP_UTCL1_REQUEST,16)" descr="Total CLIENT_UTCL1 NORMAL requests Sum over TCP instances."></metric>
|
||||
<metric name="TCP_UTCL1_TRANSLATION_MISS_sum" expr="sum(TCP_UTCL1_TRANSLATION_MISS,16)" descr="Total utcl1 translation misses Sum over TCP instances."></metric>
|
||||
<metric name="TCP_UTCL1_TRANSLATION_HIT_sum" expr="sum(TCP_UTCL1_TRANSLATION_HIT,16)" descr="Total utcl1 translation hits Sum over TCP instances."></metric>
|
||||
<metric name="TCP_UTCL1_PERMISSION_MISS_sum" expr="sum(TCP_UTCL1_PERMISSION_MISS,16)" descr="Total utcl1 permission misses Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TOTAL_CACHE_ACCESSES_sum" expr="sum(TCP_TOTAL_CACHE_ACCESSES,16)" descr="Count of total cache line (tag) accesses (includes hits and misses). Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TA_TCP_STATE_READ_sum" expr="sum(TCP_TA_TCP_STATE_READ,16)" descr="Number of state reads Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TCC_READ_REQ_sum" expr="sum(TCP_TCC_READ_REQ,16)" descr="Total read requests from TCP to all TCCs Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TCC_WRITE_REQ_sum" expr="sum(TCP_TCC_WRITE_REQ,16)" descr="Total write requests from TCP to all TCCs Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TCC_ATOMIC_WITH_RET_REQ_sum" expr="sum(TCP_TCC_ATOMIC_WITH_RET_REQ,16)" descr="Total atomic with return requests from TCP to all TCCs Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum" expr="sum(TCP_TCC_ATOMIC_WITHOUT_RET_REQ,16)" descr="Total atomic without return requests from TCP to all TCCs Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TCC_NC_READ_REQ_sum" expr="sum(TCP_TCC_NC_READ_REQ,16)" descr="Total read requests with NC mtype from this TCP to all TCCs Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TCC_NC_WRITE_RWriteUnitStalledQ_sum" expr="sum(TCP_TCC_RW_READ_REQ,16)" descr="Total write requests with RW mtype from this TCP to all TCCs. Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TCC_RW_WRITE_REQ_sum" expr="sum(TCP_TCC_RW_WRITE_REQ,16)" descr="Total write requests with RW mtype from this TCP to all TCCs. Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TCC_RW_ATOMIC_REQ_sum" expr="sum(TCP_TCC_RW_ATOMIC_REQ,16)" descr="Total atomic requests with RW mtype from this TCP to all TCCs. Sum over TCP instances."></metric>
|
||||
<metric name="TCP_PENDING_STALL_CYCLES_sum" expr="sum(TCP_PENDING_STALL_CYCLES,16)" descr="Stall due to data pending from L2. Sum over TCP instances."></metric>
|
||||
<metric name="TCA_CYCLE_sum" expr="sum(TCA_CYCLE,16)" descr="Number of cycles. Sum over all TCA instances "></metric>
|
||||
<metric name="TCA_BUSY_sum" expr="sum(TCA_BUSY,16)" descr="Number of cycles we have a request pending. Sum over all TCA instances."></metric>
|
||||
<metric name="TCC_BUSY_avr" expr="avr(TCC_BUSY,32)" descr="TCC_BUSY avr over all memory channels."></metric>
|
||||
<metric name="TCC_WRREQ_STALL_max" expr="max(TCC_EA0_WRREQ_STALL,32)" descr="Number of cycles a write request was stalled. Max over TCC instances."></metric>
|
||||
<metric name="TCC_CYCLE_sum" expr="sum(TCC_CYCLE,32)" descr="Number of cycles. Not windowable. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_BUSY_sum" expr="sum(TCC_BUSY,32)" descr="Number of cycles we have a request pending. Not windowable. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_REQ_sum" expr="sum(TCC_REQ,32)" descr="Number of requests of all types. This is measured at the tag block. This may be more than the number of requests arriving at the TCC, but it is a good indication of the total amount of work that needs to be performed. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_STREAMING_REQ_sum" expr="sum(TCC_STREAMING_REQ,32)" descr="Number of streaming requests. This is measured at the tag block. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_NC_REQ_sum" expr="sum(TCC_NC_REQ,32)" descr="The number of noncoherently cached requests. This is measured at the tag block. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_UC_REQ_sum" expr="sum(TCC_UC_REQ,32)" descr="The number of uncached requests. This is measured at the tag block. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_CC_REQ_sum" expr="sum(TCC_CC_REQ,32)" descr="The number of coherently cached requests. This is measured at the tag block. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_RW_REQ_sum" expr="sum(TCC_RW_REQ,32)" descr="The number of RW requests. This is measured at the tag block. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_PROBE_sum" expr="sum(TCC_PROBE,32)" descr="Number of probe requests. Not windowable. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_PROBE_ALL_sum" expr="sum(TCC_PROBE_ALL,32)" descr="Number of external probe requests with with EA_TCC_preq_all== 1. Not windowable. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_READ_sum" expr="sum(TCC_READ,32)" descr="Number of read requests. Compressed reads are included in this, but metadata reads are not included. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_WRITE_sum" expr="sum(TCC_WRITE,32)" descr="Number of write requests. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_ATOMIC_sum" expr="sum(TCC_ATOMIC,32)" descr="Number of atomic requests of all types. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_HIT_sum" expr="sum(TCC_HIT,32)" descr="Number of cache hits. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_MISS_sum" expr="sum(TCC_MISS,32)" descr="Number of cache misses. UC reads count as misses. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_WRITEBACK_sum" expr="sum(TCC_WRITEBACK,32)" descr="Number of lines written back to main memory. This includes writebacks of dirty lines and uncached write/atomic requests. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA0_WRREQ_sum" expr="sum(TCC_EA0_WRREQ,32)" descr="Number of transactions (either 32-byte or 64-byte) going over the TC_EA_wrreq interface. Atomics may travel over the same interface and are generally classified as write requests. This does not include probe commands. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA0_WRREQ_64B_sum" expr="sum(TCC_EA0_WRREQ_64B,32)" descr="Number of 64-byte transactions going (64-byte write or CMPSWAP) over the TC_EA_wrreq interface. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA0_WR_UNCACHED_32B_sum" expr="sum(TCC_EA0_WR_UNCACHED_32B,32)" descr="Number of 32-byte write/atomic going over the TC_EA_wrreq interface due to uncached traffic. Note that CC mtypes can produce uncached requests, and those are included in this. A 64-byte request will be counted as 2. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA0_WRREQ_STALL_sum" expr="sum(TCC_EA0_WRREQ_STALL,32)" descr="Number of cycles a write request was stalled. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA0_WRREQ_IO_CREDIT_STALL_sum" expr="sum(TCC_EA0_WRREQ_IO_CREDIT_STALL,32)" descr="Number of cycles a EA write request was stalled because the interface was out of IO credits. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA0_WRREQ_GMI_CREDIT_STALL_sum" expr="sum(TCC_EA0_WRREQ_GMI_CREDIT_STALL,32)" descr="Number of cycles a EA write request was stalled because the interface was out of GMI credits. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA0_WRREQ_DRAM_CREDIT_STALL_sum" expr="sum(TCC_EA0_WRREQ_DRAM_CREDIT_STALL,32)" descr="Number of cycles a EA write request was stalled because the interface was out of DRAM credits. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_TOO_MANY_EA_WRREQS_STALL_sum" expr="sum(TCC_TOO_MANY_EA_WRREQS_STALL,32)" descr="Number of cycles the TCC could not send a EA write request because it already reached its maximum number of pending EA write requests. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA0_WRREQ_LEVEL_sum" expr="sum(TCC_EA0_WRREQ_LEVEL,32)" descr="The sum of the number of EA write requests in flight. This is primarily meant for measure average EA write latency. Average write latency = TCC_PERF_SEL_EA_WRREQ_LEVEL/TCC_PERF_SEL_EA_WRREQ. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA0_RDREQ_LEVEL_sum" expr="sum(TCC_EA0_RDREQ_LEVEL,32)" descr="The sum of the number of TCC/EA read requests in flight. This is primarily meant for measure average EA read latency. Average read latency = TCC_PERF_SEL_EA_RDREQ_LEVEL/TCC_PERF_SEL_EA_RDREQ. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA0_ATOMIC_sum" expr="sum(TCC_EA0_ATOMIC,32)" descr="Number of transactions going over the TC_EA_wrreq interface that are actually atomic requests. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA0_ATOMIC_LEVEL_sum" expr="sum(TCC_EA0_ATOMIC_LEVEL,32)" descr="The sum of the number of EA atomics in flight. This is primarily meant for measure average EA atomic latency. Average atomic latency = TCC_PERF_SEL_EA_WRREQ_ATOMIC_LEVEL/TCC_PERF_SEL_EA_WRREQ_ATOMIC. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA0_RDREQ_sum" expr="sum(TCC_EA0_RDREQ,32)" descr="Number of TCC/EA read requests (either 32-byte or 64-byte) Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA0_RDREQ_32B_sum" expr="sum(TCC_EA0_RDREQ_32B,32)" descr="Number of 32-byte TCC/EA read requests Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA0_RD_UNCACHED_32B_sum" expr="sum(TCC_EA0_RD_UNCACHED_32B,32)" descr="Number of 32-byte TCC/EA read due to uncached traffic. A 64-byte request will be counted as 2 Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA0_RDREQ_IO_CREDIT_STALL_sum" expr="sum(TCC_EA0_RDREQ_IO_CREDIT_STALL,32)" descr="Number of cycles there was a stall because the read request interface was out of IO credits. Stalls occur regardless of whether a read needed to be performed or not. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA0_RDREQ_GMI_CREDIT_STALL_sum" expr="sum(TCC_EA0_RDREQ_GMI_CREDIT_STALL,32)" descr="Number of cycles there was a stall because the read request interface was out of GMI credits. Stalls occur regardless of whether a read needed to be performed or not. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA0_RDREQ_DRAM_CREDIT_STALL_sum" expr="sum(TCC_EA0_RDREQ_DRAM_CREDIT_STALL,32)" descr="Number of cycles there was a stall because the read request interface was out of DRAM credits. Stalls occur regardless of whether a read needed to be performed or not. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_TAG_STALL_sum" expr="sum(TCC_TAG_STALL,32)" descr="."></metric>
|
||||
<metric name="TCC_NORMAL_WRITEBACK_sum" expr="sum(TCC_NORMAL_WRITEBACK,32)" descr="Number of writebacks due to requests that are not writeback requests. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_ALL_TC_OP_WB_WRITEBACK_sum" expr="sum(TCC_ALL_TC_OP_WB_WRITEBACK,32)" descr="Number of writebacks due to all TC_OP writeback requests. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_NORMAL_EVICT_sum" expr="sum(TCC_NORMAL_EVICT,32)" descr="Number of evictions due to requests that are not invalidate or probe requests. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_ALL_TC_OP_INV_EVICT_sum" expr="sum(TCC_ALL_TC_OP_INV_EVICT,32)" descr="Number of evictions due to all TC_OP invalidate requests. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA0_RDREQ_DRAM_sum" expr="sum(TCC_EA0_RDREQ_DRAM,32)" descr="Number of TCC/EA read requests (either 32-byte or 64-byte) destined for DRAM (MC). Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA0_WRREQ_DRAM_sum" expr="sum(TCC_EA0_WRREQ_DRAM,32)" descr="Number of TCC/EA write requests (either 32-byte of 64-byte) destined for DRAM (MC). Sum over TCC instances."></metric>
|
||||
<metric name="FETCH_SIZE" expr="(TCC_EA0_RDREQ_32B_sum*32+(TCC_EA0_RDREQ_sum-TCC_EA0_RDREQ_32B_sum)*64)/1024" descr="The total kilobytes fetched from the video memory. This is measured with all extra fetches and any cache or memory effects taken into account."></metric>
|
||||
<metric name="WRITE_SIZE" expr="((TCC_EA0_WRREQ_sum-TCC_EA0_WRREQ_64B_sum)*32+TCC_EA0_WRREQ_64B_sum*64)/1024" descr="The total kilobytes written to the video memory. This is measured with all extra fetches and any cache or memory effects taken into account."></metric>
|
||||
<metric name="WRITE_REQ_32B" expr="TCC_EA0_WRREQ_64B_sum*2+(TCC_EA0_WRREQ_sum-TCC_EA0_WRREQ_64B_sum)" descr="The total number of 32-byte effective memory writes."></metric>
|
||||
</gfx940>
|
||||
|
||||
<gfx10>
|
||||
<metric name="GPUBusy" expr="100*GRBM_GUI_ACTIVE/GRBM_COUNT" descr="The percentage of time GPU was busy."></metric>
|
||||
<metric name="Wavefronts" expr="SQ_WAVES" descr="Total wavefronts."></metric>
|
||||
<metric name="VALUInsts" expr="SQ_INSTS_VALU/SQ_WAVES" descr="The average number of vector ALU instructions executed per work-item (affected by flow control)."></metric>
|
||||
<metric name="SALUInsts" expr="SQ_INSTS_SALU/SQ_WAVES" descr="The average number of scalar ALU instructions executed per work-item (affected by flow control)."></metric>
|
||||
<metric name="SFetchInsts" expr="SQ_INSTS_SMEM/SQ_WAVES" descr="The average number of scalar fetch instructions from the video memory executed per work-item (affected by flow control)."></metric>
|
||||
<metric name="GDSInsts" expr="SQ_INSTS_GDS/SQ_WAVES" descr="The average number of GDS read or GDS write instructions executed per work item (affected by flow control)."></metric>
|
||||
<metric name="MemUnitBusy" expr="100*max(TA_TA_BUSY,16)/GRBM_GUI_ACTIVE/SE_NUM" descr="The percentage of GPUTime the memory unit is active. The result includes the stall time (MemUnitStalled). This is measured with all extra fetches and writes and any cache or memory effects taken into account. Value range: 0% to 100% (fetch-bound)."></metric>
|
||||
<metric name="ALUStalledByLDS" expr="100*SQ_WAIT_INST_LDS*4/SQ_WAVES/GRBM_GUI_ACTIVE" descr="The percentage of GPUTime ALU units are stalled by the LDS input queue being full or the output queue being not ready. If there are LDS bank conflicts, reduce them. Otherwise, try reducing the number of LDS accesses if possible. Value range: 0% (optimal) to 100% (bad)."></metric>
|
||||
<metric name="GPU_UTIL" expr="100*GRBM_GUI_ACTIVE/GRBM_COUNT" descr="Percentage of the time that GUI is active"></metric>
|
||||
<metric name="CP_UTIL" expr="100*GRBM_CP_BUSY/GRBM_GUI_ACTIVE" descr="Percentage of the GRBM_GUI_ACTIVE time that any of the Command Processor (CPG/CPC/CPF) blocks are busy"></metric>
|
||||
<metric name="SPI_UTIL" expr="100*GRBM_SPI_BUSY/GRBM_GUI_ACTIVE" descr="Percentage of the GRBM_GUI_ACTIVE time that any of the Shader Pipe Interpolators (SPI) are busy in the shader engine(s)"></metric>
|
||||
<metric name="TA_UTIL" expr="100*GRBM_TA_BUSY/GRBM_GUI_ACTIVE" descr="Percentage of the GRBM_GUI_ACTIVE time that any of the Texture Pipes (TA) are busy in the shader engine(s)."></metric>
|
||||
<metric name="GDS_UTIL" expr="100*GRBM_GDS_BUSY/GRBM_GUI_ACTIVE" descr="Percentage of the GRBM_GUI_ACTIVE time that the Global Data Share (GDS) is busy."></metric>
|
||||
<metric name="EA_UTIL" expr="100*GRBM_EA_BUSY/GRBM_GUI_ACTIVE" descr="Percentage of the GRBM_GUI_ACTIVE time that the Efficiency Arbiter (EA) block is busy."></metric>
|
||||
<metric name="WAVE_DEP_WAIT" expr="100*SQ_WAIT_ANY/SQ_WAVE_CYCLES" descr="Percentage of the SQ_WAVE_CYCLE time spent waiting for anything."></metric>
|
||||
<metric name="WAVE_ISSUE_WAIT" expr="100*SQ_WAIT_INST_ANY/SQ_WAVE_CYCLES" descr="Percentage of the SQ_WAVE_CYCLE time spent waiting for any instruction issue."></metric>
|
||||
<metric name="TA_BUSY_avr" expr="avr(TA_TA_BUSY,16)" descr="TA block is busy. Average over TA instances."></metric>
|
||||
<metric name="TA_BUSY_max" expr="max(TA_TA_BUSY,16)" descr="TA block is busy. Max over TA instances."></metric>
|
||||
<metric name="TA_BUSY_min" expr="min(TA_TA_BUSY,16)" descr="TA block is busy. Min over TA instances."></metric>
|
||||
<metric name="TA_FLAT_LOAD_WAVEFRONTS_sum" expr="sum(TA_FLAT_LOAD_WAVEFRONTS,16)" descr="Number of flat load vec32 packets processed by the TA. Sum over TA instances."></metric>
|
||||
<metric name="TA_FLAT_STORE_WAVEFRONTS_sum" expr="sum(TA_FLAT_STORE_WAVEFRONTS,16)" descr="Number of flat store vec32 packets processed by the TA. Sum over TA instances."></metric>
|
||||
<metric name="GL2C_HIT_sum" expr="sum(GL2C_HIT,16)" descr="Number of cache hits. Sum over GL2C instances."></metric>
|
||||
<metric name="GL2C_MISS_sum" expr="sum(GL2C_MISS,16)" descr="Number of cache misses. Sum over GL2C instances."></metric>
|
||||
<metric name="GL2C_EA_RDREQ_32B_sum" expr="sum(GL2C_EA_RDREQ_32B,16)" descr="Number of 32-byte GL2C/EA read requests. Sum over GL2C instances."></metric>
|
||||
<metric name="GL2C_EA_RDREQ_64B_sum" expr="sum(GL2C_EA_RDREQ_64B,16)" descr="Number of 64-byte GL2C/EA read requests. Sum over GL2C instances."></metric>
|
||||
<metric name="GL2C_EA_RDREQ_96B_sum" expr="sum(GL2C_EA_RDREQ_96B,16)" descr="Number of 96-byte GL2C/EA read requests. Sum over GL2C instances."></metric>
|
||||
<metric name="GL2C_EA_RDREQ_128B_sum" expr="sum(GL2C_EA_RDREQ_128B,16)" descr="Number of 128-byte GL2C/EA read requests. Sum over GL2C instances."></metric>
|
||||
<metric name="GL2C_MC_RDREQ_sum" expr="sum(GL2C_MC_RDREQ,16)" descr="Number of GL2C/EA read requests (either 32-byte or 64-byte or 128-byte). Sum over GL2C instances."></metric>
|
||||
<metric name="GL2C_MC_WRREQ_sum" expr="sum(GL2C_MC_WRREQ,16)" descr="Number of transactions (either 32-byte or 64-byte) going over the GL2C_MC_wrreq interface. Sum over GL2C instances."></metric>
|
||||
<metric name="GL2C_EA_WRREQ_64B_sum" expr="sum(GL2C_EA_WRREQ_64B,16)" descr="Number of 64-byte transactions going (64-byte write or CMPSWAP) over the GL2C_EA_wrreq interface. Sum over GL2C instances."></metric>
|
||||
<metric name="GL2C_WRREQ_STALL_max" expr="max(GL2C_MC_WRREQ_STALL,16)" descr="Number of cycles a write request was stalled. Max over GL2C instances."></metric>
|
||||
<metric name="L2CacheHit" expr="100*sum(GL2C_HIT,16)/(sum(GL2C_HIT,16)+sum(GL2C_MISS,16))" descr="The percentage of fetch, write, atomic, and other instructions that hit the data in L2 cache. Value range: 0% (no hit) to 100% (optimal)."></metric>
|
||||
<metric name="FETCH_SIZE" expr="(GL2C_EA_RDREQ_32B_sum*32+GL2C_EA_RDREQ_64B_sum*64+GL2C_EA_RDREQ_96B_sum*96+GL2C_EA_RDREQ_128B_sum*128)/1024" descr="The total kilobytes fetched from the video memory. This is measured with all extra fetches and any cache or memory effects taken into account."></metric>
|
||||
<metric name="WriteUnitStalled" expr="100*GL2C_WRREQ_STALL_max/GRBM_GUI_ACTIVE" descr="The percentage of GPUTime the Write unit is stalled. Value range: 0% to 100% (bad)."></metric>
|
||||
<metric name="LDSBankConflict" expr="100*SQC_LDS_BANK_CONFLICT/SQC_LDS_IDX_ACTIVE" descr="The percentage of GPUTime LDS is stalled by bank conflicts. Value range: 0% (optimal) to 100% (bad)."></metric>
|
||||
</gfx10>
|
||||
|
||||
</metrics>
|
||||
@@ -0,0 +1,88 @@
|
||||
#!/usr/bin/python3
|
||||
|
||||
from collections import deque
|
||||
from re import sub
|
||||
import xml.etree.ElementTree as ET
|
||||
from lxml import etree
|
||||
import ast
|
||||
import sys
|
||||
|
||||
ops = {'Div': '/', 'Mult': '*', 'Add': '+', 'Sub': '-'}
|
||||
calls = {'avr', 'max', 'min', 'sum'}
|
||||
|
||||
def parse_expr(gpu_tag, data):
|
||||
global exprs_counters
|
||||
global exprs_counters_init
|
||||
global expr_print
|
||||
global counter_count
|
||||
global counters_dictionary
|
||||
expr_queue = deque()
|
||||
for line in data.split('\n'):
|
||||
if 'Constant' in line:
|
||||
number = line.split('(')[1].split(')')[0]
|
||||
expr_queue.append('(uint64_t)' + number)
|
||||
if 'Name' in line:
|
||||
name = line.split('\'')[1]
|
||||
if name in calls:
|
||||
expr_queue.append(name)
|
||||
else:
|
||||
if not name in exprs_counters:
|
||||
exprs_counters += "getGeneratedBasicCounter(" + name + "_id), "
|
||||
exprs_counters_init += "\n\t\tuint64_t " + name + "_id = getBasicCounter(\"" + name + "\", \"" + gpu_tag + "\");"
|
||||
counters_dictionary[name] = counter_count
|
||||
counter_count+=1
|
||||
expr_queue.append("counter.getBasicCounterFromDerived(" + str(counters_dictionary[name]) + ")")
|
||||
op = line.split('(')[0]
|
||||
if op in ops:
|
||||
expr_queue.append(ops[op])
|
||||
expr_print += "\n\t\t\t\treturn "
|
||||
i = 0
|
||||
for element in expr_queue:
|
||||
if element in calls:
|
||||
i = 1
|
||||
call = element
|
||||
elif i == 1:
|
||||
expr_print += element + "." + call + "("
|
||||
call = ""
|
||||
i = 2
|
||||
elif i == 2:
|
||||
expr_print += element + ")"
|
||||
i = 0
|
||||
else:
|
||||
expr_print += element
|
||||
if "counter.getBasicCounterFromDerived" == element[0:34]:
|
||||
expr_print += "->getValue()"
|
||||
|
||||
|
||||
if (__name__ == "__main__"):
|
||||
global exprs_counters
|
||||
global exprs_counters_init
|
||||
global expr_print
|
||||
global counter_count
|
||||
parser = etree.XMLParser(recover=True, encoding='utf-8')
|
||||
xml_file = ET.parse(sys.argv[1] + '/metrics.xml', parser=parser)
|
||||
root = xml_file.getroot()
|
||||
print(
|
||||
"uint64_t getDerivedCounter(const char* name, const char* gpu_name) {")
|
||||
for gpu in root:
|
||||
print("\n\t/**\n\t * @brief Derived " + gpu.tag + " counters\n\t *\n\t * @{\n\t */")
|
||||
print("\tif (strcmp(gpu_name, \"" + gpu.tag + "\")==0) {")
|
||||
for child in gpu:
|
||||
exprs_counters = ""
|
||||
exprs_counters_init = ""
|
||||
expr_print = ""
|
||||
counter_count = 0
|
||||
counters_dictionary = {}
|
||||
parse_expr(gpu.tag.split("_")[0], ast.dump(ast.parse(
|
||||
child.attrib['expr'], mode='eval'), annotate_fields=False, include_attributes=False, indent=0))
|
||||
print("\t/**\n\t * Derived Counter: " + child.attrib['name'] + "\n\t *\n\t * " + child.attrib['descr'] + "\n\t */\n\tif (strcmp(name, \"" +
|
||||
child.attrib['name'] + "\")==0) {" + exprs_counters_init + "\n\t\tDerivedCounter counter = DerivedCounter(\"" + child.attrib['name'] +
|
||||
"\", \"" + child.attrib['descr'] + "\", \"" + gpu.tag.split("_")[0] + "\");")
|
||||
exprs_counter_count = 0
|
||||
for expr_counter in exprs_counters[0:-2].split(", "):
|
||||
print("\n\t\tcounter.addBasicCounter(" + str(exprs_counter_count) + ", " + expr_counter + ");")
|
||||
exprs_counter_count += 1
|
||||
# print("\n\t\tcounter.evaluate_metric = [counter]() {" + expr_print + ";\n\t\t\t};")
|
||||
print("\n\t\tderived_counters.emplace(counter.getMetricId(), counter);\n\t\treturn counter.getMetricId();\n\t}")
|
||||
print("\t}\n\n\t/**\n\t * @}\n\t */")
|
||||
print("\n\treturn 0;\n}\n")
|
||||
Executable
+683
@@ -0,0 +1,683 @@
|
||||
<gfx8>
|
||||
<metric name="GRBM_COUNT" block=GRBM event=0 descr="Tie High - Count Number of Clocks"></metric>
|
||||
<metric name="GRBM_GUI_ACTIVE" block=GRBM event=2 descr="The GUI is Active"></metric>
|
||||
|
||||
<metric name="SQ_WAVES" block=SQ event=4 descr="Count number of waves sent to SQs. (per-simd, emulated, global)"></metric>
|
||||
<metric name="SQ_INSTS_VALU" block=SQ event=26 descr="Number of VALU instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VMEM_WR" block=SQ event=27 descr="Number of VMEM write instructions issued (including FLAT). (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VMEM_RD" block=SQ event=28 descr="Number of VMEM read instructions issued (including FLAT). (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_SALU" block=SQ event=30 descr="Number of SALU instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_SMEM" block=SQ event=31 descr="Number of SMEM instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_FLAT" block=SQ event=32 descr="Number of FLAT instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_FLAT_LDS_ONLY" block=SQ event=33 descr="Number of FLAT instructions issued that read/wrote only from/to LDS (only works if EARLY_TA_DONE is enabled). (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_LDS" block=SQ event=34 descr="Number of LDS instructions issued (including FLAT). (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_GDS" block=SQ event=35 descr="Number of GDS instructions issued. (per-simd, emulated)"></metric>
|
||||
|
||||
<metric name="SQ_WAIT_INST_LDS" block=SQ event=61 descr="Number of wave-cycles spent waiting for LDS instruction issue. In units of 4 cycles. (per-simd, nondeterministic)"></metric>
|
||||
<metric name="SQ_ACTIVE_INST_VALU" block=SQ event=69 descr="Number of cycles the SQ instruction arbiter is working on a VALU instruction. (per-simd, nondeterministic). Units in quad-cycles(4 cycles)"></metric>
|
||||
<metric name="SQ_INST_CYCLES_SALU" block=SQ event=86 descr="Number of cycles needed to execute non-memory read scalar operations. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_THREAD_CYCLES_VALU" block=SQ event=89 descr="Number of thread-cycles used to execute VALU operations (similar to INST_CYCLES_VALU but multiplied by # of active threads). (per-simd)"></metric>
|
||||
<metric name="SQ_LDS_BANK_CONFLICT" block=SQ event=97 descr="Number of cycles LDS is stalled by bank conflicts. (emulated)"></metric>
|
||||
|
||||
<metric name="TA_TA_BUSY" block=TA event=15 descr="TA block is busy. Perf_Windowing not supported for this counter."></metric>
|
||||
<metric name="TA_FLAT_READ_WAVEFRONTS" block=TA event=101 descr="Number of flat opcode reads processed by the TA."></metric>
|
||||
<metric name="TA_FLAT_WRITE_WAVEFRONTS" block=TA event=102 descr="Number of flat opcode writes processed by the TA."></metric>
|
||||
|
||||
<metric name="TCC_HIT" block=TCC event=18 descr="Number of cache hits."></metric>
|
||||
<metric name="TCC_MISS" block=TCC event=19 descr="Number of cache misses. UC reads count as misses."></metric>
|
||||
<metric name="TCC_MC_RDREQ" block=TCC event=35 descr="Number of 32-byte reads. The hardware actually does 64-byte reads but the number is adjusted to provide uniformity."></metric>
|
||||
<metric name="TCC_MC_WRREQ" block=TCC event=26 descr="Number of 32-byte transactions going over the TC_MC_wrreq interface. Atomics may travel over the same interface and are generally classified as write requests."></metric>
|
||||
<metric name="TCC_MC_WRREQ_STALL" block=TCC event=28 descr="Number of cycles a write request was stalled."></metric>
|
||||
|
||||
<metric name="TCP_TCP_TA_DATA_STALL_CYCLES" block=TCP event=3 descr="TCP stalls TA data interface. Now Windowed."></metric>
|
||||
</gfx8>
|
||||
|
||||
<gfx9>
|
||||
<metric name="GRBM_COUNT" block=GRBM event=0 descr="Tie High - Count Number of Clocks"></metric>
|
||||
<metric name="GRBM_GUI_ACTIVE" block=GRBM event=2 descr="The GUI is Active"></metric>
|
||||
|
||||
<metric name="SQ_WAVES" block=SQ event=4 descr="Count number of waves sent to SQs. (per-simd, emulated, global)"></metric>
|
||||
<metric name="SQ_INSTS_VALU" block=SQ event=26 descr="Number of VALU instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VMEM_WR" block=SQ event=27 descr="Number of VMEM write instructions issued (including FLAT). (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VMEM_RD" block=SQ event=28 descr="Number of VMEM read instructions issued (including FLAT). (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_SALU" block=SQ event=30 descr="Number of SALU instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_SMEM" block=SQ event=31 descr="Number of SMEM instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_FLAT" block=SQ event=32 descr="Number of FLAT instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_FLAT_LDS_ONLY" block=SQ event=33 descr="Number of FLAT instructions issued that read/wrote only from/to LDS (only works if EARLY_TA_DONE is enabled). (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_LDS" block=SQ event=34 descr="Number of LDS instructions issued (including FLAT). (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_GDS" block=SQ event=35 descr="Number of GDS instructions issued. (per-simd, emulated)"></metric>
|
||||
|
||||
<metric name="SQ_WAIT_INST_LDS" block=SQ event=63 descr="Number of wave-cycles spent waiting for LDS instruction issue. In units of 4 cycles. (per-simd, nondeterministic)"></metric>
|
||||
<metric name="SQ_ACTIVE_INST_VALU" block=SQ event=71 descr="regspec 71? Number of cycles the SQ instruction arbiter is working on a VALU instruction. (per-simd, nondeterministic). Units in quad-cycles(4 cycles)"></metric>
|
||||
<metric name="SQ_INST_CYCLES_SALU" block=SQ event=84 descr="Number of cycles needed to execute non-memory read scalar operations. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_THREAD_CYCLES_VALU" block=SQ event=85 descr="Number of thread-cycles used to execute VALU operations (similar to INST_CYCLES_VALU but multiplied by # of active threads). (per-simd)"></metric>
|
||||
<metric name="SQ_LDS_BANK_CONFLICT" block=SQ event=93 descr="Number of cycles LDS is stalled by bank conflicts. (emulated)"></metric>
|
||||
|
||||
<metric name="TA_TA_BUSY" block=TA event=15 descr="TA block is busy. Perf_Windowing not supported for this counter."></metric>
|
||||
<metric name="TA_FLAT_READ_WAVEFRONTS" block=TA event=101 descr="Number of flat opcode reads processed by the TA."></metric>
|
||||
<metric name="TA_FLAT_WRITE_WAVEFRONTS" block=TA event=102 descr="Number of flat opcode writes processed by the TA."></metric>
|
||||
|
||||
<metric name="TCC_HIT" block=TCC event=20 descr="Number of cache hits."></metric>
|
||||
<metric name="TCC_MISS" block=TCC event=22 descr="Number of cache misses. UC reads count as misses."></metric>
|
||||
<metric name="TCC_EA_WRREQ" block=TCC event=29 descr="Number of transactions (either 32-byte or 64-byte) going over the TC_EA_wrreq interface. Atomics may travel over the same interface and are generally classified as write requests. This does not include probe commands."></metric>
|
||||
<metric name="TCC_EA_WRREQ_64B" block=TCC event=30 descr="Number of 64-byte transactions going (64-byte write or CMPSWAP) over the TC_EA_wrreq interface."></metric>
|
||||
<metric name="TCC_EA_WRREQ_STALL" block=TCC event=33 descr="Number of cycles a write request was stalled."></metric>
|
||||
<metric name="TCC_EA_RDREQ" block=TCC event=41 descr="Number of TCC/EA read requests (either 32-byte or 64-byte)"></metric>
|
||||
<metric name="TCC_EA_RDREQ_32B" block=TCC event=42 descr="Number of 32-byte TCC/EA read requests"></metric>
|
||||
|
||||
<metric name="TCP_TCP_TA_DATA_STALL_CYCLES" block=TCP event=6 descr="TCP stalls TA data interface. Now Windowed."></metric>
|
||||
</gfx9>
|
||||
|
||||
<gfx906 base="gfx9">
|
||||
# EA1
|
||||
<metric name="TCC_EA1_WRREQ" block=TCC event=256 descr="Number of transactions (either 32-byte or 64-byte) going over the TC_EA_wrreq interface. Atomics may travel over the same interface and are generally classified as write requests. This does not include probe commands."></metric>
|
||||
<metric name="TCC_EA1_WRREQ_64B" block=TCC event=257 descr="Number of 64-byte transactions going (64-byte write or CMPSWAP) over the TC_EA_wrreq interface."></metric>
|
||||
<metric name="TCC_EA1_WRREQ_STALL" block=TCC event=260 descr="Number of cycles a write request was stalled."></metric>
|
||||
<metric name="TCC_EA1_RDREQ" block=TCC event=267 descr="Number of TCC/EA read requests (either 32-byte or 64-byte)"></metric>
|
||||
<metric name="TCC_EA1_RDREQ_32B" block=TCC event=268 descr="Number of 32-byte TCC/EA read requests"></metric>
|
||||
</gfx906>
|
||||
|
||||
<gfx908 base="gfx9">
|
||||
<metric name="SQ_INSTS_VMEM_WR" block=SQ event=28 descr="Number of VMEM write instructions issued (including FLAT). (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VMEM_RD" block=SQ event=29 descr="Number of VMEM read instructions issued (including FLAT). (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_SALU" block=SQ event=31 descr="Number of SALU instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_SMEM" block=SQ event=32 descr="Number of SMEM instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_FLAT" block=SQ event=33 descr="Number of FLAT instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_FLAT_LDS_ONLY" block=SQ event=34 descr="Number of FLAT instructions issued that read/wrote only from/to LDS (only works if EARLY_TA_DONE is enabled). (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_LDS" block=SQ event=35 descr="Number of LDS instructions issued (including FLAT). (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_GDS" block=SQ event=36 descr="Number of GDS instructions issued. (per-simd, emulated)"></metric>
|
||||
|
||||
<metric name="SQ_WAIT_INST_LDS" block=SQ event=64 descr="Number of wave-cycles spent waiting for LDS instruction issue. In units of 4 cycles. (per-simd, nondeterministic)"></metric>
|
||||
<metric name="SQ_ACTIVE_INST_VALU" block=SQ event=72 descr="regspec 71? Number of cycles the SQ instruction arbiter is working on a VALU instruction. (per-simd, nondeterministic). Units in quad-cycles(4 cycles)"></metric>
|
||||
<metric name="SQ_INST_CYCLES_SALU" block=SQ event=85 descr="Number of cycles needed to execute non-memory read scalar operations. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_THREAD_CYCLES_VALU" block=SQ event=86 descr="Number of thread-cycles used to execute VALU operations (similar to INST_CYCLES_VALU but multiplied by # of active threads). (per-simd)"></metric>
|
||||
<metric name="SQ_LDS_BANK_CONFLICT" block=SQ event=94 descr="Number of cycles LDS is stalled by bank conflicts. (emulated)"></metric>
|
||||
|
||||
<metric name="TCC_HIT" block=TCC event=17 descr="Number of cache hits."></metric>
|
||||
<metric name="TCC_MISS" block=TCC event=19 descr="Number of cache misses. UC reads count as misses."></metric>
|
||||
<metric name="TCC_EA_WRREQ" block=TCC event=26 descr="Number of transactions (either 32-byte or 64-byte) going over the TC_EA_wrreq interface. Atomics may travel over the same interface and are generally classified as write requests. This does not include probe commands."></metric>
|
||||
<metric name="TCC_EA_WRREQ_64B" block=TCC event=27 descr="Number of 64-byte transactions going (64-byte write or CMPSWAP) over the TC_EA_wrreq interface."></metric>
|
||||
<metric name="TCC_EA_WRREQ_STALL" block=TCC event=30 descr="Number of cycles a write request was stalled."></metric>
|
||||
<metric name="TCC_EA_RDREQ" block=TCC event=38 descr="Number of TCC/EA read requests (either 32-byte or 64-byte)"></metric>
|
||||
<metric name="TCC_EA_RDREQ_32B" block=TCC event=39 descr="Number of 32-byte TCC/EA read requests"></metric>
|
||||
</gfx908>
|
||||
|
||||
<gfx90a>
|
||||
<metric name="SQ_WAIT_INST_LDS" block=SQ event=91 descr="Number of wave-cycles spent waiting for LDS instruction issue. In units of 4 cycles. (per-simd, nondeterministic)"></metric>
|
||||
<metric name="TCP_TCP_TA_DATA_STALL_CYCLES" block=TCP event=6 descr="TCP stalls TA data interface. Now Windowed."></metric>
|
||||
<metric name="GRBM_COUNT" block=GRBM event=0 descr="Tie High - Count Number of Clocks"></metric>
|
||||
<metric name="GRBM_GUI_ACTIVE" block=GRBM event=2 descr="The GUI is Active"></metric>
|
||||
<metric name="GRBM_CP_BUSY" block=GRBM event=3 descr="Any of the Command Processor (CPG/CPC/CPF) blocks are busy."></metric>
|
||||
<metric name="GRBM_SPI_BUSY" block=GRBM event=11 descr="Any of the Shader Pipe Interpolators (SPI) are busy in the shader engine(s)."></metric>
|
||||
<metric name="GRBM_TA_BUSY" block=GRBM event=13 descr="Any of the Texture Pipes (TA) are busy in the shader engine(s)."></metric>
|
||||
<metric name="GRBM_TC_BUSY" block=GRBM event=28 descr="Any of the Texture Cache Blocks (TCP/TCI/TCA/TCC) are busy."></metric>
|
||||
<metric name="GRBM_CPC_BUSY" block=GRBM event=30 descr="The Command Processor Compute (CPC) is busy."></metric>
|
||||
<metric name="GRBM_CPF_BUSY" block=GRBM event=31 descr="The Command Processor Fetchers (CPF) is busy."></metric>
|
||||
<metric name="GRBM_UTCL2_BUSY" block=GRBM event=34 descr="The Unified Translation Cache Level-2 (UTCL2) block is busy."></metric>
|
||||
<metric name="GRBM_EA_BUSY" block=GRBM event=35 descr="The Efficiency Arbiter (EA) block is busy."></metric>
|
||||
<metric name="CPC_ME1_BUSY_FOR_PACKET_DECODE" block=CPC event=13 descr="Me1 busy for packet decode."></metric>
|
||||
<metric name="CPC_UTCL1_STALL_ON_TRANSLATION" block=CPC event=24 descr="One of the UTCL1s is stalled waiting on translation, XNACK or PENDING response."></metric>
|
||||
<metric name="CPC_CPC_STAT_BUSY" block=CPC event=25 descr="CPC Busy."></metric>
|
||||
<metric name="CPC_CPC_STAT_IDLE" block=CPC event=26 descr="CPC Idle."></metric>
|
||||
<metric name="CPC_CPC_STAT_STALL" block=CPC event=27 descr="CPC Stalled."></metric>
|
||||
<metric name="CPC_CPC_TCIU_BUSY" block=CPC event=28 descr="CPC TCIU interface Busy."></metric>
|
||||
<metric name="CPC_CPC_TCIU_IDLE" block=CPC event=29 descr="CPC TCIU interface Idle."></metric>
|
||||
<metric name="CPC_CPC_UTCL2IU_BUSY" block=CPC event=30 descr="CPC UTCL2 interface Busy."></metric>
|
||||
<metric name="CPC_CPC_UTCL2IU_IDLE" block=CPC event=31 descr="CPC UTCL2 interface Idle."></metric>
|
||||
<metric name="CPC_CPC_UTCL2IU_STALL" block=CPC event=32 descr="CPC UTCL2 interface Stalled waiting on Free, Tags or Translation."></metric>
|
||||
<metric name="CPC_ME1_DC0_SPI_BUSY" block=CPC event=33 descr="CPC Me1 Processor Busy."></metric>
|
||||
<metric name="CPF_CMP_UTCL1_STALL_ON_TRANSLATION" block=CPF event=20 descr="One of the Compute UTCL1s is stalled waiting on translation, XNACK or PENDING response."></metric>
|
||||
<metric name="CPF_CPF_STAT_BUSY" block=CPF event=23 descr="CPF Busy."></metric>
|
||||
<metric name="CPF_CPF_STAT_IDLE" block=CPF event=24 descr="CPF Idle."></metric>
|
||||
<metric name="CPF_CPF_STAT_STALL" block=CPF event=25 descr="CPF Stalled."></metric>
|
||||
<metric name="CPF_CPF_TCIU_BUSY" block=CPF event=26 descr="CPF TCIU interface Busy."></metric>
|
||||
<metric name="CPF_CPF_TCIU_IDLE" block=CPF event=27 descr="CPF TCIU interface Idle."></metric>
|
||||
<metric name="CPF_CPF_TCIU_STALL" block=CPF event=28 descr="CPF TCIU interface Stalled waiting on Free, Tags."></metric>
|
||||
<metric name="SPI_CSN_WINDOW_VALID" block=SPI event=47 descr="Clock count enabled by perfcounter_start event. Requires SPI_DEBUG_CNTL.DEBUG_PIPE_SEL to select source, DEBUG_PIPE_SEL = 1, source is CS1; DEBUG_PIPE_SEL = 2, source is CS2; DEBUG_PIPE_SEL = 3, source is CS3; default, source is CS0;"></metric>
|
||||
<metric name="SPI_CSN_BUSY" block=SPI event=48 descr="Number of clocks with outstanding waves (SPI or SH). Requires SPI_DEBUG_CNTL.DEBUG_PIPE_SEL to select source, DEBUG_PIPE_SEL = 1, source is CS1; DEBUG_PIPE_SEL = 2, source is CS2; DEBUG_PIPE_SEL = 3, source is CS3; default, source is CS0;"></metric>
|
||||
<metric name="SPI_CSN_NUM_THREADGROUPS" block=SPI event=49 descr="Number of threadgroups launched. Requires SPI_DEBUG_CNTL.DEBUG_PIPE_SEL to select source, DEBUG_PIPE_SEL = 1, source is CS1; DEBUG_PIPE_SEL = 2, source is CS2; DEBUG_PIPE_SEL = 3, source is CS3; default, source is CS0;"></metric>
|
||||
<metric name="SPI_CSN_WAVE" block=SPI event=52 descr="Number of waves. Requires SPI_DEBUG_CNTL.DEBUG_PIPE_SEL to select source, DEBUG_PIPE_SEL = 1, source is CS1; DEBUG_PIPE_SEL = 2, source is CS2; DEBUG_PIPE_SEL = 3, source is CS3; default, source is CS0;"></metric>
|
||||
<metric name="SPI_RA_REQ_NO_ALLOC" block=SPI event=79 descr="Arb cycles with requests but no allocation. Source is RA0"></metric>
|
||||
<metric name="SPI_RA_REQ_NO_ALLOC_CSN" block=SPI event=85 descr="Arb cycles with CSn req and no CSn alloc. Source is RA0"></metric>
|
||||
<metric name="SPI_RA_RES_STALL_CSN" block=SPI event=91 descr="Arb cycles with CSn req and no CSn fits. Source is RA0"></metric>
|
||||
<metric name="SPI_RA_TMP_STALL_CSN" block=SPI event=97 descr="Cycles where csn wants to req but does not fit in temp space."></metric>
|
||||
<metric name="SPI_RA_WAVE_SIMD_FULL_CSN" block=SPI event=103 descr="Sum of SIMD where WAVE can't take csn wave when !fits. Source is RA0"></metric>
|
||||
<metric name="SPI_RA_VGPR_SIMD_FULL_CSN" block=SPI event=109 descr="Sum of SIMD where VGPR can't take csn wave when !fits. Source is RA0"></metric>
|
||||
<metric name="SPI_RA_SGPR_SIMD_FULL_CSN" block=SPI event=115 descr="Sum of SIMD where SGPR can't take csn wave when !fits. Source is RA0"></metric>
|
||||
<metric name="SPI_RA_LDS_CU_FULL_CSN" block=SPI event=120 descr="Sum of CU where LDS can't take csn wave when !fits. Source is RA0"></metric>
|
||||
<metric name="SPI_RA_BAR_CU_FULL_CSN" block=SPI event=123 descr="Sum of CU where BARRIER can't take csn wave when !fits. Source is RA0"></metric>
|
||||
<metric name="SPI_RA_BULKY_CU_FULL_CSN" block=SPI event=125 descr="Sum of CU where BULKY can't take csn wave when !fits. Source is RA0"></metric>
|
||||
<metric name="SPI_RA_TGLIM_CU_FULL_CSN" block=SPI event=127 descr="Cycles where csn wants to req but all CU are at tg_limit"></metric>
|
||||
<metric name="SPI_RA_WVLIM_STALL_CSN" block=SPI event=133 descr="Number of clocks csn is stalled due to WAVE LIMIT."></metric>
|
||||
<metric name="SPI_SWC_CSC_WR" block=SPI event=189 descr="Number of clocks to write CSC waves to SGPRs (need to multiply this value by 4) Requires SPI_DEBUG_CNTL.DEBUG_PIPE_SEL to select source, DEBUG_PIPE_SEL = 1, source is CS1; DEBUG_PIPE_SEL = 2, source is CS2; DEBUG_PIPE_SEL = 3, source is CS3; default, source is CS0;"></metric>
|
||||
<metric name="SPI_VWC_CSC_WR" block=SPI event=195 descr="Number of clocks to write CSC waves to VGPRs (need to multiply this value by 4) Requires SPI_DEBUG_CNTL.DEBUG_PIPE_SEL to select source, DEBUG_PIPE_SEL = 1, source is CS1; DEBUG_PIPE_SEL = 2, source is CS2; DEBUG_PIPE_SEL = 3, source is CS3; default, source is CS0;"></metric>
|
||||
<metric name="SQ_ACCUM_PREV" block=SQ event=1 descr="For counter N, increment by the value of counter N-1. Only accumulates once every 4 cycles."></metric>
|
||||
<metric name="SQ_CYCLES" block=SQ event=2 descr="Clock cycles. (nondeterministic, per-simd, global)"></metric>
|
||||
<metric name="SQ_BUSY_CYCLES" block=SQ event=3 descr="Clock cycles while SQ is reporting that it is busy. (nondeterministic, per-simd, global)"></metric>
|
||||
<metric name="SQ_WAVES" block=SQ event=4 descr="Count number of waves sent to SQs. (per-simd, emulated, global)"></metric>
|
||||
<metric name="SQ_LEVEL_WAVES" block=SQ event=5 descr="Track the number of waves. Set ACCUM_PREV for the next counter to use this. (level, per-simd, global)"></metric>
|
||||
<metric name="SQ_WAVES_EQ_64" block=SQ event=6 descr="Count number of waves with exactly 64 active threads sent to SQs. (per-simd, emulated, global)"></metric>
|
||||
<metric name="SQ_WAVES_LT_64" block=SQ event=7 descr="Count number of waves with <64 active threads sent to SQs. (per-simd, emulated, global)"></metric>
|
||||
<metric name="SQ_WAVES_LT_48" block=SQ event=8 descr="Count number of waves with <48 active threads sent to SQs. (per-simd, emulated, global)"></metric>
|
||||
<metric name="SQ_WAVES_LT_32" block=SQ event=9 descr="Count number of waves sent <32 active threads sent to SQs. (per-simd, emulated, global)"></metric>
|
||||
<metric name="SQ_WAVES_LT_16" block=SQ event=10 descr="Count number of waves sent <16 active threads sent to SQs. (per-simd, emulated, global)"></metric>
|
||||
<metric name="SQ_BUSY_CU_CYCLES" block=SQ event=13 descr="Count quad-cycles each CU is busy. (nondeterministic, per-simd)"></metric>
|
||||
<metric name="SQ_ITEMS" block=SQ event=14 descr="Number of valid items per wave. (per-simd, global)"></metric>
|
||||
<metric name="SQ_INSTS" block=SQ event=25 descr="Number of instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU" block=SQ event=26 descr="Number of VALU instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_ADD_F16" block=SQ event=27 descr="Number of VALU ADD/SUB instructions on float16. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_MUL_F16" block=SQ event=28 descr="Number of VALU MUL instructions on float16. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_FMA_F16" block=SQ event=29 descr="Number of VALU FMA/MAD instructions on float16. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_TRANS_F16" block=SQ event=30 descr="Number of VALU transcendental instructions on float16. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_ADD_F32" block=SQ event=31 descr="Number of VALU ADD/SUB instructions on float32. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_MUL_F32" block=SQ event=32 descr="Number of VALU MUL instructions on float32. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_FMA_F32" block=SQ event=33 descr="Number of VALU FMA/MAD instructions on float32. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_TRANS_F32" block=SQ event=34 descr="Number of VALU transcendental instructions on float32. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_ADD_F64" block=SQ event=35 descr="Number of VALU ADD/SUB instructions on float64. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_MUL_F64" block=SQ event=36 descr="Number of VALU MUL instructions on float64. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_FMA_F64" block=SQ event=37 descr="Number of VALU FMA/MAD instructions on float64. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_TRANS_F64" block=SQ event=38 descr="Number of VALU transcendental instructions on float64. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_INT32" block=SQ event=39 descr="Number of VALU 32-bit integer (signed or unsigned) instructions. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_INT64" block=SQ event=40 descr="Number of VALU 64-bit integer (signed or unsigned) instructions. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_CVT" block=SQ event=41 descr="Number of VALU data conversion instructions. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_MFMA_I8" block=SQ event=42 descr="Number of VALU V_MFMA_*_I8 instructions. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_MFMA_F16" block=SQ event=43 descr="Number of VALU V_MFMA_*_F16 instructions. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_MFMA_BF16" block=SQ event=44 descr="Number of VALU V_MFMA_*_BF16 instructions. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_MFMA_F32" block=SQ event=45 descr="Number of VALU V_MFMA_*_F32 instructions. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_MFMA_F64" block=SQ event=46 descr="Number of VALU V_MFMA_*_F64 instructions. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_MFMA_MOPS_I8" block=SQ event=47 descr="Number of VALU matrix math operations (add or mul) performed dividied by 512, assuming a full EXEC mask, of data type I8. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_MFMA_MOPS_F16" block=SQ event=48 descr="Number of VALU matrix math operations (add or mul) performed dividied by 512, assuming a full EXEC mask, of data type F16. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_MFMA_MOPS_BF16" block=SQ event=49 descr="Number of VALU matrix math operations (add or mul) performed dividied by 512, assuming a full EXEC mask, of data type BF16. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_MFMA_MOPS_F32" block=SQ event=50 descr="Number of VALU matrix math operations (add or mul) performed dividied by 512, assuming a full EXEC mask, of data type F32. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_MFMA_MOPS_F64" block=SQ event=51 descr="Number of VALU matrix math operations (add or mul) performed dividied by 512, assuming a full EXEC mask, of data type F64. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_MFMA" block=SQ event=52 descr="Number of MFMA instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VMEM_WR" block=SQ event=53 descr="Number of VMEM write instructions issued (including FLAT). (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VMEM_RD" block=SQ event=54 descr="Number of VMEM read instructions issued (including FLAT). (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VMEM" block=SQ event=55 descr="Number of VMEM instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_SALU" block=SQ event=56 descr="Number of SALU instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_SMEM" block=SQ event=57 descr="Number of SMEM instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_FLAT" block=SQ event=58 descr="Number of FLAT instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_FLAT_LDS_ONLY" block=SQ event=59 descr="Number of FLAT instructions issued that read/wrote only from/to LDS (only works if EARLY_TA_DONE is enabled). (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_LDS" block=SQ event=60 descr="Number of LDS instructions issued (including FLAT). (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_GDS" block=SQ event=61 descr="Number of GDS instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_EXP_GDS" block=SQ event=63 descr="Number of EXP and GDS instructions issued, excluding skipped export instructions. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_BRANCH" block=SQ event=64 descr="Number of Branch instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_SENDMSG" block=SQ event=65 descr="Number of Sendmsg instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VSKIPPED" block=SQ event=66 descr="Number of vector instructions skipped. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INST_LEVEL_VMEM" block=SQ event=67 descr="Number of in-flight VMEM instructions. Set next counter to ACCUM_PREV and divide by INSTS_VMEM for average latency. Includes FLAT instructions. (per-simd, level, nondeterministic)"></metric>
|
||||
<metric name="SQ_INST_LEVEL_SMEM" block=SQ event=68 descr="Number of in-flight SMEM instructions (*2 load/store; *2 atomic; *2 memtime; *4 wb/inv). Set next counter to ACCUM_PREV and divide by INSTS_SMEM for average latency per smem request. Falls slightly short of total request latency because some fetches are divided into two requests that may finish at different times and this counter collects the average latency of the two. (per-simd, level, nondeterministic)"></metric>
|
||||
<metric name="SQ_INST_LEVEL_LDS" block=SQ event=69 descr="Number of in-flight LDS instructions. Set next counter to ACCUM_PREV and divide by INSTS_LDS for average latency. Includes FLAT instructions. (per-simd, level, nondeterministic)"></metric>
|
||||
<metric name="SQ_VALU_MFMA_BUSY_CYCLES" block=SQ event=72 descr="Number of cycles the MFMA ALU is busy (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_WAVE_CYCLES" block=SQ event=74 descr="Number of wave-cycles spent by waves in the CUs (per-simd, nondeterministic). Units in quad-cycles(4 cycles)"></metric>
|
||||
<metric name="SQ_WAIT_ANY" block=SQ event=85 descr="Number of wave-cycles spent waiting for anything (per-simd, nondeterministic). Units in quad-cycles(4 cycles)"></metric>
|
||||
<metric name="SQ_WAIT_INST_ANY" block=SQ event=88 descr="Number of wave-cycles spent waiting for any instruction issue. In units of 4 cycles. (per-simd, nondeterministic)"></metric>
|
||||
<metric name="SQ_ACTIVE_INST_ANY" block=SQ event=96 descr="Number of cycles each wave is working on an instruction. (per-simd, emulated). Units in quad-cycles(4 cycles)"></metric>
|
||||
<metric name="SQ_ACTIVE_INST_VMEM" block=SQ event=97 descr="Number of cycles the SQ instruction arbiter is working on a VMEM instruction. (per-simd, emulated). Units in quad-cycles(4 cycles)"></metric>
|
||||
<metric name="SQ_ACTIVE_INST_LDS" block=SQ event=98 descr="Number of cycles the SQ instruction arbiter is working on a LDS instruction. (per-simd, emulated). Units in quad-cycles(4 cycles)"></metric>
|
||||
<metric name="SQ_ACTIVE_INST_VALU" block=SQ event=99 descr="Number of cycles the SQ instruction arbiter is working on a VALU instruction. (per-simd, emulated). Units in quad-cycles(4 cycles)"></metric>
|
||||
<metric name="SQ_ACTIVE_INST_SCA" block=SQ event=100 descr="Number of cycles the SQ instruction arbiter is working on a SALU or SMEM instruction. (per-simd, emulated). Units in quad-cycles(4 cycles)"></metric>
|
||||
<metric name="SQ_ACTIVE_INST_EXP_GDS" block=SQ event=101 descr="Number of cycles the SQ instruction arbiter is working on an EXPORT or GDS instruction. (per-simd, emulated). Units in quad-cycles(4 cycles)"></metric>
|
||||
<metric name="SQ_ACTIVE_INST_MISC" block=SQ event=102 descr="Number of cycles the SQ instruction aribter is working on a BRANCH or SENDMSG instruction. (per-simd, emulated). Units in quad-cycles(4 cycles)"></metric>
|
||||
<metric name="SQ_ACTIVE_INST_FLAT" block=SQ event=103 descr="Number of cycles the SQ instruction arbiter is working on a FLAT instruction. (per-simd, emulated). Units in quad-cycles(4 cycles)"></metric>
|
||||
<metric name="SQ_INST_CYCLES_VMEM_WR" block=SQ event=104 descr="Number of cycles needed to send addr and cmd data for VMEM write instructions. (per-simd, emulated). Units in quad-cycles(4 cycles)"></metric>
|
||||
<metric name="SQ_INST_CYCLES_VMEM_RD" block=SQ event=105 descr="Number of cycles needed to send addr and cmd data for VMEM read instructions. (per-simd, emulated). Units in quad-cycles(4 cycles)"></metric>
|
||||
<metric name="SQ_INST_CYCLES_SMEM" block=SQ event=111 descr="Number of cycles needed to execute scalar memory reads. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INST_CYCLES_SALU" block=SQ event=112 descr="Number of cycles needed to execute non-memory read scalar operations. (per-simd, emulated). Units in quad-cycles(4 cycles)"></metric>
|
||||
<metric name="SQ_THREAD_CYCLES_VALU" block=SQ event=113 descr="Number of thread-cycles used to execute VALU operations (similar to INST_CYCLES_VALU but multiplied by # of active threads). (per-simd)"></metric>
|
||||
<metric name="SQ_IFETCH" block=SQ event=115 descr="Number of instruction fetch requests from cache. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_IFETCH_LEVEL" block=SQ event=116 descr="Number of instruction fetch requests from cache. (per-simd, level)"></metric>
|
||||
<metric name="SQ_LDS_BANK_CONFLICT" block=SQ event=121 descr="Number of cycles LDS is stalled by bank conflicts. (emulated)"></metric>
|
||||
<metric name="SQ_LDS_ADDR_CONFLICT" block=SQ event=122 descr="Number of cycles LDS is stalled by address conflicts. (emulated,nondeterministic)"></metric>
|
||||
<metric name="SQ_LDS_UNALIGNED_STALL" block=SQ event=123 descr="Number of cycles LDS is stalled processing flat unaligned load/store ops. (emulated)"></metric>
|
||||
<metric name="SQ_LDS_MEM_VIOLATIONS" block=SQ event=124 descr="Number of threads that have a memory violation in the LDS.(emulated)"></metric>
|
||||
<metric name="SQ_LDS_ATOMIC_RETURN" block=SQ event=125 descr="Number of atomic return cycles in LDS. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_LDS_IDX_ACTIVE" block=SQ event=126 descr="Number of cycles LDS is used for indexed (non-direct,non-interpolation) operations. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_ACCUM_PREV_HIRES" block=SQ event=185 descr="For counter N, increment by the value of counter N-1."></metric>
|
||||
<metric name="SQ_WAVES_RESTORED" block=SQ event=186 descr="Count number of context-restored waves sent to SQs. (per-simd, emulated, global)"></metric>
|
||||
<metric name="SQ_WAVES_SAVED" block=SQ event=187 descr="Count number of context-saved waves. (per-simd, emulated, global)"></metric>
|
||||
<metric name="SQ_INSTS_SMEM_NORM" block=SQ event=188 descr="Number of SMEM instructions issued normalized to match smem_level (*2 load/store; *2 atomic; *2 memtime; *4 wb/inv). (per-simd, emulated)"></metric>
|
||||
<metric name="SQC_DCACHE_INPUT_VALID_READYB" block=SQ event=260 descr="Input stalled by SQC (per-SQ, nondeterministic, unwindowed)"></metric>
|
||||
<metric name="SQC_TC_REQ" block=SQ event=262 descr="Total number of TC requests that were issued by instruction and constant caches. (No-Masking, nondeterministic)"></metric>
|
||||
<metric name="SQC_TC_INST_REQ" block=SQ event=263 descr="Number of insruction requests to the TC (No-Masking, nondeterministic)"></metric>
|
||||
<metric name="SQC_TC_DATA_READ_REQ" block=SQ event=264 descr="Number of data read requests to the TC (No-Masking, nondeterministic)"></metric>
|
||||
<metric name="SQC_TC_DATA_WRITE_REQ" block=SQ event=265 descr="Number of data write requests to the TC (No-Masking, nondeterministic)"></metric>
|
||||
<metric name="SQC_TC_DATA_ATOMIC_REQ" block=SQ event=266 descr="Number of data atomic requests to the TC (No-Masking, nondeterministic)"></metric>
|
||||
<metric name="SQC_TC_STALL" block=SQ event=267 descr="Valid request stalled TC request interface (no-credits). (No-Masking, nondeterministic, unwindowed)"></metric>
|
||||
<metric name="SQC_ICACHE_REQ" block=SQ event=270 descr="Number of requests. (per-SQ, per-Bank)"></metric>
|
||||
<metric name="SQC_ICACHE_HITS" block=SQ event=271 descr="Number of cache hits. (per-SQ, per-Bank, nondeterministic)"></metric>
|
||||
<metric name="SQC_ICACHE_MISSES" block=SQ event=272 descr="Number of cache misses, includes uncached requests. (per-SQ, per-Bank, nondeterministic)"></metric>
|
||||
<metric name="SQC_ICACHE_MISSES_DUPLICATE" block=SQ event=273 descr="Number of misses that were duplicates (access to a non-resident, miss pending CL). (per-SQ, per-Bank, nondeterministic)" ></metric>
|
||||
<metric name="SQC_DCACHE_REQ" block=SQ event=290 descr="Number of requests (post-bank-serialization). (per-SQ, per-Bank)"></metric>
|
||||
<metric name="SQC_DCACHE_HITS" block=SQ event=291 descr="Number of cache hits. (per-SQ, per-Bank, nondeterministic)"></metric>
|
||||
<metric name="SQC_DCACHE_MISSES" block=SQ event=292 descr="Number of cache misses, includes uncached requests. (per-SQ, per-Bank, nondeterministic)"></metric>
|
||||
<metric name="SQC_DCACHE_MISSES_DUPLICATE" block=SQ event=293 descr="Number of misses that were duplicates (access to a non-resident, miss pending CL). (per-SQ, per-Bank, nondeterministic)" ></metric>
|
||||
<metric name="SQC_DCACHE_ATOMIC" block=SQ event=298 descr="Number of atomic requests. (per-SQ, per-Bank)"></metric>
|
||||
<metric name="SQC_DCACHE_REQ_READ_1" block=SQ event=323 descr="Number of constant cache 1 dw read requests. (per-SQ)"></metric>
|
||||
<metric name="SQC_DCACHE_REQ_READ_2" block=SQ event=324 descr="Number of constant cache 2 dw read requests. (per-SQ)"></metric>
|
||||
<metric name="SQC_DCACHE_REQ_READ_4" block=SQ event=325 descr="Number of constant cache 4 dw read requests. (per-SQ)"></metric>
|
||||
<metric name="SQC_DCACHE_REQ_READ_8" block=SQ event=326 descr="Number of constant cache 8 dw read requests. (per-SQ)"></metric>
|
||||
<metric name="SQC_DCACHE_REQ_READ_16" block=SQ event=327 descr="Number of constant cache 16 dw read requests. (per-SQ)"></metric>
|
||||
<metric name="TA_TA_BUSY" block=TA event=15 descr="TA block is busy. Perf_Windowing not supported for this counter."></metric>
|
||||
<metric name="TA_TOTAL_WAVEFRONTS" block=TA event=32 descr="Total number of wavefronts processed by TA."></metric>
|
||||
<metric name="TA_BUFFER_WAVEFRONTS" block=TA event=44 descr="Number of buffer wavefronts processed by TA."></metric>
|
||||
<metric name="TA_BUFFER_READ_WAVEFRONTS" block=TA event=45 descr="Number of buffer read wavefronts processed by TA."></metric>
|
||||
<metric name="TA_BUFFER_WRITE_WAVEFRONTS" block=TA event=46 descr="Number of buffer write wavefronts processed by TA."></metric>
|
||||
<metric name="TA_BUFFER_ATOMIC_WAVEFRONTS" block=TA event=47 descr="Number of buffer atomic wavefronts processed by TA."></metric>
|
||||
<metric name="TA_BUFFER_TOTAL_CYCLES" block=TA event=49 descr="Number of buffer cycles issued to TC."></metric>
|
||||
<metric name="TA_BUFFER_COALESCED_READ_CYCLES" block=TA event=52 descr="Number of buffer coalesced read cycles issued to TC."></metric>
|
||||
<metric name="TA_BUFFER_COALESCED_WRITE_CYCLES" block=TA event=53 descr="Number of buffer coalesced write cycles issued to TC."></metric>
|
||||
<metric name="TA_ADDR_STALLED_BY_TC_CYCLES" block=TA event=54 descr="Number of cycles addr path stalled by TC. Perf_Windowing not supported for this counter."></metric>
|
||||
<metric name="TA_ADDR_STALLED_BY_TD_CYCLES" block=TA event=55 descr="Number of cycles addr path stalled by TD. Perf_Windowing not supported for this counter."></metric>
|
||||
<metric name="TA_DATA_STALLED_BY_TC_CYCLES" block=TA event=56 descr="Number of cycles data path stalled by TC. Perf_Windowing not supported for this counter."></metric>
|
||||
<metric name="TA_FLAT_WAVEFRONTS" block=TA event=100 descr="Number of flat opcode wavfronts processed by the TA."></metric>
|
||||
<metric name="TA_FLAT_READ_WAVEFRONTS" block=TA event=101 descr="Number of flat opcode reads processed by the TA."></metric>
|
||||
<metric name="TA_FLAT_WRITE_WAVEFRONTS" block=TA event=102 descr="Number of flat opcode writes processed by the TA."></metric>
|
||||
<metric name="TA_FLAT_ATOMIC_WAVEFRONTS" block=TA event=103 descr="Number of flat opcode atomics processed by the TA."></metric>
|
||||
<metric name="TD_TD_BUSY" block=TD event=1 descr="TD is processing or waiting for data. Perf_Windowing not supported for this counter."></metric>
|
||||
<metric name="TD_TC_STALL" block=TD event=15 descr="TD is stalled waiting for TC data."></metric>
|
||||
<metric name="TD_SPI_STALL" block=TD event=18 descr="TD is stalled SPI vinit"></metric>
|
||||
<metric name="TD_LOAD_WAVEFRONT" block=TD event=25 descr="Count the wavefronts with opcode = load, include atomics and store."></metric>
|
||||
<metric name="TD_ATOMIC_WAVEFRONT" block=TD event=26 descr="Count the wavefronts with opcode = atomic."></metric>
|
||||
<metric name="TD_STORE_WAVEFRONT" block=TD event=27 descr="Count the wavefronts with opcode = store."></metric>
|
||||
<metric name="TD_COALESCABLE_WAVEFRONT" block=TD event=32 descr="Count wavefronts that TA finds coalescable."></metric>
|
||||
<metric name="TCP_GATE_EN1" block=TCP event=0 descr="TCP interface clocks are turned on. Not Windowed."></metric>
|
||||
<metric name="TCP_GATE_EN2" block=TCP event=1 descr="TCP core clocks are turned on. Not Windowed."></metric>
|
||||
<metric name="TCP_TD_TCP_STALL_CYCLES" block=TCP event=7 descr="TD stalls TCP"></metric>
|
||||
<metric name="TCP_TCR_TCP_STALL_CYCLES" block=TCP event=8 descr="TCR stalls TCP_TCR_req interface"></metric>
|
||||
<metric name="TCP_READ_TAGCONFLICT_STALL_CYCLES" block=TCP event=11 descr="Tagram conflict stall on a read"></metric>
|
||||
<metric name="TCP_WRITE_TAGCONFLICT_STALL_CYCLES" block=TCP event=12 descr="Tagram conflict stall on a write"></metric>
|
||||
<metric name="TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES" block=TCP event=13 descr="Tagram conflict stall on an atomic"></metric>
|
||||
<metric name="TCP_PENDING_STALL_CYCLES" block=TCP event=22 descr="Stall due to data pending from L2"></metric>
|
||||
<metric name="TCP_TA_TCP_STATE_READ" block=TCP event=27 descr="Number of state reads"></metric>
|
||||
<metric name="TCP_VOLATILE" block=TCP event=28 descr="Total number of L1 volatile pixels/buffers from TA"></metric>
|
||||
<metric name="TCP_TOTAL_ACCESSES" block=TCP event=29 descr="Total number of pixels/buffers from TA. Equals TCP_PERF_SEL_TOTAL_READ+TCP_PERF_SEL_TOTAL_NONREAD"></metric>
|
||||
<metric name="TCP_TOTAL_READ" block=TCP event=30 descr="Total number of read pixels/buffers from TA. Equals TCP_PERF_SEL_TOTAL_HIT_LRU_READ + TCP_PERF_SEL_TOTAL_MISS_LRU_READ + TCP_PERF_SEL_TOTAL_MISS_EVICT_READ"></metric>
|
||||
<metric name="TCP_TOTAL_WRITE" block=TCP event=32 descr="Total number of local write pixels/buffers from TA. Equals TCP_PERF_SEL_TOTAL_MISS_LRU_WRITE+ TCP_PERF_SEL_TOTAL_MISS_EVICT_WRITE"></metric>
|
||||
<metric name="TCP_TOTAL_ATOMIC_WITH_RET" block=TCP event=38 descr="Total number of atomic with return pixels/buffers from TA"></metric>
|
||||
<metric name="TCP_TOTAL_ATOMIC_WITHOUT_RET" block=TCP event=39 descr="Total number of atomic without return pixels/buffers from TA"></metric>
|
||||
<metric name="TCP_TOTAL_WRITEBACK_INVALIDATES" block=TCP event=45 descr="Total number of cache invalidates. Equals TCP_PERF_SEL_TOTAL_WBINVL1+ TCP_PERF_SEL_TOTAL_WBINVL1_VOL+ TCP_PERF_SEL_CP_TCP_INVALIDATE+ TCP_PERF_SEL_SQ_TCP_INVALIDATE_VOL. Not Windowed."></metric>
|
||||
<metric name="TCP_UTCL1_REQUEST" block=TCP event=47 descr="Total CLIENT_UTCL1 NORMAL requests"></metric>
|
||||
<metric name="TCP_UTCL1_TRANSLATION_MISS" block=TCP event=48 descr="Total utcl1 translation misses"></metric>
|
||||
<metric name="TCP_UTCL1_TRANSLATION_HIT" block=TCP event=49 descr="Total utcl1 translation hits"></metric>
|
||||
<metric name="TCP_UTCL1_PERMISSION_MISS" block=TCP event=50 descr="Total utcl1 permission misses"></metric>
|
||||
<metric name="TCP_TOTAL_CACHE_ACCESSES" block=TCP event=60 descr="Count of total cache line (tag) accesses (includes hits and misses)."></metric>
|
||||
<metric name="TCP_TCP_LATENCY" block=TCP event=65 descr="Total TCP wave latency (from first clock of wave entering to first clock of wave leaving), divide by TA_TCP_STATE_READ to avg wave latency"></metric>
|
||||
<metric name="TCP_TCC_READ_REQ_LATENCY" block=TCP event=66 descr="Total TCP->TCC request latency for reads and atomics with return. Not Windowed."></metric>
|
||||
<metric name="TCP_TCC_WRITE_REQ_LATENCY" block=TCP event=67 descr="Total TCP->TCC request latency for writes and atomics without return. Not Windowed."></metric>
|
||||
<metric name="TCP_TCC_READ_REQ" block=TCP event=69 descr="Total read requests from TCP to all TCCs"></metric>
|
||||
<metric name="TCP_TCC_WRITE_REQ" block=TCP event=70 descr="Total write requests from TCP to all TCCs"></metric>
|
||||
<metric name="TCP_TCC_ATOMIC_WITH_RET_REQ" block=TCP event=71 descr="Total atomic with return requests from TCP to all TCCs"></metric>
|
||||
<metric name="TCP_TCC_ATOMIC_WITHOUT_RET_REQ" block=TCP event=72 descr="Total atomic without return requests from TCP to all TCCs"></metric>
|
||||
<metric name="TCP_TCC_NC_READ_REQ" block=TCP event=75 descr="Total read requests with NC mtype from this TCP to all TCCs"></metric>
|
||||
<metric name="TCP_TCC_NC_WRITE_REQ" block=TCP event=76 descr="Total write requests with NC mtype from this TCP to all TCCs"></metric>
|
||||
<metric name="TCP_TCC_NC_ATOMIC_REQ" block=TCP event=77 descr="Total atomic requests with NC mtype from this TCP to all TCCs"></metric>
|
||||
<metric name="TCP_TCC_UC_READ_REQ" block=TCP event=78 descr="Total read requests with UC mtype from this TCP to all TCCs"></metric>
|
||||
<metric name="TCP_TCC_UC_WRITE_REQ" block=TCP event=79 descr="Total write requests with UC mtype from this TCP to all TCCs"></metric>
|
||||
<metric name="TCP_TCC_UC_ATOMIC_REQ" block=TCP event=80 descr="Total atomic requests with UC mtype from this TCP to all TCCs"></metric>
|
||||
<metric name="TCP_TCC_CC_READ_REQ" block=TCP event=81 descr="Total write requests with CC mtype from this TCP to all TCCs"></metric>
|
||||
<metric name="TCP_TCC_CC_WRITE_REQ" block=TCP event=82 descr="Total write requests with CC mtype from this TCP to all TCCs"></metric>
|
||||
<metric name="TCP_TCC_CC_ATOMIC_REQ" block=TCP event=83 descr="Total atomic requests with CC mtype from this TCP to all TCCs"></metric>
|
||||
<metric name="TCP_TCC_RW_READ_REQ" block=TCP event=85 descr="Total write requests with RW mtype from this TCP to all TCCs"></metric>
|
||||
<metric name="TCP_TCC_RW_WRITE_REQ" block=TCP event=86 descr="Total write requests with RW mtype from this TCP to all TCCs"></metric>
|
||||
<metric name="TCP_TCC_RW_ATOMIC_REQ" block=TCP event=87 descr="Total atomic requests with RW mtype from this TCP to all TCCs"></metric>
|
||||
<metric name="TCA_CYCLE" block=TCA event=1 descr="Number of cycles. Not windowable."></metric>
|
||||
<metric name="TCA_BUSY" block=TCA event=2 descr="Number of cycles we have a request pending. Not windowable."></metric>
|
||||
<metric name="TCC_CYCLE" block=TCC event=1 descr="Number of cycles. Not windowable."></metric>
|
||||
<metric name="TCC_BUSY" block=TCC event=2 descr="Number of cycles we have a request pending. Not windowable."></metric>
|
||||
<metric name="TCC_REQ" block=TCC event=3 descr="Number of requests of all types. This is measured at the tag block. This may be more than the number of requests arriving at the TCC, but it is a good indication of the total amount of work that needs to be performed."></metric>
|
||||
<metric name="TCC_STREAMING_REQ" block=TCC event=4 descr="Number of streaming requests. This is measured at the tag block."></metric>
|
||||
<metric name="TCC_NC_REQ" block=TCC event=5 descr="The number of noncoherently cached requests. This is measured at the tag block."></metric>
|
||||
<metric name="TCC_UC_REQ" block=TCC event=6 descr="The number of uncached requests. This is measured at the tag block."></metric>
|
||||
<metric name="TCC_CC_REQ" block=TCC event=7 descr="The number of coherently cached requests. This is measured at the tag block."></metric>
|
||||
<metric name="TCC_RW_REQ" block=TCC event=8 descr="The number of RW requests. This is measured at the tag block."></metric>
|
||||
<metric name="TCC_PROBE" block=TCC event=9 descr="Number of probe requests. Not windowable."></metric>
|
||||
<metric name="TCC_PROBE_ALL" block=TCC event=10 descr="Number of external probe requests with with EA_TCC_preq_all== 1. Not windowable."></metric>
|
||||
<metric name="TCC_READ" block=TCC event=12 descr="Number of read requests. Compressed reads are included in this, but metadata reads are not included."></metric>
|
||||
<metric name="TCC_WRITE" block=TCC event=13 descr="Number of write requests."></metric>
|
||||
<metric name="TCC_ATOMIC" block=TCC event=14 descr="Number of atomic requests of all types."></metric>
|
||||
<metric name="TCC_HIT" block=TCC event=17 descr="Number of cache hits."></metric>
|
||||
<metric name="TCC_MISS" block=TCC event=19 descr="Number of cache misses. UC reads count as misses."></metric>
|
||||
<metric name="TCC_WRITEBACK" block=TCC event=22 descr="Number of lines written back to main memory. This includes writebacks of dirty lines and uncached write/atomic requests."></metric>
|
||||
<metric name="TCC_EA_WRREQ" block=TCC event=26 descr="Number of transactions (either 32-byte or 64-byte) going over the TC_EA_wrreq interface. Atomics may travel over the same interface and are generally classified as write requests. This does not include probe commands."></metric>
|
||||
<metric name="TCC_EA_WRREQ_64B" block=TCC event=27 descr="Number of 64-byte transactions going (64-byte write or CMPSWAP) over the TC_EA_wrreq interface."></metric>
|
||||
<metric name="TCC_EA_WR_UNCACHED_32B" block=TCC event=29 descr="Number of 32-byte write/atomic going over the TC_EA_wrreq interface due to uncached traffic. Note that CC mtypes can produce uncached requests, and those are included in this. A 64-byte request will be counted as 2"></metric>
|
||||
<metric name="TCC_EA_WRREQ_STALL" block=TCC event=30 descr="Number of cycles a write request was stalled."></metric>
|
||||
<metric name="TCC_EA_WRREQ_IO_CREDIT_STALL" block=TCC event=31 descr="Number of cycles a EA write request was stalled because the interface was out of IO credits."></metric>
|
||||
<metric name="TCC_EA_WRREQ_GMI_CREDIT_STALL" block=TCC event=32 descr="Number of cycles a EA write request was stalled because the interface was out of GMI credits."></metric>
|
||||
<metric name="TCC_EA_WRREQ_DRAM_CREDIT_STALL" block=TCC event=33 descr="Number of cycles a EA write request was stalled because the interface was out of DRAM credits."></metric>
|
||||
<metric name="TCC_TOO_MANY_EA_WRREQS_STALL" block=TCC event=34 descr="Number of cycles the TCC could not send a EA write request because it already reached its maximum number of pending EA write requests."></metric>
|
||||
<metric name="TCC_EA_WRREQ_LEVEL" block=TCC event=35 descr="The sum of the number of EA write requests in flight. This is primarily meant for measure average EA write latency. Average write latency = TCC_PERF_SEL_EA_WRREQ_LEVEL/TCC_PERF_SEL_EA_WRREQ."></metric>
|
||||
<metric name="TCC_EA_ATOMIC" block=TCC event=36 descr="Number of transactions going over the TC_EA_wrreq interface that are actually atomic requests."></metric>
|
||||
<metric name="TCC_EA_ATOMIC_LEVEL" block=TCC event=37 descr="The sum of the number of EA atomics in flight. This is primarily meant for measure average EA atomic latency. Average atomic latency = TCC_PERF_SEL_EA_WRREQ_ATOMIC_LEVEL/TCC_PERF_SEL_EA_WRREQ_ATOMIC."></metric>
|
||||
<metric name="TCC_EA_RDREQ" block=TCC event=38 descr="Number of TCC/EA read requests (either 32-byte or 64-byte)"></metric>
|
||||
<metric name="TCC_EA_RDREQ_32B" block=TCC event=39 descr="Number of 32-byte TCC/EA read requests"></metric>
|
||||
<metric name="TCC_EA_RD_UNCACHED_32B" block=TCC event=40 descr="Number of 32-byte TCC/EA read due to uncached traffic. A 64-byte request will be counted as 2"></metric>
|
||||
<metric name="TCC_EA_RDREQ_IO_CREDIT_STALL" block=TCC event=41 descr="Number of cycles there was a stall because the read request interface was out of IO credits. Stalls occur regardless of whether a read needed to be performed or not."></metric>
|
||||
<metric name="TCC_EA_RDREQ_GMI_CREDIT_STALL" block=TCC event=42 descr="Number of cycles there was a stall because the read request interface was out of GMI credits. Stalls occur regardless of whether a read needed to be performed or not."></metric>
|
||||
<metric name="TCC_EA_RDREQ_DRAM_CREDIT_STALL" block=TCC event=43 descr="Number of cycles there was a stall because the read request interface was out of DRAM credits. Stalls occur regardless of whether a read needed to be performed or not."></metric>
|
||||
<metric name="TCC_EA_RDREQ_LEVEL" block=TCC event=44 descr="The sum of the number of TCC/EA read requests in flight. This is primarily meant for measure average EA read latency. Average read latency = TCC_PERF_SEL_EA_RDREQ_LEVEL/TCC_PERF_SEL_EA_RDREQ."></metric>
|
||||
<metric name="TCC_TAG_STALL" block=TCC event=45 descr="Number of cycles the normal request pipeline in the tag was stalled for any reason. Normally, stalls of this nature are measured exactly from one point the pipeline, but that is not the case for this counter. Probes can stall the pipeline at a variety of places, and there is no single point that can reasonably measure the total stalls accurately."></metric>
|
||||
<metric name="TCC_NORMAL_WRITEBACK" block=TCC event=68 descr="Number of writebacks due to requests that are not writeback requests."></metric>
|
||||
<metric name="TCC_ALL_TC_OP_WB_WRITEBACK" block=TCC event=73 descr="Number of writebacks due to all TC_OP writeback requests."></metric>
|
||||
<metric name="TCC_NORMAL_EVICT" block=TCC event=74 descr="Number of evictions due to requests that are not invalidate or probe requests."></metric>
|
||||
<metric name="TCC_ALL_TC_OP_INV_EVICT" block=TCC event=80 descr="Number of evictions due to all TC_OP invalidate requests."></metric>
|
||||
<metric name="TCC_EA_RDREQ_DRAM" block=TCC event=102 descr="Number of TCC/EA read requests (either 32-byte or 64-byte) destined for DRAM (MC)."></metric>
|
||||
<metric name="TCC_EA_WRREQ_DRAM" block=TCC event=103 descr="Number of TCC/EA write requests (either 32-byte of 64-byte) destined for DRAM (MC)."></metric>
|
||||
</gfx90a>
|
||||
|
||||
<gfx940>
|
||||
<metric name="SQ_WAIT_INST_LDS" block=SQ event=96 descr="Number of wave-cycles spent waiting for LDS instruction issue. In units of 4 cycles. (per-simd, nondeterministic)"></metric>
|
||||
<metric name="TCP_TCP_TA_DATA_STALL_CYCLES" block=TCP event=6 descr="TCP stalls TA data interface. Now Windowed."></metric>
|
||||
<metric name="GRBM_COUNT" block=GRBM event=0 descr="Tie High - Count Number of Clocks"></metric>
|
||||
<metric name="GRBM_GUI_ACTIVE" block=GRBM event=2 descr="The GUI is Active"></metric>
|
||||
<metric name="GRBM_CP_BUSY" block=GRBM event=3 descr="Any of the Command Processor (CPG/CPC/CPF) blocks are busy."></metric>
|
||||
<metric name="GRBM_SPI_BUSY" block=GRBM event=11 descr="Any of the Shader Pipe Interpolators (SPI) are busy in the shader engine(s)."></metric>
|
||||
<metric name="GRBM_TA_BUSY" block=GRBM event=13 descr="Any of the Texture Pipes (TA) are busy in the shader engine(s)."></metric>
|
||||
<metric name="GRBM_TC_BUSY" block=GRBM event=28 descr="Any of the Texture Cache Blocks (TCP/TCI/TCA/TCC) are busy."></metric>
|
||||
<metric name="GRBM_CPC_BUSY" block=GRBM event=30 descr="The Command Processor Compute (CPC) is busy."></metric>
|
||||
<metric name="GRBM_CPF_BUSY" block=GRBM event=31 descr="The Command Processor Fetchers (CPF) is busy."></metric>
|
||||
<metric name="GRBM_UTCL2_BUSY" block=GRBM event=34 descr="The Unified Translation Cache Level-2 (UTCL2) block is busy."></metric>
|
||||
<metric name="GRBM_EA_BUSY" block=GRBM event=35 descr="The Efficiency Arbiter (EA) block is busy."></metric>
|
||||
<metric name="CPC_ME1_BUSY_FOR_PACKET_DECODE" block=CPC event=13 descr="Me1 busy for packet decode."></metric>
|
||||
<metric name="CPC_UTCL1_STALL_ON_TRANSLATION" block=CPC event=24 descr="One of the UTCL1s is stalled waiting on translation, XNACK or PENDING response."></metric>
|
||||
<metric name="CPC_CPC_STAT_BUSY" block=CPC event=25 descr="CPC Busy."></metric>
|
||||
<metric name="CPC_CPC_STAT_IDLE" block=CPC event=26 descr="CPC Idle."></metric>
|
||||
<metric name="CPC_CPC_STAT_STALL" block=CPC event=27 descr="CPC Stalled."></metric>
|
||||
<metric name="CPC_CPC_TCIU_BUSY" block=CPC event=28 descr="CPC TCIU interface Busy."></metric>
|
||||
<metric name="CPC_CPC_TCIU_IDLE" block=CPC event=29 descr="CPC TCIU interface Idle."></metric>
|
||||
<metric name="CPC_CPC_UTCL2IU_BUSY" block=CPC event=30 descr="CPC UTCL2 interface Busy."></metric>
|
||||
<metric name="CPC_CPC_UTCL2IU_IDLE" block=CPC event=31 descr="CPC UTCL2 interface Idle."></metric>
|
||||
<metric name="CPC_CPC_UTCL2IU_STALL" block=CPC event=32 descr="CPC UTCL2 interface Stalled waiting on Free, Tags or Translation."></metric>
|
||||
<metric name="CPC_ME1_DC0_SPI_BUSY" block=CPC event=33 descr="CPC Me1 Processor Busy."></metric>
|
||||
<metric name="CPF_CMP_UTCL1_STALL_ON_TRANSLATION" block=CPF event=20 descr="One of the Compute UTCL1s is stalled waiting on translation, XNACK or PENDING response."></metric>
|
||||
<metric name="CPF_CPF_STAT_BUSY" block=CPF event=23 descr="CPF Busy."></metric>
|
||||
<metric name="CPF_CPF_STAT_IDLE" block=CPF event=24 descr="CPF Idle."></metric>
|
||||
<metric name="CPF_CPF_STAT_STALL" block=CPF event=25 descr="CPF Stalled."></metric>
|
||||
<metric name="CPF_CPF_TCIU_BUSY" block=CPF event=26 descr="CPF TCIU interface Busy."></metric>
|
||||
<metric name="CPF_CPF_TCIU_IDLE" block=CPF event=27 descr="CPF TCIU interface Idle."></metric>
|
||||
<metric name="CPF_CPF_TCIU_STALL" block=CPF event=28 descr="CPF TCIU interface Stalled waiting on Free, Tags."></metric>
|
||||
<metric name="SPI_CSN_WINDOW_VALID" block=SPI event=47 descr="Clock count enabled by perfcounter_start event. Requires SPI_DEBUG_CNTL.DEBUG_PIPE_SEL to select source, DEBUG_PIPE_SEL = 1, source is CS1; DEBUG_PIPE_SEL = 2, source is CS2; DEBUG_PIPE_SEL = 3, source is CS3; default, source is CS0;"></metric>
|
||||
<metric name="SPI_CSN_BUSY" block=SPI event=48 descr="Number of clocks with outstanding waves (SPI or SH). Requires SPI_DEBUG_CNTL.DEBUG_PIPE_SEL to select source, DEBUG_PIPE_SEL = 1, source is CS1; DEBUG_PIPE_SEL = 2, source is CS2; DEBUG_PIPE_SEL = 3, source is CS3; default, source is CS0;"></metric>
|
||||
<metric name="SPI_CSN_NUM_THREADGROUPS" block=SPI event=49 descr="Number of threadgroups launched. Requires SPI_DEBUG_CNTL.DEBUG_PIPE_SEL to select source, DEBUG_PIPE_SEL = 1, source is CS1; DEBUG_PIPE_SEL = 2, source is CS2; DEBUG_PIPE_SEL = 3, source is CS3; default, source is CS0;"></metric>
|
||||
<metric name="SPI_CSN_WAVE" block=SPI event=52 descr="Number of waves. Requires SPI_DEBUG_CNTL.DEBUG_PIPE_SEL to select source, DEBUG_PIPE_SEL = 1, source is CS1; DEBUG_PIPE_SEL = 2, source is CS2; DEBUG_PIPE_SEL = 3, source is CS3; default, source is CS0;"></metric>
|
||||
<metric name="SPI_RA_REQ_NO_ALLOC" block=SPI event=79 descr="Arb cycles with requests but no allocation. Source is RA0"></metric>
|
||||
<metric name="SPI_RA_REQ_NO_ALLOC_CSN" block=SPI event=85 descr="Arb cycles with CSn req and no CSn alloc. Source is RA0"></metric>
|
||||
<metric name="SPI_RA_RES_STALL_CSN" block=SPI event=91 descr="Arb cycles with CSn req and no CSn fits. Source is RA0"></metric>
|
||||
<metric name="SPI_RA_TMP_STALL_CSN" block=SPI event=97 descr="Cycles where csn wants to req but does not fit in temp space."></metric>
|
||||
<metric name="SPI_RA_WAVE_SIMD_FULL_CSN" block=SPI event=103 descr="Sum of SIMD where WAVE can't take csn wave when !fits. Source is RA0"></metric>
|
||||
<metric name="SPI_RA_VGPR_SIMD_FULL_CSN" block=SPI event=109 descr="Sum of SIMD where VGPR can't take csn wave when !fits. Source is RA0"></metric>
|
||||
<metric name="SPI_RA_SGPR_SIMD_FULL_CSN" block=SPI event=115 descr="Sum of SIMD where SGPR can't take csn wave when !fits. Source is RA0"></metric>
|
||||
<metric name="SPI_RA_LDS_CU_FULL_CSN" block=SPI event=120 descr="Sum of CU where LDS can't take csn wave when !fits. Source is RA0"></metric>
|
||||
<metric name="SPI_RA_BAR_CU_FULL_CSN" block=SPI event=123 descr="Sum of CU where BARRIER can't take csn wave when !fits. Source is RA0"></metric>
|
||||
<metric name="SPI_RA_BULKY_CU_FULL_CSN" block=SPI event=125 descr="Sum of CU where BULKY can't take csn wave when !fits. Source is RA0"></metric>
|
||||
<metric name="SPI_RA_TGLIM_CU_FULL_CSN" block=SPI event=127 descr="Cycles where csn wants to req but all CU are at tg_limit"></metric>
|
||||
<metric name="SPI_RA_WVLIM_STALL_CSN" block=SPI event=133 descr="Number of clocks csn is stalled due to WAVE LIMIT."></metric>
|
||||
<metric name="SPI_SWC_CSC_WR" block=SPI event=189 descr="Number of clocks to write CSC waves to SGPRs (need to multiply this value by 4) Requires SPI_DEBUG_CNTL.DEBUG_PIPE_SEL to select source, DEBUG_PIPE_SEL = 1, source is CS1; DEBUG_PIPE_SEL = 2, source is CS2; DEBUG_PIPE_SEL = 3, source is CS3; default, source is CS0;"></metric>
|
||||
<metric name="SPI_VWC_CSC_WR" block=SPI event=195 descr="Number of clocks to write CSC waves to VGPRs (need to multiply this value by 4) Requires SPI_DEBUG_CNTL.DEBUG_PIPE_SEL to select source, DEBUG_PIPE_SEL = 1, source is CS1; DEBUG_PIPE_SEL = 2, source is CS2; DEBUG_PIPE_SEL = 3, source is CS3; default, source is CS0;"></metric>
|
||||
<metric name="SQ_ACCUM_PREV" block=SQ event=1 descr="For counter N, increment by the value of counter N-1. Only accumulates once every 4 cycles."></metric>
|
||||
<metric name="SQ_CYCLES" block=SQ event=2 descr="Clock cycles. (nondeterministic, per-simd, global)"></metric>
|
||||
<metric name="SQ_BUSY_CYCLES" block=SQ event=3 descr="Clock cycles while SQ is reporting that it is busy. (nondeterministic, per-simd, global)"></metric>
|
||||
<metric name="SQ_WAVES" block=SQ event=4 descr="Count number of waves sent to SQs. (per-simd, emulated, global)"></metric>
|
||||
<metric name="SQ_LEVEL_WAVES" block=SQ event=5 descr="Track the number of waves. Set ACCUM_PREV for the next counter to use this. (level, per-simd, global)"></metric>
|
||||
<metric name="SQ_WAVES_EQ_64" block=SQ event=6 descr="Count number of waves with exactly 64 active threads sent to SQs. (per-simd, emulated, global)"></metric>
|
||||
<metric name="SQ_WAVES_LT_64" block=SQ event=7 descr="Count number of waves with <64 active threads sent to SQs. (per-simd, emulated, global)"></metric>
|
||||
<metric name="SQ_WAVES_LT_48" block=SQ event=8 descr="Count number of waves with <48 active threads sent to SQs. (per-simd, emulated, global)"></metric>
|
||||
<metric name="SQ_WAVES_LT_32" block=SQ event=9 descr="Count number of waves sent <32 active threads sent to SQs. (per-simd, emulated, global)"></metric>
|
||||
<metric name="SQ_WAVES_LT_16" block=SQ event=10 descr="Count number of waves sent <16 active threads sent to SQs. (per-simd, emulated, global)"></metric>
|
||||
<metric name="SQ_BUSY_CU_CYCLES" block=SQ event=13 descr="Count quad-cycles each CU is busy. (nondeterministic, per-simd)"></metric>
|
||||
<metric name="SQ_ITEMS" block=SQ event=14 descr="Number of valid items per wave. (per-simd, global)"></metric>
|
||||
<metric name="SQ_INSTS" block=SQ event=25 descr="Number of instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU" block=SQ event=26 descr="Number of VALU instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_ADD_F16" block=SQ event=27 descr="Number of VALU ADD/SUB instructions on float16. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_MUL_F16" block=SQ event=28 descr="Number of VALU MUL instructions on float16. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_FMA_F16" block=SQ event=29 descr="Number of VALU FMA/MAD instructions on float16. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_TRANS_F16" block=SQ event=30 descr="Number of VALU transcendental instructions on float16. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_ADD_F32" block=SQ event=31 descr="Number of VALU ADD/SUB instructions on float32. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_MUL_F32" block=SQ event=32 descr="Number of VALU MUL instructions on float32. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_FMA_F32" block=SQ event=33 descr="Number of VALU FMA/MAD instructions on float32. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_TRANS_F32" block=SQ event=34 descr="Number of VALU transcendental instructions on float32. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_ADD_F64" block=SQ event=35 descr="Number of VALU ADD/SUB instructions on float64. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_MUL_F64" block=SQ event=36 descr="Number of VALU MUL instructions on float64. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_FMA_F64" block=SQ event=37 descr="Number of VALU FMA/MAD instructions on float64. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_TRANS_F64" block=SQ event=38 descr="Number of VALU transcendental instructions on float64. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_INT32" block=SQ event=39 descr="Number of VALU 32-bit integer (signed or unsigned) instructions. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_INT64" block=SQ event=40 descr="Number of VALU 64-bit integer (signed or unsigned) instructions. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_CVT" block=SQ event=41 descr="Number of VALU data conversion instructions. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_MFMA_I8" block=SQ event=42 descr="Number of VALU V_MFMA_*_I8 instructions. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_MFMA_F16" block=SQ event=43 descr="Number of VALU V_MFMA_*_F16 instructions. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_MFMA_BF16" block=SQ event=44 descr="Number of VALU V_MFMA_*_BF16 instructions. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_MFMA_F32" block=SQ event=45 descr="Number of VALU V_MFMA_*_F32 instructions. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_MFMA_F64" block=SQ event=46 descr="Number of VALU V_MFMA_*_F64 instructions. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_MFMA_MOPS_I8" block=SQ event=49 descr="Number of VALU matrix math operations (add or mul) performed dividied by 512, assuming a full EXEC mask, of data type I8. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_MFMA_MOPS_F16" block=SQ event=50 descr="Number of VALU matrix math operations (add or mul) performed dividied by 512, assuming a full EXEC mask, of data type F16. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_MFMA_MOPS_BF16" block=SQ event=51 descr="Number of VALU matrix math operations (add or mul) performed dividied by 512, assuming a full EXEC mask, of data type BF16. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_MFMA_MOPS_F32" block=SQ event=52 descr="Number of VALU matrix math operations (add or mul) performed dividied by 512, assuming a full EXEC mask, of data type F32. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VALU_MFMA_MOPS_F64" block=SQ event=53 descr="Number of VALU matrix math operations (add or mul) performed dividied by 512, assuming a full EXEC mask, of data type F64. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_MFMA" block=SQ event=56 descr="Number of MFMA instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VMEM_WR" block=SQ event=57 descr="Number of VMEM write instructions issued (including FLAT). (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VMEM_RD" block=SQ event=58 descr="Number of VMEM read instructions issued (including FLAT). (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VMEM" block=SQ event=59 descr="Number of VMEM instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_SALU" block=SQ event=60 descr="Number of SALU instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_SMEM" block=SQ event=61 descr="Number of SMEM instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_FLAT" block=SQ event=62 descr="Number of FLAT instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_LDS" block=SQ event=65 descr="Number of LDS instructions issued (including FLAT). (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_GDS" block=SQ event=66 descr="Number of GDS instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_EXP_GDS" block=SQ event=68 descr="Number of EXP and GDS instructions issued, excluding skipped export instructions. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_BRANCH" block=SQ event=69 descr="Number of Branch instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_SENDMSG" block=SQ event=70 descr="Number of Sendmsg instructions issued. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INSTS_VSKIPPED" block=SQ event=71 descr="Number of vector instructions skipped. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INST_LEVEL_VMEM" block=SQ event=72 descr="Number of in-flight VMEM instructions. Set next counter to ACCUM_PREV and divide by INSTS_VMEM for average latency. Includes FLAT instructions. (per-simd, level, nondeterministic)"></metric>
|
||||
<metric name="SQ_INST_LEVEL_SMEM" block=SQ event=73 descr="Number of in-flight SMEM instructions (*2 load/store; *2 atomic; *2 memtime; *4 wb/inv). Set next counter to ACCUM_PREV and divide by INSTS_SMEM for average latency per smem request. Falls slightly short of total request latency because some fetches are divided into two requests that may finish at different times and this counter collects the average latency of the two. (per-simd, level, nondeterministic)"></metric>
|
||||
<metric name="SQ_INST_LEVEL_LDS" block=SQ event=74 descr="Number of in-flight LDS instructions. Set next counter to ACCUM_PREV and divide by INSTS_LDS for average latency. Includes FLAT instructions. (per-simd, level, nondeterministic)"></metric>
|
||||
<metric name="SQ_VALU_MFMA_BUSY_CYCLES" block=SQ event=77 descr="Number of cycles the MFMA ALU is busy (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_WAVE_CYCLES" block=SQ event=79 descr="Number of wave-cycles spent by waves in the CUs (per-simd, nondeterministic). Units in quad-cycles(4 cycles)"></metric>
|
||||
<metric name="SQ_WAIT_ANY" block=SQ event=90 descr="Number of wave-cycles spent waiting for anything (per-simd, nondeterministic). Units in quad-cycles(4 cycles)"></metric>
|
||||
<metric name="SQ_WAIT_INST_ANY" block=SQ event=93 descr="Number of wave-cycles spent waiting for any instruction issue. In units of 4 cycles. (per-simd, nondeterministic)"></metric>
|
||||
<metric name="SQ_ACTIVE_INST_ANY" block=SQ event=101 descr="Number of cycles each wave is working on an instruction. (per-simd, emulated). Units in quad-cycles(4 cycles)"></metric>
|
||||
<metric name="SQ_ACTIVE_INST_VMEM" block=SQ event=102 descr="Number of cycles the SQ instruction arbiter is working on a VMEM instruction. (per-simd, emulated). Units in quad-cycles(4 cycles)"></metric>
|
||||
<metric name="SQ_ACTIVE_INST_LDS" block=SQ event=103 descr="Number of cycles the SQ instruction arbiter is working on a LDS instruction. (per-simd, emulated). Units in quad-cycles(4 cycles)"></metric>
|
||||
<metric name="SQ_ACTIVE_INST_VALU" block=SQ event=104 descr="Number of cycles the SQ instruction arbiter is working on a VALU instruction. (per-simd, emulated). Units in quad-cycles(4 cycles)"></metric>
|
||||
<metric name="SQ_ACTIVE_INST_SCA" block=SQ event=105 descr="Number of cycles the SQ instruction arbiter is working on a SALU or SMEM instruction. (per-simd, emulated). Units in quad-cycles(4 cycles)"></metric>
|
||||
<metric name="SQ_ACTIVE_INST_EXP_GDS" block=SQ event=106 descr="Number of cycles the SQ instruction arbiter is working on an EXPORT or GDS instruction. (per-simd, emulated). Units in quad-cycles(4 cycles)"></metric>
|
||||
<metric name="SQ_ACTIVE_INST_MISC" block=SQ event=107 descr="Number of cycles the SQ instruction aribter is working on a BRANCH or SENDMSG instruction. (per-simd, emulated). Units in quad-cycles(4 cycles)"></metric>
|
||||
<metric name="SQ_ACTIVE_INST_FLAT" block=SQ event=108 descr="Number of cycles the SQ instruction arbiter is working on a FLAT instruction. (per-simd, emulated). Units in quad-cycles(4 cycles)"></metric>
|
||||
<metric name="SQ_INST_CYCLES_VMEM_WR" block=SQ event=109 descr="Number of cycles needed to send addr and cmd data for VMEM write instructions. (per-simd, emulated). Units in quad-cycles(4 cycles)"></metric>
|
||||
<metric name="SQ_INST_CYCLES_VMEM_RD" block=SQ event=110 descr="Number of cycles needed to send addr and cmd data for VMEM read instructions. (per-simd, emulated). Units in quad-cycles(4 cycles)"></metric>
|
||||
<metric name="SQ_INST_CYCLES_SMEM" block=SQ event=116 descr="Number of cycles needed to execute scalar memory reads. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_INST_CYCLES_SALU" block=SQ event=117 descr="Number of cycles needed to execute non-memory read scalar operations. (per-simd, emulated). Units in quad-cycles(4 cycles)"></metric>
|
||||
<metric name="SQ_THREAD_CYCLES_VALU" block=SQ event=118 descr="Number of thread-cycles used to execute VALU operations (similar to INST_CYCLES_VALU but multiplied by # of active threads). (per-simd)"></metric>
|
||||
<metric name="SQ_IFETCH" block=SQ event=120 descr="Number of instruction fetch requests from cache. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_IFETCH_LEVEL" block=SQ event=121 descr="Number of instruction fetch requests from cache. (per-simd, level)"></metric>
|
||||
<metric name="SQ_LDS_BANK_CONFLICT" block=SQ event=126 descr="Number of cycles LDS is stalled by bank conflicts. (emulated)"></metric>
|
||||
<metric name="SQ_LDS_ADDR_CONFLICT" block=SQ event=127 descr="Number of cycles LDS is stalled by address conflicts. (emulated,nondeterministic)"></metric>
|
||||
<metric name="SQ_LDS_UNALIGNED_STALL" block=SQ event=128 descr="Number of cycles LDS is stalled processing flat unaligned load/store ops. (emulated)"></metric>
|
||||
<metric name="SQ_LDS_MEM_VIOLATIONS" block=SQ event=129 descr="Number of threads that have a memory violation in the LDS.(emulated)"></metric>
|
||||
<metric name="SQ_LDS_ATOMIC_RETURN" block=SQ event=130 descr="Number of atomic return cycles in LDS. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_LDS_IDX_ACTIVE" block=SQ event=131 descr="Number of cycles LDS is used for indexed (non-direct,non-interpolation) operations. (per-simd, emulated)"></metric>
|
||||
<metric name="SQ_ACCUM_PREV_HIRES" block=SQ event=184 descr="For counter N, increment by the value of counter N-1."></metric>
|
||||
<metric name="SQ_WAVES_RESTORED" block=SQ event=185 descr="Count number of context-restored waves sent to SQs. (per-simd, emulated, global)"></metric>
|
||||
<metric name="SQ_WAVES_SAVED" block=SQ event=186 descr="Count number of context-saved waves. (per-simd, emulated, global)"></metric>
|
||||
<metric name="SQ_INSTS_SMEM_NORM" block=SQ event=187 descr="Number of SMEM instructions issued normalized to match smem_level (*2 load/store; *2 atomic; *2 memtime; *4 wb/inv). (per-simd, emulated)"></metric>
|
||||
<metric name="SQC_DCACHE_INPUT_VALID_READYB" block=SQ event=260 descr="Input stalled by SQC (per-SQ, nondeterministic, unwindowed)"></metric>
|
||||
<metric name="SQC_TC_REQ" block=SQ event=262 descr="Total number of TC requests that were issued by instruction and constant caches. (No-Masking, nondeterministic)"></metric>
|
||||
<metric name="SQC_TC_INST_REQ" block=SQ event=263 descr="Number of insruction requests to the TC (No-Masking, nondeterministic)"></metric>
|
||||
<metric name="SQC_TC_DATA_READ_REQ" block=SQ event=264 descr="Number of data read requests to the TC (No-Masking, nondeterministic)"></metric>
|
||||
<metric name="SQC_TC_DATA_WRITE_REQ" block=SQ event=265 descr="Number of data write requests to the TC (No-Masking, nondeterministic)"></metric>
|
||||
<metric name="SQC_TC_DATA_ATOMIC_REQ" block=SQ event=266 descr="Number of data atomic requests to the TC (No-Masking, nondeterministic)"></metric>
|
||||
<metric name="SQC_TC_STALL" block=SQ event=267 descr="Valid request stalled TC request interface (no-credits). (No-Masking, nondeterministic, unwindowed)"></metric>
|
||||
<metric name="SQC_ICACHE_REQ" block=SQ event=270 descr="Number of requests. (per-SQ, per-Bank)"></metric>
|
||||
<metric name="SQC_ICACHE_HITS" block=SQ event=271 descr="Number of cache hits. (per-SQ, per-Bank, nondeterministic)"></metric>
|
||||
<metric name="SQC_ICACHE_MISSES" block=SQ event=272 descr="Number of cache misses, includes uncached requests. (per-SQ, per-Bank, nondeterministic)"></metric>
|
||||
<metric name="SQC_ICACHE_MISSES_DUPLICATE" block=SQ event=273 descr="Number of misses that were duplicates (access to a non-resident, miss pending CL). (per-SQ, per-Bank, nondeterministic)" ></metric>
|
||||
<metric name="SQC_DCACHE_REQ" block=SQ event=290 descr="Number of requests (post-bank-serialization). (per-SQ, per-Bank)"></metric>
|
||||
<metric name="SQC_DCACHE_HITS" block=SQ event=291 descr="Number of cache hits. (per-SQ, per-Bank, nondeterministic)"></metric>
|
||||
<metric name="SQC_DCACHE_MISSES" block=SQ event=292 descr="Number of cache misses, includes uncached requests. (per-SQ, per-Bank, nondeterministic)"></metric>
|
||||
<metric name="SQC_DCACHE_MISSES_DUPLICATE" block=SQ event=293 descr="Number of misses that were duplicates (access to a non-resident, miss pending CL). (per-SQ, per-Bank, nondeterministic)" ></metric>
|
||||
<metric name="SQC_DCACHE_ATOMIC" block=SQ event=298 descr="Number of atomic requests. (per-SQ, per-Bank)"></metric>
|
||||
<metric name="SQC_DCACHE_REQ_READ_1" block=SQ event=323 descr="Number of constant cache 1 dw read requests. (per-SQ)"></metric>
|
||||
<metric name="SQC_DCACHE_REQ_READ_2" block=SQ event=324 descr="Number of constant cache 2 dw read requests. (per-SQ)"></metric>
|
||||
<metric name="SQC_DCACHE_REQ_READ_4" block=SQ event=325 descr="Number of constant cache 4 dw read requests. (per-SQ)"></metric>
|
||||
<metric name="SQC_DCACHE_REQ_READ_8" block=SQ event=326 descr="Number of constant cache 8 dw read requests. (per-SQ)"></metric>
|
||||
<metric name="SQC_DCACHE_REQ_READ_16" block=SQ event=327 descr="Number of constant cache 16 dw read requests. (per-SQ)"></metric>
|
||||
<metric name="TA_TA_BUSY" block=TA event=13 descr="TA block is busy. Perf_Windowing not supported for this counter."></metric>
|
||||
<metric name="TA_TOTAL_WAVEFRONTS" block=TA event=29 descr="Total number of wavefronts processed by TA."></metric>
|
||||
<metric name="TA_BUFFER_WAVEFRONTS" block=TA event=32 descr="Number of buffer wavefronts processed by TA."></metric>
|
||||
<metric name="TA_BUFFER_READ_WAVEFRONTS" block=TA event=33 descr="Number of buffer read wavefronts processed by TA."></metric>
|
||||
<metric name="TA_BUFFER_WRITE_WAVEFRONTS" block=TA event=34 descr="Number of buffer write wavefronts processed by TA."></metric>
|
||||
<metric name="TA_BUFFER_ATOMIC_WAVEFRONTS" block=TA event=35 descr="Number of buffer atomic wavefronts processed by TA."></metric>
|
||||
<metric name="TA_BUFFER_TOTAL_CYCLES" block=TA event=37 descr="Number of buffer cycles issued to TC."></metric>
|
||||
<metric name="TA_BUFFER_COALESCED_READ_CYCLES" block=TA event=40 descr="Number of buffer coalesced read cycles issued to TC."></metric>
|
||||
<metric name="TA_BUFFER_COALESCED_WRITE_CYCLES" block=TA event=41 descr="Number of buffer coalesced write cycles issued to TC."></metric>
|
||||
<metric name="TA_ADDR_STALLED_BY_TC_CYCLES" block=TA event=42 descr="Number of cycles addr path stalled by TC. Perf_Windowing not supported for this counter."></metric>
|
||||
<metric name="TA_ADDR_STALLED_BY_TD_CYCLES" block=TA event=43 descr="Number of cycles addr path stalled by TD. Perf_Windowing not supported for this counter."></metric>
|
||||
<metric name="TA_DATA_STALLED_BY_TC_CYCLES" block=TA event=44 descr="Number of cycles data path stalled by TC. Perf_Windowing not supported for this counter."></metric>
|
||||
<metric name="TA_FLAT_WAVEFRONTS" block=TA event=51 descr="Number of flat opcode wavfronts processed by the TA."></metric>
|
||||
<metric name="TA_FLAT_READ_WAVEFRONTS" block=TA event=52 descr="Number of flat opcode reads processed by the TA."></metric>
|
||||
<metric name="TA_FLAT_WRITE_WAVEFRONTS" block=TA event=53 descr="Number of flat opcode writes processed by the TA."></metric>
|
||||
<metric name="TA_FLAT_ATOMIC_WAVEFRONTS" block=TA event=54 descr="Number of flat opcode atomics processed by the TA."></metric>
|
||||
<metric name="TD_TD_BUSY" block=TD event=1 descr="TD is processing or waiting for data. Perf_Windowing not supported for this counter."></metric>
|
||||
<metric name="TD_TC_STALL" block=TD event=12 descr="TD is stalled waiting for TC data."></metric>
|
||||
<metric name="TD_SPI_STALL" block=TD event=15 descr="TD is stalled SPI vinit"></metric>
|
||||
<metric name="TD_LOAD_WAVEFRONT" block=TD event=16 descr="Count the wavefronts with opcode = load, include atomics and store."></metric>
|
||||
<metric name="TD_ATOMIC_WAVEFRONT" block=TD event=17 descr="Count the wavefronts with opcode = atomic."></metric>
|
||||
<metric name="TD_STORE_WAVEFRONT" block=TD event=18 descr="Count the wavefronts with opcode = store."></metric>
|
||||
<metric name="TD_COALESCABLE_WAVEFRONT" block=TD event=21 descr="Count wavefronts that TA finds coalescable."></metric>
|
||||
<metric name="TCP_GATE_EN1" block=TCP event=0 descr="TCP interface clocks are turned on. Not Windowed."></metric>
|
||||
<metric name="TCP_GATE_EN2" block=TCP event=1 descr="TCP core clocks are turned on. Not Windowed."></metric>
|
||||
<metric name="TCP_TD_TCP_STALL_CYCLES" block=TCP event=7 descr="TD stalls TCP"></metric>
|
||||
<metric name="TCP_TCR_TCP_STALL_CYCLES" block=TCP event=8 descr="TCR stalls TCP_TCR_req interface"></metric>
|
||||
<metric name="TCP_READ_TAGCONFLICT_STALL_CYCLES" block=TCP event=10 descr="Tagram conflict stall on a read"></metric>
|
||||
<metric name="TCP_WRITE_TAGCONFLICT_STALL_CYCLES" block=TCP event=11 descr="Tagram conflict stall on a write"></metric>
|
||||
<metric name="TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES" block=TCP event=12 descr="Tagram conflict stall on an atomic"></metric>
|
||||
<metric name="TCP_PENDING_STALL_CYCLES" block=TCP event=21 descr="Stall due to data pending from L2"></metric>
|
||||
<metric name="TCP_TA_TCP_STATE_READ" block=TCP event=25 descr="Number of state reads"></metric>
|
||||
<metric name="TCP_VOLATILE" block=TCP event=26 descr="Total number of L1 volatile pixels/buffers from TA"></metric>
|
||||
<metric name="TCP_TOTAL_ACCESSES" block=TCP event=27 descr="Total number of pixels/buffers from TA. Equals TCP_PERF_SEL_TOTAL_READ+TCP_PERF_SEL_TOTAL_NONREAD"></metric>
|
||||
<metric name="TCP_TOTAL_READ" block=TCP event=28 descr="Total number of read pixels/buffers from TA. Equals TCP_PERF_SEL_TOTAL_HIT_LRU_READ + TCP_PERF_SEL_TOTAL_MISS_LRU_READ + TCP_PERF_SEL_TOTAL_MISS_EVICT_READ"></metric>
|
||||
<metric name="TCP_TOTAL_WRITE" block=TCP event=30 descr="Total number of local write pixels/buffers from TA. Equals TCP_PERF_SEL_TOTAL_MISS_LRU_WRITE+ TCP_PERF_SEL_TOTAL_MISS_EVICT_WRITE"></metric>
|
||||
<metric name="TCP_TOTAL_ATOMIC_WITH_RET" block=TCP event=36 descr="Total number of atomic with return pixels/buffers from TA"></metric>
|
||||
<metric name="TCP_TOTAL_ATOMIC_WITHOUT_RET" block=TCP event=37 descr="Total number of atomic without return pixels/buffers from TA"></metric>
|
||||
<metric name="TCP_TOTAL_WRITEBACK_INVALIDATES" block=TCP event=43 descr="Total number of cache invalidates. Equals TCP_PERF_SEL_TOTAL_WBINVL1+ TCP_PERF_SEL_TOTAL_WBINVL1_VOL+ TCP_PERF_SEL_CP_TCP_INVALIDATE+ TCP_PERF_SEL_SQ_TCP_INVALIDATE_VOL. Not Windowed."></metric>
|
||||
<metric name="TCP_UTCL1_REQUEST" block=TCP event=45 descr="Total CLIENT_UTCL1 NORMAL requests"></metric>
|
||||
<metric name="TCP_UTCL1_TRANSLATION_MISS" block=TCP event=47 descr="Total utcl1 translation misses"></metric>
|
||||
<metric name="TCP_UTCL1_TRANSLATION_HIT" block=TCP event=48 descr="Total utcl1 translation hits"></metric>
|
||||
<metric name="TCP_UTCL1_PERMISSION_MISS" block=TCP event=49 descr="Total utcl1 permission misses"></metric>
|
||||
<metric name="TCP_TOTAL_CACHE_ACCESSES" block=TCP event=60 descr="Count of total cache line (tag) accesses (includes hits and misses)."></metric>
|
||||
<metric name="TCP_TCC_READ_REQ" block=TCP event=65 descr="Total read requests from TCP to all TCCs"></metric>
|
||||
<metric name="TCP_TCC_WRITE_REQ" block=TCP event=66 descr="Total write requests from TCP to all TCCs"></metric>
|
||||
<metric name="TCP_TCC_ATOMIC_WITH_RET_REQ" block=TCP event=67 descr="Total atomic with return requests from TCP to all TCCs"></metric>
|
||||
<metric name="TCP_TCC_ATOMIC_WITHOUT_RET_REQ" block=TCP event=68 descr="Total atomic without return requests from TCP to all TCCs"></metric>
|
||||
<metric name="TCP_TCC_NC_READ_REQ" block=TCP event=71 descr="Total read requests with NC mtype from this TCP to all TCCs"></metric>
|
||||
<metric name="TCP_TCC_NC_WRITE_REQ" block=TCP event=72 descr="Total write requests with NC mtype from this TCP to all TCCs"></metric>
|
||||
<metric name="TCP_TCC_NC_ATOMIC_REQ" block=TCP event=73 descr="Total atomic requests with NC mtype from this TCP to all TCCs"></metric>
|
||||
<metric name="TCP_TCC_UC_READ_REQ" block=TCP event=74 descr="Total read requests with UC mtype from this TCP to all TCCs"></metric>
|
||||
<metric name="TCP_TCC_UC_WRITE_REQ" block=TCP event=75 descr="Total write requests with UC mtype from this TCP to all TCCs"></metric>
|
||||
<metric name="TCP_TCC_UC_ATOMIC_REQ" block=TCP event=76 descr="Total atomic requests with UC mtype from this TCP to all TCCs"></metric>
|
||||
<metric name="TCP_TCC_CC_READ_REQ" block=TCP event=77 descr="Total write requests with CC mtype from this TCP to all TCCs"></metric>
|
||||
<metric name="TCP_TCC_CC_WRITE_REQ" block=TCP event=78 descr="Total write requests with CC mtype from this TCP to all TCCs"></metric>
|
||||
<metric name="TCP_TCC_CC_ATOMIC_REQ" block=TCP event=79 descr="Total atomic requests with CC mtype from this TCP to all TCCs"></metric>
|
||||
<metric name="TCP_TCC_RW_READ_REQ" block=TCP event=80 descr="Total write requests with RW mtype from this TCP to all TCCs"></metric>
|
||||
<metric name="TCP_TCC_RW_WRITE_REQ" block=TCP event=81 descr="Total write requests with RW mtype from this TCP to all TCCs"></metric>
|
||||
<metric name="TCP_TCC_RW_ATOMIC_REQ" block=TCP event=82 descr="Total atomic requests with RW mtype from this TCP to all TCCs"></metric>
|
||||
<metric name="TCA_CYCLE" block=TCA event=1 descr="Number of cycles. Not windowable."></metric>
|
||||
<metric name="TCA_BUSY" block=TCA event=2 descr="Number of cycles we have a request pending. Not windowable."></metric>
|
||||
<metric name="TCC_CYCLE" block=TCC event=1 descr="Number of cycles. Not windowable."></metric>
|
||||
<metric name="TCC_BUSY" block=TCC event=2 descr="Number of cycles we have a request pending. Not windowable."></metric>
|
||||
<metric name="TCC_REQ" block=TCC event=3 descr="Number of requests of all types. This is measured at the tag block. This may be more than the number of requests arriving at the TCC, but it is a good indication of the total amount of work that needs to be performed."></metric>
|
||||
<metric name="TCC_STREAMING_REQ" block=TCC event=4 descr="Number of streaming requests. This is measured at the tag block."></metric>
|
||||
<metric name="TCC_NC_REQ" block=TCC event=5 descr="The number of noncoherently cached requests. This is measured at the tag block."></metric>
|
||||
<metric name="TCC_UC_REQ" block=TCC event=6 descr="The number of uncached requests. This is measured at the tag block."></metric>
|
||||
<metric name="TCC_CC_REQ" block=TCC event=7 descr="The number of coherently cached requests. This is measured at the tag block."></metric>
|
||||
<metric name="TCC_RW_REQ" block=TCC event=8 descr="The number of RW requests. This is measured at the tag block."></metric>
|
||||
<metric name="TCC_PROBE" block=TCC event=9 descr="Number of probe requests. Not windowable."></metric>
|
||||
<metric name="TCC_PROBE_ALL" block=TCC event=10 descr="Number of external probe requests with with EA_TCC_preq_all== 1. Not windowable."></metric>
|
||||
<metric name="TCC_READ" block=TCC event=12 descr="Number of read requests. Compressed reads are included in this, but metadata reads are not included."></metric>
|
||||
<metric name="TCC_WRITE" block=TCC event=13 descr="Number of write requests."></metric>
|
||||
<metric name="TCC_ATOMIC" block=TCC event=14 descr="Number of atomic requests of all types."></metric>
|
||||
<metric name="TCC_HIT" block=TCC event=17 descr="Number of cache hits."></metric>
|
||||
<metric name="TCC_MISS" block=TCC event=19 descr="Number of cache misses. UC reads count as misses."></metric>
|
||||
<metric name="TCC_WRITEBACK" block=TCC event=22 descr="Number of lines written back to main memory. This includes writebacks of dirty lines and uncached write/atomic requests."></metric>
|
||||
<metric name="TCC_EA0_WRREQ" block=TCC event=26 descr="Number of transactions (either 32-byte or 64-byte) going over the TC_EA_wrreq interface. Atomics may travel over the same interface and are generally classified as write requests. This does not include probe commands."></metric>
|
||||
<metric name="TCC_EA0_WRREQ_64B" block=TCC event=27 descr="Number of 64-byte transactions going (64-byte write or CMPSWAP) over the TC_EA_wrreq interface."></metric>
|
||||
<metric name="TCC_EA0_WR_UNCACHED_32B" block=TCC event=29 descr="Number of 32-byte write/atomic going over the TC_EA_wrreq interface due to uncached traffic. Note that CC mtypes can produce uncached requests, and those are included in this. A 64-byte request will be counted as 2"></metric>
|
||||
<metric name="TCC_EA0_WRREQ_STALL" block=TCC event=30 descr="Number of cycles a write request was stalled."></metric>
|
||||
<metric name="TCC_EA0_WRREQ_IO_CREDIT_STALL" block=TCC event=31 descr="Number of cycles a EA write request was stalled because the interface was out of IO credits."></metric>
|
||||
<metric name="TCC_EA0_WRREQ_GMI_CREDIT_STALL" block=TCC event=32 descr="Number of cycles a EA write request was stalled because the interface was out of GMI credits."></metric>
|
||||
<metric name="TCC_EA0_WRREQ_DRAM_CREDIT_STALL" block=TCC event=33 descr="Number of cycles a EA write request was stalled because the interface was out of DRAM credits."></metric>
|
||||
<metric name="TCC_TOO_MANY_EA_WRREQS_STALL" block=TCC event=34 descr="Number of cycles the TCC could not send a EA write request because it already reached its maximum number of pending EA write requests."></metric>
|
||||
<metric name="TCC_EA0_WRREQ_LEVEL" block=TCC event=35 descr="The sum of the number of EA write requests in flight. This is primarily meant for measure average EA write latency. Average write latency = TCC_PERF_SEL_EA_WRREQ_LEVEL/TCC_PERF_SEL_EA_WRREQ."></metric>
|
||||
<metric name="TCC_EA0_ATOMIC" block=TCC event=36 descr="Number of transactions going over the TC_EA_wrreq interface that are actually atomic requests."></metric>
|
||||
<metric name="TCC_EA0_ATOMIC_LEVEL" block=TCC event=37 descr="The sum of the number of EA atomics in flight. This is primarily meant for measure average EA atomic latency. Average atomic latency = TCC_PERF_SEL_EA_WRREQ_ATOMIC_LEVEL/TCC_PERF_SEL_EA_WRREQ_ATOMIC."></metric>
|
||||
<metric name="TCC_EA0_RDREQ" block=TCC event=38 descr="Number of TCC/EA read requests (either 32-byte or 64-byte)"></metric>
|
||||
<metric name="TCC_EA0_RDREQ_32B" block=TCC event=39 descr="Number of 32-byte TCC/EA read requests"></metric>
|
||||
<metric name="TCC_EA0_RD_UNCACHED_32B" block=TCC event=40 descr="Number of 32-byte TCC/EA read due to uncached traffic. A 64-byte request will be counted as 2"></metric>
|
||||
<metric name="TCC_EA0_RDREQ_IO_CREDIT_STALL" block=TCC event=41 descr="Number of cycles there was a stall because the read request interface was out of IO credits. Stalls occur regardless of whether a read needed to be performed or not."></metric>
|
||||
<metric name="TCC_EA0_RDREQ_GMI_CREDIT_STALL" block=TCC event=42 descr="Number of cycles there was a stall because the read request interface was out of GMI credits. Stalls occur regardless of whether a read needed to be performed or not."></metric>
|
||||
<metric name="TCC_EA0_RDREQ_DRAM_CREDIT_STALL" block=TCC event=43 descr="Number of cycles there was a stall because the read request interface was out of DRAM credits. Stalls occur regardless of whether a read needed to be performed or not."></metric>
|
||||
<metric name="TCC_EA0_RDREQ_LEVEL" block=TCC event=44 descr="The sum of the number of TCC/EA read requests in flight. This is primarily meant for measure average EA read latency. Average read latency = TCC_PERF_SEL_EA_RDREQ_LEVEL/TCC_PERF_SEL_EA_RDREQ."></metric>
|
||||
<metric name="TCC_TAG_STALL" block=TCC event=45 descr="Number of cycles the normal request pipeline in the tag was stalled for any reason. Normally, stalls of this nature are measured exactly from one point the pipeline, but that is not the case for this counter. Probes can stall the pipeline at a variety of places, and there is no single point that can reasonably measure the total stalls accurately."></metric>
|
||||
<metric name="TCC_NORMAL_WRITEBACK" block=TCC event=68 descr="Number of writebacks due to requests that are not writeback requests."></metric>
|
||||
<metric name="TCC_ALL_TC_OP_WB_WRITEBACK" block=TCC event=73 descr="Number of writebacks due to all TC_OP writeback requests."></metric>
|
||||
<metric name="TCC_NORMAL_EVICT" block=TCC event=74 descr="Number of evictions due to requests that are not invalidate or probe requests."></metric>
|
||||
<metric name="TCC_ALL_TC_OP_INV_EVICT" block=TCC event=80 descr="Number of evictions due to all TC_OP invalidate requests."></metric>
|
||||
<metric name="TCC_EA0_RDREQ_DRAM" block=TCC event=102 descr="Number of TCC/EA read requests (either 32-byte or 64-byte) destined for DRAM (MC)."></metric>
|
||||
<metric name="TCC_EA0_WRREQ_DRAM" block=TCC event=103 descr="Number of TCC/EA write requests (either 32-byte of 64-byte) destined for DRAM (MC)."></metric>
|
||||
</gfx940>
|
||||
|
||||
<gfx10>
|
||||
<metric name="GRBM_COUNT" block=GRBM event=0 descr="Tie High - Count Number of Clocks"></metric>
|
||||
<metric name="GRBM_GUI_ACTIVE" block=GRBM event=2 descr="The GUI is Active"></metric>
|
||||
<metric name="GRBM_CP_BUSY" block=GRBM event=3 descr="Any of the Command Processor (CPG/CPC/CPF) blocks are busy."></metric>
|
||||
<metric name="GRBM_SPI_BUSY" block=GRBM event=11 descr="Any of the Shader Pipe Interpolators (SPI) are busy in the shader engine(s)."></metric>
|
||||
<metric name="GRBM_TA_BUSY" block=GRBM event=13 descr="Any of the Texture Pipes (TA) are busy in the shader engine(s)."></metric>
|
||||
<metric name="GRBM_GDS_BUSY" block=GRBM event=25 descr="The Global Data Share (GDS) is busy."></metric>
|
||||
<metric name="GRBM_EA_BUSY" block=GRBM event=35 descr="The Efficiency Arbiter (EA) block is busy."></metric>
|
||||
<metric name="GRBM_GL2CC_BUSY" block=GRBM event=40 descr="The GL2CC block is busy."></metric>
|
||||
|
||||
<metric name="GL2C_HIT" block=GL2C event=42 descr="Number of cache hits"></metric>
|
||||
<metric name="GL2C_MISS" block=GL2C event=43 descr="Number of cache misses. UC reads count as misses."></metric>
|
||||
<metric name="GL2C_MC_WRREQ" block=GL2C event=83 descr="Number of transactions (either 32-byte or 64-byte) going over the GL2C_EA_wrreq interface. Atomics may travel over the same interface and are generally classified as write requests. This does not include probe commands"></metric>
|
||||
<metric name="GL2C_EA_WRREQ_64B" block=GL2C event=85 descr="Number of 64-byte transactions going (64-byte write or CMPSWAP) over the TC_EA_wrreq interface."></metric>
|
||||
<metric name="GL2C_MC_WRREQ_STALL" block=GL2C event=88 descr="Number of cycles a write request was stalled."></metric>
|
||||
<metric name="GL2C_MC_RDREQ" block=GL2C event=96 descr="Number of GL2C/EA read requests (either 32-byte or 64-byte or 128-byte)."></metric>
|
||||
<metric name="GL2C_EA_RDREQ_32B" block=GL2C event=99 descr="Number of 32-byte GL2C/EA read requests"></metric>
|
||||
<metric name="GL2C_EA_RDREQ_64B" block=GL2C event=100 descr="Number of 64-byte GL2C/EA read requests"></metric>
|
||||
<metric name="GL2C_EA_RDREQ_96B" block=GL2C event=101 descr="Number of 96-byte GL2C/EA read requests"></metric>
|
||||
<metric name="GL2C_EA_RDREQ_128B" block=GL2C event=102 descr="Number of 128-byte GL2C/EA read requests"></metric>
|
||||
|
||||
<metric name="SQ_WAVES" block=SQ event=4 descr="Count number of waves sent to SQs. {emulated, global, C1}"></metric>
|
||||
<metric name="SQ_WAVE_CYCLES" block=SQ event=26 descr="Number of clock cycles spent by waves in the SQs. Incremented by # of living (valid) waves each cycle. {nondeterministic, C1}"></metric>
|
||||
<metric name="SQ_WAIT_INST_ANY" block=SQ event=28 descr="Number of clock cycles spent waiting for any instruction issue. In units of cycles. {nondeterministic}"></metric>
|
||||
<metric name="SQ_WAIT_ANY" block=SQ event=37 descr="Number of clock cycles spent waiting for anything. {nondeterministic, C1}"></metric>
|
||||
<metric name="SQ_INSTS_WAVE32" block=SQ event=71 descr="Number of wave32 instructions issued, for flat, lds, valu, tex. {emulated, C1}"></metric>
|
||||
<metric name="SQ_INSTS_WAVE32_LDS" block=SQ event=74 descr="Number of wave32 LDS indexed instructions issued. Wave64 may count 1 or 2, depending on what gets issued. {emulated, C1}"></metric>
|
||||
<metric name="SQ_INSTS_WAVE32_VALU" block=SQ event=75 descr="Number of wave32 valu instructions issued. Wave64 may count 1 or 2, depending on what gets issued. {emulated, C1}"></metric>
|
||||
<metric name="SQ_WAVE32_INSTS" block=SQ event=84 descr="Number of instructions issued by wave32 waves. Skipped instructions are not counted. {emulated}"></metric>
|
||||
<metric name="SQ_WAVE64_INSTS" block=SQ event=85 descr="Number of instructions issued by wave64 waves. Skipped instructions are not counted. {emulated}"></metric>
|
||||
<metric name="SQ_INST_LEVEL_GDS" block=SQ event=98 descr="Number of in-flight GDS instructions. Set next counter to ACCUM_PREV and divide by INSTS_GDS for average latency. {level, nondeterministic, C1}"></metric>
|
||||
<metric name="SQ_INST_LEVEL_LDS" block=SQ event=99 descr="Number of in-flight LDS instructions. Set next counter to ACCUM_PREV and divide by INSTS_LDS for average latency. Includes FLAT instructions. {level, nondeterministic, C1}"></metric>
|
||||
<metric name="SQ_INST_CYCLES_VMEM" block=SQ event=120 descr="Number of cycles needed to send addr and data for VMEM (lds, buffer, image, flat, scratch, global) instructions, windowed by perf_en. {emulated, C1}"></metric>
|
||||
<metric name="SQC_LDS_BANK_CONFLICT" block=SQ event=285 descr="Number of cycles LDS is stalled by bank conflicts. (emulated, C1)"></metric>
|
||||
<metric name="SQC_LDS_IDX_ACTIVE" block=SQ event=290 descr="Number of cycles LDS is used for indexed (non-direct,non-interpolation) operations. {per-simd, emulated, C1}"></metric>
|
||||
<metric name="SQ_INSTS_VALU" block=SQ event=64 descr="Number of VALU instructions issued excluding skipped instructions. {emulated, C1}"></metric>
|
||||
<metric name="SQ_INSTS_SALU" block=SQ event=60 descr="Number of SALU instructions issued. {emulated, C1}"></metric>
|
||||
<metric name="SQ_INSTS_SMEM" block=SQ event=61 descr="Number of SMEM instructions issued. {emulated, C1}"></metric>
|
||||
<metric name="SQ_INSTS_FLAT" block=SQ event=57 descr="Number of FLAT instructions issued. {emulated, C2}"></metric>
|
||||
<metric name="SQ_INSTS_LDS" block=SQ event=59 descr="Number of LDS indexed instructions issued. {emulated, C1}"></metric>
|
||||
<metric name="SQ_INSTS_GDS" block=SQ event=55 descr="Number of GDS instructions issued. {emulated, C1}"></metric>
|
||||
<metric name="SQ_WAIT_INST_LDS" block=SQ event=31 descr="Number of clock cycles spent waiting for LDS (indexed) instruction issue. In units of cycles. {nondeterministic, C1}"></metric>
|
||||
|
||||
<metric name="TA_TA_BUSY" block=TA event=15 descr="TA block is busy. Perf_Windowing not supported for this counter."></metric>
|
||||
<metric name="TA_FLAT_LOAD_WAVEFRONTS" block=TA event=101 descr=" Number of flat load vec32 packets processed by TA, same as flat_read_wavefronts in earlier IP"></metric>
|
||||
<metric name="TA_FLAT_STORE_WAVEFRONTS" block=TA event=102 descr="Number of flat store vec32 packets processed by TA, same as flat_write_wavefronts in earlier IP"></metric>
|
||||
</gfx10>
|
||||
|
||||
<gfx1030 base="gfx10">
|
||||
</gfx1030>
|
||||
|
||||
<gfx1031 base="gfx10">
|
||||
</gfx1031>
|
||||
|
||||
<gfx1032 base="gfx10">
|
||||
</gfx1032>
|
||||
|
||||
+538
@@ -0,0 +1,538 @@
|
||||
#include "basic_counters.xml"
|
||||
|
||||
<gfx8_expr>
|
||||
<metric name="TA_BUSY_avr" expr=avr(TA_TA_BUSY,16) descr="TA block is busy. Average over TA instances."></metric>
|
||||
<metric name="TA_BUSY_max" expr=max(TA_TA_BUSY,16) descr="TA block is busy. Max over TA instances."></metric>
|
||||
<metric name="TA_BUSY_min" expr=min(TA_TA_BUSY,16) descr="TA block is busy. Min over TA instances."></metric>
|
||||
<metric name="TA_FLAT_READ_WAVEFRONTS_sum" expr=sum(TA_FLAT_READ_WAVEFRONTS,16) descr="Number of flat opcode reads processed by the TA. Sum over TA instances."></metric>
|
||||
<metric name="TA_FLAT_WRITE_WAVEFRONTS_sum" expr=sum(TA_FLAT_WRITE_WAVEFRONTS,16) descr="Number of flat opcode writes processed by the TA. Sum over TA instances."></metric>
|
||||
|
||||
<metric name="TCC_HIT_sum" expr=sum(TCC_HIT,16) descr="Number of cache hits. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_MISS_sum" expr=sum(TCC_MISS,16) descr="Number of cache misses. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_MC_RDREQ_sum" expr=sum(TCC_MC_RDREQ,16) descr="Number of 32-byte reads. Sum over TCC instaces."></metric>
|
||||
<metric name="TCC_MC_WRREQ_sum" expr=sum(TCC_MC_WRREQ,16) descr="Number of 32-byte transactions going over the TC_MC_wrreq interface. Sum over TCC instaces."></metric>
|
||||
<metric name="TCC_WRREQ_STALL_max" expr=max(TCC_MC_WRREQ_STALL,16) descr="Number of cycles a write request was stalled. Max over TCC instances."></metric>
|
||||
|
||||
<metric name="FETCH_SIZE" expr=(TCC_MC_RDREQ_sum*32)/1024 descr="The total kilobytes fetched from the video memory. This is measured with all extra fetches and any cache or memory effects taken into account."></metric>
|
||||
<metric name="WRITE_SIZE" expr=(TCC_MC_WRREQ_sum*32)/1024 descr="The total kilobytes written to the video memory. This is measured with all extra fetches and any cache or memory effects taken into account."></metric>
|
||||
<metric name="WRITE_REQ_32B" expr=TCC_MC_WRREQ_sum descr="The total number of 32-byte effective memory writes."></metric>
|
||||
<metric name="VFetchInsts" expr=(SQ_INSTS_VMEM_RD-TA_FLAT_READ_WAVEFRONTS_sum)/SQ_WAVES descr="The average number of vector fetch instructions from the video memory executed per work-item (affected by flow control). Excludes FLAT instructions that fetch from video memory."></metric>
|
||||
<metric name="VWriteInsts" expr=(SQ_INSTS_VMEM_WR-TA_FLAT_WRITE_WAVEFRONTS_sum)/SQ_WAVES descr="The average number of vector write instructions to the video memory executed per work-item (affected by flow control). Excludes FLAT instructions that write to video memory."></metric>
|
||||
<metric name="FlatVMemInsts" expr=(SQ_INSTS_FLAT-SQ_INSTS_FLAT_LDS_ONLY)/SQ_WAVES descr="The average number of FLAT instructions that read from or write to the video memory executed per work item (affected by flow control). Includes FLAT instructions that read from or write to scratch."></metric>
|
||||
<metric name="LDSInsts" expr=(SQ_INSTS_LDS-SQ_INSTS_FLAT_LDS_ONLY)/SQ_WAVES descr="The average number of LDS read or LDS write instructions executed per work item (affected by flow control). Excludes FLAT instructions that read from or write to LDS."></metric>
|
||||
<metric name="FlatLDSInsts" expr=SQ_INSTS_FLAT_LDS_ONLY/SQ_WAVES descr="The average number of FLAT instructions that read or write to LDS executed per work item (affected by flow control)."></metric>
|
||||
<metric name="VALUUtilization" expr=100*SQ_THREAD_CYCLES_VALU/(SQ_ACTIVE_INST_VALU*MAX_WAVE_SIZE) descr="The percentage of active vector ALU threads in a wave. A lower number can mean either more thread divergence in a wave or that the work-group size is not a multiple of 64. Value range: 0% (bad), 100% (ideal - no thread divergence)."></metric>
|
||||
<metric name="VALUBusy" expr=100*SQ_ACTIVE_INST_VALU*4/SIMD_NUM/GRBM_GUI_ACTIVE descr="The percentage of GPUTime vector ALU instructions are processed. Value range: 0% (bad) to 100% (optimal)."></metric>
|
||||
<metric name="SALUBusy" expr=100*SQ_INST_CYCLES_SALU*4/SIMD_NUM/GRBM_GUI_ACTIVE descr="The percentage of GPUTime scalar ALU instructions are processed. Value range: 0% (bad) to 100% (optimal)."></metric>
|
||||
<metric name="FetchSize" expr=FETCH_SIZE descr="The total kilobytes fetched from the video memory. This is measured with all extra fetches and any cache or memory effects taken into account."></metric>
|
||||
<metric name="WriteSize" expr=WRITE_SIZE descr="The total kilobytes written to the video memory. This is measured with all extra fetches and any cache or memory effects taken into account."></metric>
|
||||
<metric name="MemWrites32B" expr=WRITE_REQ_32B descr="The total number of effective 32B write transactions to the memory"></metric>
|
||||
<metric name="L2CacheHit" expr=100*sum(TCC_HIT,16)/(sum(TCC_HIT,16)+sum(TCC_MISS,16)) descr="The percentage of fetch, write, atomic, and other instructions that hit the data in L2 cache. Value range: 0% (no hit) to 100% (optimal)."></metric>
|
||||
<metric name="MemUnitStalled" expr=100*max(TCP_TCP_TA_DATA_STALL_CYCLES,16)/GRBM_GUI_ACTIVE/SE_NUM descr="The percentage of GPUTime the memory unit is stalled. Try reducing the number or size of fetches and writes if possible. Value range: 0% (optimal) to 100% (bad)."></metric>
|
||||
<metric name="WriteUnitStalled" expr=100*TCC_WRREQ_STALL_max/GRBM_GUI_ACTIVE descr="The percentage of GPUTime the Write unit is stalled. Value range: 0% to 100% (bad)."></metric>
|
||||
# LDSBankConflict The percentage of GPUTime LDS is stalled by bank conflicts. Value range: 0% (optimal) to 100% (bad).
|
||||
<metric name="LDSBankConflict" expr=100*SQ_LDS_BANK_CONFLICT/GRBM_GUI_ACTIVE/CU_NUM descr="The percentage of GPUTime LDS is stalled by bank conflicts. Value range: 0% (optimal) to 100% (bad)."></metric>
|
||||
</gfx8_expr>
|
||||
|
||||
<gfx9_expr>
|
||||
<metric name="TA_BUSY_avr" expr=avr(TA_TA_BUSY,16) descr="TA block is busy. Average over TA instances."></metric>
|
||||
<metric name="TA_BUSY_max" expr=max(TA_TA_BUSY,16) descr="TA block is busy. Max over TA instances."></metric>
|
||||
<metric name="TA_BUSY_min" expr=min(TA_TA_BUSY,16) descr="TA block is busy. Min over TA instances."></metric>
|
||||
<metric name="TA_FLAT_READ_WAVEFRONTS_sum" expr=sum(TA_FLAT_READ_WAVEFRONTS,16) descr="Number of flat opcode reads processed by the TA. Sum over TA instances."></metric>
|
||||
<metric name="TA_FLAT_WRITE_WAVEFRONTS_sum" expr=sum(TA_FLAT_WRITE_WAVEFRONTS,16) descr="Number of flat opcode writes processed by the TA. Sum over TA instances."></metric>
|
||||
|
||||
<metric name="TCC_HIT_sum" expr=sum(TCC_HIT,16) descr="Number of cache hits. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_MISS_sum" expr=sum(TCC_MISS,16) descr="Number of cache misses. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA_RDREQ_32B_sum" expr=sum(TCC_EA_RDREQ_32B,16) descr="Number of 32-byte TCC/EA read requests. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA_RDREQ_sum" expr=sum(TCC_EA_RDREQ,16) descr="Number of TCC/EA read requests (either 32-byte or 64-byte). Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA_WRREQ_sum" expr=sum(TCC_EA_WRREQ,16) descr="Number of transactions (either 32-byte or 64-byte) going over the TC_EA_wrreq interface. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA_WRREQ_64B_sum" expr=sum(TCC_EA_WRREQ_64B,16) descr="Number of 64-byte transactions going (64-byte write or CMPSWAP) over the TC_EA_wrreq interface. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_WRREQ_STALL_max" expr=max(TCC_EA_WRREQ_STALL,16) descr="Number of cycles a write request was stalled. Max over TCC instances."></metric>
|
||||
|
||||
<metric name="TCP_TCP_TA_DATA_STALL_CYCLES_sum" expr=sum(TCP_TCP_TA_DATA_STALL_CYCLES,16) decr="Total number of TCP stalls TA data interface."></metric>
|
||||
<metric name="TCP_TCP_TA_DATA_STALL_CYCLES_max" expr=max(TCP_TCP_TA_DATA_STALL_CYCLES,16) decr="Maximum number of TCP stalls TA data interface."></metric>
|
||||
|
||||
<metric name="FETCH_SIZE" expr=(TCC_EA_RDREQ_32B_sum*32+(TCC_EA_RDREQ_sum-TCC_EA_RDREQ_32B_sum)*64)/1024 descr="The total kilobytes fetched from the video memory. This is measured with all extra fetches and any cache or memory effects taken into account."></metric>
|
||||
<metric name="WRITE_SIZE" expr=((TCC_EA_WRREQ_sum-TCC_EA_WRREQ_64B_sum)*32+TCC_EA_WRREQ_64B_sum*64)/1024 descr="The total kilobytes written to the video memory. This is measured with all extra fetches and any cache or memory effects taken into account."></metric>
|
||||
<metric name="WRITE_REQ_32B" expr=TCC_EA_WRREQ_64B_sum*2+(TCC_EA_WRREQ_sum-TCC_EA_WRREQ_64B_sum) descr="The total number of 32-byte effective memory writes."></metric>
|
||||
<metric name="VFetchInsts" expr=(SQ_INSTS_VMEM_RD-TA_FLAT_READ_WAVEFRONTS_sum)/SQ_WAVES descr="The average number of vector fetch instructions from the video memory executed per work-item (affected by flow control). Excludes FLAT instructions that fetch from video memory."></metric>
|
||||
<metric name="VWriteInsts" expr=(SQ_INSTS_VMEM_WR-TA_FLAT_WRITE_WAVEFRONTS_sum)/SQ_WAVES descr="The average number of vector write instructions to the video memory executed per work-item (affected by flow control). Excludes FLAT instructions that write to video memory."></metric>
|
||||
<metric name="FlatVMemInsts" expr=(SQ_INSTS_FLAT-SQ_INSTS_FLAT_LDS_ONLY)/SQ_WAVES descr="The average number of FLAT instructions that read from or write to the video memory executed per work item (affected by flow control). Includes FLAT instructions that read from or write to scratch."></metric>
|
||||
<metric name="LDSInsts" expr=(SQ_INSTS_LDS-SQ_INSTS_FLAT_LDS_ONLY)/SQ_WAVES descr="The average number of LDS read or LDS write instructions executed per work item (affected by flow control). Excludes FLAT instructions that read from or write to LDS."></metric>
|
||||
<metric name="FlatLDSInsts" expr=SQ_INSTS_FLAT_LDS_ONLY/SQ_WAVES descr="The average number of FLAT instructions that read or write to LDS executed per work item (affected by flow control)."></metric>
|
||||
<metric name="VALUUtilization" expr=100*SQ_THREAD_CYCLES_VALU/(SQ_ACTIVE_INST_VALU*MAX_WAVE_SIZE) descr="The percentage of active vector ALU threads in a wave. A lower number can mean either more thread divergence in a wave or that the work-group size is not a multiple of 64. Value range: 0% (bad), 100% (ideal - no thread divergence)."></metric>
|
||||
<metric name="VALUBusy" expr=100*SQ_ACTIVE_INST_VALU*4/SIMD_NUM/GRBM_GUI_ACTIVE descr="The percentage of GPUTime vector ALU instructions are processed. Value range: 0% (bad) to 100% (optimal)."></metric>
|
||||
<metric name="SALUBusy" expr=100*SQ_INST_CYCLES_SALU*4/SIMD_NUM/GRBM_GUI_ACTIVE descr="The percentage of GPUTime scalar ALU instructions are processed. Value range: 0% (bad) to 100% (optimal)."></metric>
|
||||
<metric name="FetchSize" expr=FETCH_SIZE descr="The total kilobytes fetched from the video memory. This is measured with all extra fetches and any cache or memory effects taken into account."></metric>
|
||||
<metric name="WriteSize" expr=WRITE_SIZE descr="The total kilobytes written to the video memory. This is measured with all extra fetches and any cache or memory effects taken into account."></metric>
|
||||
<metric name="MemWrites32B" expr=WRITE_REQ_32B descr="The total number of effective 32B write transactions to the memory"></metric>
|
||||
<metric name="L2CacheHit" expr=100*sum(TCC_HIT,16)/(sum(TCC_HIT,16)+sum(TCC_MISS,16)) descr="The percentage of fetch, write, atomic, and other instructions that hit the data in L2 cache. Value range: 0% (no hit) to 100% (optimal)."></metric>
|
||||
<metric name="MemUnitStalled" expr=100*TCP_TCP_TA_DATA_STALL_CYCLES_max/GRBM_GUI_ACTIVE/SE_NUM descr="The percentage of GPUTime the memory unit is stalled. Try reducing the number or size of fetches and writes if possible. Value range: 0% (optimal) to 100% (bad)."></metric>
|
||||
<metric name="WriteUnitStalled" expr=100*TCC_WRREQ_STALL_max/GRBM_GUI_ACTIVE descr="The percentage of GPUTime the Write unit is stalled. Value range: 0% to 100% (bad)."></metric>
|
||||
# LDSBankConflict The percentage of GPUTime LDS is stalled by bank conflicts. Value range: 0% (optimal) to 100% (bad).
|
||||
<metric name="LDSBankConflict" expr=100*SQ_LDS_BANK_CONFLICT/GRBM_GUI_ACTIVE/CU_NUM descr="The percentage of GPUTime LDS is stalled by bank conflicts. Value range: 0% (optimal) to 100% (bad)."></metric>
|
||||
</gfx9_expr>
|
||||
|
||||
<gfx906_expr base="gfx9_expr">
|
||||
# EA1
|
||||
<metric name="TCC_EA1_RDREQ_32B_sum" expr=sum(TCC_EA1_RDREQ_32B,16) descr="Number of 32-byte TCC/EA read requests. Sum over TCC EA1s."></metric>
|
||||
<metric name="TCC_EA1_RDREQ_sum" expr=sum(TCC_EA1_RDREQ,16) descr="Number of TCC/EA read requests (either 32-byte or 64-byte). Sum over TCC EA1s."></metric>
|
||||
<metric name="TCC_EA1_WRREQ_sum" expr=sum(TCC_EA1_WRREQ,16) descr="Number of transactions (either 32-byte or 64-byte) going over the TC_EA_wrreq interface. Sum over TCC EA1s."></metric>
|
||||
<metric name="TCC_EA1_WRREQ_64B_sum" expr=sum(TCC_EA1_WRREQ_64B,16) descr="Number of 64-byte transactions going (64-byte write or CMPSWAP) over the TC_EA_wrreq interface. Sum over TCC EA1s."></metric>
|
||||
<metric name="TCC_WRREQ1_STALL_max" expr=max(TCC_EA1_WRREQ_STALL,16) descr="Number of cycles a write request was stalled. Max over TCC instances."></metric>
|
||||
|
||||
<metric name="RDATA1_SIZE" expr=(TCC_EA1_RDREQ_32B_sum*32+(TCC_EA1_RDREQ_sum-TCC_EA1_RDREQ_32B_sum)*64) descr="The total kilobytes fetched from the video memory. This is measured on EA1s."></metric>
|
||||
<metric name="WDATA1_SIZE" expr=((TCC_EA1_WRREQ_sum-TCC_EA1_WRREQ_64B_sum)*32+TCC_EA1_WRREQ_64B_sum*64) descr="The total kilobytes written to the video memory. This is measured on EA1s."></metric>
|
||||
|
||||
# both EA0 and EA1 should be included
|
||||
<metric name="FETCH_SIZE" expr=(TCC_EA_RDREQ_32B_sum*32+(TCC_EA_RDREQ_sum-TCC_EA_RDREQ_32B_sum)*64+RDATA1_SIZE)/1024 descr="The total kilobytes fetched from the video memory. This is measured with all extra fetches and any cache or memory effects taken into account."></metric>
|
||||
<metric name="WRITE_SIZE" expr=((TCC_EA_WRREQ_sum-TCC_EA_WRREQ_64B_sum)*32+TCC_EA_WRREQ_64B_sum*64+WDATA1_SIZE)/1024 descr="The total kilobytes written to the video memory. This is measured with all extra fetches and any cache or memory effects taken into account."></metric>
|
||||
<metric name="WRITE_REQ_32B" expr=(TCC_EA_WRREQ_sum-TCC_EA_WRREQ_64B_sum)+(TCC_EA1_WRREQ_sum-TCC_EA1_WRREQ_64B_sum)+(TCC_EA_WRREQ_64B_sum+TCC_EA1_WRREQ_64B_sum)*2 descr="The total number of 32-byte effective memory writes."></metric>
|
||||
</gfx906_expr>
|
||||
|
||||
<gfx908_expr base="gfx9_expr">
|
||||
<metric name="TCC_HIT_sum" expr=sum(TCC_HIT,32) descr="Number of cache hits. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_MISS_sum" expr=sum(TCC_MISS,32) descr="Number of cache misses. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA_RDREQ_32B_sum" expr=sum(TCC_EA_RDREQ_32B,32) descr="Number of 32-byte TCC/EA read requests. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA_RDREQ_sum" expr=sum(TCC_EA_RDREQ,32) descr="Number of TCC/EA read requests (either 32-byte or 64-byte). Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA_WRREQ_sum" expr=sum(TCC_EA_WRREQ,32) descr="Number of transactions (either 32-byte or 64-byte) going over the TC_EA_wrreq interface. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA_WRREQ_64B_sum" expr=sum(TCC_EA_WRREQ_64B,32) descr="Number of 64-byte transactions going (64-byte write or CMPSWAP) over the TC_EA_wrreq interface. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_WRREQ_STALL_max" expr=max(TCC_EA_WRREQ_STALL,32) descr="Number of cycles a write request was stalled. Max over TCC instances."></metric>
|
||||
|
||||
<metric name="CU_UTILIZATION" expr=GRBM_GUI_ACTIVE/GRBM_COUNT descr="The total number of active cycles divided by total number of elapsed cycles"></metric>
|
||||
</gfx908_expr>
|
||||
|
||||
<gfx90a_expr base="gfx9_expr">
|
||||
<metric name="TA_BUSY_avr" expr=avr(TA_TA_BUSY,16) descr="TA block is busy. Average over TA instances."></metric>
|
||||
<metric name="TA_BUSY_max" expr=max(TA_TA_BUSY,16) descr="TA block is busy. Max over TA instances."></metric>
|
||||
<metric name="TA_BUSY_min" expr=min(TA_TA_BUSY,16) descr="TA block is busy. Min over TA instances."></metric>
|
||||
<metric name="TA_TA_BUSY_sum" expr=sum(TA_TA_BUSY,16) descr="TA block is busy. Perf_Windowing not supported for this counter. Sum over TA instances."></metric>
|
||||
<metric name="TA_TOTAL_WAVEFRONTS_sum" expr=sum(TA_TOTAL_WAVEFRONTS,16) descr="Total number of wavefronts processed by TA. Sum over TA instances."></metric>
|
||||
<metric name="TA_ADDR_STALLED_BY_TC_CYCLES_sum" expr=sum(TA_ADDR_STALLED_BY_TC_CYCLES,16) descr="Number of cycles addr path stalled by TC. Perf_Windowing not supported for this counter. Sum over TA instances."></metric>
|
||||
<metric name="TA_ADDR_STALLED_BY_TD_CYCLES_sum" expr=sum(TA_ADDR_STALLED_BY_TD_CYCLES,16) descr="Number of cycles addr path stalled by TD. Perf_Windowing not supported for this counter. Sum over TA instances."></metric>
|
||||
<metric name="TA_DATA_STALLED_BY_TC_CYCLES_sum" expr=sum(TA_DATA_STALLED_BY_TC_CYCLES,16) descr="Number of cycles data path stalled by TC. Perf_Windowing not supported for this counter. Sum over TA instances."></metric>
|
||||
<metric name="TA_FLAT_WAVEFRONTS_sum" expr=sum(TA_FLAT_WAVEFRONTS,16) descr="Number of flat opcode wavfronts processed by the TA. Sum over TA instances."></metric>
|
||||
<metric name="TA_FLAT_READ_WAVEFRONTS_sum" expr=sum(TA_FLAT_READ_WAVEFRONTS,16) descr="Number of flat opcode reads processed by the TA. Sum over TA instances."></metric>
|
||||
<metric name="TA_FLAT_WRITE_WAVEFRONTS_sum" expr=sum(TA_FLAT_WRITE_WAVEFRONTS,16) descr="Number of flat opcode writes processed by the TA. Sum over TA instances."></metric>
|
||||
<metric name="TA_FLAT_ATOMIC_WAVEFRONTS_sum" expr=sum(TA_FLAT_ATOMIC_WAVEFRONTS,16) descr="Number of flat opcode atomics processed by the TA. Sum over TA instances."></metric>
|
||||
<metric name="TA_BUFFER_WAVEFRONTS_sum" expr=sum(TA_BUFFER_WAVEFRONTS,16) descr="Number of buffer wavefronts processed by TA. Sum over TA instances."></metric>
|
||||
<metric name="TA_BUFFER_READ_WAVEFRONTS_sum" expr=sum(TA_BUFFER_READ_WAVEFRONTS,16) descr="Number of buffer read wavefronts processed by TA. Sum over TA instances."></metric>
|
||||
<metric name="TA_BUFFER_WRITE_WAVEFRONTS_sum" expr=sum(TA_BUFFER_WRITE_WAVEFRONTS,16) descr="Number of buffer write wavefronts processed by TA. Sum over TA instances."></metric>
|
||||
<metric name="TA_BUFFER_ATOMIC_WAVEFRONTS_sum" expr=sum(TA_BUFFER_ATOMIC_WAVEFRONTS,16) descr="Number of buffer atomic wavefronts processed by TA. Sum over TA instances."></metric>
|
||||
<metric name="TA_BUFFER_TOTAL_CYCLES_sum" expr=sum(TA_BUFFER_TOTAL_CYCLES,16) descr="Number of buffer cycles issued to TC. Sum over TA instances."></metric>
|
||||
<metric name="TA_BUFFER_COALESCED_READ_CYCLES_sum" expr=sum(TA_BUFFER_COALESCED_READ_CYCLES,16) descr="Number of buffer coalesced read cycles issued to TC. Sum over TA instances."></metric>
|
||||
<metric name="TA_BUFFER_COALESCED_WRITE_CYCLES_sum" expr=sum(TA_BUFFER_COALESCED_WRITE_CYCLES,16) descr="Number of buffer coalesced write cycles issued to TC. Sum over TA instances."></metric>
|
||||
<metric name="TD_TD_BUSY_sum" expr=sum(TD_TD_BUSY,16) descr="TD is processing or waiting for data. Perf_Windowing not supported for this counter. Sum over TD instances."></metric>
|
||||
<metric name="TD_TC_STALL_sum" expr=sum(TD_TC_STALL,16) descr="TD is stalled waiting for TC data. Sum over TD instances."></metric>
|
||||
<metric name="TD_LOAD_WAVEFRONT_sum" expr=sum(TD_LOAD_WAVEFRONT,16) descr="Count the wavefronts with opcode = load, include atomics and store. Sum over TD instances."></metric>
|
||||
<metric name="TD_ATOMIC_WAVEFRONT_sum" expr=sum(TD_ATOMIC_WAVEFRONT,16) descr="Count the wavefronts with opcode = atomic. Sum over TD instances."></metric>
|
||||
<metric name="TD_STORE_WAVEFRONT_sum" expr=sum(TD_STORE_WAVEFRONT,16) descr="Count the wavefronts with opcode = store. Sum over TD instances."></metric>
|
||||
<metric name="TD_COALESCABLE_WAVEFRONT_sum" expr=sum(TD_COALESCABLE_WAVEFRONT,16) descr="Count wavefronts that TA finds coalescable. Sum over TD instances."></metric>
|
||||
<metric name="TD_SPI_STALL_sum" expr=sum(TD_SPI_STALL,16) descr="TD is stalled SPI vinit, sum of TCP instances"></metric>
|
||||
<metric name="TCP_GATE_EN1_sum" expr=sum(TCP_GATE_EN1,16) descr="TCP interface clocks are turned on. Not Windowed. Sum over TCP instances."></metric>
|
||||
<metric name="TCP_GATE_EN2_sum" expr=sum(TCP_GATE_EN2,16) descr="TCP core clocks are turned on. Not Windowed. Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TD_TCP_STALL_CYCLES_sum" expr=sum(TCP_TD_TCP_STALL_CYCLES,16) descr="TD stalls TCP. Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TCR_TCP_STALL_CYCLES_sum" expr=sum(TCP_TCR_TCP_STALL_CYCLES,16) descr="TCR stalls TCP_TCR_req interface. Sum over TCP instances."></metric>
|
||||
<metric name="TCP_READ_TAGCONFLICT_STALL_CYCLES_sum" expr=sum(TCP_READ_TAGCONFLICT_STALL_CYCLES,16) descr="Tagram conflict stall on a read. Sum over TCP instances."></metric>
|
||||
<metric name="TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum" expr=sum(TCP_WRITE_TAGCONFLICT_STALL_CYCLES,16) descr="Tagram conflict stall on a write. Sum over TCP instances."></metric>
|
||||
<metric name="TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum" expr=sum(TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES,16) descr="Tagram conflict stall on an atomic. Sum over TCP instances."></metric>
|
||||
<metric name="TCP_VOLATILE_sum" expr=sum(TCP_VOLATILE,16) descr="Total number of L1 volatile pixels/buffers from TA. Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TOTAL_ACCESSES_sum" expr=sum(TCP_TOTAL_ACCESSES,16) descr="Total number of pixels/buffers from TA. Equals TCP_PERF_SEL_TOTAL_READ+TCP_PERF_SEL_TOTAL_NONREAD. Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TOTAL_READ_sum" expr=sum(TCP_TOTAL_READ,16) descr="Total number of read pixels/buffers from TA. Equals TCP_PERF_SEL_TOTAL_HIT_LRU_READ + TCP_PERF_SEL_TOTAL_MISS_LRU_READ + TCP_PERF_SEL_TOTAL_MISS_EVICT_READ. Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TOTAL_WRITE_sum" expr=sum(TCP_TOTAL_WRITE,16) descr="Total number of local write pixels/buffers from TA. Equals TCP_PERF_SEL_TOTAL_MISS_LRU_WRITE+ TCP_PERF_SEL_TOTAL_MISS_EVICT_WRITE. Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TOTAL_ATOMIC_WITH_RET_sum" expr=sum(TCP_TOTAL_ATOMIC_WITH_RET,16) descr="Total number of atomic with return pixels/buffers from TA. Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TOTAL_ATOMIC_WITHOUT_RET_sum" expr=sum(TCP_TOTAL_ATOMIC_WITHOUT_RET,16) descr="Total number of atomic without return pixels/buffers from TA Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TOTAL_WRITEBACK_INVALIDATES_sum" expr=sum(TCP_TOTAL_WRITEBACK_INVALIDATES,16) descr="Total number of cache invalidates. Equals TCP_PERF_SEL_TOTAL_WBINVL1+ TCP_PERF_SEL_TOTAL_WBINVL1_VOL+ TCP_PERF_SEL_CP_TCP_INVALIDATE+ TCP_PERF_SEL_SQ_TCP_INVALIDATE_VOL. Not Windowed. Sum over TCP instances."></metric>
|
||||
<metric name="TCP_UTCL1_REQUEST_sum" expr=sum(TCP_UTCL1_REQUEST,16) descr="Total CLIENT_UTCL1 NORMAL requests Sum over TCP instances."></metric>
|
||||
<metric name="TCP_UTCL1_TRANSLATION_MISS_sum" expr=sum(TCP_UTCL1_TRANSLATION_MISS,16) descr="Total utcl1 translation misses Sum over TCP instances."></metric>
|
||||
<metric name="TCP_UTCL1_TRANSLATION_HIT_sum" expr=sum(TCP_UTCL1_TRANSLATION_HIT,16) descr="Total utcl1 translation hits Sum over TCP instances."></metric>
|
||||
<metric name="TCP_UTCL1_PERMISSION_MISS_sum" expr=sum(TCP_UTCL1_PERMISSION_MISS,16) descr="Total utcl1 permission misses Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TOTAL_CACHE_ACCESSES_sum" expr=sum(TCP_TOTAL_CACHE_ACCESSES,16) descr="Count of total cache line (tag) accesses (includes hits and misses). Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TCP_LATENCY_sum" expr=sum(TCP_TCP_LATENCY,16) descr="Total TCP wave latency (from first clock of wave entering to first clock of wave leaving), divide by TA_TCP_STATE_READ to avg wave latency Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TA_TCP_STATE_READ_sum" expr=sum(TCP_TA_TCP_STATE_READ,16) descr="Number of state reads Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TCC_READ_REQ_LATENCY_sum" expr=sum(TCP_TCC_READ_REQ_LATENCY,16) descr="Total TCP->TCC request latency for reads and atomics with return. Not Windowed. Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TCC_WRITE_REQ_LATENCY_sum" expr=sum(TCP_TCC_WRITE_REQ_LATENCY,16) descr="Total TCP->TCC request latency for writes and atomics without return. Not Windowed. Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TCC_READ_REQ_sum" expr=sum(TCP_TCC_READ_REQ,16) descr="Total read requests from TCP to all TCCs Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TCC_WRITE_REQ_sum" expr=sum(TCP_TCC_WRITE_REQ,16) descr="Total write requests from TCP to all TCCs Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TCC_ATOMIC_WITH_RET_REQ_sum" expr=sum(TCP_TCC_ATOMIC_WITH_RET_REQ,16) descr="Total atomic with return requests from TCP to all TCCs Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum" expr=sum(TCP_TCC_ATOMIC_WITHOUT_RET_REQ,16) descr="Total atomic without return requests from TCP to all TCCs Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TCC_NC_READ_REQ_sum" expr=sum(TCP_TCC_NC_READ_REQ,16) descr="Total read requests with NC mtype from this TCP to all TCCs Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TCC_NC_WRITE_REQ_sum" expr=sum(TCP_TCC_NC_WRITE_REQ,16) descr="Total write requests with NC mtype from this TCP to all TCCs Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TCC_NC_ATOMIC_REQ_sum" expr=sum(TCP_TCC_NC_ATOMIC_REQ,16) descr="Total atomic requests with NC mtype from this TCP to all TCCs Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TCC_UC_READ_REQ_sum" expr=sum(TCP_TCC_UC_READ_REQ,16) descr="Total read requests with UC mtype from this TCP to all TCCs Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TCC_UC_WRITE_REQ_sum" expr=sum(TCP_TCC_UC_WRITE_REQ,16) descr="Total write requests with UC mtype from this TCP to all TCCs Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TCC_UC_ATOMIC_REQ_sum" expr=sum(TCP_TCC_UC_ATOMIC_REQ,16) descr="Total atomic requests with UC mtype from this TCP to all TCCs Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TCC_CC_READ_REQ_sum" expr=sum(TCP_TCC_CC_READ_REQ,16) descr="Total write requests with CC mtype from this TCP to all TCCs Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TCC_CC_WRITE_REQ_sum" expr=sum(TCP_TCC_CC_WRITE_REQ,16) descr="Total write requests with CC mtype from this TCP to all TCCs Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TCC_CC_ATOMIC_REQ_sum" expr=sum(TCP_TCC_CC_ATOMIC_REQ,16) descr="Total atomic requests with CC mtype from this TCP to all TCCs Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TCC_RW_READ_REQ_sum" expr=sum(TCP_TCC_RW_READ_REQ,16) descr="Total write requests with RW mtype from this TCP to all TCCs. Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TCC_RW_WRITE_REQ_sum" expr=sum(TCP_TCC_RW_WRITE_REQ,16) descr="Total write requests with RW mtype from this TCP to all TCCs. Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TCC_RW_ATOMIC_REQ_sum" expr=sum(TCP_TCC_RW_ATOMIC_REQ,16) descr="Total atomic requests with RW mtype from this TCP to all TCCs. Sum over TCP instances."></metric>
|
||||
<metric name="TCP_PENDING_STALL_CYCLES_sum" expr=sum(TCP_PENDING_STALL_CYCLES,16) descr="Stall due to data pending from L2. Sum over TCP instances."></metric>
|
||||
<metric name="TCA_CYCLE_sum" expr=sum(TCA_CYCLE,16) descr="Number of cycles. Sum over all TCA instances "></metric>
|
||||
<metric name="TCA_BUSY_sum" expr=sum(TCA_BUSY,16) descr="Number of cycles we have a request pending. Sum over all TCA instances."></metric>
|
||||
<metric name="TCC_BUSY_avr" expr=avr(TCC_BUSY,32) descr="TCC_BUSY avr over all memory channels."></metric>
|
||||
<metric name="TCC_WRREQ_STALL_max" expr=max(TCC_EA_WRREQ_STALL,32) descr="Number of cycles a write request was stalled. Max over TCC instances."></metric>
|
||||
<metric name="TCC_CYCLE_sum" expr=sum(TCC_CYCLE,32) descr="Number of cycles. Not windowable. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_BUSY_sum" expr=sum(TCC_BUSY,32) descr="Number of cycles we have a request pending. Not windowable. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_REQ_sum" expr=sum(TCC_REQ,32) descr="Number of requests of all types. This is measured at the tag block. This may be more than the number of requests arriving at the TCC, but it is a good indication of the total amount of work that needs to be performed. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_STREAMING_REQ_sum" expr=sum(TCC_STREAMING_REQ,32) descr="Number of streaming requests. This is measured at the tag block. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_NC_REQ_sum" expr=sum(TCC_NC_REQ,32) descr="The number of noncoherently cached requests. This is measured at the tag block. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_UC_REQ_sum" expr=sum(TCC_UC_REQ,32) descr="The number of uncached requests. This is measured at the tag block. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_CC_REQ_sum" expr=sum(TCC_CC_REQ,32) descr="The number of coherently cached requests. This is measured at the tag block. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_RW_REQ_sum" expr=sum(TCC_RW_REQ,32) descr="The number of RW requests. This is measured at the tag block. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_PROBE_sum" expr=sum(TCC_PROBE,32) descr="Number of probe requests. Not windowable. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_PROBE_ALL_sum" expr=sum(TCC_PROBE_ALL,32) descr="Number of external probe requests with with EA_TCC_preq_all== 1. Not windowable. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_READ_sum" expr=sum(TCC_READ,32) descr="Number of read requests. Compressed reads are included in this, but metadata reads are not included. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_WRITE_sum" expr=sum(TCC_WRITE,32) descr="Number of write requests. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_ATOMIC_sum" expr=sum(TCC_ATOMIC,32) descr="Number of atomic requests of all types. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_HIT_sum" expr=sum(TCC_HIT,32) descr="Number of cache hits. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_MISS_sum" expr=sum(TCC_MISS,32) descr="Number of cache misses. UC reads count as misses. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_WRITEBACK_sum" expr=sum(TCC_WRITEBACK,32) descr="Number of lines written back to main memory. This includes writebacks of dirty lines and uncached write/atomic requests. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA_WRREQ_sum" expr=sum(TCC_EA_WRREQ,32) descr="Number of transactions (either 32-byte or 64-byte) going over the TC_EA_wrreq interface. Atomics may travel over the same interface and are generally classified as write requests. This does not include probe commands. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA_WRREQ_64B_sum" expr=sum(TCC_EA_WRREQ_64B,32) descr="Number of 64-byte transactions going (64-byte write or CMPSWAP) over the TC_EA_wrreq interface. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA_WR_UNCACHED_32B_sum" expr=sum(TCC_EA_WR_UNCACHED_32B,32) descr="Number of 32-byte write/atomic going over the TC_EA_wrreq interface due to uncached traffic. Note that CC mtypes can produce uncached requests, and those are included in this. A 64-byte request will be counted as 2. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA_WRREQ_STALL_sum" expr=sum(TCC_EA_WRREQ_STALL,32) descr="Number of cycles a write request was stalled. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA_WRREQ_IO_CREDIT_STALL_sum" expr=sum(TCC_EA_WRREQ_IO_CREDIT_STALL,32) descr="Number of cycles a EA write request was stalled because the interface was out of IO credits. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA_WRREQ_GMI_CREDIT_STALL_sum" expr=sum(TCC_EA_WRREQ_GMI_CREDIT_STALL,32) descr="Number of cycles a EA write request was stalled because the interface was out of GMI credits. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum" expr=sum(TCC_EA_WRREQ_DRAM_CREDIT_STALL,32) descr="Number of cycles a EA write request was stalled because the interface was out of DRAM credits. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_TOO_MANY_EA_WRREQS_STALL_sum" expr=sum(TCC_TOO_MANY_EA_WRREQS_STALL,32) descr="Number of cycles the TCC could not send a EA write request because it already reached its maximum number of pending EA write requests. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA_WRREQ_LEVEL_sum" expr=sum(TCC_EA_WRREQ_LEVEL,32) descr="The sum of the number of EA write requests in flight. This is primarily meant for measure average EA write latency. Average write latency = TCC_PERF_SEL_EA_WRREQ_LEVEL/TCC_PERF_SEL_EA_WRREQ. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA_RDREQ_LEVEL_sum" expr=sum(TCC_EA_RDREQ_LEVEL,32) descr="The sum of the number of TCC/EA read requests in flight. This is primarily meant for measure average EA read latency. Average read latency = TCC_PERF_SEL_EA_RDREQ_LEVEL/TCC_PERF_SEL_EA_RDREQ. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA_ATOMIC_sum" expr=sum(TCC_EA_ATOMIC,32) descr="Number of transactions going over the TC_EA_wrreq interface that are actually atomic requests. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA_ATOMIC_LEVEL_sum" expr=sum(TCC_EA_ATOMIC_LEVEL,32) descr="The sum of the number of EA atomics in flight. This is primarily meant for measure average EA atomic latency. Average atomic latency = TCC_PERF_SEL_EA_WRREQ_ATOMIC_LEVEL/TCC_PERF_SEL_EA_WRREQ_ATOMIC. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA_RDREQ_sum" expr=sum(TCC_EA_RDREQ,32) descr="Number of TCC/EA read requests (either 32-byte or 64-byte) Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA_RDREQ_32B_sum" expr=sum(TCC_EA_RDREQ_32B,32) descr="Number of 32-byte TCC/EA read requests Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA_RD_UNCACHED_32B_sum" expr=sum(TCC_EA_RD_UNCACHED_32B,32) descr="Number of 32-byte TCC/EA read due to uncached traffic. A 64-byte request will be counted as 2 Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA_RDREQ_IO_CREDIT_STALL_sum" expr=sum(TCC_EA_RDREQ_IO_CREDIT_STALL,32) descr="Number of cycles there was a stall because the read request interface was out of IO credits. Stalls occur regardless of whether a read needed to be performed or not. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA_RDREQ_GMI_CREDIT_STALL_sum" expr=sum(TCC_EA_RDREQ_GMI_CREDIT_STALL,32) descr="Number of cycles there was a stall because the read request interface was out of GMI credits. Stalls occur regardless of whether a read needed to be performed or not. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum" expr=sum(TCC_EA_RDREQ_DRAM_CREDIT_STALL,32) descr="Number of cycles there was a stall because the read request interface was out of DRAM credits. Stalls occur regardless of whether a read needed to be performed or not. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_TAG_STALL_sum" expr=sum(TCC_TAG_STALL,32) descr="."></metric>
|
||||
<metric name="TCC_NORMAL_WRITEBACK_sum" expr=sum(TCC_NORMAL_WRITEBACK,32) descr="Number of writebacks due to requests that are not writeback requests. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_ALL_TC_OP_WB_WRITEBACK_sum" expr=sum(TCC_ALL_TC_OP_WB_WRITEBACK,32) descr="Number of writebacks due to all TC_OP writeback requests. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_NORMAL_EVICT_sum" expr=sum(TCC_NORMAL_EVICT,32) descr="Number of evictions due to requests that are not invalidate or probe requests. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_ALL_TC_OP_INV_EVICT_sum" expr=sum(TCC_ALL_TC_OP_INV_EVICT,32) descr="Number of evictions due to all TC_OP invalidate requests. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA_RDREQ_DRAM_sum" expr=sum(TCC_EA_RDREQ_DRAM,32) descr="Number of TCC/EA read requests (either 32-byte or 64-byte) destined for DRAM (MC). Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA_WRREQ_DRAM_sum" expr=sum(TCC_EA_WRREQ_DRAM,32) descr="Number of TCC/EA write requests (either 32-byte of 64-byte) destined for DRAM (MC). Sum over TCC instances."></metric>
|
||||
|
||||
<metric name="FETCH_SIZE" expr=(TCC_EA_RDREQ_32B_sum*32+(TCC_EA_RDREQ_sum-TCC_EA_RDREQ_32B_sum)*64)/1024 descr="The total kilobytes fetched from the video memory. This is measured with all extra fetches and any cache or memory effects taken into account."></metric>
|
||||
<metric name="WRITE_SIZE" expr=((TCC_EA_WRREQ_sum-TCC_EA_WRREQ_64B_sum)*32+TCC_EA_WRREQ_64B_sum*64)/1024 descr="The total kilobytes written to the video memory. This is measured with all extra fetches and any cache or memory effects taken into account."></metric>
|
||||
<metric name="WRITE_REQ_32B" expr=TCC_EA_WRREQ_64B_sum*2+(TCC_EA_WRREQ_sum-TCC_EA_WRREQ_64B_sum) descr="The total number of 32-byte effective memory writes."></metric>
|
||||
<metric name="CU_OCCUPANCY" expr=(SQ_CYCLES/(SQ_WAVE_CYCLES*4))/MAX_WAVE_SIZE descr="The ratio of active waves on a CU to the maximum number of active waves supported by the CU"></metric>
|
||||
<metric name="CU_UTILIZATION" expr=GRBM_GUI_ACTIVE/GRBM_COUNT descr="The total number of active cycles divided by total number of elapsed cycles"></metric>
|
||||
<metric name="TOTAL_16_OPS" expr=(SQ_INSTS_VALU_FMA_F16*2+SQ_INSTS_VALU_ADD_F16+SQ_INSTS_VALU_MUL_F16+SQ_INSTS_VALU_TRANS_F16)*64+((SQ_INSTS_VALU_MFMA_MOPS_F16+SQ_INSTS_VALU_MFMA_MOPS_BF16)*512) descr="The number of 16 bits OPS executed"></metric>
|
||||
<metric name="TOTAL_32_OPS" expr=(SQ_INSTS_VALU_FMA_F32*2+SQ_INSTS_VALU_INT32+SQ_INSTS_VALU_ADD_F32+SQ_INSTS_VALU_MUL_F32+SQ_INSTS_VALU_TRANS_F32)*64+(SQ_INSTS_VALU_MFMA_MOPS_F32*512) descr="The number of 32 bits OPS executed"></metric>
|
||||
<metric name="TOTAL_64_OPS" expr=(SQ_INSTS_VALU_FMA_F64*2+SQ_INSTS_VALU_INT64+SQ_INSTS_VALU_ADD_F64+SQ_INSTS_VALU_MUL_F64)*64+(SQ_INSTS_VALU_MFMA_MOPS_F64*512) descr="The number of 64 bits OPS executed"></metric>
|
||||
|
||||
<metric name="AggSysCycles" expr=GRBM_GUI_ACTIVE*CU_NUM descr="Unit: cycles"></metric>
|
||||
## IP Block Utilization Metrics
|
||||
<metric name="GpuUtil" expr=100*GRBM_GUI_ACTIVE/GRBM_COUNT descr="Unit: percent"></metric>
|
||||
<metric name="CpUtil" expr=100*GRBM_CP_BUSY/GRBM_GUI_ACTIVE descr="Unit: percent"></metric>
|
||||
<metric name="SpiUtil" expr=100*GRBM_SPI_BUSY/GRBM_GUI_ACTIVE descr="Unit: percent"></metric>
|
||||
<metric name="TaUtil" expr=100*GRBM_TA_BUSY/GRBM_GUI_ACTIVE descr="Unit: percent"></metric>
|
||||
<metric name="TcUtil" expr=100*GRBM_TC_BUSY/GRBM_GUI_ACTIVE descr="Unit: percent"></metric>
|
||||
<metric name="EaUtil" expr=100*GRBM_EA_BUSY/GRBM_GUI_ACTIVE descr="Unit: percent"></metric>
|
||||
## Instruction Fetch Metrics
|
||||
<metric name="InstrFetchLatency" expr=SQ_ACCUM_PREV_HIRES/SQ_IFETCH descr="Unit: cycles"></metric>
|
||||
## Wavefront Metrics
|
||||
<metric name="WaveOccupancy" expr=SQ_ACCUM_PREV_HIRES/GRBM_GUI_ACTIVE descr="Unit: wavefronts"></metric>
|
||||
<metric name="WaveDuration" expr=4*SQ_WAVE_CYCLES/SQ_WAVES descr="Unit: cycles"></metric>
|
||||
<metric name="WaveDepWait" expr=100*SQ_WAIT_ANY/SQ_WAVE_CYCLES descr="Unit: percent"></metric>
|
||||
<metric name="WaveIssueWait" expr=100*SQ_WAIT_INST_ANY/SQ_WAVE_CYCLES descr="Unit: percent"></metric>
|
||||
<metric name="WaveExec" expr=100*SQ_ACTIVE_INST_ANY/SQ_WAVE_CYCLES descr="Unit: percent"></metric>
|
||||
## Compute Unit Metrics
|
||||
<metric name="ValuIops" expr=(SQ_INSTS_VALU_INT32+SQ_INSTS_VALU_INT64)*64 descr="Unit: IOP"></metric>
|
||||
<metric name="MfmaFlops" expr=(SQ_INSTS_VALU_MFMA_MOPS_F16+SQ_INSTS_VALU_MFMA_MOPS_BF16+SQ_INSTS_VALU_MFMA_MOPS_F32+SQ_INSTS_VALU_MFMA_MOPS_F64)*512 descr="Unit: FLOP"></metric>
|
||||
<metric name="MfmaFlopsF16" expr=SQ_INSTS_VALU_MFMA_MOPS_F16*512 descr="Unit: FLOP"></metric>
|
||||
<metric name="MfmaFlopsBF16" expr=SQ_INSTS_VALU_MFMA_MOPS_BF16*512 descr="Unit: FLOP"></metric>
|
||||
<metric name="MfmaFlopsF32" expr=SQ_INSTS_VALU_MFMA_MOPS_F32*512 descr="Unit: FLOP"></metric>
|
||||
<metric name="MfmaFlopsF64" expr=SQ_INSTS_VALU_MFMA_MOPS_F64*512 descr="Unit: IOP"></metric>
|
||||
<metric name="ScaPipeIssueUtil" expr=100*SQ_ACTIVE_INST_SCA/(GRBM_GUI_ACTIVE*CU_NUM) descr="Unit: percent"></metric>
|
||||
<metric name="ValuPipeIssueUtil" expr=100*SQ_ACTIVE_INST_VALU/(GRBM_GUI_ACTIVE*CU_NUM) descr="Unit: percent"></metric>
|
||||
<metric name="VmemPipeIssueUtil" expr=100*4*(SQ_ACTIVE_INST_VMEM+SQ_ACTIVE_INST_FLAT)/(GRBM_GUI_ACTIVE*CU_NUM) descr="Unit: percent"></metric>
|
||||
<metric name="MfmaUtil" expr=100*SQ_VALU_MFMA_BUSY_CYCLES/(GRBM_GUI_ACTIVE*CU_NUM*4) descr="Unit: percent"></metric>
|
||||
<metric name="AvgNumActiveThreads" expr=SQ_THREAD_CYCLES_VALU/SQ_ACTIVE_INST_VALU descr="Unit: percent"></metric>
|
||||
<metric name="VmemLatency" expr=SQ_ACCUM_PREV_HIRES/SQ_INSTS_VMEM descr="Unit: cycles"></metric>
|
||||
<metric name="SmemLatency" expr=SQ_ACCUM_PREV_HIRES/SQ_INSTS_SMEM_NORM descr="Unit: cycles"></metric>
|
||||
## Local Data Share (LDS) Metrics
|
||||
<metric name="LdsUtil" expr=100*SQ_LDS_IDX_ACTIVE/(GRBM_GUI_ACTIVE*CU_NUM) descr="Unit: percent"></metric>
|
||||
<metric name="LdsPipeIssueUtil" expr=100*4*SQ_ACTIVE_INST_LDS/(GRBM_GUI_ACTIVE*CU_NUM*2) descr="Unit: percent"></metric>
|
||||
<metric name="LdsLatency" expr=SQ_ACCUM_PREV_HIRES/SQ_INSTS_LDS descr="Unit: cycles"></metric>
|
||||
<metric name="LdsBankConflict" expr=SQ_LDS_BANK_CONFLICT/(SQ_LDS_IDX_ACTIVE-SQ_LDS_BANK_CONFLICT) descr="Unit: conflicts/access"></metric>
|
||||
## L1I and sL1D Cache Metrics
|
||||
<metric name="L1iCacheHitRate" expr=100*SQC_ICACHE_HITS/SQC_ICACHE_REQ descr="Unit: percent"></metric>
|
||||
<metric name="sL1dCacheHitRate" expr=100*SQC_DCACHE_HITS/SQC_DCACHE_REQ descr="Unit: percent"></metric>
|
||||
## vL1D Cache Metrics
|
||||
<metric name="vL1dBufCoalesceRate" expr=100*64*TA_TOTAL_WAVEFRONTS_sum/(TCP_TOTAL_ACCESSES_sum*4) descr="Unit: percent"></metric>
|
||||
<metric name="vL1dCacheUtil" expr=100*TCP_GATE_EN2_sum/TCP_GATE_EN1_sum descr="Unit: percent"></metric>
|
||||
<metric name="vL1dCacheTcbHitRate" expr=100*TCP_UTCL1_TRANSLATION_HIT_sum/TCP_UTCL1_REQUEST_sum descr="Unit: percent"></metric>
|
||||
<metric name="vL1dCacheWaveLatency" expr=TCP_TCP_LATENCY_sum/TCP_TA_TCP_STATE_READ_sum descr="Unit: cycles"></metric>
|
||||
<metric name="vL1dReadFromL2Latency" expr=TCP_TCC_READ_REQ_LATENCY_sum/(TCP_TCC_READ_REQ_sum+TCP_TCC_ATOMIC_WITH_RET_REQ_sum) descr="Unit: cycles"></metric>
|
||||
<metric name="vL1dWriteToL2Latency" expr=TCP_TCC_WRITE_REQ_LATENCY_sum/(TCP_TCC_WRITE_REQ_sum+TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum) descr="Unit: cycles"></metric>
|
||||
<metric name="vL1dRdTagConfStallRate" expr=100*TCP_READ_TAGCONFLICT_STALL_CYCLES_sum/TCP_GATE_EN2_sum descr="Unit: percent"></metric>
|
||||
<metric name="vL1dWrTagConfStallRate" expr=100*TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum/TCP_GATE_EN2_sum descr="Unit: percent"></metric>
|
||||
<metric name="vL1dAtomicTagConfStallRate" expr=100*TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum/TCP_GATE_EN2_sum descr="Unit: percent"></metric>
|
||||
<metric name="vL1dMissReqStallRate" expr=100*TCP_TCR_TCP_STALL_CYCLES_sum/TCP_GATE_EN2_sum descr="Unit: percent"></metric>
|
||||
<metric name="vL1dDataPendRate" expr=100*TCP_PENDING_STALL_CYCLES_sum/TCP_GATE_EN2_sum descr="Unit: percent"></metric>
|
||||
<metric name="vL1dDataRetStallRate" expr=100*TD_TC_STALL_sum/TD_TD_BUSY_sum descr="Unit: percent"></metric>
|
||||
## L2 Cache Metrics
|
||||
<metric name="L2CacheHitRate" expr=100*TCC_HIT_sum/(TCC_HIT_sum+TCC_MISS_sum) descr="Unit: percent"></metric>
|
||||
<metric name="L2CacheTagRamStallRate" expr=100*TCC_TAG_STALL_sum/TCC_BUSY_sum descr="Unit: percent"></metric>
|
||||
<metric name="EaRdLatency" expr=TCC_EA_RDREQ_LEVEL_sum/TCC_EA_RDREQ_sum descr="Unit: cycles"></metric>
|
||||
<metric name="EaRdIoStallRate" expr=100*TCC_EA_RDREQ_IO_CREDIT_STALL_sum/TCC_BUSY_sum descr="Unit: percent"></metric>
|
||||
<metric name="EaRdGmiStallRate" expr=100*TCC_EA_RDREQ_GMI_CREDIT_STALL_sum/TCC_BUSY_sum descr="Unit: percent"></metric>
|
||||
<metric name="EaRdDramStallRate" expr=100*TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum/TCC_BUSY_sum descr="Unit: percent"></metric>
|
||||
<metric name="EaWrLatency" expr=TCC_EA_WRREQ_LEVEL_sum/TCC_EA_WRREQ_sum descr="Unit: cycles"></metric>
|
||||
<metric name="EaWrIoStallRate" expr=100*TCC_EA_WRREQ_IO_CREDIT_STALL_sum/TCC_BUSY_sum descr="Unit: percent"></metric>
|
||||
<metric name="EaWrGmiStallRate" expr=100*TCC_EA_WRREQ_GMI_CREDIT_STALL_sum/TCC_BUSY_sum descr="Unit: percent"></metric>
|
||||
<metric name="EaWrDramStallRate" expr=100*TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum/TCC_BUSY_sum descr="Unit: percent"></metric>
|
||||
<metric name="EaWrStarveRate" expr=100*TCC_TOO_MANY_EA_WRREQS_STALL_sum/TCC_BUSY_sum descr="Unit: percent"></metric>
|
||||
<metric name="EaAtomicLatency" expr=TCC_EA_ATOMIC_LEVEL_sum/TCC_EA_ATOMIC_sum descr="Unit: cycles"></metric>
|
||||
</gfx90a_expr>
|
||||
|
||||
<gfx940_expr>
|
||||
<metric name="TCP_TCP_TA_DATA_STALL_CYCLES_sum" expr=sum(TCP_TCP_TA_DATA_STALL_CYCLES,16) decr="Total number of TCP stalls TA data interface."></metric>
|
||||
<metric name="TCP_TCP_TA_DATA_STALL_CYCLES_max" expr=max(TCP_TCP_TA_DATA_STALL_CYCLES,16) decr="Maximum number of TCP stalls TA data interface."></metric>
|
||||
|
||||
<metric name="VFetchInsts" expr=(SQ_INSTS_VMEM_RD-TA_FLAT_READ_WAVEFRONTS_sum)/SQ_WAVES descr="The average number of vector fetch instructions from the video memory executed per work-item (affected by flow control). Excludes FLAT instructions that fetch from video memory."></metric>
|
||||
<metric name="VWriteInsts" expr=(SQ_INSTS_VMEM_WR-TA_FLAT_WRITE_WAVEFRONTS_sum)/SQ_WAVES descr="The average number of vector write instructions to the video memory executed per work-item (affected by flow control). Excludes FLAT instructions that write to video memory."></metric>
|
||||
<metric name="VALUUtilization" expr=100*SQ_THREAD_CYCLES_VALU/(SQ_ACTIVE_INST_VALU*MAX_WAVE_SIZE) descr="The percentage of active vector ALU threads in a wave. A lower number can mean either more thread divergence in a wave or that the work-group size is not a multiple of 64. Value range: 0% (bad), 100% (ideal - no thread divergence)."></metric>
|
||||
<metric name="VALUBusy" expr=100*SQ_ACTIVE_INST_VALU*4/SIMD_NUM/GRBM_GUI_ACTIVE descr="The percentage of GPUTime vector ALU instructions are processed. Value range: 0% (bad) to 100% (optimal)."></metric>
|
||||
<metric name="SALUBusy" expr=100*SQ_INST_CYCLES_SALU*4/SIMD_NUM/GRBM_GUI_ACTIVE descr="The percentage of GPUTime scalar ALU instructions are processed. Value range: 0% (bad) to 100% (optimal)."></metric>
|
||||
<metric name="FetchSize" expr=FETCH_SIZE descr="The total kilobytes fetched from the video memory. This is measured with all extra fetches and any cache or memory effects taken into account."></metric>
|
||||
<metric name="WriteSize" expr=WRITE_SIZE descr="The total kilobytes written to the video memory. This is measured with all extra fetches and any cache or memory effects taken into account."></metric>
|
||||
<metric name="MemWrites32B" expr=WRITE_REQ_32B descr="The total number of effective 32B write transactions to the memory"></metric>
|
||||
<metric name="MemUnitStalled" expr=100*TCP_TCP_TA_DATA_STALL_CYCLES_max/GRBM_GUI_ACTIVE/SE_NUM descr="The percentage of GPUTime the memory unit is stalled. Try reducing the number or size of fetches and writes if possible. Value range: 0% (optimal) to 100% (bad)."></metric>
|
||||
<metric name="TA_BUSY_avr" expr=avr(TA_TA_BUSY,16) descr="TA block is busy. Average over TA instances."></metric>
|
||||
<metric name="TA_BUSY_max" expr=max(TA_TA_BUSY,16) descr="TA block is busy. Max over TA instances."></metric>
|
||||
<metric name="TA_BUSY_min" expr=min(TA_TA_BUSY,16) descr="TA block is busy. Min over TA instances."></metric>
|
||||
<metric name="TA_TA_BUSY_sum" expr=sum(TA_TA_BUSY,16) descr="TA block is busy. Perf_Windowing not supported for this counter. Sum over TA instances."></metric>
|
||||
<metric name="TA_TOTAL_WAVEFRONTS_sum" expr=sum(TA_TOTAL_WAVEFRONTS,16) descr="Total number of wavefronts processed by TA. Sum over TA instances."></metric>
|
||||
<metric name="TA_ADDR_STALLED_BY_TC_CYCLES_sum" expr=sum(TA_ADDR_STALLED_BY_TC_CYCLES,16) descr="Number of cycles addr path stalled by TC. Perf_Windowing not supported for this counter. Sum over TA instances."></metric>
|
||||
<metric name="TA_ADDR_STALLED_BY_TD_CYCLES_sum" expr=sum(TA_ADDR_STALLED_BY_TD_CYCLES,16) descr="Number of cycles addr path stalled by TD. Perf_Windowing not supported for this counter. Sum over TA instances."></metric>
|
||||
<metric name="TA_DATA_STALLED_BY_TC_CYCLES_sum" expr=sum(TA_DATA_STALLED_BY_TC_CYCLES,16) descr="Number of cycles data path stalled by TC. Perf_Windowing not supported for this counter. Sum over TA instances."></metric>
|
||||
<metric name="TA_FLAT_WAVEFRONTS_sum" expr=sum(TA_FLAT_WAVEFRONTS,16) descr="Number of flat opcode wavfronts processed by the TA. Sum over TA instances."></metric>
|
||||
<metric name="TA_FLAT_READ_WAVEFRONTS_sum" expr=sum(TA_FLAT_READ_WAVEFRONTS,16) descr="Number of flat opcode reads processed by the TA. Sum over TA instances."></metric>
|
||||
<metric name="TA_FLAT_WRITE_WAVEFRONTS_sum" expr=sum(TA_FLAT_WRITE_WAVEFRONTS,16) descr="Number of flat opcode writes processed by the TA. Sum over TA instances."></metric>
|
||||
<metric name="TA_FLAT_ATOMIC_WAVEFRONTS_sum" expr=sum(TA_FLAT_ATOMIC_WAVEFRONTS,16) descr="Number of flat opcode atomics processed by the TA. Sum over TA instances."></metric>
|
||||
<metric name="TA_BUFFER_WAVEFRONTS_sum" expr=sum(TA_BUFFER_WAVEFRONTS,16) descr="Number of buffer wavefronts processed by TA. Sum over TA instances."></metric>
|
||||
<metric name="TA_BUFFER_READ_WAVEFRONTS_sum" expr=sum(TA_BUFFER_READ_WAVEFRONTS,16) descr="Number of buffer read wavefronts processed by TA. Sum over TA instances."></metric>
|
||||
<metric name="TA_BUFFER_WRITE_WAVEFRONTS_sum" expr=sum(TA_BUFFER_WRITE_WAVEFRONTS,16) descr="Number of buffer write wavefronts processed by TA. Sum over TA instances."></metric>
|
||||
<metric name="TA_BUFFER_ATOMIC_WAVEFRONTS_sum" expr=sum(TA_BUFFER_ATOMIC_WAVEFRONTS,16) descr="Number of buffer atomic wavefronts processed by TA. Sum over TA instances."></metric>
|
||||
<metric name="TA_BUFFER_TOTAL_CYCLES_sum" expr=sum(TA_BUFFER_TOTAL_CYCLES,16) descr="Number of buffer cycles issued to TC. Sum over TA instances."></metric>
|
||||
<metric name="TA_BUFFER_COALESCED_READ_CYCLES_sum" expr=sum(TA_BUFFER_COALESCED_READ_CYCLES,16) descr="Number of buffer coalesced read cycles issued to TC. Sum over TA instances."></metric>
|
||||
<metric name="TA_BUFFER_COALESCED_WRITE_CYCLES_sum" expr=sum(TA_BUFFER_COALESCED_WRITE_CYCLES,16) descr="Number of buffer coalesced write cycles issued to TC. Sum over TA instances."></metric>
|
||||
<metric name="TD_TD_BUSY_sum" expr=sum(TD_TD_BUSY,16) descr="TD is processing or waiting for data. Perf_Windowing not supported for this counter. Sum over TD instances."></metric>
|
||||
<metric name="TD_TC_STALL_sum" expr=sum(TD_TC_STALL,16) descr="TD is stalled waiting for TC data. Sum over TD instances."></metric>
|
||||
<metric name="TD_LOAD_WAVEFRONT_sum" expr=sum(TD_LOAD_WAVEFRONT,16) descr="Count the wavefronts with opcode = load, include atomics and store. Sum over TD instances."></metric>
|
||||
<metric name="TD_ATOMIC_WAVEFRONT_sum" expr=sum(TD_ATOMIC_WAVEFRONT,16) descr="Count the wavefronts with opcode = atomic. Sum over TD instances."></metric>
|
||||
<metric name="TD_STORE_WAVEFRONT_sum" expr=sum(TD_STORE_WAVEFRONT,16) descr="Count the wavefronts with opcode = store. Sum over TD instances."></metric>
|
||||
<metric name="TD_COALESCABLE_WAVEFRONT_sum" expr=sum(TD_COALESCABLE_WAVEFRONT,16) descr="Count wavefronts that TA finds coalescable. Sum over TD instances."></metric>
|
||||
<metric name="TD_SPI_STALL_sum" expr=sum(TD_SPI_STALL,16) descr="TD is stalled SPI vinit, sum of TCP instances"></metric>
|
||||
<metric name="TCP_GATE_EN1_sum" expr=sum(TCP_GATE_EN1,16) descr="TCP interface clocks are turned on. Not Windowed. Sum over TCP instances."></metric>
|
||||
<metric name="TCP_GATE_EN2_sum" expr=sum(TCP_GATE_EN2,16) descr="TCP core clocks are turned on. Not Windowed. Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TD_TCP_STALL_CYCLES_sum" expr=sum(TCP_TD_TCP_STALL_CYCLES,16) descr="TD stalls TCP. Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TCR_TCP_STALL_CYCLES_sum" expr=sum(TCP_TCR_TCP_STALL_CYCLES,16) descr="TCR stalls TCP_TCR_req interface. Sum over TCP instances."></metric>
|
||||
<metric name="TCP_READ_TAGCONFLICT_STALL_CYCLES_sum" expr=sum(TCP_READ_TAGCONFLICT_STALL_CYCLES,16) descr="Tagram conflict stall on a read. Sum over TCP instances."></metric>
|
||||
<metric name="TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum" expr=sum(TCP_WRITE_TAGCONFLICT_STALL_CYCLES,16) descr="Tagram conflict stall on a write. Sum over TCP instances."></metric>
|
||||
<metric name="TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum" expr=sum(TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES,16) descr="Tagram conflict stall on an atomic. Sum over TCP instances."></metric>
|
||||
<metric name="TCP_VOLATILE_sum" expr=sum(TCP_VOLATILE,16) descr="Total number of L1 volatile pixels/buffers from TA. Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TOTAL_ACCESSES_sum" expr=sum(TCP_TOTAL_ACCESSES,16) descr="Total number of pixels/buffers from TA. Equals TCP_PERF_SEL_TOTAL_READ+TCP_PERF_SEL_TOTAL_NONREAD. Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TOTAL_READ_sum" expr=sum(TCP_TOTAL_READ,16) descr="Total number of read pixels/buffers from TA. Equals TCP_PERF_SEL_TOTAL_HIT_LRU_READ + TCP_PERF_SEL_TOTAL_MISS_LRU_READ + TCP_PERF_SEL_TOTAL_MISS_EVICT_READ. Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TOTAL_WRITE_sum" expr=sum(TCP_TOTAL_WRITE,16) descr="Total number of local write pixels/buffers from TA. Equals TCP_PERF_SEL_TOTAL_MISS_LRU_WRITE+ TCP_PERF_SEL_TOTAL_MISS_EVICT_WRITE. Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TOTAL_ATOMIC_WITH_RET_sum" expr=sum(TCP_TOTAL_ATOMIC_WITH_RET,16) descr="Total number of atomic with return pixels/buffers from TA. Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TOTAL_ATOMIC_WITHOUT_RET_sum" expr=sum(TCP_TOTAL_ATOMIC_WITHOUT_RET,16) descr="Total number of atomic without return pixels/buffers from TA Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TOTAL_WRITEBACK_INVALIDATES_sum" expr=sum(TCP_TOTAL_WRITEBACK_INVALIDATES,16) descr="Total number of cache invalidates. Equals TCP_PERF_SEL_TOTAL_WBINVL1+ TCP_PERF_SEL_TOTAL_WBINVL1_VOL+ TCP_PERF_SEL_CP_TCP_INVALIDATE+ TCP_PERF_SEL_SQ_TCP_INVALIDATE_VOL. Not Windowed. Sum over TCP instances."></metric>
|
||||
<metric name="TCP_UTCL1_REQUEST_sum" expr=sum(TCP_UTCL1_REQUEST,16) descr="Total CLIENT_UTCL1 NORMAL requests Sum over TCP instances."></metric>
|
||||
<metric name="TCP_UTCL1_TRANSLATION_MISS_sum" expr=sum(TCP_UTCL1_TRANSLATION_MISS,16) descr="Total utcl1 translation misses Sum over TCP instances."></metric>
|
||||
<metric name="TCP_UTCL1_TRANSLATION_HIT_sum" expr=sum(TCP_UTCL1_TRANSLATION_HIT,16) descr="Total utcl1 translation hits Sum over TCP instances."></metric>
|
||||
<metric name="TCP_UTCL1_PERMISSION_MISS_sum" expr=sum(TCP_UTCL1_PERMISSION_MISS,16) descr="Total utcl1 permission misses Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TOTAL_CACHE_ACCESSES_sum" expr=sum(TCP_TOTAL_CACHE_ACCESSES,16) descr="Count of total cache line (tag) accesses (includes hits and misses). Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TA_TCP_STATE_READ_sum" expr=sum(TCP_TA_TCP_STATE_READ,16) descr="Number of state reads Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TCC_READ_REQ_sum" expr=sum(TCP_TCC_READ_REQ,16) descr="Total read requests from TCP to all TCCs Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TCC_WRITE_REQ_sum" expr=sum(TCP_TCC_WRITE_REQ,16) descr="Total write requests from TCP to all TCCs Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TCC_ATOMIC_WITH_RET_REQ_sum" expr=sum(TCP_TCC_ATOMIC_WITH_RET_REQ,16) descr="Total atomic with return requests from TCP to all TCCs Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum" expr=sum(TCP_TCC_ATOMIC_WITHOUT_RET_REQ,16) descr="Total atomic without return requests from TCP to all TCCs Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TCC_NC_READ_REQ_sum" expr=sum(TCP_TCC_NC_READ_REQ,16) descr="Total read requests with NC mtype from this TCP to all TCCs Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TCC_NC_WRITE_REQ_sum" expr=sum(TCP_TCC_NC_WRITE_REQ,16) descr="Total write requests with NC mtype from this TCP to all TCCs Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TCC_NC_ATOMIC_REQ_sum" expr=sum(TCP_TCC_NC_ATOMIC_REQ,16) descr="Total atomic requests with NC mtype from this TCP to all TCCs Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TCC_UC_READ_REQ_sum" expr=sum(TCP_TCC_UC_READ_REQ,16) descr="Total read requests with UC mtype from this TCP to all TCCs Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TCC_UC_WRITE_REQ_sum" expr=sum(TCP_TCC_UC_WRITE_REQ,16) descr="Total write requests with UC mtype from this TCP to all TCCs Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TCC_UC_ATOMIC_REQ_sum" expr=sum(TCP_TCC_UC_ATOMIC_REQ,16) descr="Total atomic requests with UC mtype from this TCP to all TCCs Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TCC_CC_READ_REQ_sum" expr=sum(TCP_TCC_CC_READ_REQ,16) descr="Total write requests with CC mtype from this TCP to all TCCs Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TCC_CC_WRITE_REQ_sum" expr=sum(TCP_TCC_CC_WRITE_REQ,16) descr="Total write requests with CC mtype from this TCP to all TCCs Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TCC_CC_ATOMIC_REQ_sum" expr=sum(TCP_TCC_CC_ATOMIC_REQ,16) descr="Total atomic requests with CC mtype from this TCP to all TCCs Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TCC_RW_READ_REQ_sum" expr=sum(TCP_TCC_RW_READ_REQ,16) descr="Total write requests with RW mtype from this TCP to all TCCs. Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TCC_RW_WRITE_REQ_sum" expr=sum(TCP_TCC_RW_WRITE_REQ,16) descr="Total write requests with RW mtype from this TCP to all TCCs. Sum over TCP instances."></metric>
|
||||
<metric name="TCP_TCC_RW_ATOMIC_REQ_sum" expr=sum(TCP_TCC_RW_ATOMIC_REQ,16) descr="Total atomic requests with RW mtype from this TCP to all TCCs. Sum over TCP instances."></metric>
|
||||
<metric name="TCP_PENDING_STALL_CYCLES_sum" expr=sum(TCP_PENDING_STALL_CYCLES,16) descr="Stall due to data pending from L2. Sum over TCP instances."></metric>
|
||||
<metric name="TCA_CYCLE_sum" expr=sum(TCA_CYCLE,16) descr="Number of cycles. Sum over all TCA instances "></metric>
|
||||
<metric name="TCA_BUSY_sum" expr=sum(TCA_BUSY,16) descr="Number of cycles we have a request pending. Sum over all TCA instances."></metric>
|
||||
<metric name="TCC_BUSY_avr" expr=avr(TCC_BUSY,32) descr="TCC_BUSY avr over all memory channels."></metric>
|
||||
<metric name="TCC_WRREQ_STALL_max" expr=max(TCC_EA_WRREQ_STALL,32) descr="Number of cycles a write request was stalled. Max over TCC instances."></metric>
|
||||
<metric name="TCC_CYCLE_sum" expr=sum(TCC_CYCLE,32) descr="Number of cycles. Not windowable. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_BUSY_sum" expr=sum(TCC_BUSY,32) descr="Number of cycles we have a request pending. Not windowable. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_REQ_sum" expr=sum(TCC_REQ,32) descr="Number of requests of all types. This is measured at the tag block. This may be more than the number of requests arriving at the TCC, but it is a good indication of the total amount of work that needs to be performed. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_STREAMING_REQ_sum" expr=sum(TCC_STREAMING_REQ,32) descr="Number of streaming requests. This is measured at the tag block. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_NC_REQ_sum" expr=sum(TCC_NC_REQ,32) descr="The number of noncoherently cached requests. This is measured at the tag block. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_UC_REQ_sum" expr=sum(TCC_UC_REQ,32) descr="The number of uncached requests. This is measured at the tag block. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_CC_REQ_sum" expr=sum(TCC_CC_REQ,32) descr="The number of coherently cached requests. This is measured at the tag block. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_RW_REQ_sum" expr=sum(TCC_RW_REQ,32) descr="The number of RW requests. This is measured at the tag block. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_PROBE_sum" expr=sum(TCC_PROBE,32) descr="Number of probe requests. Not windowable. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_PROBE_ALL_sum" expr=sum(TCC_PROBE_ALL,32) descr="Number of external probe requests with with EA_TCC_preq_all== 1. Not windowable. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_READ_sum" expr=sum(TCC_READ,32) descr="Number of read requests. Compressed reads are included in this, but metadata reads are not included. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_WRITE_sum" expr=sum(TCC_WRITE,32) descr="Number of write requests. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_ATOMIC_sum" expr=sum(TCC_ATOMIC,32) descr="Number of atomic requests of all types. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_HIT_sum" expr=sum(TCC_HIT,32) descr="Number of cache hits. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_MISS_sum" expr=sum(TCC_MISS,32) descr="Number of cache misses. UC reads count as misses. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_WRITEBACK_sum" expr=sum(TCC_WRITEBACK,32) descr="Number of lines written back to main memory. This includes writebacks of dirty lines and uncached write/atomic requests. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA0_WRREQ_sum" expr=sum(TCC_EA0_WRREQ,32) descr="Number of transactions (either 32-byte or 64-byte) going over the TC_EA_wrreq interface. Atomics may travel over the same interface and are generally classified as write requests. This does not include probe commands. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA0_WRREQ_64B_sum" expr=sum(TCC_EA0_WRREQ_64B,32) descr="Number of 64-byte transactions going (64-byte write or CMPSWAP) over the TC_EA_wrreq interface. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA0_WR_UNCACHED_32B_sum" expr=sum(TCC_EA0_WR_UNCACHED_32B,32) descr="Number of 32-byte write/atomic going over the TC_EA_wrreq interface due to uncached traffic. Note that CC mtypes can produce uncached requests, and those are included in this. A 64-byte request will be counted as 2. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA0_WRREQ_STALL_sum" expr=sum(TCC_EA0_WRREQ_STALL,32) descr="Number of cycles a write request was stalled. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA0_WRREQ_IO_CREDIT_STALL_sum" expr=sum(TCC_EA0_WRREQ_IO_CREDIT_STALL,32) descr="Number of cycles a EA write request was stalled because the interface was out of IO credits. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA0_WRREQ_GMI_CREDIT_STALL_sum" expr=sum(TCC_EA0_WRREQ_GMI_CREDIT_STALL,32) descr="Number of cycles a EA write request was stalled because the interface was out of GMI credits. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA0_WRREQ_DRAM_CREDIT_STALL_sum" expr=sum(TCC_EA0_WRREQ_DRAM_CREDIT_STALL,32) descr="Number of cycles a EA write request was stalled because the interface was out of DRAM credits. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_TOO_MANY_EA_WRREQS_STALL_sum" expr=sum(TCC_TOO_MANY_EA_WRREQS_STALL,32) descr="Number of cycles the TCC could not send a EA write request because it already reached its maximum number of pending EA write requests. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA0_WRREQ_LEVEL_sum" expr=sum(TCC_EA0_WRREQ_LEVEL,32) descr="The sum of the number of EA write requests in flight. This is primarily meant for measure average EA write latency. Average write latency = TCC_PERF_SEL_EA_WRREQ_LEVEL/TCC_PERF_SEL_EA_WRREQ. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA0_RDREQ_LEVEL_sum" expr=sum(TCC_EA0_RDREQ_LEVEL,32) descr="The sum of the number of TCC/EA read requests in flight. This is primarily meant for measure average EA read latency. Average read latency = TCC_PERF_SEL_EA_RDREQ_LEVEL/TCC_PERF_SEL_EA_RDREQ. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA0_ATOMIC_sum" expr=sum(TCC_EA0_ATOMIC,32) descr="Number of transactions going over the TC_EA_wrreq interface that are actually atomic requests. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA0_ATOMIC_LEVEL_sum" expr=sum(TCC_EA0_ATOMIC_LEVEL,32) descr="The sum of the number of EA atomics in flight. This is primarily meant for measure average EA atomic latency. Average atomic latency = TCC_PERF_SEL_EA_WRREQ_ATOMIC_LEVEL/TCC_PERF_SEL_EA_WRREQ_ATOMIC. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA0_RDREQ_sum" expr=sum(TCC_EA0_RDREQ,32) descr="Number of TCC/EA read requests (either 32-byte or 64-byte) Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA0_RDREQ_32B_sum" expr=sum(TCC_EA0_RDREQ_32B,32) descr="Number of 32-byte TCC/EA read requests Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA0_RD_UNCACHED_32B_sum" expr=sum(TCC_EA0_RD_UNCACHED_32B,32) descr="Number of 32-byte TCC/EA read due to uncached traffic. A 64-byte request will be counted as 2 Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA0_RDREQ_IO_CREDIT_STALL_sum" expr=sum(TCC_EA0_RDREQ_IO_CREDIT_STALL,32) descr="Number of cycles there was a stall because the read request interface was out of IO credits. Stalls occur regardless of whether a read needed to be performed or not. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA0_RDREQ_GMI_CREDIT_STALL_sum" expr=sum(TCC_EA0_RDREQ_GMI_CREDIT_STALL,32) descr="Number of cycles there was a stall because the read request interface was out of GMI credits. Stalls occur regardless of whether a read needed to be performed or not. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA0_RDREQ_DRAM_CREDIT_STALL_sum" expr=sum(TCC_EA0_RDREQ_DRAM_CREDIT_STALL,32) descr="Number of cycles there was a stall because the read request interface was out of DRAM credits. Stalls occur regardless of whether a read needed to be performed or not. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_TAG_STALL_sum" expr=sum(TCC_TAG_STALL,32) descr="."></metric>
|
||||
<metric name="TCC_NORMAL_WRITEBACK_sum" expr=sum(TCC_NORMAL_WRITEBACK,32) descr="Number of writebacks due to requests that are not writeback requests. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_ALL_TC_OP_WB_WRITEBACK_sum" expr=sum(TCC_ALL_TC_OP_WB_WRITEBACK,32) descr="Number of writebacks due to all TC_OP writeback requests. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_NORMAL_EVICT_sum" expr=sum(TCC_NORMAL_EVICT,32) descr="Number of evictions due to requests that are not invalidate or probe requests. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_ALL_TC_OP_INV_EVICT_sum" expr=sum(TCC_ALL_TC_OP_INV_EVICT,32) descr="Number of evictions due to all TC_OP invalidate requests. Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA0_RDREQ_DRAM_sum" expr=sum(TCC_EA0_RDREQ_DRAM,32) descr="Number of TCC/EA read requests (either 32-byte or 64-byte) destined for DRAM (MC). Sum over TCC instances."></metric>
|
||||
<metric name="TCC_EA0_WRREQ_DRAM_sum" expr=sum(TCC_EA0_WRREQ_DRAM,32) descr="Number of TCC/EA write requests (either 32-byte of 64-byte) destined for DRAM (MC). Sum over TCC instances."></metric>
|
||||
<metric name="FETCH_SIZE" expr=(TCC_EA0_RDREQ_32B_sum*32+(TCC_EA_RDREQ_sum-TCC_EA_RDREQ_32B_sum)*64)/1024 descr="The total kilobytes fetched from the video memory. This is measured with all extra fetches and any cache or memory effects taken into account."></metric>
|
||||
<metric name="WRITE_SIZE" expr=((TCC_EA0_WRREQ_sum-TCC_EA_WRREQ_64B_sum)*32+TCC_EA_WRREQ_64B_sum*64)/1024 descr="The total kilobytes written to the video memory. This is measured with all extra fetches and any cache or memory effects taken into account."></metric>
|
||||
<metric name="WRITE_REQ_32B" expr=TCC_EA0_WRREQ_64B_sum*2+(TCC_EA_WRREQ_sum-TCC_EA_WRREQ_64B_sum) descr="The total number of 32-byte effective memory writes."></metric>
|
||||
<metric name="CU_OCCUPANCY" expr=(SQ_CYCLES/(SQ_WAVE_CYCLES*4))/MAX_WAVE_SIZE descr="The ratio of active waves on a CU to the maximum number of active waves supported by the CU"></metric>
|
||||
<metric name="CU_UTILIZATION" expr=GRBM_GUI_ACTIVE/GRBM_COUNT descr="The total number of active cycles divided by total number of elapsed cycles"></metric>
|
||||
<metric name="TOTAL_16_OPS" expr=(SQ_INSTS_VALU_FMA_F16*2+SQ_INSTS_VALU_ADD_F16+SQ_INSTS_VALU_MUL_F16+SQ_INSTS_VALU_TRANS_F16)*64+((SQ_INSTS_VALU_MFMA_MOPS_F16+SQ_INSTS_VALU_MFMA_MOPS_BF16)*512) descr="The number of 16 bits OPS executed"></metric>
|
||||
<metric name="TOTAL_32_OPS" expr=(SQ_INSTS_VALU_FMA_F32*2+SQ_INSTS_VALU_INT32+SQ_INSTS_VALU_ADD_F32+SQ_INSTS_VALU_MUL_F32+SQ_INSTS_VALU_TRANS_F32)*64+(SQ_INSTS_VALU_MFMA_MOPS_F32*512) descr="The number of 32 bits OPS executed"></metric>
|
||||
<metric name="TOTAL_64_OPS" expr=(SQ_INSTS_VALU_FMA_F64*2+SQ_INSTS_VALU_INT64+SQ_INSTS_VALU_ADD_F64+SQ_INSTS_VALU_MUL_F64)*64+(SQ_INSTS_VALU_MFMA_MOPS_F64*512) descr="The number of 64 bits OPS executed"></metric>
|
||||
</gfx940_expr>
|
||||
|
||||
<gfx10_expr>
|
||||
<metric name="GPU_UTIL" expr=100*GRBM_GUI_ACTIVE/GRBM_COUNT descr="Percentage of the time that GUI is active"></metric>
|
||||
<metric name="CP_UTIL" expr=100*GRBM_CP_BUSY/GRBM_GUI_ACTIVE descr="Percentage of the GRBM_GUI_ACTIVE time that any of the Command Processor (CPG/CPC/CPF) blocks are busy"></metric>
|
||||
<metric name="SPI_UTIL" expr=100*GRBM_SPI_BUSY/GRBM_GUI_ACTIVE descr="Percentage of the GRBM_GUI_ACTIVE time that any of the Shader Pipe Interpolators (SPI) are busy in the shader engine(s)"></metric>
|
||||
<metric name="TA_UTIL" expr=100*GRBM_TA_BUSY/GRBM_GUI_ACTIVE descr="Percentage of the GRBM_GUI_ACTIVE time that any of the Texture Pipes (TA) are busy in the shader engine(s)."></metric>
|
||||
<metric name="GDS_UTIL" expr=100*GRBM_GDS_BUSY/GRBM_GUI_ACTIVE descr="Percentage of the GRBM_GUI_ACTIVE time that the Global Data Share (GDS) is busy."></metric>
|
||||
<metric name="EA_UTIL" expr=100*GRBM_EA_BUSY/GRBM_GUI_ACTIVE descr="Percentage of the GRBM_GUI_ACTIVE time that the Efficiency Arbiter (EA) block is busy."></metric>
|
||||
<metric name="WAVE_DEP_WAIT" expr=100*SQ_WAIT_ANY/SQ_WAVE_CYCLES descr="Percentage of the SQ_WAVE_CYCLE time spent waiting for anything."></metric>
|
||||
<metric name="WAVE_ISSUE_WAIT" expr=100*SQ_WAIT_INST_ANY/SQ_WAVE_CYCLES descr="Percentage of the SQ_WAVE_CYCLE time spent waiting for any instruction issue."></metric>
|
||||
|
||||
<metric name="TA_BUSY_avr" expr=avr(TA_TA_BUSY,16) descr="TA block is busy. Average over TA instances."></metric>
|
||||
<metric name="TA_BUSY_max" expr=max(TA_TA_BUSY,16) descr="TA block is busy. Max over TA instances."></metric>
|
||||
<metric name="TA_BUSY_min" expr=min(TA_TA_BUSY,16) descr="TA block is busy. Min over TA instances."></metric>
|
||||
<metric name="TA_FLAT_LOAD_WAVEFRONTS_sum" expr=sum(TA_FLAT_LOAD_WAVEFRONTS,16) descr="Number of flat load vec32 packets processed by the TA. Sum over TA instances."></metric>
|
||||
<metric name="TA_FLAT_STORE_WAVEFRONTS_sum" expr=sum(TA_FLAT_STORE_WAVEFRONTS,16) descr="Number of flat store vec32 packets processed by the TA. Sum over TA instances."></metric>
|
||||
|
||||
<metric name="GL2C_HIT_sum" expr=sum(GL2C_HIT,16) descr="Number of cache hits. Sum over GL2C instances."></metric>
|
||||
<metric name="GL2C_MISS_sum" expr=sum(GL2C_MISS,16) descr="Number of cache misses. Sum over GL2C instances."></metric>
|
||||
<metric name="GL2C_EA_RDREQ_32B_sum" expr=sum(GL2C_EA_RDREQ_32B,16) descr="Number of 32-byte GL2C/EA read requests. Sum over GL2C instances."></metric>
|
||||
<metric name="GL2C_EA_RDREQ_64B_sum" expr=sum(GL2C_EA_RDREQ_64B,16) descr="Number of 64-byte GL2C/EA read requests. Sum over GL2C instances."></metric>
|
||||
<metric name="GL2C_EA_RDREQ_96B_sum" expr=sum(GL2C_EA_RDREQ_96B,16) descr="Number of 96-byte GL2C/EA read requests. Sum over GL2C instances."></metric>
|
||||
<metric name="GL2C_EA_RDREQ_128B_sum" expr=sum(GL2C_EA_RDREQ_128B,16) descr="Number of 128-byte GL2C/EA read requests. Sum over GL2C instances."></metric>
|
||||
<metric name="GL2C_MC_RDREQ_sum" expr=sum(GL2C_MC_RDREQ,16) descr="Number of GL2C/EA read requests (either 32-byte or 64-byte or 128-byte). Sum over GL2C instances."></metric>
|
||||
<metric name="GL2C_MC_WRREQ_sum" expr=sum(GL2C_MC_WRREQ,16) descr="Number of transactions (either 32-byte or 64-byte) going over the GL2C_MC_wrreq interface. Sum over GL2C instances."></metric>
|
||||
<metric name="GL2C_EA_WRREQ_64B_sum" expr=sum(GL2C_EA_WRREQ_64B,16) descr="Number of 64-byte transactions going (64-byte write or CMPSWAP) over the GL2C_EA_wrreq interface. Sum over GL2C instances."></metric>
|
||||
<metric name="GL2C_WRREQ_STALL_max" expr=max(GL2C_MC_WRREQ_STALL,16) descr="Number of cycles a write request was stalled. Max over GL2C instances."></metric>
|
||||
<metric name="L2CacheHit" expr=100*sum(GL2C_HIT,16)/(sum(GL2C_HIT,16)+sum(GL2C_MISS,16)) descr="The percentage of fetch, write, atomic, and other instructions that hit the data in L2 cache. Value range: 0% (no hit) to 100% (optimal)."></metric>
|
||||
<metric name="FETCH_SIZE" expr=(GL2C_EA_RDREQ_32B_sum*32+GL2C_EA_RDREQ_64B_sum*64+GL2C_EA_RDREQ_96B_sum*96+GL2C_EA_RDREQ_128B_sum*128)/1024 descr="The total kilobytes fetched from the video memory. This is measured with all extra fetches and any cache or memory effects taken into account."></metric>
|
||||
<metric name="WriteUnitStalled" expr=100*GL2C_WRREQ_STALL_max/GRBM_GUI_ACTIVE descr="The percentage of GPUTime the Write unit is stalled. Value range: 0% to 100% (bad)."></metric>
|
||||
<metric name="LDSBankConflict" expr=100*SQC_LDS_BANK_CONFLICT/SQC_LDS_IDX_ACTIVE descr="The percentage of GPUTime LDS is stalled by bank conflicts. Value range: 0% (optimal) to 100% (bad)."></metric>
|
||||
</gfx10_expr>
|
||||
|
||||
<gfx1030_expr base="gfx10_expr">
|
||||
</gfx1030_expr>
|
||||
|
||||
<gfx1031_expr base="gfx10_expr">
|
||||
</gfx1031_expr>
|
||||
|
||||
<gfx1032_expr base="gfx10_expr">
|
||||
</gfx1032_expr>
|
||||
|
||||
<gfx8 base="gfx8_expr"></gfx8>
|
||||
<gfx9 base="gfx9_expr"></gfx9>
|
||||
<gfx10 base="gfx10_expr"></gfx10>
|
||||
# Vega20
|
||||
<gfx906 base="gfx906_expr"></gfx906>
|
||||
# Arcturus
|
||||
<gfx908 base="gfx908_expr"></gfx908>
|
||||
# Aldebaran
|
||||
<gfx90a base="gfx90a_expr"></gfx90a>
|
||||
#Navi21
|
||||
<gfx1030 base="gfx1030_expr"></gfx1030>
|
||||
|
||||
<gfx1031 base="gfx1031_expr"></gfx1031>
|
||||
|
||||
<gfx1032 base="gfx1032_expr"></gfx1032>
|
||||
|
||||
<global>
|
||||
# GPUBusy The percentage of time GPU was busy.
|
||||
<metric
|
||||
name="GPUBusy"
|
||||
descr="The percentage of time GPU was busy."
|
||||
expr=100*GRBM_GUI_ACTIVE/GRBM_COUNT
|
||||
></metric>
|
||||
|
||||
# Wavefronts Total wavefronts.
|
||||
<metric
|
||||
name="Wavefronts"
|
||||
descr="Total wavefronts."
|
||||
expr=SQ_WAVES
|
||||
></metric>
|
||||
|
||||
# VALUInsts The average number of vector ALU instructions executed per work-item (affected by flow control).
|
||||
<metric
|
||||
name="VALUInsts"
|
||||
descr="The average number of vector ALU instructions executed per work-item (affected by flow control)."
|
||||
expr=SQ_INSTS_VALU/SQ_WAVES
|
||||
></metric>
|
||||
|
||||
# SALUInsts The average number of scalar ALU instructions executed per work-item (affected by flow control).
|
||||
<metric
|
||||
name="SALUInsts"
|
||||
descr="The average number of scalar ALU instructions executed per work-item (affected by flow control)."
|
||||
expr=SQ_INSTS_SALU/SQ_WAVES
|
||||
></metric>
|
||||
|
||||
# SFetchInsts The average number of scalar fetch instructions from the video memory executed per work-item (affected by flow control).
|
||||
<metric
|
||||
name="SFetchInsts"
|
||||
descr="The average number of scalar fetch instructions from the video memory executed per work-item (affected by flow control)."
|
||||
expr=SQ_INSTS_SMEM/SQ_WAVES
|
||||
></metric>
|
||||
|
||||
# GDSInsts The average number of GDS read or GDS write instructions executed per work item (affected by flow control).
|
||||
<metric
|
||||
name="GDSInsts"
|
||||
descr="The average number of GDS read or GDS write instructions executed per work item (affected by flow control)."
|
||||
expr=SQ_INSTS_GDS/SQ_WAVES
|
||||
></metric>
|
||||
|
||||
# MemUnitBusy The percentage of GPUTime the memory unit is active. The result includes the stall time (MemUnitStalled). This is measured with all extra fetches and writes and any cache or memory effects taken into account. Value range: 0% to 100% (fetch-bound).
|
||||
<metric
|
||||
name="MemUnitBusy"
|
||||
descr="The percentage of GPUTime the memory unit is active. The result includes the stall time (MemUnitStalled). This is measured with all extra fetches and writes and any cache or memory effects taken into account. Value range: 0% to 100% (fetch-bound)."
|
||||
expr=100*max(TA_TA_BUSY,16)/GRBM_GUI_ACTIVE/SE_NUM
|
||||
></metric>
|
||||
|
||||
# ALUStalledByLDS The percentage of GPUTime ALU units are stalled by the LDS input queue being full or the output queue being not ready. If there are LDS bank conflicts, reduce them. Otherwise, try reducing the number of LDS accesses if possible. Value range: 0% (optimal) to 100% (bad).
|
||||
<metric
|
||||
name="ALUStalledByLDS"
|
||||
descr="The percentage of GPUTime ALU units are stalled by the LDS input queue being full or the output queue being not ready. If there are LDS bank conflicts, reduce them. Otherwise, try reducing the number of LDS accesses if possible. Value range: 0% (optimal) to 100% (bad)."
|
||||
expr=100*SQ_WAIT_INST_LDS*4/SQ_WAVES/GRBM_GUI_ACTIVE
|
||||
></metric>
|
||||
|
||||
</global>
|
||||
@@ -0,0 +1,199 @@
|
||||
#include "eval_metrics.h"
|
||||
#include "src/utils/helper.h"
|
||||
|
||||
#include <set>
|
||||
|
||||
using namespace rocmtools;
|
||||
|
||||
|
||||
struct block_des_t {
|
||||
uint32_t id;
|
||||
uint32_t index;
|
||||
};
|
||||
struct lt_block_des {
|
||||
bool operator()(const block_des_t& a1, const block_des_t& a2) const {
|
||||
return (a1.id < a2.id) || ((a1.id == a2.id) && (a1.index < a2.index));
|
||||
}
|
||||
};
|
||||
|
||||
struct block_status_t {
|
||||
uint32_t max_counters;
|
||||
uint32_t counter_index;
|
||||
uint32_t group_index;
|
||||
};
|
||||
|
||||
typedef struct {
|
||||
std::vector<results_t*>* results;
|
||||
size_t index;
|
||||
} callback_data_t;
|
||||
|
||||
static inline bool IsEventMatch(const hsa_ven_amd_aqlprofile_event_t& event1,
|
||||
const hsa_ven_amd_aqlprofile_event_t& event2) {
|
||||
return (event1.block_name == event2.block_name) && (event1.block_index == event2.block_index) &&
|
||||
(event1.counter_id == event2.counter_id);
|
||||
}
|
||||
|
||||
hsa_status_t pmcCallback(hsa_ven_amd_aqlprofile_info_type_t info_type,
|
||||
hsa_ven_amd_aqlprofile_info_data_t* info_data, void* data) {
|
||||
hsa_status_t status = HSA_STATUS_SUCCESS;
|
||||
callback_data_t* passed_data = reinterpret_cast<callback_data_t*>(data);
|
||||
passed_data->index += 1;
|
||||
|
||||
for (auto data_it = passed_data->results->begin(); data_it != passed_data->results->end();
|
||||
++data_it) {
|
||||
if (info_type == HSA_VEN_AMD_AQLPROFILE_INFO_PMC_DATA) {
|
||||
if (IsEventMatch(info_data->pmc_data.event, (*data_it)->event)) {
|
||||
(*data_it)->val_double += info_data->pmc_data.result; // TODO: += or =
|
||||
}
|
||||
}
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
|
||||
template <class Map> class MetricArgs : public xml::args_cache_t {
|
||||
public:
|
||||
MetricArgs(const Map* map) : map_(map) {}
|
||||
~MetricArgs() {}
|
||||
bool Lookup(const std::string& name, double& result) const {
|
||||
results_t* counter_result = NULL;
|
||||
auto it = map_->find(name);
|
||||
if (it == map_->end()) std::cout << "var '" << name << "' is not found" << std::endl;
|
||||
counter_result = it->second;
|
||||
if (counter_result) {
|
||||
result = counter_result->val_double;
|
||||
} else
|
||||
std::cout << "var '" << name << "' info is NULL" << std::endl;
|
||||
return (counter_result != NULL);
|
||||
}
|
||||
|
||||
private:
|
||||
const Map* map_;
|
||||
};
|
||||
|
||||
static std::mutex extract_metric_events_lock;
|
||||
|
||||
bool metrics::ExtractMetricEvents(
|
||||
std::vector<std::string>& metric_names, hsa_agent_t gpu_agent, MetricsDict* metrics_dict,
|
||||
std::map<std::string, results_t*>& results_map, std::vector<event_t>& events_list,
|
||||
std::vector<results_t*>& results_list,
|
||||
std::map<std::pair<uint32_t, uint32_t>, uint64_t>& event_to_max_block_count,
|
||||
std::map<std::string, std::set<std::string>>& metrics_counters) {
|
||||
std::map<block_des_t, block_status_t, lt_block_des> groups_map;
|
||||
|
||||
/* brief:
|
||||
results_map holds the result objects for each metric name(basic or derived)
|
||||
events_list holds the list of unique events from all the metrics entered
|
||||
results_list holds the result objects for each event (which means, basic counters only)
|
||||
*/
|
||||
try {
|
||||
for (size_t i = 0; i < metric_names.size(); i++) {
|
||||
counters_vec_t counters_vec;
|
||||
// TODO: saurabh
|
||||
// const Metric* metric = metrics_dict->GetMetricByName(metric_names[i]);
|
||||
const Metric* metric = metrics_dict->Get(metric_names[i]);
|
||||
if (metric == nullptr) fatal("input metric'%s' not found", metric_names[i].c_str());
|
||||
|
||||
// adding result object for derived metric
|
||||
std::lock_guard<std::mutex> lock(extract_metric_events_lock);
|
||||
if (results_map.find(metric_names[i]) == results_map.end()) {
|
||||
results_map[metric_names[i]] = new results_t{metric_names[i], 0, {}};
|
||||
} // else {
|
||||
// continue;
|
||||
// }
|
||||
|
||||
counters_vec = metric->GetCounters();
|
||||
if (counters_vec.empty())
|
||||
rocmtools::fatal("bad metric '%s' is empty", metric_names[i].c_str());
|
||||
|
||||
for (const counter_t* counter : counters_vec) {
|
||||
results_t* result = nullptr;
|
||||
if (metric->GetExpr()) {
|
||||
metrics_counters[metric->GetName()].insert(counter->name);
|
||||
// add this counter event only if it wasn't repeated before
|
||||
if (results_map.find(counter->name) != results_map.end()) {
|
||||
// std::cout << "Metric : " << metric->GetName() << " has " << counter->name
|
||||
// << " which is already part of the results map!" << std::endl;
|
||||
// continue;
|
||||
result = results_map.at(counter->name);
|
||||
} else {
|
||||
// result object for base metric
|
||||
// std::cout << "Metric : " << metric->GetName() << " : " << counter->name << std::endl;
|
||||
result = new results_t{counter->name, 0, {}}; // TODO: set correct initial value
|
||||
results_map[counter->name] = result;
|
||||
}
|
||||
} else {
|
||||
// std::cout << "Counter : " << metric->GetName() << " : " << counter->name << std::endl;
|
||||
result = results_map.at(counter->name);
|
||||
}
|
||||
// std::cout << "General Counter : " << metric->GetName() << " : " << counter->name <<
|
||||
// std::endl;
|
||||
const event_t* event = &(counter->event);
|
||||
const block_des_t block_des = {event->block_name, event->block_index};
|
||||
auto ret = groups_map.insert({block_des, {}});
|
||||
block_status_t& block_status = ret.first->second;
|
||||
if (block_status.max_counters == 0) {
|
||||
hsa_ven_amd_aqlprofile_profile_t query = {};
|
||||
query.agent = gpu_agent;
|
||||
query.type = HSA_VEN_AMD_AQLPROFILE_EVENT_TYPE_PMC;
|
||||
query.events = event;
|
||||
|
||||
uint32_t max_block_counters;
|
||||
hsa_status_t status = hsa_ven_amd_aqlprofile_get_info(
|
||||
&query, HSA_VEN_AMD_AQLPROFILE_INFO_BLOCK_COUNTERS, &max_block_counters);
|
||||
if (status != HSA_STATUS_SUCCESS) fatal("get block_counters info failed");
|
||||
block_status.max_counters = max_block_counters;
|
||||
}
|
||||
|
||||
// std::cout << "Counter: " << result->name << ", Block Index: " <<
|
||||
// counter->event.block_index
|
||||
// << ", Counter ID: " << counter->event.counter_id
|
||||
// << "\nBlock Status Group Index: " << block_status.group_index
|
||||
// << ", Block Max Counters: " << block_status.max_counters
|
||||
// << ", Block Status Counter ID: " << block_status.counter_index << std::endl;
|
||||
|
||||
if (block_status.counter_index >= block_status.max_counters) {
|
||||
rocmtools::fatal("Metrics specified have exceeded HW limits!");
|
||||
return false;
|
||||
}
|
||||
block_status.counter_index += 1;
|
||||
events_list.push_back(counter->event);
|
||||
result->event = counter->event;
|
||||
results_list.push_back(result);
|
||||
event_to_max_block_count.emplace(
|
||||
std::make_pair(static_cast<uint32_t>(counter->event.block_name),
|
||||
static_cast<uint32_t>(counter->event.block_index)),
|
||||
block_status.max_counters);
|
||||
}
|
||||
}
|
||||
} catch (std::string ex) {
|
||||
std::cout << ex << std::endl;
|
||||
abort();
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
|
||||
bool metrics::GetCounterData(hsa_ven_amd_aqlprofile_profile_t* profile,
|
||||
std::vector<results_t*>& results_list) {
|
||||
callback_data_t callback_data{&results_list, 0};
|
||||
hsa_status_t status = hsa_ven_amd_aqlprofile_iterate_data(profile, pmcCallback, &callback_data);
|
||||
return (status == HSA_STATUS_SUCCESS);
|
||||
}
|
||||
|
||||
bool metrics::GetMetricsData(std::map<std::string, results_t*>& results_map,
|
||||
std::vector<const Metric*>& metrics_list) {
|
||||
MetricArgs<std::map<std::string, results_t*>> args(&results_map);
|
||||
for (auto& metric : metrics_list) {
|
||||
const xml::Expr* expr = metric->GetExpr();
|
||||
if (expr) {
|
||||
auto it = results_map.find(metric->GetName());
|
||||
if (it == results_map.end()) rocmtools::fatal("metric results not found ");
|
||||
results_t* res = it->second;
|
||||
res->val_double = expr->Eval(args);
|
||||
}
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
@@ -0,0 +1,74 @@
|
||||
/******************************************************************************
|
||||
Copyright (c) 2018 Advanced Micro Devices, Inc. All rights reserved.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef SRC_CORE_METRICS_EVALMETRICS_H_
|
||||
#define SRC_CORE_METRICS_EVALMETRICS_H_
|
||||
|
||||
#include <vector>
|
||||
#include <map>
|
||||
#include "metrics.h"
|
||||
#include <hsa/hsa.h>
|
||||
|
||||
#include <atomic>
|
||||
#include <set>
|
||||
|
||||
namespace rocmtools {
|
||||
|
||||
typedef struct {
|
||||
std::string name;
|
||||
double val_double;
|
||||
event_t event;
|
||||
} results_t;
|
||||
|
||||
typedef struct {
|
||||
packet_t* start_packet;
|
||||
packet_t* stop_packet;
|
||||
packet_t* read_packet;
|
||||
rocmtools::MetricsDict* metrics_dict;
|
||||
std::vector<const rocmtools::Metric*> metrics_list;
|
||||
std::map<std::string, rocmtools::results_t*> results_map;
|
||||
std::vector<rocmtools::results_t*> results_list;
|
||||
std::vector<event_t> events_list;
|
||||
hsa_agent_t gpu_agent;
|
||||
hsa_signal_t begin_signal;
|
||||
std::atomic<bool> begin_completed{false};
|
||||
} profiling_context_t;
|
||||
|
||||
namespace metrics {
|
||||
bool ExtractMetricEvents(
|
||||
std::vector<std::string>& metric_names, hsa_agent_t gpu_agent, MetricsDict* metrics_dict,
|
||||
std::map<std::string, results_t*>& results_map, std::vector<event_t>& events_list,
|
||||
std::vector<results_t*>& results_list,
|
||||
std::map<std::pair<uint32_t, uint32_t>, uint64_t>& event_to_max_block_count,
|
||||
std::map<std::string, std::set<std::string>>& metrics_counters);
|
||||
|
||||
|
||||
bool GetCounterData(hsa_ven_amd_aqlprofile_profile_t* profile,
|
||||
std::vector<results_t*>& results_list);
|
||||
|
||||
bool GetMetricsData(std::map<std::string, results_t*>& results_map,
|
||||
std::vector<const Metric*>& metrics_list);
|
||||
|
||||
} // namespace metrics
|
||||
} // namespace rocmtools
|
||||
|
||||
#endif // SRC_CORE_METRICS_EVALMETRICS_H_
|
||||
@@ -0,0 +1,75 @@
|
||||
/******************************************************************************
|
||||
Copyright (c) 2018 Advanced Micro Devices, Inc. All rights reserved.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef SRC_UTIL_EXCEPTION_H_
|
||||
#define SRC_UTIL_EXCEPTION_H_
|
||||
|
||||
#include <hsa/hsa.h>
|
||||
#include <hsa/hsa_ven_amd_aqlprofile.h>
|
||||
|
||||
#include <exception>
|
||||
#include <sstream>
|
||||
#include <string>
|
||||
|
||||
#define EXC_ABORT(error, stream) \
|
||||
do { \
|
||||
const char* hsa_err_str = NULL; \
|
||||
if (hsa_status_string(error, &hsa_err_str) != HSA_STATUS_SUCCESS) hsa_err_str = NULL; \
|
||||
std::ostringstream oss; \
|
||||
oss << "error(" << error << ") \"" << __FUNCTION__ << "(), " << stream << "\"" << std::endl; \
|
||||
if (hsa_err_str != NULL) oss << hsa_err_str << std::endl; \
|
||||
std::cout << oss.str() << std::flush; \
|
||||
abort(); \
|
||||
} while (0)
|
||||
|
||||
#define EXC_RAISING(error, stream) \
|
||||
do { \
|
||||
std::ostringstream oss; \
|
||||
oss << __FUNCTION__ << "(), " << stream; \
|
||||
throw rocmtools::util::exception(error, oss.str()); \
|
||||
} while (0)
|
||||
|
||||
#define AQL_EXC_RAISING(error, stream) \
|
||||
do { \
|
||||
const char* error_string = NULL; \
|
||||
hsa_ven_amd_aqlprofile_error_string(&error_string); \
|
||||
EXC_RAISING(error, stream << ", " << error_string); \
|
||||
} while (0)
|
||||
|
||||
namespace rocmtools {
|
||||
namespace util {
|
||||
|
||||
class exception : public std::exception {
|
||||
public:
|
||||
explicit exception(const uint32_t& status, const std::string& msg) : status_(status), str_(msg) {}
|
||||
const char* what() const throw() { return str_.c_str(); }
|
||||
uint32_t status() const throw() { return status_; }
|
||||
|
||||
protected:
|
||||
const uint32_t status_;
|
||||
const std::string str_;
|
||||
};
|
||||
|
||||
} // namespace util
|
||||
} // namespace rocmtools
|
||||
|
||||
#endif // SRC_UTIL_EXCEPTION_H_
|
||||
@@ -0,0 +1,449 @@
|
||||
/******************************************************************************
|
||||
Copyright (c) 2022 Advanced Micro Devices, Inc. All rights reserved.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _SRC_CORE_COUNTERS_METRICS_XML_EXPR_H
|
||||
#define _SRC_CORE_COUNTERS_METRICS_XML_EXPR_H
|
||||
|
||||
#include <exception>
|
||||
#include <map>
|
||||
#include <string>
|
||||
#include <iostream>
|
||||
#include <sstream>
|
||||
#include <string.h>
|
||||
#include <float.h>
|
||||
|
||||
namespace xml {
|
||||
class exception_t : public std::exception {
|
||||
public:
|
||||
explicit exception_t(const std::string& msg) : str_(msg) {}
|
||||
const char* what() const throw() { return str_.c_str(); }
|
||||
|
||||
protected:
|
||||
const std::string str_;
|
||||
};
|
||||
|
||||
class div_zero_exception_t : public exception_t {
|
||||
public:
|
||||
explicit div_zero_exception_t(const std::string& msg)
|
||||
: exception_t("Divide by zero exception " + msg) {}
|
||||
};
|
||||
|
||||
typedef double args_t;
|
||||
static const args_t ARGS_MAX = DBL_MAX;
|
||||
typedef std::map<std::string, args_t> args_map_t;
|
||||
class Expr;
|
||||
|
||||
template <class T> class any_cache_t {
|
||||
public:
|
||||
virtual ~any_cache_t() {}
|
||||
virtual bool Lookup(const std::string& name, T& result) const = 0;
|
||||
};
|
||||
|
||||
typedef any_cache_t<std::string> expr_cache_t;
|
||||
typedef any_cache_t<args_t> args_cache_t;
|
||||
|
||||
class bin_expr_t {
|
||||
public:
|
||||
static const bin_expr_t* CreateExpr(const bin_expr_t* arg1, const bin_expr_t* arg2,
|
||||
const char op);
|
||||
static const bin_expr_t* CreateArg(Expr* obj, const std::string str);
|
||||
|
||||
bin_expr_t() : arg1_(NULL), arg2_(NULL) {}
|
||||
bin_expr_t(const bin_expr_t* arg1, const bin_expr_t* arg2) : arg1_(arg1), arg2_(arg2) {}
|
||||
virtual ~bin_expr_t() {
|
||||
if (arg1_) delete arg1_;
|
||||
if (arg2_) delete arg2_;
|
||||
}
|
||||
|
||||
virtual args_t Eval(const args_cache_t& args) const = 0;
|
||||
virtual std::string Symbol() const = 0;
|
||||
|
||||
std::string String() const {
|
||||
std::string str;
|
||||
if (arg1_) {
|
||||
str = "(" + arg1_->String() + " " + Symbol() + " " + arg2_->String() + ")";
|
||||
} else
|
||||
str = Symbol();
|
||||
return str;
|
||||
}
|
||||
|
||||
protected:
|
||||
const bin_expr_t* arg1_;
|
||||
const bin_expr_t* arg2_;
|
||||
};
|
||||
|
||||
class Expr {
|
||||
public:
|
||||
explicit Expr(const std::string& expr, const expr_cache_t* cache)
|
||||
: expr_(expr), pos_(0), sub_count_(0), cache_(cache), is_sub_expr_(false) {
|
||||
sub_vec_ = new std::vector<const Expr*>;
|
||||
var_vec_ = new std::vector<std::string>;
|
||||
tree_ = ParseExpr();
|
||||
}
|
||||
|
||||
explicit Expr(const std::string& expr, const Expr* obj)
|
||||
: expr_(expr),
|
||||
pos_(0),
|
||||
sub_count_(0),
|
||||
cache_(obj->cache_),
|
||||
sub_vec_(obj->sub_vec_),
|
||||
var_vec_(obj->var_vec_),
|
||||
is_sub_expr_(true) {
|
||||
sub_vec_->push_back(this);
|
||||
tree_ = ParseExpr();
|
||||
if (!SubCheck()) throw exception_t("expr '" + expr_ + "', bad parenthesis count");
|
||||
}
|
||||
|
||||
~Expr() {
|
||||
if (!is_sub_expr_) {
|
||||
delete cache_;
|
||||
for (auto it : *sub_vec_) delete it;
|
||||
delete sub_vec_;
|
||||
delete var_vec_;
|
||||
delete tree_;
|
||||
}
|
||||
}
|
||||
|
||||
std::string GetStr() const { return expr_; }
|
||||
const expr_cache_t* GetCache() const { return cache_; }
|
||||
const bin_expr_t* GetTree() const { return tree_; }
|
||||
|
||||
args_t Eval(const args_cache_t& args) const {
|
||||
args_t result = 0;
|
||||
try {
|
||||
result = tree_->Eval(args);
|
||||
} catch (const div_zero_exception_t& e) {
|
||||
if (div_zero_exc_on)
|
||||
std::cout << "Expr::Eval() exc(" << e.what() << ") : " << String() << std::endl;
|
||||
} catch (const exception_t& e) {
|
||||
throw e;
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
||||
std::string Lookup(const std::string& str) const {
|
||||
std::string result;
|
||||
if (cache_ && !(cache_->Lookup(str, result)))
|
||||
throw exception_t("expr '" + expr_ + "', lookup '" + str + "' failed");
|
||||
return result;
|
||||
}
|
||||
|
||||
void AddVar(const std::string& str) {
|
||||
bool found = false;
|
||||
for (std::string s : *var_vec_)
|
||||
if (s == str) found = true;
|
||||
if (!found) var_vec_->push_back(str);
|
||||
}
|
||||
|
||||
const std::vector<std::string>& GetVars() const { return *var_vec_; }
|
||||
|
||||
std::string String() const { return tree_->String(); }
|
||||
|
||||
private:
|
||||
const bin_expr_t* ParseExpr() {
|
||||
const bin_expr_t* expr = ParseArg();
|
||||
while (!IsEnd()) {
|
||||
const char op = Symb();
|
||||
const bin_expr_t* second_arg = NULL;
|
||||
if (IsSymb(')')) {
|
||||
Next();
|
||||
SubClose();
|
||||
break;
|
||||
}
|
||||
if (IsSymb('*') || IsSymb('/')) {
|
||||
Next();
|
||||
second_arg = ParseArg();
|
||||
expr = bin_expr_t::CreateExpr(expr, second_arg, op);
|
||||
} else if (IsSymb('+') || IsSymb('-')) {
|
||||
Next();
|
||||
second_arg = ParseExpr();
|
||||
expr = bin_expr_t::CreateExpr(expr, second_arg, op);
|
||||
break;
|
||||
} else {
|
||||
throw exception_t("expr '" + expr_ + "', bad operator '" + op + "'");
|
||||
}
|
||||
}
|
||||
return expr;
|
||||
}
|
||||
|
||||
const bin_expr_t* ParseArg() {
|
||||
const bin_expr_t* arg = NULL;
|
||||
if (IsSymb('(')) {
|
||||
Next();
|
||||
SubOpen();
|
||||
arg = ParseExpr();
|
||||
} else {
|
||||
const unsigned pos = FindOp();
|
||||
const std::string str = CutTill(pos);
|
||||
arg = bin_expr_t::CreateArg(this, str);
|
||||
if (arg == NULL) throw exception_t("expr '" + expr_ + "', bad argument '" + str + "'");
|
||||
}
|
||||
return arg;
|
||||
}
|
||||
|
||||
char Symb() const { return Symb(pos_); }
|
||||
char Symb(const unsigned ind) const { return expr_[ind]; }
|
||||
bool IsEnd() const { return (pos_ >= expr_.length()); }
|
||||
bool IsSymb(const char c) const { return IsSymb(pos_, c); }
|
||||
bool IsSymb(const unsigned ind, const char c) const { return (expr_[ind] == c); }
|
||||
void Next() { ++pos_; }
|
||||
void SubOpen() { ++sub_count_; }
|
||||
void SubClose() { --sub_count_; }
|
||||
bool SubCheck() const { return (sub_count_ == 0); }
|
||||
unsigned FindOp() const {
|
||||
unsigned i = pos_;
|
||||
unsigned open_n = 0;
|
||||
while (i < expr_.length()) {
|
||||
switch (Symb(i)) {
|
||||
case '*':
|
||||
case '/':
|
||||
case '+':
|
||||
case '-':
|
||||
goto end;
|
||||
case '(':
|
||||
++open_n;
|
||||
break;
|
||||
case ')':
|
||||
if (open_n != 0) i += 1;
|
||||
goto end;
|
||||
}
|
||||
++i;
|
||||
}
|
||||
end:
|
||||
return i;
|
||||
}
|
||||
std::string CutTill(const unsigned pos) {
|
||||
const std::string str = (pos > pos_) ? expr_.substr(pos_, pos - pos_) : "";
|
||||
pos_ = pos;
|
||||
return str;
|
||||
}
|
||||
|
||||
static const bool div_zero_exc_on = false;
|
||||
|
||||
const std::string expr_;
|
||||
unsigned pos_;
|
||||
unsigned sub_count_;
|
||||
const bin_expr_t* tree_;
|
||||
const expr_cache_t* const cache_;
|
||||
std::vector<const Expr*>* sub_vec_;
|
||||
std::vector<std::string>* var_vec_;
|
||||
const bool is_sub_expr_;
|
||||
};
|
||||
|
||||
class add_expr_t : public bin_expr_t {
|
||||
public:
|
||||
add_expr_t(const bin_expr_t* arg1, const bin_expr_t* arg2) : bin_expr_t(arg1, arg2) {}
|
||||
args_t Eval(const args_cache_t& args) const { return (arg1_->Eval(args) + arg2_->Eval(args)); }
|
||||
std::string Symbol() const { return "+"; }
|
||||
};
|
||||
class sub_expr_t : public bin_expr_t {
|
||||
public:
|
||||
sub_expr_t(const bin_expr_t* arg1, const bin_expr_t* arg2) : bin_expr_t(arg1, arg2) {}
|
||||
args_t Eval(const args_cache_t& args) const { return (arg1_->Eval(args) - arg2_->Eval(args)); }
|
||||
std::string Symbol() const { return "-"; }
|
||||
};
|
||||
class mul_expr_t : public bin_expr_t {
|
||||
public:
|
||||
mul_expr_t(const bin_expr_t* arg1, const bin_expr_t* arg2) : bin_expr_t(arg1, arg2) {}
|
||||
args_t Eval(const args_cache_t& args) const { return (arg1_->Eval(args) * arg2_->Eval(args)); }
|
||||
std::string Symbol() const { return "*"; }
|
||||
};
|
||||
class div_expr_t : public bin_expr_t {
|
||||
public:
|
||||
div_expr_t(const bin_expr_t* arg1, const bin_expr_t* arg2) : bin_expr_t(arg1, arg2) {}
|
||||
args_t Eval(const args_cache_t& args) const {
|
||||
const args_t denominator = arg2_->Eval(args);
|
||||
if (denominator == 0) throw div_zero_exception_t("div_expr_t::Eval()");
|
||||
return (static_cast<double>(arg1_->Eval(args)) / denominator);
|
||||
}
|
||||
std::string Symbol() const { return "/"; }
|
||||
};
|
||||
class const_expr_t : public bin_expr_t {
|
||||
public:
|
||||
const_expr_t(const args_t value) : value_(value) {}
|
||||
args_t Eval(const args_cache_t&) const { return value_; }
|
||||
std::string Symbol() const {
|
||||
std::ostringstream os;
|
||||
os << value_;
|
||||
return os.str();
|
||||
}
|
||||
|
||||
private:
|
||||
const args_t value_;
|
||||
};
|
||||
class var_expr_t : public bin_expr_t {
|
||||
public:
|
||||
var_expr_t(const std::string name) : name_(name) {}
|
||||
args_t Eval(const args_cache_t& args) const {
|
||||
args_t result = 0;
|
||||
if (!args.Lookup(name_, result)) throw exception_t("expr arg lookup '" + name_ + "' failed");
|
||||
return result;
|
||||
}
|
||||
std::string Symbol() const { return name_; }
|
||||
|
||||
private:
|
||||
const std::string name_;
|
||||
};
|
||||
|
||||
class fun_expr_t : public bin_expr_t {
|
||||
public:
|
||||
typedef std::vector<var_expr_t> vvect_t;
|
||||
fun_expr_t(const std::string& fname, const std::string& vname, const uint32_t& vnum)
|
||||
: fname_(fname) {
|
||||
for (uint32_t i = 0; i < vnum; ++i) {
|
||||
std::ostringstream var_full_name;
|
||||
var_full_name << vname << "[" << i << "]";
|
||||
vvect.push_back(var_expr_t(var_full_name.str()));
|
||||
}
|
||||
}
|
||||
const vvect_t& GetVars() const { return vvect; }
|
||||
std::string Symbol() const {
|
||||
const std::string var = vvect[0].Symbol();
|
||||
const std::string vname = var.substr(0, var.length() - 3);
|
||||
std::ostringstream oss;
|
||||
std::string str("(");
|
||||
str.back() = ')';
|
||||
oss << fname_ << "(" << vname << "," << vvect.size() << ")";
|
||||
return oss.str();
|
||||
}
|
||||
|
||||
private:
|
||||
const std::string fname_;
|
||||
vvect_t vvect;
|
||||
};
|
||||
class sum_expr_t : public fun_expr_t {
|
||||
public:
|
||||
sum_expr_t(const std::string& vname, const uint32_t& vnum) : fun_expr_t("sum", vname, vnum) {}
|
||||
args_t Eval(const args_cache_t& args) const {
|
||||
args_t result = 0;
|
||||
for (const auto& var : GetVars()) result += var.Eval(args);
|
||||
return result;
|
||||
}
|
||||
};
|
||||
class avr_expr_t : public fun_expr_t {
|
||||
public:
|
||||
avr_expr_t(const std::string& vname, const uint32_t& vnum) : fun_expr_t("avr", vname, vnum) {}
|
||||
args_t Eval(const args_cache_t& args) const {
|
||||
args_t result = 0;
|
||||
for (const auto& var : GetVars()) result += var.Eval(args);
|
||||
return result / GetVars().size();
|
||||
}
|
||||
};
|
||||
class min_expr_t : public fun_expr_t {
|
||||
public:
|
||||
min_expr_t(const std::string& vname, const uint32_t& vnum) : fun_expr_t("min", vname, vnum) {}
|
||||
args_t Eval(const args_cache_t& args) const {
|
||||
args_t result = ARGS_MAX;
|
||||
for (const auto& var : GetVars()) {
|
||||
args_t val = var.Eval(args);
|
||||
result = (val < result) ? val : result;
|
||||
}
|
||||
return result;
|
||||
}
|
||||
};
|
||||
class max_expr_t : public fun_expr_t {
|
||||
public:
|
||||
max_expr_t(const std::string& vname, const uint32_t& vnum) : fun_expr_t("max", vname, vnum) {}
|
||||
args_t Eval(const args_cache_t& args) const {
|
||||
args_t result = 0;
|
||||
for (const auto& var : GetVars()) {
|
||||
args_t val = var.Eval(args);
|
||||
result = (val > result) ? val : result;
|
||||
}
|
||||
return result;
|
||||
}
|
||||
};
|
||||
|
||||
inline const bin_expr_t* bin_expr_t::CreateExpr(const bin_expr_t* arg1, const bin_expr_t* arg2,
|
||||
const char op) {
|
||||
const bin_expr_t* expr = NULL;
|
||||
switch (op) {
|
||||
case '+':
|
||||
expr = new add_expr_t(arg1, arg2);
|
||||
break;
|
||||
case '-':
|
||||
expr = new sub_expr_t(arg1, arg2);
|
||||
break;
|
||||
case '*':
|
||||
expr = new mul_expr_t(arg1, arg2);
|
||||
break;
|
||||
case '/':
|
||||
expr = new div_expr_t(arg1, arg2);
|
||||
break;
|
||||
}
|
||||
return expr;
|
||||
}
|
||||
|
||||
inline const bin_expr_t* bin_expr_t::CreateArg(Expr* obj, const std::string str) {
|
||||
const bin_expr_t* arg = NULL;
|
||||
|
||||
const unsigned i = strspn(str.c_str(), "1234567890");
|
||||
if (i == str.length()) {
|
||||
const unsigned value = atoi(str.c_str());
|
||||
arg = new const_expr_t(value);
|
||||
}
|
||||
|
||||
if (arg == NULL) {
|
||||
const std::size_t pos = str.find('(');
|
||||
if (pos != std::string::npos) {
|
||||
char* fname = NULL;
|
||||
char* vname = NULL;
|
||||
int vnum = 0;
|
||||
int ret = sscanf(str.c_str(), "%m[a-zA-Z_](%m[0-9a-zA-Z_],%d)", &fname, &vname, &vnum);
|
||||
if (ret == 3) {
|
||||
const std::string fun_name(fname);
|
||||
const fun_expr_t* farg = NULL;
|
||||
if (fun_name == "sum") {
|
||||
farg = new sum_expr_t(vname, vnum);
|
||||
} else if (fun_name == "avr") {
|
||||
farg = new avr_expr_t(vname, vnum);
|
||||
} else if (fun_name == "min") {
|
||||
farg = new min_expr_t(vname, vnum);
|
||||
} else if (fun_name == "max") {
|
||||
farg = new max_expr_t(vname, vnum);
|
||||
}
|
||||
if (farg)
|
||||
for (const auto& var : farg->GetVars()) obj->AddVar(var.Symbol());
|
||||
arg = farg;
|
||||
}
|
||||
free(fname);
|
||||
free(vname);
|
||||
}
|
||||
}
|
||||
|
||||
if (arg == NULL) {
|
||||
const std::string sub_expr = obj->Lookup(str);
|
||||
if (sub_expr.empty()) {
|
||||
arg = new var_expr_t(str);
|
||||
obj->AddVar(str);
|
||||
} else {
|
||||
const Expr* expr = new Expr(sub_expr, obj);
|
||||
arg = expr->GetTree();
|
||||
}
|
||||
}
|
||||
|
||||
return arg;
|
||||
}
|
||||
|
||||
} // namespace xml
|
||||
|
||||
#endif // _SRC_CORE_COUNTERS_METRICS_XML_EXPR_H
|
||||
@@ -0,0 +1,28 @@
|
||||
/******************************************************************************
|
||||
Copyright (c) 2018 Advanced Micro Devices, Inc. All rights reserved.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
*******************************************************************************/
|
||||
|
||||
#include "metrics.h"
|
||||
|
||||
namespace rocmtools {
|
||||
MetricsDict::map_t* MetricsDict::map_ = NULL;
|
||||
MetricsDict::mutex_t MetricsDict::mutex_;
|
||||
} // namespace rocmtools
|
||||
Executable
+367
@@ -0,0 +1,367 @@
|
||||
/******************************************************************************
|
||||
Copyright (c) 2018 Advanced Micro Devices, Inc. All rights reserved.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef SRC_CORE_COUNTERS_METRICS_METRICS_H_
|
||||
#define SRC_CORE_COUNTERS_METRICS_METRICS_H_
|
||||
|
||||
#include <fcntl.h>
|
||||
#include <sys/stat.h>
|
||||
#include <sys/types.h>
|
||||
|
||||
#include <fstream>
|
||||
#include <iostream>
|
||||
#include <thread>
|
||||
#include <list>
|
||||
#include <map>
|
||||
#include <vector>
|
||||
|
||||
#include "types.h"
|
||||
#include "exception.h"
|
||||
#include "expr.h"
|
||||
#include "xml.h"
|
||||
#include <mutex>
|
||||
#include "src/core/hardware/hsa_info.h"
|
||||
|
||||
namespace rocmtools {
|
||||
struct counter_t {
|
||||
std::string name;
|
||||
event_t event;
|
||||
};
|
||||
typedef std::vector<const counter_t*> counters_vec_t;
|
||||
|
||||
class Metric {
|
||||
public:
|
||||
Metric(const std::string& name) : name_(name) {}
|
||||
virtual ~Metric() {}
|
||||
std::string GetName() const { return name_; }
|
||||
virtual void GetCounters(counters_vec_t& vec) const = 0;
|
||||
counters_vec_t GetCounters() const {
|
||||
counters_vec_t counters;
|
||||
GetCounters(counters);
|
||||
return counters;
|
||||
}
|
||||
virtual const xml::Expr* GetExpr() const = 0;
|
||||
|
||||
private:
|
||||
const std::string name_;
|
||||
};
|
||||
|
||||
class BaseMetric : public Metric {
|
||||
public:
|
||||
BaseMetric(const std::string& name, const counter_t& counter) : Metric(name), counter_(counter) {}
|
||||
void GetCounters(counters_vec_t& vec) const { vec.push_back(&counter_); }
|
||||
const xml::Expr* GetExpr() const { return NULL; }
|
||||
|
||||
private:
|
||||
const counter_t counter_;
|
||||
};
|
||||
|
||||
class ExprMetric : public Metric {
|
||||
public:
|
||||
ExprMetric(const std::string& name, const counters_vec_t& counters, const xml::Expr* expr)
|
||||
: Metric(name), counters_(counters), expr_(expr) {}
|
||||
~ExprMetric() { delete expr_; }
|
||||
void GetCounters(counters_vec_t& vec) const {
|
||||
vec.insert(vec.end(), counters_.begin(), counters_.end());
|
||||
}
|
||||
const xml::Expr* GetExpr() const { return expr_; }
|
||||
|
||||
private:
|
||||
const counters_vec_t counters_;
|
||||
const xml::Expr* expr_;
|
||||
};
|
||||
|
||||
class MetricsDict {
|
||||
public:
|
||||
typedef std::map<std::string, const Metric*> cache_t;
|
||||
typedef cache_t::const_iterator const_iterator_t;
|
||||
typedef std::map<std::string, MetricsDict*> map_t;
|
||||
typedef std::mutex mutex_t;
|
||||
|
||||
class ExprCache : public xml::expr_cache_t {
|
||||
public:
|
||||
ExprCache(const cache_t* cache) : cache_(cache) {}
|
||||
bool Lookup(const std::string& name, std::string& result) const {
|
||||
bool ret = false;
|
||||
auto it = cache_->find(name);
|
||||
if (it != cache_->end()) {
|
||||
ret = true;
|
||||
const rocmtools::ExprMetric* expr_metric =
|
||||
dynamic_cast<const rocmtools::ExprMetric*>(it->second);
|
||||
if (expr_metric) result = expr_metric->GetExpr()->GetStr();
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
private:
|
||||
const cache_t* const cache_;
|
||||
};
|
||||
|
||||
static MetricsDict* Create(const Agent::AgentInfo* agent_info) {
|
||||
std::lock_guard<mutex_t> lck(mutex_);
|
||||
if (map_ == NULL) map_ = new map_t;
|
||||
std::string name = agent_info->getGfxip();
|
||||
auto ret = map_->insert({name, NULL});
|
||||
if (ret.second) ret.first->second = new MetricsDict(agent_info);
|
||||
return ret.first->second;
|
||||
}
|
||||
|
||||
static void Destroy() {
|
||||
if (map_ != NULL) {
|
||||
for (auto& entry : *map_) delete entry.second;
|
||||
delete map_;
|
||||
map_ = NULL;
|
||||
}
|
||||
}
|
||||
|
||||
const Metric* Get(const std::string& name) const {
|
||||
const Metric* metric = NULL;
|
||||
|
||||
auto it = cache_.find(name);
|
||||
if (it != cache_.end())
|
||||
metric = it->second;
|
||||
else {
|
||||
const std::size_t pos = name.find(':');
|
||||
if (pos != std::string::npos) {
|
||||
std::string block_name = name.substr(0, pos);
|
||||
const std::string event_str = name.substr(pos + 1);
|
||||
|
||||
uint32_t block_index = 0;
|
||||
bool indexed = false;
|
||||
const std::size_t pos1 = block_name.find('[');
|
||||
if (pos1 != std::string::npos) {
|
||||
const std::size_t pos2 = block_name.find(']');
|
||||
if (pos2 == std::string::npos)
|
||||
EXC_RAISING(HSA_STATUS_ERROR, "Malformed metric name '" << name << "'");
|
||||
block_name = name.substr(0, pos1);
|
||||
const std::string block_index_str = name.substr(pos1 + 1, pos2 - (pos1 + 1));
|
||||
block_index = atol(block_index_str.c_str());
|
||||
indexed = true;
|
||||
}
|
||||
|
||||
const hsa_ven_amd_aqlprofile_id_query_t query = Translate(agent_info_, block_name);
|
||||
const hsa_ven_amd_aqlprofile_block_name_t block_id =
|
||||
(hsa_ven_amd_aqlprofile_block_name_t)query.id;
|
||||
if ((query.instance_count > 1) && (indexed == false))
|
||||
EXC_RAISING(HSA_STATUS_ERROR, "Malformed indexed metric name '" << name << "'");
|
||||
const uint32_t event_id = atol(event_str.c_str());
|
||||
const counter_t counter = {name, {block_id, block_index, event_id}};
|
||||
metric = new BaseMetric(name, counter);
|
||||
}
|
||||
}
|
||||
|
||||
return metric;
|
||||
}
|
||||
|
||||
uint32_t Size() const { return cache_.size(); }
|
||||
const_iterator_t Begin() const { return cache_.begin(); }
|
||||
const_iterator_t End() const { return cache_.end(); }
|
||||
|
||||
std::string GetAgentName() const { return agent_name_; }
|
||||
|
||||
xml::Xml::nodes_t GetNodes() const {
|
||||
auto nodes_vec = GetNodes(agent_name_);
|
||||
auto global_vec = GetNodes("global");
|
||||
nodes_vec.insert(nodes_vec.end(), global_vec.begin(), global_vec.end());
|
||||
return nodes_vec;
|
||||
}
|
||||
|
||||
private:
|
||||
xml::Xml::nodes_t GetNodes(const std::string& scope) const {
|
||||
return (xml_ != NULL) ? xml_->GetNodes("top." + scope + ".metric") : xml::Xml::nodes_t();
|
||||
}
|
||||
|
||||
MetricsDict(const Agent::AgentInfo* agent_info) : xml_(NULL), agent_info_(agent_info) {
|
||||
const char* xml_name = getenv("ROCPROFILER_METRICS_PATH");
|
||||
if (xml_name != NULL) {
|
||||
xml_ = xml::Xml::Create(xml_name);
|
||||
if (xml_ == NULL)
|
||||
EXC_RAISING(HSA_STATUS_ERROR, "metrics .xml open error '" << xml_name << "'");
|
||||
xml_->AddConst("top.const.metric", "MAX_WAVE_SIZE", agent_info->getMaxQueueSize());
|
||||
xml_->AddConst("top.const.metric", "CU_NUM", agent_info->getCUCount());
|
||||
xml_->AddConst("top.const.metric", "SIMD_NUM",
|
||||
agent_info->getSimdCountPerCU() * agent_info->getCUCount());
|
||||
xml_->AddConst("top.const.metric", "SE_NUM", agent_info->getShaderEngineCount());
|
||||
ImportMetrics(agent_info, "const");
|
||||
agent_name_ = agent_info->getName();
|
||||
if (std::string("gfx906") == agent_name_ || std::string("gfx908") == agent_name_ ||
|
||||
std::string("gfx90a") == agent_name_ || std::string("gfx1032") == agent_name_ ||
|
||||
std::string("gfx1031") == agent_name_ || std::string("gfx1030") == agent_name_) {
|
||||
ImportMetrics(agent_info, agent_name_);
|
||||
} else {
|
||||
agent_name_ = agent_info->getGfxip();
|
||||
ImportMetrics(agent_info, agent_name_);
|
||||
}
|
||||
ImportMetrics(agent_info, "global");
|
||||
}
|
||||
}
|
||||
|
||||
~MetricsDict() {
|
||||
xml::Xml::Destroy(xml_);
|
||||
for (auto& entry : cache_) delete entry.second;
|
||||
}
|
||||
|
||||
static hsa_ven_amd_aqlprofile_id_query_t Translate(const Agent::AgentInfo* agent_info,
|
||||
const std::string& block_name) {
|
||||
hsa_ven_amd_aqlprofile_profile_t profile{};
|
||||
profile.agent = hsa_agent_t{agent_info->getHandle()};
|
||||
hsa_ven_amd_aqlprofile_id_query_t query = {block_name.c_str(), 0, 0};
|
||||
hsa_status_t status =
|
||||
hsa_ven_amd_aqlprofile_get_info(&profile, HSA_VEN_AMD_AQLPROFILE_INFO_BLOCK_ID, &query);
|
||||
if (status != HSA_STATUS_SUCCESS)
|
||||
AQL_EXC_RAISING(HSA_STATUS_ERROR, "ImportMetrics: bad block name '" << block_name << "'");
|
||||
return query;
|
||||
}
|
||||
|
||||
void ImportMetrics(const Agent::AgentInfo* agent_info, const std::string& scope) {
|
||||
auto arr = xml_->GetNodes("top." + scope + ".metric");
|
||||
xml::Xml::node_list_t metrics_list(arr.begin(), arr.end());
|
||||
uint32_t metrics_number = metrics_list.size();
|
||||
bool do_lookup = true;
|
||||
if (!metrics_list.empty()) {
|
||||
uint32_t it_number = metrics_number;
|
||||
auto it = metrics_list.begin();
|
||||
auto end = metrics_list.end();
|
||||
while (it != end) {
|
||||
auto node = *it;
|
||||
const std::string name = node->opts["name"];
|
||||
const std::string expr_str = node->opts["expr"];
|
||||
std::string descr = node->opts["descr"];
|
||||
if (descr.empty()) descr = (expr_str.empty()) ? name : expr_str;
|
||||
|
||||
if (expr_str.empty()) {
|
||||
const std::string block_name = node->opts["block"];
|
||||
const std::string event_str = node->opts["event"];
|
||||
const uint32_t event_id = atol(event_str.c_str());
|
||||
|
||||
const hsa_ven_amd_aqlprofile_id_query_t query = Translate(agent_info, block_name);
|
||||
const hsa_ven_amd_aqlprofile_block_name_t block_id =
|
||||
(hsa_ven_amd_aqlprofile_block_name_t)query.id;
|
||||
if (query.instance_count > 1) {
|
||||
for (unsigned block_index = 0; block_index < query.instance_count; ++block_index) {
|
||||
std::ostringstream full_name;
|
||||
full_name << name << '[' << block_index << ']';
|
||||
std::ostringstream block_insance;
|
||||
block_insance << block_name << "[" << block_index << "]";
|
||||
std::ostringstream alias;
|
||||
alias << block_insance.str() << ":" << event_str;
|
||||
const counter_t counter = {full_name.str(), {block_id, block_index, event_id}};
|
||||
AddMetric(full_name.str(), alias.str(), counter);
|
||||
}
|
||||
} else {
|
||||
const std::string alias = block_name + ":" + event_str;
|
||||
const counter_t counter = {name, {block_id, 0, event_id}};
|
||||
AddMetric(name, alias, counter);
|
||||
}
|
||||
} else {
|
||||
xml::Expr* expr_obj = NULL;
|
||||
try {
|
||||
expr_obj = new xml::Expr(expr_str, new ExprCache(&cache_));
|
||||
} catch (const xml::exception_t& exc) {
|
||||
if (do_lookup)
|
||||
metrics_list.push_back(node);
|
||||
else
|
||||
throw(exc);
|
||||
}
|
||||
if (expr_obj) {
|
||||
#if 0
|
||||
std::cout << "# " << descr << std::endl;
|
||||
std::cout << name << "=" << expr_obj->String() << "\n" << std::endl;
|
||||
#endif
|
||||
counters_vec_t counters_vec;
|
||||
for (const std::string& var : expr_obj->GetVars()) {
|
||||
auto it = cache_.find(var);
|
||||
if (it == cache_.end()) {
|
||||
EXC_RAISING(HSA_STATUS_ERROR,
|
||||
"Bad metric '" << name << "', var '" << var << "' is not found");
|
||||
}
|
||||
it->second->GetCounters(counters_vec);
|
||||
}
|
||||
AddMetric(name, counters_vec, expr_obj);
|
||||
}
|
||||
}
|
||||
|
||||
auto cur = it++;
|
||||
metrics_list.erase(cur);
|
||||
if (--it_number == 0) {
|
||||
it_number = metrics_list.size();
|
||||
if (it_number < metrics_number) {
|
||||
metrics_number = it_number;
|
||||
} else if (it_number == metrics_number) {
|
||||
do_lookup = false;
|
||||
} else {
|
||||
EXC_RAISING(HSA_STATUS_ERROR, "Internal error");
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
const Metric* AddMetric(const std::string& name, const std::string& /*alias*/,
|
||||
const counter_t& counter) {
|
||||
const Metric* metric = NULL;
|
||||
const auto ret = cache_.insert({name, NULL});
|
||||
if (ret.second) {
|
||||
metric = new BaseMetric(name, counter);
|
||||
ret.first->second = metric;
|
||||
} else
|
||||
EXC_RAISING(HSA_STATUS_ERROR, "metric redefined '" << name << "'");
|
||||
return metric;
|
||||
}
|
||||
|
||||
const Metric* AddMetric(const std::string& name, const counters_vec_t& counters_vec,
|
||||
const xml::Expr* expr_obj) {
|
||||
const Metric* metric = NULL;
|
||||
const auto ret = cache_.insert({name, NULL});
|
||||
if (ret.second) {
|
||||
metric = new ExprMetric(name, counters_vec, expr_obj);
|
||||
ret.first->second = metric;
|
||||
} else
|
||||
EXC_RAISING(HSA_STATUS_ERROR, "expr-metric redefined '" << name << "'");
|
||||
return metric;
|
||||
}
|
||||
|
||||
void Print() {
|
||||
for (auto& v : cache_) {
|
||||
const Metric* metric = v.second;
|
||||
counters_vec_t counters_vec;
|
||||
printf("> Metric '%s'\n", metric->GetName().c_str());
|
||||
metric->GetCounters(counters_vec);
|
||||
for (auto c : counters_vec) {
|
||||
printf(" counter %s, b(%u), i (%u), e (%u)\n", c->name.c_str(), c->event.block_name,
|
||||
c->event.block_index, c->event.counter_id);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
xml::Xml* xml_;
|
||||
const Agent::AgentInfo* agent_info_;
|
||||
std::string agent_name_;
|
||||
cache_t cache_;
|
||||
|
||||
static map_t* map_;
|
||||
static mutex_t mutex_;
|
||||
};
|
||||
|
||||
} // namespace rocmtools
|
||||
|
||||
#endif // SRC_CORE_COUNTERS_METRICS_METRICS_H_
|
||||
@@ -0,0 +1,51 @@
|
||||
/******************************************************************************
|
||||
Copyright (c) 2018 Advanced Micro Devices, Inc. All rights reserved.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef SRC_CORE_TYPES_H_
|
||||
#define SRC_CORE_TYPES_H_
|
||||
|
||||
#include <iostream>
|
||||
|
||||
#include <hsa/hsa_ven_amd_aqlprofile.h>
|
||||
|
||||
namespace rocmtools {
|
||||
typedef hsa_ven_amd_aqlprofile_pfn_t pfn_t;
|
||||
typedef hsa_ven_amd_aqlprofile_event_t event_t;
|
||||
typedef hsa_ven_amd_aqlprofile_parameter_t parameter_t;
|
||||
typedef hsa_ven_amd_aqlprofile_profile_t profile_t;
|
||||
typedef hsa_ext_amd_aql_pm4_packet_t packet_t;
|
||||
typedef uint32_t packet_word_t;
|
||||
typedef uint64_t timestamp_t;
|
||||
|
||||
inline std::ostream& operator<<(std::ostream& out, const event_t& event) {
|
||||
out << "[block_name(" << event.block_name << "). block_index(" << event.block_index
|
||||
<< "). counter_id(" << event.counter_id << ")]";
|
||||
return out;
|
||||
}
|
||||
inline std::ostream& operator<<(std::ostream& out, const parameter_t& parameter) {
|
||||
out << "[parameter_name(" << parameter.parameter_name << "). value(" << parameter.value << ")]";
|
||||
return out;
|
||||
}
|
||||
|
||||
} // namespace rocmtools
|
||||
|
||||
#endif // SRC_CORE_TYPES_H_
|
||||
@@ -0,0 +1,512 @@
|
||||
/******************************************************************************
|
||||
Copyright (c) 2018 Advanced Micro Devices, Inc. All rights reserved.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef SRC_CORE_COUNTERS_METRICS_XML_XML_H_
|
||||
#define SRC_CORE_COUNTERS_METRICS_XML_XML_H_
|
||||
|
||||
#include <fcntl.h>
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
#include <sys/stat.h>
|
||||
#include <sys/types.h>
|
||||
#include <unistd.h>
|
||||
|
||||
#include <fstream>
|
||||
#include <iostream>
|
||||
#include <map>
|
||||
#include <string>
|
||||
#include <vector>
|
||||
|
||||
namespace xml {
|
||||
|
||||
class Xml {
|
||||
public:
|
||||
typedef std::vector<char> token_t;
|
||||
|
||||
struct level_t;
|
||||
typedef std::vector<level_t*> node_vect_t;
|
||||
typedef std::list<level_t*> node_list_t;
|
||||
|
||||
typedef node_vect_t nodes_t;
|
||||
typedef std::map<std::string, std::string> opts_t;
|
||||
struct level_t {
|
||||
std::string tag;
|
||||
nodes_t nodes;
|
||||
opts_t opts;
|
||||
const level_t* copy;
|
||||
};
|
||||
typedef std::vector<level_t*> nodes_vec_t;
|
||||
typedef std::map<std::string, nodes_vec_t> map_t;
|
||||
|
||||
enum { DECL_STATE, BODY_STATE };
|
||||
|
||||
static Xml* Create(const std::string& file_name, const Xml* obj = NULL) {
|
||||
Xml* xml = new Xml(file_name, obj);
|
||||
if (xml != NULL) {
|
||||
if (xml->Init() == false) {
|
||||
delete xml;
|
||||
xml = NULL;
|
||||
} else {
|
||||
const std::size_t pos = file_name.rfind('/');
|
||||
const std::string path = (pos != std::string::npos) ? file_name.substr(0, pos + 1) : "";
|
||||
|
||||
xml->PreProcess();
|
||||
nodes_t incl_nodes;
|
||||
for (auto* node : xml->GetNodes("top.include")) {
|
||||
if (node->opts.find("touch") == node->opts.end()) {
|
||||
node->opts["touch"] = "";
|
||||
incl_nodes.push_back(node);
|
||||
}
|
||||
}
|
||||
for (auto* incl : incl_nodes) {
|
||||
const std::string& incl_name = path + incl->opts["file"];
|
||||
Xml* ixml = Create(incl_name, xml);
|
||||
if (ixml == NULL) {
|
||||
delete xml;
|
||||
xml = NULL;
|
||||
break;
|
||||
} else {
|
||||
delete ixml;
|
||||
}
|
||||
}
|
||||
if (xml) {
|
||||
xml->Process();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return xml;
|
||||
}
|
||||
|
||||
static void Destroy(Xml* xml) { delete xml; }
|
||||
|
||||
std::string GetName() { return file_name_; }
|
||||
|
||||
void AddExpr(const std::string& full_tag, const std::string& name, const std::string& expr) {
|
||||
const std::size_t pos = full_tag.rfind('.');
|
||||
const std::size_t pos1 = (pos == std::string::npos) ? 0 : pos + 1;
|
||||
const std::string level_tag = full_tag.substr(pos1);
|
||||
level_t* level = new level_t;
|
||||
(*map_)[full_tag].push_back(level);
|
||||
level->tag = level_tag;
|
||||
level->opts["name"] = name;
|
||||
level->opts["expr"] = expr;
|
||||
}
|
||||
|
||||
void AddConst(const std::string& full_tag, const std::string& name, const uint64_t& val) {
|
||||
std::ostringstream oss;
|
||||
oss << val;
|
||||
AddExpr(full_tag, name, oss.str());
|
||||
}
|
||||
|
||||
nodes_t GetNodes(const std::string& global_tag) { return (*map_)[global_tag]; }
|
||||
|
||||
template <class F> F ForEach(const F& f_i) {
|
||||
F f = f_i;
|
||||
if (map_) {
|
||||
for (auto& entry : *map_) {
|
||||
for (auto node : entry.second) {
|
||||
if (f.fun(entry.first, node) == false) break;
|
||||
}
|
||||
}
|
||||
}
|
||||
return f;
|
||||
}
|
||||
|
||||
template <class F> F ForEach(const F& f_i) const {
|
||||
F f = f_i;
|
||||
if (map_) {
|
||||
for (auto& entry : *map_) {
|
||||
for (auto node : entry.second) {
|
||||
if (f.fun(entry.first, node) == false) break;
|
||||
}
|
||||
}
|
||||
}
|
||||
return f;
|
||||
}
|
||||
|
||||
struct print_func {
|
||||
bool fun(const std::string& global_tag, level_t* node) {
|
||||
std::cout << global_tag << ":" << std::endl;
|
||||
for (auto& opt : node->opts) {
|
||||
std::cout << global_tag << "." << opt.first << " = " << opt.second << std::endl;
|
||||
}
|
||||
return true;
|
||||
}
|
||||
};
|
||||
|
||||
void Print() const {
|
||||
std::cout << "XML file '" << file_name_ << "':" << std::endl;
|
||||
ForEach(print_func());
|
||||
}
|
||||
|
||||
private:
|
||||
Xml(const std::string& file_name, const Xml* obj)
|
||||
: file_name_(file_name),
|
||||
file_line_(0),
|
||||
data_size_(0),
|
||||
index_(0),
|
||||
state_(BODY_STATE),
|
||||
comment_(false),
|
||||
included_(false),
|
||||
level_(NULL),
|
||||
map_(NULL) {
|
||||
if (obj != NULL) {
|
||||
map_ = obj->map_;
|
||||
level_ = obj->level_;
|
||||
included_ = true;
|
||||
}
|
||||
}
|
||||
|
||||
struct delete_func {
|
||||
bool fun(const std::string&, level_t* node) {
|
||||
delete node;
|
||||
return true;
|
||||
}
|
||||
};
|
||||
|
||||
~Xml() {
|
||||
if (included_ == false) {
|
||||
ForEach(delete_func());
|
||||
delete map_;
|
||||
}
|
||||
}
|
||||
|
||||
bool Init() {
|
||||
fd_ = open(file_name_.c_str(), O_RDONLY);
|
||||
if (fd_ == -1) {
|
||||
// perror((std::string("open XML file ") + file_name_).c_str());
|
||||
return false;
|
||||
}
|
||||
|
||||
if (map_ == NULL) {
|
||||
map_ = new map_t;
|
||||
if (map_ == NULL) return false;
|
||||
AddLevel("top");
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
void PreProcess() {
|
||||
uint32_t ind = 0;
|
||||
char buf[kBufSize];
|
||||
bool error = false;
|
||||
|
||||
while (1) {
|
||||
const uint32_t pos = lseek(fd_, 0, SEEK_CUR);
|
||||
uint32_t size = read(fd_, buf, kBufSize);
|
||||
if (size <= 0) break;
|
||||
buf[size - 1] = '\0';
|
||||
|
||||
if (strncmp(buf, "#include \"", 10) == 0) {
|
||||
for (ind = 0; (ind < size) && (buf[ind] != '\n'); ++ind) {
|
||||
}
|
||||
if (ind < size) {
|
||||
buf[ind] = '\0';
|
||||
size = ind;
|
||||
lseek(fd_, pos + ind + 1, SEEK_SET);
|
||||
}
|
||||
|
||||
for (ind = 10; (ind < size) && (buf[ind] != '"'); ++ind) {
|
||||
}
|
||||
if (ind == size) {
|
||||
error = true;
|
||||
break;
|
||||
}
|
||||
buf[ind] = '\0';
|
||||
|
||||
AddLevel("include");
|
||||
AddOption("file", &buf[10]);
|
||||
UpLevel();
|
||||
}
|
||||
}
|
||||
|
||||
if (error) {
|
||||
fprintf(stderr, "XML PreProcess failed, line '%s'\n", buf);
|
||||
abort();
|
||||
}
|
||||
|
||||
lseek(fd_, 0, SEEK_SET);
|
||||
}
|
||||
|
||||
void Process() {
|
||||
token_t remainder;
|
||||
|
||||
while (1) {
|
||||
token_t token = (remainder.size()) ? remainder : NextToken();
|
||||
remainder.clear();
|
||||
|
||||
// token_t token1 = token;
|
||||
// token1.push_back('\0');
|
||||
// std::cout << ">>> " << &token1[0] << std::endl;
|
||||
|
||||
// End of file
|
||||
if (token.size() == 0) break;
|
||||
|
||||
switch (state_) {
|
||||
case BODY_STATE:
|
||||
if (token[0] == '<') {
|
||||
bool node_begin = true;
|
||||
unsigned ind = 1;
|
||||
if (token[1] == '/') {
|
||||
node_begin = false;
|
||||
++ind;
|
||||
}
|
||||
|
||||
unsigned i = ind;
|
||||
while (i < token.size()) {
|
||||
if (token[i] == '>') break;
|
||||
++i;
|
||||
}
|
||||
for (unsigned j = i + 1; j < token.size(); ++j) remainder.push_back(token[j]);
|
||||
|
||||
if (i == token.size()) {
|
||||
if (node_begin)
|
||||
state_ = DECL_STATE;
|
||||
else
|
||||
BadFormat(token);
|
||||
token.push_back('\0');
|
||||
} else {
|
||||
token[i] = '\0';
|
||||
}
|
||||
|
||||
const char* tag = &token[ind];
|
||||
if (node_begin) {
|
||||
AddLevel(tag);
|
||||
} else {
|
||||
Inherit(GetOption("base"));
|
||||
|
||||
if (strncmp(CurrentLevel().c_str(), tag, strlen(tag)) != 0) {
|
||||
token.back() = '>';
|
||||
BadFormat(token);
|
||||
}
|
||||
UpLevel();
|
||||
}
|
||||
} else {
|
||||
BadFormat(token);
|
||||
}
|
||||
break;
|
||||
case DECL_STATE:
|
||||
if (token[0] == '>') {
|
||||
state_ = BODY_STATE;
|
||||
for (unsigned j = 1; j < token.size(); ++j) remainder.push_back(token[j]);
|
||||
continue;
|
||||
} else {
|
||||
token.push_back('\0');
|
||||
unsigned j = 0;
|
||||
for (j = 0; j < token.size(); ++j)
|
||||
if (token[j] == '=') break;
|
||||
if (j == token.size()) BadFormat(token);
|
||||
token[j] = '\0';
|
||||
const std::string key = &token[0];
|
||||
const std::string value = &token[j + 1];
|
||||
AddOption(key, value);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
std::cout << "XML parser error: wrong state: " << state_ << std::endl;
|
||||
abort();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
bool SpaceCheck() const {
|
||||
bool cond = ((buffer_[index_] == ' ') || (buffer_[index_] == '\t'));
|
||||
return cond;
|
||||
}
|
||||
|
||||
bool LineEndCheck() {
|
||||
bool found = false;
|
||||
if (buffer_[index_] == '\n') {
|
||||
buffer_[index_] = ' ';
|
||||
++file_line_;
|
||||
found = true;
|
||||
comment_ = false;
|
||||
} else if (comment_ || (buffer_[index_] == '#')) {
|
||||
found = true;
|
||||
comment_ = true;
|
||||
}
|
||||
return found;
|
||||
}
|
||||
|
||||
token_t NextToken() {
|
||||
token_t token;
|
||||
bool in_string = false;
|
||||
bool special_symb = false;
|
||||
|
||||
while (1) {
|
||||
if (data_size_ == 0) {
|
||||
data_size_ = read(fd_, buffer_, kBufSize);
|
||||
if (data_size_ <= 0) break;
|
||||
}
|
||||
|
||||
if (token.empty()) {
|
||||
while ((index_ < data_size_) && (SpaceCheck() || LineEndCheck())) {
|
||||
++index_;
|
||||
}
|
||||
}
|
||||
while ((index_ < data_size_) && (in_string || !(SpaceCheck() || LineEndCheck()))) {
|
||||
const char symb = buffer_[index_];
|
||||
bool skip_symb = false;
|
||||
|
||||
switch (symb) {
|
||||
case '\\':
|
||||
if (special_symb) {
|
||||
special_symb = false;
|
||||
} else {
|
||||
special_symb = true;
|
||||
skip_symb = true;
|
||||
}
|
||||
break;
|
||||
case '"':
|
||||
if (special_symb) {
|
||||
special_symb = false;
|
||||
} else {
|
||||
in_string = !in_string;
|
||||
if (!in_string) {
|
||||
buffer_[index_] = ' ';
|
||||
--index_;
|
||||
}
|
||||
skip_symb = true;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
if (!skip_symb) token.push_back(symb);
|
||||
++index_;
|
||||
}
|
||||
|
||||
if (index_ == data_size_) {
|
||||
index_ = 0;
|
||||
data_size_ = 0;
|
||||
} else {
|
||||
if (special_symb || in_string) BadFormat(token);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return token;
|
||||
}
|
||||
|
||||
void BadFormat(token_t token) {
|
||||
token.push_back('\0');
|
||||
std::cout << "Error: " << file_name_ << ", line " << file_line_ << ", bad XML token '"
|
||||
<< &token[0] << "'" << std::endl;
|
||||
abort();
|
||||
}
|
||||
|
||||
void AddLevel(const std::string& tag) {
|
||||
level_t* level = new level_t{};
|
||||
level->tag = tag;
|
||||
if (level_) {
|
||||
level_->nodes.push_back(level);
|
||||
stack_.push_back(level_);
|
||||
}
|
||||
level_ = level;
|
||||
|
||||
std::string global_tag = GlobalTag(tag);
|
||||
(*map_)[global_tag].push_back(level_);
|
||||
}
|
||||
|
||||
void UpLevel() {
|
||||
level_ = stack_.back();
|
||||
stack_.pop_back();
|
||||
}
|
||||
|
||||
void Copy(const level_t* from, level_t* to) {
|
||||
level_t* level = to;
|
||||
if (level == NULL) {
|
||||
AddLevel(from->tag);
|
||||
level = level_;
|
||||
}
|
||||
level->copy = from;
|
||||
level->opts = from->opts;
|
||||
|
||||
for (auto node : from->nodes) {
|
||||
bool found = false;
|
||||
const std::string name = GetOption("name", node);
|
||||
const std::string global_tag = GlobalTag(level->tag) + "." + node->tag;
|
||||
for (auto item : (*map_)[global_tag]) {
|
||||
if ((name == GetOption("name", item)) || (node == item->copy)) {
|
||||
found = true;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (found == false) Copy(node, NULL);
|
||||
}
|
||||
|
||||
if (to == NULL) UpLevel();
|
||||
}
|
||||
|
||||
void Inherit(const std::string& tag) {
|
||||
if (!tag.empty()) {
|
||||
const std::string global_tag = GlobalTag(tag);
|
||||
auto it = map_->find(global_tag);
|
||||
if (it == map_->end()) {
|
||||
fprintf(stderr, "Node \"%s\": Base not found \"%s\"\n", level_->tag.c_str(), tag.c_str());
|
||||
abort();
|
||||
}
|
||||
for (auto node : it->second) {
|
||||
Copy(node, level_);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
std::string CurrentLevel() const { return level_->tag; }
|
||||
|
||||
std::string GlobalTag(const std::string& tag) const {
|
||||
std::string global_tag;
|
||||
for (level_t* level : stack_) {
|
||||
global_tag += level->tag + ".";
|
||||
}
|
||||
global_tag += tag;
|
||||
return global_tag;
|
||||
}
|
||||
|
||||
void AddOption(const std::string& key, const std::string& value) { level_->opts[key] = value; }
|
||||
std::string GetOption(const std::string& key, const level_t* level = NULL) {
|
||||
level = (level != NULL) ? level : level_;
|
||||
auto it = level->opts.find(key);
|
||||
return (it != level->opts.end()) ? it->second : "";
|
||||
}
|
||||
|
||||
const std::string file_name_;
|
||||
unsigned file_line_;
|
||||
int fd_;
|
||||
|
||||
static const size_t kBufSize = 256;
|
||||
char buffer_[kBufSize];
|
||||
|
||||
unsigned data_size_;
|
||||
unsigned index_;
|
||||
unsigned state_;
|
||||
bool comment_;
|
||||
std::vector<level_t*> stack_;
|
||||
bool included_;
|
||||
level_t* level_;
|
||||
map_t* map_;
|
||||
};
|
||||
|
||||
} // namespace xml
|
||||
|
||||
#endif // SRC_CORE_COUNTERS_METRICS_XML_XML_H_
|
||||
Reference in new issue
Block a user