From 84a4f293f4cb9a1f7777b5d378ddb64a1fa1b876 Mon Sep 17 00:00:00 2001
From: "Andryeyev, German" <German.Andryeyev@amd.com>
Date: Wed, 30 Apr 2025 14:27:41 -0400
Subject: [PATCH] SWDEV-526836 - add PipelineStageBlt flag (#229)

CP sync requires PipelineStageBlt flag.
---
 rocclr/device/pal/palvirtual.hpp | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/rocclr/device/pal/palvirtual.hpp b/rocclr/device/pal/palvirtual.hpp
index 2d4a123296..7e16dea9ff 100644
--- a/rocclr/device/pal/palvirtual.hpp
+++ b/rocclr/device/pal/palvirtual.hpp
@@ -504,12 +504,17 @@ class VirtualGPU : public device::VirtualDevice {
     };
 
     if (type == BarrierType::KernelToCopy) {
+      barrier.dstGlobalStageMask = Pal::PipelineStageBlt;
       barrier.dstGlobalAccessMask = Pal::CoherCopy;
     } else if (type == BarrierType::CopyToKernel) {
+      barrier.srcGlobalStageMask = Pal::PipelineStageBlt;
       barrier.srcGlobalAccessMask  = Pal::CoherCopy;
     } else if (type == BarrierType::CopyToCopy) {
+      barrier.srcGlobalStageMask = barrier.dstGlobalStageMask = Pal::PipelineStageBlt;
       barrier.srcGlobalAccessMask = barrier.dstGlobalAccessMask = Pal::CoherCopy;
     } else if (type == BarrierType::FlushL2) {
+      barrier.srcGlobalStageMask |= Pal::PipelineStageBlt; 
+      barrier.dstGlobalStageMask |= Pal::PipelineStageBlt;
       barrier.srcGlobalAccessMask = barrier.dstGlobalAccessMask = Pal::CoherCopy | Pal::CoherCpu;
     }