diff --git a/projects/rocr-runtime/runtime/hsa-runtime/core/runtime/amd_blit_sdma.cpp b/projects/rocr-runtime/runtime/hsa-runtime/core/runtime/amd_blit_sdma.cpp
index 9a52948f1a..a75988c510 100644
--- a/projects/rocr-runtime/runtime/hsa-runtime/core/runtime/amd_blit_sdma.cpp
+++ b/projects/rocr-runtime/runtime/hsa-runtime/core/runtime/amd_blit_sdma.cpp
@@ -456,9 +456,12 @@ hsa_status_t BlitSdma<RingIndexTy, HwIndexMonotonic, SizeToCountOffset>::Initial
     return HSA_STATUS_ERROR;
   }
 
-  if (amd_gpu_agent.isa()->version() == core::Isa::Version(7, 0, 1) ||
-      amd_gpu_agent.isa()->GetMajorVersion() == 9) {
+  if (amd_gpu_agent.isa()->version() == core::Isa::Version(7, 0, 1)) {
     platform_atomic_support_ = false;
+  } else {
+    const core::Runtime::LinkInfo& link = core::Runtime::runtime_singleton_->GetLinkInfo(
+        amd_gpu_agent.node_id(), core::Runtime::runtime_singleton_->cpu_agents()[0]->node_id());
+    platform_atomic_support_ = link.info.atomic_support_64bit;
   }
 
   // Determine if sDMA microcode supports HDP flush command
diff --git a/projects/rocr-runtime/runtime/hsa-runtime/core/runtime/amd_gpu_agent.cpp b/projects/rocr-runtime/runtime/hsa-runtime/core/runtime/amd_gpu_agent.cpp
index 68d5ca5aea..6778359758 100644
--- a/projects/rocr-runtime/runtime/hsa-runtime/core/runtime/amd_gpu_agent.cpp
+++ b/projects/rocr-runtime/runtime/hsa-runtime/core/runtime/amd_gpu_agent.cpp
@@ -562,12 +562,16 @@ void GpuAgent::InitDma() {
 
   // Decide which engine to use for blits.
   auto blit_lambda = [this](bool h2d, lazy_ptr<core::Queue>& queue) {
-    std::string sdma_override = core::Runtime::runtime_singleton_->flag().enable_sdma();
-    bool use_sdma = (sdma_override.size() == 0) ? (isa_->GetMajorVersion() != 8) : (sdma_override == "1");
+    const std::string& sdma_override = core::Runtime::runtime_singleton_->flag().enable_sdma();
+    const core::Runtime::LinkInfo& link = core::Runtime::runtime_singleton_->GetLinkInfo(
+        node_id(), core::Runtime::runtime_singleton_->cpu_agents()[0]->node_id());
+
+    bool use_sdma = (isa_->GetMajorVersion() != 8) && link.info.atomic_support_64bit;
+    if (sdma_override.size() != 0) use_sdma = (sdma_override == "1");
 
     if (use_sdma && (HSA_PROFILE_BASE == profile_)) {
-        auto ret = CreateBlitSdma(h2d);
-        if (ret != nullptr) return ret;
+      auto ret = CreateBlitSdma(h2d);
+      if (ret != nullptr) return ret;
     }
 
     auto ret = CreateBlitKernel((*queue).get());
diff --git a/projects/rocr-runtime/runtime/hsa-runtime/core/runtime/amd_topology.cpp b/projects/rocr-runtime/runtime/hsa-runtime/core/runtime/amd_topology.cpp
index 69e5f811e4..3f60d6034c 100644
--- a/projects/rocr-runtime/runtime/hsa-runtime/core/runtime/amd_topology.cpp
+++ b/projects/rocr-runtime/runtime/hsa-runtime/core/runtime/amd_topology.cpp
@@ -97,6 +97,34 @@ void RegisterLinkInfo(uint32_t node_id, uint32_t num_link) {
     // Populate link info with thunk property.
     hsa_amd_memory_pool_link_info_t link_info = {0};
 
+    switch (io_link.IoLinkType) {
+      case HSA_IOLINKTYPE_HYPERTRANSPORT:
+        link_info.link_type = HSA_AMD_LINK_INFO_TYPE_HYPERTRANSPORT;
+        link_info.atomic_support_32bit = true;
+        link_info.atomic_support_64bit = true;
+        link_info.coherent_support = true;
+        break;
+      case HSA_IOLINKTYPE_PCIEXPRESS:
+        link_info.link_type = HSA_AMD_LINK_INFO_TYPE_PCIE;
+        link_info.atomic_support_32bit = true;
+        link_info.atomic_support_64bit = true;
+        link_info.coherent_support = true;
+        break;
+      case HSA_IOLINK_TYPE_QPI_1_1:
+        link_info.link_type = HSA_AMD_LINK_INFO_TYPE_QPI;
+        link_info.atomic_support_32bit = true;
+        link_info.atomic_support_64bit = true;
+        link_info.coherent_support = true;
+        break;
+      case HSA_IOLINK_TYPE_INFINIBAND:
+        link_info.link_type = HSA_AMD_LINK_INFO_TYPE_INFINBAND;
+        debug_print("IOLINK is missing atomic and coherency defaults.\n");
+        break;
+      default:
+        debug_print("Unrecognized IOLINK type.\n");
+        break;
+    }
+
     if (io_link.Flags.ui32.Override == 1) {
       if (io_link.Flags.ui32.NoPeerToPeerDMA == 1) {
         // Ignore this link since peer to peer is not allowed.
@@ -105,26 +133,6 @@ void RegisterLinkInfo(uint32_t node_id, uint32_t num_link) {
       link_info.atomic_support_32bit = (io_link.Flags.ui32.NoAtomics32bit == 0);
       link_info.atomic_support_64bit = (io_link.Flags.ui32.NoAtomics64bit == 0);
       link_info.coherent_support = (io_link.Flags.ui32.NonCoherent == 0);
-    } else {
-      // TODO: decipher HSA_IOLINKTYPE to fill out the atomic
-      // and coherent information.
-    }
-
-    switch (io_link.IoLinkType) {
-      case HSA_IOLINKTYPE_HYPERTRANSPORT:
-        link_info.link_type = HSA_AMD_LINK_INFO_TYPE_HYPERTRANSPORT;
-        break;
-      case HSA_IOLINKTYPE_PCIEXPRESS:
-        link_info.link_type = HSA_AMD_LINK_INFO_TYPE_PCIE;
-        break;
-      case HSA_IOLINK_TYPE_QPI_1_1:
-        link_info.link_type = HSA_AMD_LINK_INFO_TYPE_QPI;
-        break;
-      case HSA_IOLINK_TYPE_INFINIBAND:
-        link_info.link_type = HSA_AMD_LINK_INFO_TYPE_INFINBAND;
-        break;
-      default:
-        break;
     }
 
     link_info.max_bandwidth = io_link.MaximumBandwidth;