SWDEV-384557 - Fix engine status query
- Maintain a map of SDMA engine# to stream allocated following a greedy
approach
- Anything past that will query SDMA engine status always and go with a
SDMA or Blit copy path
Change-Id: Ibfaed7f951ab84d80cb0430596a4d11b5aec9202
[ROCm/clr commit: 5865c642d4]
Αυτή η υποβολή περιλαμβάνεται σε:
Saleel Kudchadker
υποβλήθηκε από
Rahul Garg
Rahul Garg
γονέας
74405e021d
υποβολή
8ae30e036d
@@ -240,12 +240,12 @@ Device::~Device() {
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hsa_queue_t* queue = qIter->first;
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auto& qInfo = qIter->second;
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if (qInfo.hostcallBuffer_) {
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ClPrint(amd::LOG_INFO, amd::LOG_QUEUE, "deleting hostcall buffer %p for hardware queue %p",
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ClPrint(amd::LOG_INFO, amd::LOG_QUEUE, "Deleting hostcall buffer %p for hardware queue %p",
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qInfo.hostcallBuffer_, qIter->first);
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disableHostcalls(qInfo.hostcallBuffer_);
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context().svmFree(qInfo.hostcallBuffer_);
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}
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ClPrint(amd::LOG_INFO, amd::LOG_QUEUE, "deleting hardware queue %p with refCount 0", queue);
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ClPrint(amd::LOG_INFO, amd::LOG_QUEUE, "Deleting hardware queue %p with refCount 0", queue);
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qIter = it.erase(qIter);
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hsa_queue_destroy(queue);
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}
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@@ -1183,6 +1183,17 @@ bool Device::populateOCLDeviceConstants() {
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return false;
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}
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if (HSA_STATUS_SUCCESS !=
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hsa_agent_get_info(bkendDevice_,
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static_cast<hsa_agent_info_t>(HSA_AMD_AGENT_INFO_NUM_SDMA_ENG),
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&info_.numSDMAengines_)) {
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return false;
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}
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for (uint32_t i = 0; i < info_.numSDMAengines_; i++) {
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engineAssignMap_[1 << i] = 0;
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}
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setupCpuAgent();
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checkAtomicSupport();
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@@ -1200,7 +1211,8 @@ bool Device::populateOCLDeviceConstants() {
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hsa_status_t err;
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// Can another GPU (agent) have access to the current GPU memory pool (gpuvm_segment_)?
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hsa_amd_memory_pool_access_t access;
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err = hsa_amd_agent_memory_pool_get_info(agent, gpuvm_segment_, HSA_AMD_AGENT_MEMORY_POOL_INFO_ACCESS, &access);
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err = hsa_amd_agent_memory_pool_get_info(agent, gpuvm_segment_,
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HSA_AMD_AGENT_MEMORY_POOL_INFO_ACCESS, &access);
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if (err != HSA_STATUS_SUCCESS) {
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continue;
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}
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@@ -1214,7 +1226,7 @@ bool Device::populateOCLDeviceConstants() {
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}
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}
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/* Keep track of all P2P Agents in a Array including current device handle for IPC */
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// Keep track of all P2P Agents in a Array including current device handle for IPC
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p2p_agents_list_ = new hsa_agent_t[1 + p2p_agents_.size()];
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p2p_agents_list_[0] = getBackendDevice();
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for (size_t agent_idx = 0; agent_idx < p2p_agents_.size(); ++agent_idx) {
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@@ -1229,6 +1241,20 @@ bool Device::populateOCLDeviceConstants() {
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}
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assert(group_segment_size > 0);
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// Find SDMA read mask
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if (HSA_STATUS_SUCCESS != hsa_amd_memory_copy_engine_status(getCpuAgent(), getBackendDevice(),
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&maxSdmaReadMask)) {
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return false;
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}
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assert(maxSdmaReadMask > 0 && "No SDMA engines available for Read");
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// Find SDMA write mask
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if (HSA_STATUS_SUCCESS != hsa_amd_memory_copy_engine_status(getBackendDevice(), getCpuAgent(),
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&maxSdmaWriteMask)) {
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return false;
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}
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assert(maxSdmaWriteMask > 0 && "No SDMA engines available for Write");
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info_.localMemSizePerCU_ = group_segment_size;
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info_.localMemSize_ = group_segment_size;
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@@ -1631,7 +1657,7 @@ bool Device::populateOCLDeviceConstants() {
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LogError("HSA_AMD_AGENT_INFO_SVM_DIRECT_HOST_ACCESS query failed.");
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}
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ClPrint(amd::LOG_INFO, amd::LOG_INIT, "HMM support: %d, xnack: %d, direct host access: %d\n",
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ClPrint(amd::LOG_INFO, amd::LOG_INIT, "HMM support: %d, xnack: %d, direct host access: %d",
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info_.hmmSupported_, info_.hmmCpuMemoryAccessible_, info_.hmmDirectHostAccess_);
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info_.globalCUMask_ = {};
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@@ -2185,7 +2211,7 @@ bool Device::IpcCreate(void* dev_ptr, size_t* mem_size, void* handle, size_t* me
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amd::Memory* amd_mem_obj = amd::MemObjMap::FindMemObj(dev_ptr);
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if (amd_mem_obj == nullptr) {
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DevLogPrintfError("Cannot retrieve amd_mem_obj for dev_ptr: 0x%x \n", dev_ptr);
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DevLogPrintfError("Cannot retrieve amd_mem_obj for dev_ptr: 0x%x", dev_ptr);
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return false;
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}
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@@ -2788,7 +2814,7 @@ hsa_queue_t* Device::getQueueFromPool(const uint qIndex) {
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for (auto it = queuePool_[qIndex].begin(); it != queuePool_[qIndex].end(); it++) {
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if (it->second.refCount == 0) {
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it->second.refCount++;
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ClPrint(amd::LOG_INFO, amd::LOG_QUEUE, "selected queue refCount: %p (%d)\n", it->first,
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ClPrint(amd::LOG_INFO, amd::LOG_QUEUE, "selected queue refCount: %p (%d)", it->first,
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it->second.refCount);
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return it->first;
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}
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@@ -2930,7 +2956,7 @@ hsa_queue_t* Device::acquireQueue(uint32_t queue_size_hint, bool coop_queue,
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for (int i = mask.size() - 1; i >= 0; i--) {
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ss << mask[i];
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}
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ClPrint(amd::LOG_INFO, amd::LOG_QUEUE, "setting CU mask 0x%s for hardware queue %p",
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ClPrint(amd::LOG_INFO, amd::LOG_QUEUE, "Setting CU mask 0x%s for hardware queue %p",
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ss.str().c_str(), queue);
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hsa_status_t status = hsa_amd_queue_cu_set_mask(queue, mask.size() * 32, mask.data());
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@@ -2960,7 +2986,7 @@ hsa_queue_t* Device::acquireQueue(uint32_t queue_size_hint, bool coop_queue,
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assert(result.second && "QueueInfo already exists");
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auto &qInfo = result.first->second;
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qInfo.refCount = 1;
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ClPrint(amd::LOG_INFO, amd::LOG_QUEUE, "acquireQueue refCount: %p (%d)\n", result.first->first,
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ClPrint(amd::LOG_INFO, amd::LOG_QUEUE, "acquireQueue refCount: %p (%d)", result.first->first,
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result.first->second.refCount);
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return queue;
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}
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@@ -2972,7 +2998,7 @@ void Device::releaseQueue(hsa_queue_t* queue, const std::vector<uint32_t>& cuMas
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auto &qInfo = qIter->second;
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assert(qInfo.refCount > 0);
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qInfo.refCount--;
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ClPrint(amd::LOG_INFO, amd::LOG_QUEUE, "releaseQueue refCount:%p (%d)\n", qIter->first,
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ClPrint(amd::LOG_INFO, amd::LOG_QUEUE, "releaseQueue refCount:%p (%d)", qIter->first,
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qIter->second.refCount);
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}
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}
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@@ -3292,6 +3318,45 @@ void Device::HiddenHeapAlloc(const VirtualGPU& gpu) {
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std::call_once(heap_initialized_, HeapAllocZeroOut);
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}
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// ================================================================================================
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uint32_t Device::fetchSDMAMask(const device::BlitManager* handle, bool readEngine) const {
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uint32_t engine = 0;
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{
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amd::ScopedLock lock(vgpusAccess());
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for (auto it = engineAssignMap_.rbegin(); it != engineAssignMap_.rend(); ++it) {
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// If blitManager handle is in the map return the engine ID else
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// add to the map
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if (it->second == handle) {
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engine = it->first;
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break;
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} else if (it->second == 0) {
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it->second = handle;
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engine = it->first;
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break;
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}
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}
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}
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uint32_t mask = (readEngine ? maxSdmaReadMask : maxSdmaWriteMask) & engine;
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if (engine != 0 && mask == 0 ) {
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return kSkipQueryStatus;
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} else {
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return mask;
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}
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}
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// ================================================================================================
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void Device::resetSDMAMask(const device::BlitManager* handle) const {
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amd::ScopedLock lock(vgpusAccess());
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for (auto& it : engineAssignMap_) {
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if (it.second == handle) {
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it.second = 0;
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break;
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}
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}
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}
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// ================================================================================================
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ProfilingSignal::~ProfilingSignal() {
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if (signal_.handle != 0) {
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