2.17.1-1
Add new NVLS algorithm for allreduce using NVLink SHARP (intra-node only).
Add new config options: cgaClusterSize, minCTAs, maxCTAs, netName.
Enable LL128 when we use PXN to close rings.
NVTX3 includes update.
Fix crash when one CollNet (SHARP) rail fails to initialize.
[ROCm/rccl commit: 5d3ab08b69]
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@@ -53,7 +53,8 @@ struct ncclDevRedOpFull {
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DECL4(func, RING, devredop, type, undef) \
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DECL4(func, TREE, devredop, type, undef) \
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DECL4(func, COLLNET_DIRECT, devredop, type, undef) \
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DECL4(func, COLLNET_CHAIN, devredop, type, undef)
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DECL4(func, COLLNET_CHAIN, devredop, type, undef) \
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DECL4(func, NVLS, devredop, type, undef)
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#if defined(__CUDA_BF16_TYPES_EXIST__)
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#define DECL2(func, devredop, undefForFloat) \
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@@ -121,4 +122,13 @@ extern __device__ void NCCL_ONERANK_REDUCE_NAME(PreMulSum, double)();
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#define REDUCE_CHUNKSTEPS 1
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#define NCCL_MAX_SLICE_PER_CHUNK 2 // max value for CHUNKSTEPS/SLICESTEPS, must accord with above
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// We can't use the enum identifiers like ncclSum, ncclFloat, etc since this
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// macro will be used in preprocessor conditionals where enums have no meaning.
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#define NCCL_NVLS_SUPPORTS(/*ncclDataType_t*/ type, /*ncclDevRedOp_t*/ red) \
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(((type==2 || type==3) && (red==0 || red==2 || red==3)) || \
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((type==4 || type==5) && (red==0 || red==2 || red==3)) || \
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((type==6 || type==9) && (red==0 || red==2 || red==3)) || \
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(type==7 && red==0) || \
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(type==8 && red==0))
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#endif
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