diff --git a/projects/rocprofiler-compute/tests/test_analyze_workloads.py b/projects/rocprofiler-compute/tests/test_analyze_workloads.py
index 20e5ecc1bd..29af0d97f1 100644
--- a/projects/rocprofiler-compute/tests/test_analyze_workloads.py
+++ b/projects/rocprofiler-compute/tests/test_analyze_workloads.py
@@ -256,7 +256,7 @@ def test_no_roof_mixbench1_mi200():
         ):
             omniperf.main()
     assert e.type == SystemExit
-    assert e.value.code == 0
+    assert e.value.code == 1
 
 
 def test_analyze_no_roof_TA_mi100():
@@ -333,7 +333,7 @@ def test_analyze_K_str_inv3_mi100():
         ):
             omniperf.main()
     assert e.type == SystemExit
-    assert e.value.code == 0
+    assert e.value.code == 1
 
 
 def test_K_str_inv3_mi200():
@@ -344,7 +344,7 @@ def test_K_str_inv3_mi200():
         ):
             omniperf.main()
     assert e.type == SystemExit
-    assert e.value.code == 0
+    assert e.value.code == 1
 
 
 def test_analyze_LDS_mi100():
@@ -654,7 +654,7 @@ def test_analyze_no_roof_D_int_inv2_mi100():
         ):
             omniperf.main()
     assert e.type == SystemExit
-    assert e.value.code == 0
+    assert e.value.code == 1
 
 
 def test_no_roof_D_int_inv2_mi200():
@@ -665,7 +665,7 @@ def test_no_roof_D_int_inv2_mi200():
         ):
             omniperf.main()
     assert e.type == SystemExit
-    assert e.value.code == 0
+    assert e.value.code == 1
 
 
 def test_analyze_TD_mi100():
@@ -745,7 +745,7 @@ def test_no_roof_mixbench2_mi200():
         ):
             omniperf.main()
     assert e.type == SystemExit
-    assert e.value.code == 0
+    assert e.value.code == 1
 
 
 def test_roof_only_SPI_mi200():
@@ -789,7 +789,7 @@ def test_analyze_K_str_inv1_mi100():
         ):
             omniperf.main()
     assert e.type == SystemExit
-    assert e.value.code == 0
+    assert e.value.code == 1
 
 
 def test_K_str_inv1_mi200():
@@ -800,7 +800,7 @@ def test_K_str_inv1_mi200():
         ):
             omniperf.main()
     assert e.type == SystemExit
-    assert e.value.code == 0
+    assert e.value.code == 1
 
 
 def test_roof_only_TA_mi200():
@@ -1037,7 +1037,7 @@ def test_analyze_K_int_inv2_mi100():
         ):
             omniperf.main()
     assert e.type == SystemExit
-    assert e.value.code == 0
+    assert e.value.code == 1
 
 
 def test_K_int_inv2_mi200():
@@ -1048,7 +1048,7 @@ def test_K_int_inv2_mi200():
         ):
             omniperf.main()
     assert e.type == SystemExit
-    assert e.value.code == 0
+    assert e.value.code == 1
 
 
 def test_roof_only_TCP_mi200():
@@ -1086,7 +1086,7 @@ def test_analyze_D_int_inv2_mi100():
         ):
             omniperf.main()
     assert e.type == SystemExit
-    assert e.value.code == 0
+    assert e.value.code == 1
 
 
 def test_D_int_inv2_mi200():
@@ -1097,7 +1097,7 @@ def test_D_int_inv2_mi200():
         ):
             omniperf.main()
     assert e.type == SystemExit
-    assert e.value.code == 0
+    assert e.value.code == 1
 
 
 def test_roof_only_Axes3_mi200():
@@ -1263,7 +1263,7 @@ def test_analyze_no_roof_K_int_inv1_mi100():
         ):
             omniperf.main()
     assert e.type == SystemExit
-    assert e.value.code == 0
+    assert e.value.code == 1
 
 
 def test_no_roof_K_int_inv1_mi200():
@@ -1274,7 +1274,7 @@ def test_no_roof_K_int_inv1_mi200():
         ):
             omniperf.main()
     assert e.type == SystemExit
-    assert e.value.code == 0
+    assert e.value.code == 1
 
 
 def test_analyze_no_roof_Axes1_mi100():
@@ -1365,7 +1365,7 @@ def test_analyze_K_str_inv2_mi100():
         ):
             omniperf.main()
     assert e.type == SystemExit
-    assert e.value.code == 0
+    assert e.value.code == 1
 
 
 def test_K_str_inv2_mi200():
@@ -1376,7 +1376,7 @@ def test_K_str_inv2_mi200():
         ):
             omniperf.main()
     assert e.type == SystemExit
-    assert e.value.code == 0
+    assert e.value.code == 1
 
 
 def test_analyze_CPC_mi100():
@@ -1428,7 +1428,7 @@ def test_roof_only_mixbench2_mi200():
         ):
             omniperf.main()
     assert e.type == SystemExit
-    assert e.value.code == 0
+    assert e.value.code == 1
 
 
 def test_analyze_Axes4_mi100():
@@ -1572,7 +1572,7 @@ def test_analyze_no_roof_K_str_inv3_mi100():
         ):
             omniperf.main()
     assert e.type == SystemExit
-    assert e.value.code == 0
+    assert e.value.code == 1
 
 
 def test_no_roof_K_str_inv3_mi200():
@@ -1583,7 +1583,7 @@ def test_no_roof_K_str_inv3_mi200():
         ):
             omniperf.main()
     assert e.type == SystemExit
-    assert e.value.code == 0
+    assert e.value.code == 1
 
 
 def test_analyze_no_roof_K_str_inv2_mi100():
@@ -1594,7 +1594,7 @@ def test_analyze_no_roof_K_str_inv2_mi100():
         ):
             omniperf.main()
     assert e.type == SystemExit
-    assert e.value.code == 0
+    assert e.value.code == 1
 
 
 def test_no_roof_K_str_inv2_mi200():
@@ -1605,7 +1605,7 @@ def test_no_roof_K_str_inv2_mi200():
         ):
             omniperf.main()
     assert e.type == SystemExit
-    assert e.value.code == 0
+    assert e.value.code == 1
 
 
 def test_analyze_D_str_inv2_mi100():
@@ -1679,7 +1679,7 @@ def test_analyze_CMD_INV_mi100():
         ):
             omniperf.main()
     assert e.type == SystemExit
-    assert e.value.code == 0
+    assert e.value.code == 1
 
 
 def test_analyze_K_int_inv1_mi100():
@@ -1690,7 +1690,7 @@ def test_analyze_K_int_inv1_mi100():
         ):
             omniperf.main()
     assert e.type == SystemExit
-    assert e.value.code == 0
+    assert e.value.code == 1
 
 
 def test_K_int_inv1_mi200():
@@ -1701,7 +1701,7 @@ def test_K_int_inv1_mi200():
         ):
             omniperf.main()
     assert e.type == SystemExit
-    assert e.value.code == 0
+    assert e.value.code == 1
 
 
 def test_analyze_mixbench2_mi100():
@@ -1723,7 +1723,7 @@ def test_mixbench2_mi200():
         ):
             omniperf.main()
     assert e.type == SystemExit
-    assert e.value.code == 0
+    assert e.value.code == 1
 
 
 def test_roof_only_Double_N_flag_mi200():
@@ -1739,7 +1739,7 @@ def test_roof_only_Double_N_flag_mi200():
         ):
             omniperf.main()
     assert e.type == SystemExit
-    assert e.value.code == 0
+    assert e.value.code == 1
 
 
 def test_analyze_no_roof_TD_mi100():
@@ -1879,7 +1879,7 @@ def test_no_roof_Double_N_flag_mi200():
         ):
             omniperf.main()
     assert e.type == SystemExit
-    assert e.value.code == 0
+    assert e.value.code == 1
 
 
 def test_analyze_Double_N_flag_mi100():
@@ -1901,7 +1901,7 @@ def test_Double_N_flag_mi200():
         ):
             omniperf.main()
     assert e.type == SystemExit
-    assert e.value.code == 0
+    assert e.value.code == 1
 
 
 def test_roof_only_K_int_inv1_mi200():
@@ -1933,7 +1933,7 @@ def test_analyze_no_roof_K_str_valid_1_mi100():
         ):
             omniperf.main()
     assert e.type == SystemExit
-    assert e.value.code == 0
+    assert e.value.code == 1
 
 
 def test_no_roof_K_str_valid_1_mi200():
@@ -1965,7 +1965,7 @@ def test_roof_only_mixbench1_mi200():
         ):
             omniperf.main()
     assert e.type == SystemExit
-    assert e.value.code == 0
+    assert e.value.code == 1
 
 
 def test_analyze_dev1_mi100():
@@ -1996,7 +1996,7 @@ def test_analyze_no_roof_K_str_inv1_mi100():
         ):
             omniperf.main()
     assert e.type == SystemExit
-    assert e.value.code == 0
+    assert e.value.code == 1
 
 
 def test_no_roof_K_str_inv1_mi200():
@@ -2007,7 +2007,7 @@ def test_no_roof_K_str_inv1_mi200():
         ):
             omniperf.main()
     assert e.type == SystemExit
-    assert e.value.code == 0
+    assert e.value.code == 1
 
 
 def test_analyze_K_str_valid_1_mi100():
@@ -2018,7 +2018,7 @@ def test_analyze_K_str_valid_1_mi100():
         ):
             omniperf.main()
     assert e.type == SystemExit
-    assert e.value.code == 0
+    assert e.value.code == 1
 
 
 def test_K_str_valid_1_mi200():
@@ -2051,7 +2051,7 @@ def test_mixbench1_mi200():
         ):
             omniperf.main()
     assert e.type == SystemExit
-    assert e.value.code == 0
+    assert e.value.code == 1
 
 
 def test_analyze_no_roof_CMD_INV_mi100():
@@ -2062,7 +2062,7 @@ def test_analyze_no_roof_CMD_INV_mi100():
         ):
             omniperf.main()
     assert e.type == SystemExit
-    assert e.value.code == 0
+    assert e.value.code == 1
 
 
 def test_roof_only_D_str_inv1_mi200():
@@ -2122,7 +2122,7 @@ def test_analyze_D_int_inv1_mi100():
         ):
             omniperf.main()
     assert e.type == SystemExit
-    assert e.value.code == 0
+    assert e.value.code == 1
 
 
 def test_D_int_inv1_mi200():
@@ -2133,7 +2133,7 @@ def test_D_int_inv1_mi200():
         ):
             omniperf.main()
     assert e.type == SystemExit
-    assert e.value.code == 0
+    assert e.value.code == 1
 
 
 def test_analyze_K_str_valid_2_mi100():
@@ -2292,7 +2292,7 @@ def test_analyze_no_roof_D_int_inv1_mi100():
         ):
             omniperf.main()
     assert e.type == SystemExit
-    assert e.value.code == 0
+    assert e.value.code == 1
 
 
 def test_no_roof_D_int_inv1_mi200():
@@ -2303,7 +2303,7 @@ def test_no_roof_D_int_inv1_mi200():
         ):
             omniperf.main()
     assert e.type == SystemExit
-    assert e.value.code == 0
+    assert e.value.code == 1
 
 
 def test_analyze_dispatches_mi100():
@@ -2347,7 +2347,7 @@ def test_analyze_no_roof_K_int_inv2_mi100():
         ):
             omniperf.main()
     assert e.type == SystemExit
-    assert e.value.code == 0
+    assert e.value.code == 1
 
 
 def test_no_roof_K_int_inv2_mi200():
@@ -2358,4 +2358,4 @@ def test_no_roof_K_int_inv2_mi200():
         ):
             omniperf.main()
     assert e.type == SystemExit
-    assert e.value.code == 0
+    assert e.value.code == 1
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/SQ_IFETCH_LEVEL.csv
index dc76497f11..3bea8f3ce1 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/SQ_IFETCH_LEVEL.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,899514,899519,33554432,256,0,0,8,32,6464,0x0,0x7f1fa6004180,503617,503617,524288,6291456,791394,101370956,12075916066690965,12075916308968012,12075916309291690,12075916309401692
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,899514,899519,32768,256,0,0,24,24,12480,0x0,0x7f1fa6035100,28476,28476,512,8192,8822,1126348,12075916323842971,12075916324149848,12075916324156728,12075916324169417
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,899514,899519,4194304,256,0,0,24,24,12928,0x7f20b1c5c900,0x7f1fa6035140,219068,219068,65536,917504,139994,17933088,12075916324227495,12075916324447606,12075916324581365,12075916324585631
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/SQ_INST_LEVEL_LDS.csv
index 47ba43a8aa..3c2c338a5a 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/SQ_INST_LEVEL_LDS.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,901311,901316,33554432,256,0,0,8,32,6464,0x0,0x7f8ba1604180,0,0,0,12075942327036344,12075942571037950,12075942571360189,12075942571463912
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,901311,901316,32768,256,0,0,24,24,12480,0x0,0x7f8ba1635100,0,0,0,12075942586056261,12075942586355119,12075942586361839,12075942586377678
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,901311,901316,4194304,256,0,0,24,24,12928,0x7f8cad17c900,0x7f8ba1635140,0,0,0,12075942586430637,12075942586646478,12075942586779597,12075942586783532
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/SQ_INST_LEVEL_SMEM.csv
index c0261613a6..3db4e8498e 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/SQ_INST_LEVEL_SMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,900933,900938,33554432,256,0,0,8,32,6464,0x0,0x7fde4da04180,4194304,3099050,396455528,12075939814530162,12075940060541623,12075940060866101,12075940060977444
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,900933,900938,32768,256,0,0,24,24,12480,0x0,0x7fde4da35100,512,21834,2778040,12075940075409134,12075940075710667,12075940075716907,12075940075730201
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,900933,900938,4194304,256,0,0,24,24,12928,0x7fdf5971c900,0x7fde4da35140,65536,170266,21950512,12075940075787127,12075940075998985,12075940076129225,12075940076133521
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/SQ_INST_LEVEL_VMEM.csv
index 7a3e11e067..f44546b762 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/SQ_INST_LEVEL_VMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,901123,901128,33554432,256,0,0,8,32,6464,0x0,0x7f34bac04180,1048576,11105144,1422096704,12075941073738305,12075941319842027,12075941320166985,12075941320278178
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,901123,901128,32768,256,0,0,24,24,12480,0x0,0x7f34bac35100,4096,114185,14602220,12075941334761004,12075941335062034,12075941335068594,12075941335073605
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,901123,901128,4194304,256,0,0,24,24,12928,0x7f35ead59900,0x7f34bac35140,524288,12413352,1588891204,12075941335135089,12075941335348753,12075941335481872,12075941335485801
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/SQ_LEVEL_WAVES.csv
index 0c848b4059..af10745c6c 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/SQ_LEVEL_WAVES.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,901499,901504,33554432,256,0,0,8,32,6464,0x0,0x7f2728204180,503201,503201,16824,4025616,524288,368372692,3819010,0,1488255924,12075943579867225,12075943823748052,12075943824071410,12075943824181973
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,901499,901504,32768,256,0,0,24,24,12480,0x0,0x7f2728235100,27688,27688,20343,221512,512,1099987,74919,0,4414100,12075943838718799,12075943839049613,12075943839056013,12075943839064461
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,901499,901504,4194304,256,0,0,24,24,12928,0x7f2833ec6900,0x7f2728235140,226925,226925,20091,1815408,65536,115632522,1642353,0,464339996,12075943839137166,12075943839377931,12075943839516651,12075943839520970
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/pmc_dispatch_info.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/pmc_perf.csv
index e7290388ba..c32d2fdbb2 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBuffer.kd,0,0,0,900248,900253,33554432,256,0,0,8,32,6464,0x0,0x7f3bc4c04180,1048576,0,1048576,9437184,0,4194304,1048576,0,507153,507153,58086129,55469033,129,13311114,54728162,54644836,55427765,54243156,4057224,3856864,507153,0,507153,0,16228896,15334730,0,0,0,0,0,17567640,1048576,0,506737,0,0,0,506737,0,0,0,506737,0,0,0,506737,0,0,0,506737,0,0,0,506737,0,0,0,506737,0,0,0,506737,0,0,0,506737,0,0,0,506737,0,0,0,506737,0,0,0,506737,0,0,0,506737,0,0,0,506737,0,0,0,506737,0,0,0,506737,0,0,0,506737,0,0,0,506737,0,0,0,506737,0,0,0,506737,0,0,0,506737,0,0,0,506737,0,0,0,506737,0,0,0,506737,0,0,0,506737,0,0,0,506737,0,0,0,506737,0,0,0,506737,0,0,0,506737,0,0,0,506737,0,0,0,506737,0,0,0,506737,0,0,0,37331948,2489,0,0,0,4,0,0,0,1,0,0,0,0,0,0,0,2628,0,0,0,3,0,0,0,48,0,0,0,49,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,3,0,0,0,0,0,0,0,0,0,0,0,2593,0,0,0,0,0,0,0,48,0,0,0,0,0,0,0,2700,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,22,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1048576,0,0,3226019,131076,131076,0,20068,131076,131076,0,0,131076,131076,0,0,131072,131072,0,2952414,131072,131072,0,0,131072,131072,0,0,131072,131072,0,0,131076,131076,0,0,131076,131076,0,0,131072,131072,0,0,131076,131076,0,0,131072,131072,0,5271,131072,131072,0,0,131080,131080,0,521506,131072,131072,0,0,131072,131072,0,1399,131076,131076,0,781,131072,131072,0,0,131076,131076,0,0,131076,131076,0,262,131076,131076,0,0,131076,131076,0,0,131072,131072,0,0,131076,131076,0,3216942,131072,131072,0,0,131072,131072,0,0,131076,131076,0,1570,131072,131072,0,2828639,131076,131076,0,0,131072,131072,0,0,131072,131072,0,1907,131072,131072,1048576,0,1026,0,0,17441761,971,0,0,17142079,1209,0,0,17070966,2102,0,0,17329446,1063,0,0,17589621,972,0,0,17364439,793,0,0,17721506,1842,0,0,18691327,1808,0,0,17369537,1828,0,0,17467183,732,0,0,16964404,50145,0,0,30571801,1231,0,0,17634715,895,0,0,17377635,722,0,0,17853438,1616,0,0,18524701,837,0,0,17198341,48369,0,0,29732204,1165,0,0,16829632,2231,0,0,16999240,758,0,0,17512103,914,0,0,17328482,792,0,0,17778192,43289,0,0,30746554,635,0,0,16996305,738,0,0,16893211,681,0,0,16893099,43862,0,0,29091329,743,0,0,17591619,1135,0,0,17495065,669,0,0,17857550,677,0,0,18737810,1048576,131072,131121,49,262193,131260,131079,195,262339,131072,131072,0,262144,131072,133747,2675,264819,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131092,20,262164,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131119,131074,49,262193,131072,131073,1,262145,131072,133589,2517,264661,131119,131073,48,262192,131213,131075,144,262288,131072,131072,0,262144,131072,133951,2879,265023,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131073,1,262145,131072,133632,2560,264704,262144,0,262144,262336,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262288,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,0,0,3145728,524288,32505856,373924347,219311274,122107217,479420,0,0,0,1048576,53028653,52830943,1048576,1048576,131072,524288,728,500607,3972,0,96,10735,0,8388944,32505856,4008048,3809339,57003729,11534336,0,0,14155776,67108864,67108864,0,67108864,53963222,53558440,0,1048576,242005,766293,10838,2395,0,496965,8399631,0,4194727,4204904,13631488,0,3670016,1048576,1048576,0,4194304,9437184,0,0,360,33554432,54308752,4194304,0,0,2796,501051,0,11110,8388608,0,4194374,905969664,6291456,0,0,0,524288,524288,0,15352,16608488,0,16777216,4194304,4194304,0,0,0,17787,4194372,4194372,0,216810,0,0,0,33554432,0,0,0,0,637962940,0,2793830231,0,0,0,0,0,480801,0,0,221717,0,0,8388608,336,144,0,0,0,480,8388608,0,0,0,0,369366,0,0,0,10868,0,21718,0,6291456,6289265,96,2347,1884443,0,0,0,0,0,0,0,0,0,3145728,0,0,0,146977,4194304,4189867,144,4293,2097152,524288,1572864,0,0,0,0,0,0,524288,0,4128836,65536,4063245,0,0,8388608,0,42167103,0,1048576,10553,4194368,13005296,605244728,12075918178631914,12075944713091723,12075944713416199,12075918424062756
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,900248,900253,32768,256,0,0,24,24,12480,0x0,0x7f3bc4c35100,0,4096,4096,512,0,512,4096,0,28607,28607,1486547,595216,219,128414,93521,80213,587132,566633,228856,84925,28607,0,28607,0,915424,201238,0,0,0,0,0,45058,4096,0,28046,0,0,0,28046,0,0,0,28046,0,0,0,28046,0,0,0,28046,0,0,0,28046,0,0,0,28046,0,0,0,28046,0,0,0,28046,0,0,0,28046,0,0,0,28046,0,0,0,28046,0,0,0,28046,0,0,0,28046,0,0,0,28046,0,0,0,28046,0,0,0,28046,0,0,0,28046,0,0,0,28046,0,0,0,28046,0,0,0,28046,0,0,0,28046,0,0,0,28046,0,0,0,28046,0,0,0,28046,0,0,0,28046,0,0,0,28046,0,0,0,28046,0,0,0,28046,0,0,0,28046,0,0,0,28046,0,0,0,28046,0,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,305,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,304,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,377,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,4096,4096,0,123487,0,0,0,121421,0,0,0,85327,0,0,0,77346,0,0,0,77692,0,0,0,105017,0,0,0,86522,0,0,0,90086,0,0,0,125455,0,0,0,83827,0,0,0,75809,0,0,0,85015,0,0,0,168309,0,0,0,85637,0,0,0,63336,0,0,0,73197,0,0,0,119916,0,0,0,88779,0,0,0,64572,0,0,0,78349,0,0,0,86315,0,0,0,80603,0,0,0,87160,0,0,0,136128,0,0,0,177375,0,0,0,128545,0,0,0,87893,0,0,0,98513,0,0,0,210615,0,0,0,86453,0,0,0,109920,0,0,0,81716,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4096,0,305,305,305,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,376,376,376,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,257,257,257,188,261,449,449,0,256,256,256,47,257,304,304,0,256,256,256,188,260,448,448,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,47,258,305,305,0,256,256,256,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,304,0,0,256,0,0,0,0,512,512,35328,1137335,1076721,24262,11571,0,0,0,4096,87901,85072,4096,4096,128,512,638,26630,3967,0,48,221,0,8624,36352,224952,80304,1125672,26624,0,0,30208,65536,65536,65536,0,0,0,0,0,114,626,11538,2398,0,24079,8892,0,470,8422,1024,0,1024,4096,0,4096,512,512,0,0,360,16384,0,16384,0,0,2839,24352,0,8844,0,0,31,1933312,8192,0,0,0,512,512,0,120,15064,0,16384,16384,0,0,0,0,20958,0,0,0,0,0,0,0,32768,0,0,0,0,12046996,17134078,0,8192,0,0,0,0,695,0,0,0,0,0,1024,432,48,0,0,0,480,0,0,0,0,0,3336,0,0,0,8421,0,438,0,8192,6584,48,1560,1074,0,0,0,0,0,0,0,0,0,2560,0,0,0,50146,512,0,48,464,0,512,0,0,0,0,0,0,0,512,0,0,0,0,0,8192,0,0,471492,0,4096,8420,0,3786424,0,12075918439028810,12075944728173211,12075944728179771,12075918440025592
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,900248,900253,4194304,256,0,0,24,24,12928,0x7f3cd082f900,0x7f3bc4c35140,0,524288,524288,65536,0,65536,524288,0,221389,221389,24500897,23243716,29840,8922080,22644899,22547849,23230140,21068471,1771112,1617399,221389,0,221389,0,7084448,6340936,0,0,0,0,0,20899426,524288,0,222093,0,0,0,222093,0,0,0,222093,0,0,0,222093,0,0,0,222093,0,0,0,222093,0,0,0,222093,0,0,0,222093,0,0,0,222093,0,0,0,222093,0,0,0,222093,0,0,0,222093,0,0,0,222093,0,0,0,222093,0,0,0,222093,0,0,0,222093,0,0,0,222093,0,0,0,222093,0,0,0,222093,0,0,0,222093,0,0,0,222093,0,0,0,222093,0,0,0,222093,0,0,0,222093,0,0,0,222093,0,0,0,222093,0,0,0,222093,0,0,0,222093,0,0,0,222093,0,0,0,222093,0,0,0,222093,0,0,0,222093,0,0,0,0,65845,0,10945,0,65536,0,8805,0,65541,0,2420,0,65536,0,2414,0,65536,0,20810,0,65536,0,7403,0,65536,0,12005,0,65585,0,21369,0,65536,0,123,0,65536,0,3685,0,65537,0,12840,0,65536,0,24205,0,65536,0,9028,0,65536,0,18636,0,65536,0,12884,0,65536,0,12964,0,65536,0,5251,0,65536,0,8332,0,65536,0,7654,0,65536,0,13549,0,65536,0,26843,0,65536,0,27211,0,65584,0,3382,0,65536,0,1506,0,67890,0,65934,0,65536,0,13746,0,65537,0,27227,0,65536,0,8020,0,65657,0,31995,0,65536,0,24169,0,65540,0,22681,0,65536,0,58202,0,524288,524288,0,45607242,0,0,0,26289972,0,0,0,25353639,0,0,0,26691092,0,0,0,28318625,0,0,0,27282822,0,0,0,26632340,0,0,0,29071044,0,0,0,29144155,0,0,0,28608654,0,0,0,24861213,0,0,0,29611871,0,0,0,31164194,0,0,0,31491237,0,0,0,28554250,0,0,0,30870996,0,0,0,30934788,0,0,0,28169263,0,0,0,31068234,0,0,0,30490323,0,0,0,26522482,0,0,0,29541729,0,0,0,30899371,0,0,0,29428081,0,0,0,26823740,0,0,0,30472625,0,0,0,29751557,0,0,0,30060322,0,0,0,49772735,0,0,0,29498306,0,0,0,24451120,0,0,0,28793526,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,524288,0,65585,65585,65585,0,65536,65536,65536,188,65540,65728,65728,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65656,65656,65656,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65537,65537,65537,0,65537,65537,65537,0,65864,65864,65864,47,65537,65584,65584,0,65536,65536,65536,0,65536,65536,65536,0,68155,68155,68155,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,188,65541,65729,65729,0,65536,65536,65536,65536,0,0,65536,0,0,65728,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65728,0,0,65536,0,0,0,0,65536,65536,4128768,142119985,45657585,92202560,210509,0,0,0,524288,23684009,23679036,524288,524288,16384,65536,778,349362,3913,0,48,4981,0,2097536,4259840,1746600,1586673,23488565,3014656,0,0,3473408,8388608,8388608,8388608,0,0,0,0,0,183157,210885,11229,2433,0,214332,2100789,0,423,2100366,131072,0,131072,524288,0,524288,65536,65536,0,0,360,2097152,0,2097152,30058,0,3191,220742,0,2101956,0,0,31,222298112,917504,0,0,0,65536,65536,0,7597,2019399,0,2097152,2097152,0,728283,730770,0,21948,0,0,0,0,0,0,0,4194304,0,0,0,0,1152549175,2058162424,0,2097152,0,0,0,0,190174,0,0,0,0,0,131072,384,48,0,0,0,432,0,0,0,0,0,12029,0,0,0,2100300,0,6278,0,917504,914942,68,5113,203670,0,0,0,0,0,0,0,0,0,327680,0,0,688535,742538,65536,64048,48,1440,0,65536,0,0,0,0,0,0,0,65536,0,0,0,1966104,0,2097152,0,0,14527803,0,524288,2101712,0,946605465,0,12075918440659470,12075944728248250,12075944728379609,12075918441907600
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/prev_analysis/1.csv
index 20e69f5894..49a2aed36d 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,6051952.0,6051952.0,6051952.0,9.136726903467284
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4525565.0,4525565.0,4525565.0,6.832316497039289
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 256u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,3050056.0,3050056.0,3050056.0,4.604717405604309
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/prev_analysis/1001.csv
index ca08330db0..0e3bf5267e 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,46.862275449101794,Instr per wave
 SMEM,1.8083832335329342,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/prev_analysis/101.csv
index 6dc12b06fe..06e523d8e8 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx908
 mi100
 48
 1228.8
-SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/prev_analysis/1202.csv
index 35d46636a0..f064ec5042 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,33669.99006456386,2852.8163681030273,547920.7350463867,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/prev_analysis/1901.csv
index b840ee3aa6..00a285cbd9 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,2.0,smem_
 VALU,735.0,valu_
 MFMA,,mfma_
 VMEM,8.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,22.0,br_
 VGPR,24.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,67894.0,wavefronts_
 Workgroups,16973.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,163.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,0.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,44.0,hbm_rd_
 HBM Wr,0.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,70.0,vl1_coales_
 VL1 Stall,30.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,35.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/prev_analysis/2001.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/prev_analysis/201.csv
index 1095703319..31d8a82a6c 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,59.58449821812784,Pct,100,59.58449821812784
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,63.967830830447085,Threads,64,99.94973567257357
 IPC - Issue,0.8437266214800547,Instr/cycle,5,16.874532429601096
-LDS BW,0.0,Gb/sec,23070.72,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,23070.72,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99343846471189,Pct,100,99.99343846471189
 Instr Cache BW,1402.474168265396,Gb/s,4614.144,30.39511051812418
 Scalar L1D Cache Hit Rate,99.35620448529356,Pct,100,99.35620448529356
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/prev_analysis/602.csv
index fe48f2d37a..f74ea934fc 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,65959.77844311377,0,728283,Simd
 Insufficient SIMD VGPRs,582374.6826347306,0,30915166,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/prev_analysis/701.csv
index d3f1bff5a3..1071413faa 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,23.976047904191617,8,36,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/sysinfo.csv
index 6da4405bc4..ab029e44a2 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-Axes1,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 11:24:51 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+Axes1,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 11:24:51 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/timestamps.csv
index a8f3dfedd3..d3428342dc 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes1/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,901550,901555,33554432,256,0,0,8,32,6464,0x0,0x7f38b4604180,12075944713040777,12075944713091723,12075944713416199,12075944713499991
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,901550,901555,32768,256,0,0,24,24,12480,0x0,0x7f38b4635100,12075944728070880,12075944728173211,12075944728179771,12075944728183740
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,901550,901555,4194304,256,0,0,24,24,12928,0x7f39c020d900,0x7f38b4635140,12075944728232350,12075944728248250,12075944728379609,12075944728383171
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/SQ_IFETCH_LEVEL.csv
index c05e63753d..f07bcc6b35 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/SQ_IFETCH_LEVEL.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,200200,200200,33554432,256,0,0,4,32,4160,0x0,0x7f3043a04280,380449,380449,524288,4718592,680823,76291444,17230491852189,17229803716158,17230639935378,17230640050298
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,200200,200200,32768,256,0,0,12,24,13888,0x0,0x7f3043a23f80,33388,33388,512,8192,6035,679208,17230645228208,17230639935378,17230645362261,17230645367004
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,200200,200200,4194304,256,0,0,12,24,14336,0x7f304aaf0380,0x7f3043a23fc0,164997,164997,65536,917504,142337,15939976,17230645404843,17230645362261,17230645745301,17230645747704
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/SQ_INST_LEVEL_LDS.csv
index 43d1baba80..23c540262e 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/SQ_INST_LEVEL_LDS.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,202048,202048,33554432,256,0,0,4,32,4160,0x0,0x7ff18ec04280,0,0,0,17249839171366,17249136551505,17249986734818,17249986848227
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,202048,202048,32768,256,0,0,12,24,13888,0x0,0x7ff18ec23f80,0,0,0,17249992035347,17249986734818,17249992162336,17249992165533
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,202048,202048,4194304,256,0,0,12,24,14336,0x7ff191cc5380,0x7ff18ec23fc0,0,0,0,17249992202162,17249992162336,17249992490176,17249992492374
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/SQ_INST_LEVEL_SMEM.csv
index 3e9f9a1d14..51cb9bcab3 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/SQ_INST_LEVEL_SMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,199978,199978,33554432,256,0,0,4,32,4160,0x0,0x7fe1d2a04280,3670016,3040452,340321896,17229574411755,17224026851585,17229723837237,17229723948727
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,199978,199978,32768,256,0,0,12,24,13888,0x0,0x7fe1d2a23f80,512,97598,10948992,17229729109777,17229723837237,17229729235641,17229729240263
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,199978,199978,4194304,256,0,0,12,24,14336,0x7fe1d5a50380,0x7fe1d2a23fc0,65536,619714,69394784,17229729274252,17229729235641,17229729595641,17229729597774
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/SQ_INST_LEVEL_VMEM.csv
index f5093b83e2..873ddb6bed 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/SQ_INST_LEVEL_VMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,201826,201826,33554432,256,0,0,4,32,4160,0x0,0x7f4602604280,524288,5464894,612004276,17248909572510,17246651988621,17249056201395,17249056314154
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,201826,201826,32768,256,0,0,12,24,13888,0x0,0x7f4602623f80,4096,40146,4496804,17249061450266,17249056201395,17249061580271,17249061585092
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,201826,201826,4194304,256,0,0,12,24,14336,0x7f4605631380,0x7f4602623fc0,524288,10522350,1178437788,17249061620532,17249061580271,17249061951471,17249061954023
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/SQ_LEVEL_WAVES.csv
index d24613ef4c..1412029554 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/SQ_LEVEL_WAVES.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,200422,200422,33554432,256,0,0,4,32,4160,0x0,0x7f294c004280,381872,381872,8673,3054984,524288,239943240,2968704,0,976030444,17231436888452,17230723230837,17231579793472,17231579902522
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,200422,200422,32768,256,0,0,12,24,13888,0x0,0x7f294c023f80,33766,33766,29849,270136,512,1763704,170161,0,7068488,17231585064932,17231579793472,17231585197473,17231585201818
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,200422,200422,4194304,256,0,0,12,24,14336,0x7f295a882380,0x7f294c023fc0,163877,163877,13443,1311024,65536,79496243,1203897,0,319710652,17231585245607,17231585197473,17231585576993,17231585579388
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/pmc_perf.csv
index 050796967e..41eed7f780 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDI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],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBufferAligned.kd,0,0,0,201188,201188,33554432,256,0,0,4,32,4160,0x0,0x7fc054604280,3090680,3004796,524288,39039609,244397387,392,224,0,386334,386334,39304257.0,38326934.0,21.0,4176858.0,31446788.0,31081951.0,38304270.0,37743504.0,3088969,3011187,386334,0,386334,0,12362688.0,9447009.0,0.0,0.0,0,0,616,0,4718592,4714880,112,3600,377162,0.0,0.0,0.0,524288.0,28640369.0,27920290.0,7556.0,524288.0,131072,524288,302,386660,2274,0,56.0,304.0,0.0,4194696.0,0,0,0,0,0,7340032,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,20080097.0,524288.0,0,383525,0,0,0,383525,0,0,0,383525,0,0,0,383525,0,0,0,383525,0,0,0,383525,0,0,0,383525,0,0,0,383525,0,0,0,383525,0,0,0,383525,0,0,0,383525,0,0,0,383525,0,0,0,383525,0,0,0,383525,0,0,0,383525,0,0,0,383525,0,0,0,383525,0,0,0,383525,0,0,0,383525,0,0,0,383525,0,0,0,383525,0,0,0,383525,0,0,0,383525,0,0,0,383525,0,0,0,383525,0,0,0,383525,0,0,0,383525,0,0,0,383525,0,0,0,383525,0,0,0,383525,0,0,0,383525,0,0,0,383525,0,0,0,0,0,0.0,21053549.0,32,0,0,0,0,0,0,0,1,0,0,0,1,0,0,0,2,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2,0,0,0,0,0,0,0,1,0,0,0,147,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4,0,0,0,0,0,0,0,0,0,0,0,56,0,0,0,0,0,0,0,32,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,524288.0,0.0,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,45272,129024,129024,0,329,129024,129024,0,423,129024,129024,0,279028,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,43073,129024,129024,0,548606,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,200,129024,129024,0,23908,129024,129024,0,867,129024,129024,0,0,129024,129024,0,158,129024,129024,0,0,129024,129024,0,0,129024,129024,0,853,129024,129024,0,0,129024,129024,0,0,129024,129024,0,44725,129024,129024,0,184,129024,129024,524288.0,0.0,44535,0,0,50919218,46120,0,0,51379154,45991,0,0,50997810,47572,0,0,52483664,44901,0,0,51669795,46424,0,0,51869190,45269,0,0,51332192,47983,0,0,53270097,45452,0,0,51279125,47302,0,0,51588981,45003,0,0,50860262,48107,0,0,52595459,47151,0,0,52506177,48661,0,0,52512436,45971,0,0,51666791,49502,0,0,53766252,45237,0,0,51159262,46099,0,0,51188357,44963,0,0,50808554,48208,0,0,52531666,45221,0,0,51688009,47344,0,0,52128294,45122,0,0,51200814,48604,0,0,53239811,46519,0,0,51361554,46781,0,0,51488415,45876,0,0,50758719,48787,0,0,52771593,46283,0,0,51996011,47485,0,0,52170792,46632,0,0,51784114,48945,0,0,53351841,0.0,65536,65568,32,131104,65536,65536,0,131072,65591,65537,56,131128,65536,65536,0,131072,65646,65538,112,131184,65536,65536,0,131072,65536,65536,0,131072,65536,65538,2,131074,65536,65536,0,131072,65536,65568,32,131104,65536,65536,0,131072,65536,65536,0,131072,65536,65539,3,131075,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65537,1,131073,65536,65572,36,131108,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65758,65538,224,131296,65536,65536,0,131072,65536,65536,0,131072,65536,65648,112,131184,65536,65536,0,131072,65536,65568,32,131104,65536,65536,0,131072,65536,65536,0,131072,65536,65592,56,131128,65591,65537,56,131128,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131184,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131296,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131128,0,131072,1051601,0,524288,3670016,3663333,224,6459,1048576,33554432.0,33554432.0,0.0,33554432.0,29936796.0,28288994.0,0.0,524288.0,212400,538313,8675,931,0,380106,4195055.0,0.0,2097594.0,2097461.0,1048576,1048576,0,524288,0,524288,7340032,0,0.0,0.0,104.0,8388608.0,29584423.0,2097152.0,0.0,204446,0,1203,383529,0,750.0,4194304.0,0.0,2064387.0,25690112,9437184,0,0,0,0,0,0,13288.0,8242440.0,0.0,8388608.0,2097152.0,4194304.0,9767153,0,0,8911,4128768.0,4128768.0,0.0,1476772.0,0,0,0,0,0,0,5767168,1048576,319170054.0,0.0,1481865816.0,0.0,20.0,0.0,0,0,377597,0.0,0.0,1529973.0,0.0,3670016,524288,0,0,0,2621440,524288,179427669,4194304.0,0.0,0.0,0.0,0.0,1164582.0,0,0,0.0,310.0,0.0,604.0,44841389,24117248,0,0,9437184,11010048,0,3145728,0.0,0.0,0.0,0.0,0.0,0.0,0,1572864,0.0,0.0,0.0,190179.0,524288,524288,0,3670016,7340032,603979776,4718592,0,0.0,0.0,0.0,0.0,0.0,0.0,524288,0,2064384.0,0.0,2031623.0,0.0,0,0,524288,0,0,0,0,33554432,0.0,4194304.0,0.0,18894012.0,0.0,0.0,140.0,4128768.0,987852.0,1700414862.0,17232867893883,17250653618423,17250653858583,17233014515566
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,201188,201188,32768,256,0,0,12,24,13888,0x0,0x7fc054623f80,264192,160645,512,1355992,1666709,504,56,0,33023,33023,2320097.0,151128.0,171.0,0.0,35205.0,31884.0,144860.0,126097.0,264184,167646,33023,0,33023,0,1056736.0,379801.0,0.0,0.0,0,0,560,0,8192,6159,56,1977,23339,0.0,0.0,0.0,4096.0,29087.0,27620.0,0.0,4096.0,128,512,302,32543,2236,0,0.0,59.0,0.0,4600.0,0,0,0,0,0,1024,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,23114.0,4096.0,0,33220,0,0,0,33220,0,0,0,33220,0,0,0,33220,0,0,0,33220,0,0,0,33220,0,0,0,33220,0,0,0,33220,0,0,0,33220,0,0,0,33220,0,0,0,33220,0,0,0,33220,0,0,0,33220,0,0,0,33220,0,0,0,33220,0,0,0,33220,0,0,0,33220,0,0,0,33220,0,0,0,33220,0,0,0,33220,0,0,0,33220,0,0,0,33220,0,0,0,33220,0,0,0,33220,0,0,0,33220,0,0,0,33220,0,0,0,33220,0,0,0,33220,0,0,0,33220,0,0,0,33220,0,0,0,33220,0,0,0,33220,0,0,0,0,0,0.0,0.0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,260,0,0,0,257,0,0,0,256,0,0,0,257,0,0,0,314,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,4096.0,4096.0,0,76623,0,0,0,91017,0,0,0,86218,0,0,0,83451,0,0,0,85827,0,0,0,84547,0,0,0,88171,0,0,0,137635,0,0,0,123050,0,0,0,83450,0,0,0,97353,0,0,0,82639,0,0,0,77851,0,0,0,656517,0,0,0,78768,0,0,0,88309,0,0,0,103976,0,0,0,81772,0,0,0,98706,0,0,0,83204,0,0,0,77583,0,0,0,78856,0,0,0,87961,0,0,0,87913,0,0,0,79118,0,0,0,102454,0,0,0,74203,0,0,0,85238,0,0,0,81857,0,0,0,78829,0,0,0,78067,0,0,0,87092,0,0,0.0,0.0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4096.0,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,222,130,352,352,0,128,128,128,0,129,129,129,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,129,129,129,0,128,128,128,222,130,352,352,0,128,128,128,0,128,128,128,0,129,129,129,0,130,130,130,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,55,129,184,184,0,128,128,128,0,184,184,184,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,352,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,352,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,184,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,670,0,0,512,0,56,456,0,65536.0,65536.0,65536.0,0.0,0.0,0.0,0.0,0.0,4,516,11360,1056,0,30808,4659.0,0.0,499.0,4160.0,512,0,0,0,4096,4096,512,0,0.0,0.0,104.0,16384.0,0.0,16384.0,4096.0,0,0,1325,32330,0,4662.0,0.0,0.0,31.0,35328,26112,0,0,0,0,0,0,104.0,15240.0,0.0,16384.0,16384.0,0.0,0,0,0,29759,0.0,0.0,0.0,0.0,0,0,0,0,0,0,10752,3584,4383169.0,5617542.0,0.0,8192.0,2.0,0.0,0,0,498,0.0,0.0,0.0,0.0,512,4096,0,0,0,512,512,1713534,0.0,0.0,0.0,0.0,0.0,1381.0,0,0,0.0,8262.0,0.0,122.0,15379,32256,0,0,26112,1024,0,1024,0.0,0.0,0.0,0.0,0.0,0.0,0,1024,0.0,0.0,0.0,52493.0,4096,0,4096,512,512,1671168,8192,0,0.0,0.0,0.0,0.0,0.0,0.0,512,0,0.0,0.0,0.0,0.0,0,0,512,0,0,0,0,32768,8192.0,0.0,0.0,108432.0,0.0,4096.0,8206.0,0.0,3395781.0,0.0,17233020693309,17250658698896,17250658712016,17233021176306
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,201188,201188,4194304,256,0,0,12,24,14336,0x7fc072ea2380,0x7fc054623fc0,1315640,1210632,65536,15672081,78293072,392,56,0,164454,164454,15969642.0,14530844.0,24626.0,765886.0,13520180.0,13218336.0,14524544.0,12388263.0,1315632,1217614,164454,0,164454,0,5262528.0,4728854.0,0.0,0.0,0,0,448,0,917504,913417,0,4087,154723,0.0,0.0,0.0,524288.0,13403311.0,13380931.0,2251.0,524288.0,16384,65536,302,165830,2239,0,0.0,179.0,0.0,1048968.0,0,0,0,0,0,131072,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,10841521.0,524288.0,0,165129,0,0,0,165129,0,0,0,165129,0,0,0,165129,0,0,0,165129,0,0,0,165129,0,0,0,165129,0,0,0,165129,0,0,0,165129,0,0,0,165129,0,0,0,165129,0,0,0,165129,0,0,0,165129,0,0,0,165129,0,0,0,165129,0,0,0,165129,0,0,0,165129,0,0,0,165129,0,0,0,165129,0,0,0,165129,0,0,0,165129,0,0,0,165129,0,0,0,165129,0,0,0,165129,0,0,0,165129,0,0,0,165129,0,0,0,165129,0,0,0,165129,0,0,0,165129,0,0,0,165129,0,0,0,165129,0,0,0,165129,0,0,0,0,0,0.0,0.0,65537,0,4922,0,65536,0,9700,0,65536,0,21391,0,65537,0,14881,0,65536,0,21743,0,65536,0,33978,0,65536,0,10751,0,65536,0,31455,0,65536,0,21664,0,65536,0,6414,0,65536,0,10646,0,65536,0,5309,0,65536,0,12005,0,65536,0,26032,0,65536,0,22981,0,65537,0,26374,0,65536,0,16310,0,65537,0,19624,0,65655,0,13922,0,65537,0,10497,0,65536,0,8041,0,65536,0,16668,0,65536,0,17380,0,65539,0,8216,0,65540,0,6465,0,65536,0,12184,0,65536,0,13008,0,65598,0,18913,0,65536,0,4264,0,65536,0,10963,0,65536,0,9457,0,65536,0,31030,0,524288.0,524288.0,0,45080961,0,0,0,40218423,0,0,0,41404492,0,0,0,40982909,0,0,0,45451188,0,0,0,46996487,0,0,0,47969577,0,0,0,45184284,0,0,0,44186585,0,0,0,46906503,0,0,0,44285466,0,0,0,46388948,0,0,0,47837262,0,0,0,46986336,0,0,0,46618877,0,0,0,43717470,0,0,0,40983161,0,0,0,46422239,0,0,0,38292554,0,0,0,45289551,0,0,0,47751294,0,0,0,48401763,0,0,0,48589018,0,0,0,42467059,0,0,0,43204204,0,0,0,46137662,0,0,0,37374308,0,0,0,45740990,0,0,0,46299986,0,0,0,43593354,0,0,0,44553373,0,0,0,52123907,0,0,0.0,0.0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,524288.0,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32769,32769,32769,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32769,32769,32769,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32769,32769,32769,0,32828,32828,32828,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,166,32770,32936,32936,222,32770,32992,32992,0,32824,32824,32824,0,32768,32768,32768,0,32833,32833,32833,0,32769,32769,32769,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32936,0,0,32992,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,911374,0,0,65536,63800,56,1680,0,8388608.0,8388608.0,8388608.0,0.0,0.0,0.0,0.0,0.0,122813,147514,10002,3287,0,162432,1049149.0,0.0,388.0,1048761.0,65536,0,0,0,524288,524288,131072,0,0.0,0.0,104.0,2097152.0,0.0,2097152.0,524288.0,43035,0,3551,160302,0,1049158.0,0.0,0.0,31.0,4063232,2883584,0,0,0,0,0,0,6604.0,2027575.0,0.0,2097152.0,2097152.0,0.0,1348054,0,0,14410,0.0,0.0,0.0,0.0,262144,0,0,0,0,0,1507328,458752,999345218.0,2224829893.0,0.0,2097152.0,115.0,0.0,0,0,148270,0.0,0.0,0.0,0.0,65536,524288,0,0,0,65536,65536,49113071,0.0,0.0,0.0,0.0,0.0,23330.0,0,0,0.0,2097343.0,0.0,368.0,31538854,3735552,0,0,2883584,196608,0,131072,0.0,0.0,0.0,0.0,0.0,0.0,0,131072,0.0,0.0,572588.0,1636616.0,524288,0,524288,65536,131072,184549376,917504,0,0.0,0.0,0.0,0.0,0.0,0.0,65536,0,0.0,0.0,983047.0,0.0,0,0,65536,0,0,0,0,4194304,2097152.0,0.0,0.0,12300035.0,0.0,524288.0,2097286.0,0.0,1495759975.0,0.0,17233022273806,17250658782576,17250658874896,17233023039486
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/prev_analysis/1.csv
index 495d1a19c3..d5ef5b8687 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,3358076.0,3358076.0,3358076.0,7.841553576961169
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,1725119.0,1725119.0,1725119.0,4.028382045294292
 "void benchmark_func<double, 256, 8u, 512u>(double, double*) [clone .kd]",1,1715679.0,1715679.0,1715679.0,4.006338391199949
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/prev_analysis/1001.csv
index f475f954a6..fb5988001a 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,494.8622754491018,Instr per wave
 VMEM,7.958083832335329,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,0.0,Instr per wave
 SALU,24.520958083832337,Instr per wave
 SMEM,1.8023952095808384,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/prev_analysis/101.csv
index b1fe75d7f6..908baae241 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx90a
 mi200
 56
 1638.4
-roofline|SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+roofline|SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/prev_analysis/1202.csv
index 4b84a700a7..36cfb20bd2 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,18370.77323406471,1864.6040878295898,258441.6922607422,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/prev_analysis/1901.csv
index 5a6c03282e..0edb8b58ca 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,2.0,smem_
 VALU,495.0,valu_
 MFMA,0.0,mfma_
 VMEM,8.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,10.0,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,67894.0,wavefronts_
 Workgroups,16973.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,128.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,0.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,44.0,hbm_rd_
 HBM Wr,0.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,70.0,vl1_coales_
 VL1 Stall,2.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,26.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/prev_analysis/201.csv
index d67f64cf51..5ee9c1afb5 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,58.34159376029337,Pct,100,58.34159376029337
 MFMA Util,0.0,Pct,100,0.0
 VALU Active Threads/Wave,64.0,Threads,64,100.0
 IPC - Issue,1.0,Instr/cycle,5,20.0
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.9925706103068,Pct,100,99.9925706103068
 Instr Cache BW,1672.543170726904,Gb/s,6092.8,27.45114185147886
 Scalar L1D Cache Hit Rate,99.34855886083365,Pct,100,99.34855886083365
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/prev_analysis/602.csv
index 9943d1e735..330e93b132 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,12537381.628742514,0,378193491,Simd
 Insufficient SIMD VGPRs,0.0,0,0,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/prev_analysis/701.csv
index 12250d77c0..db0925a109 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/sysinfo.csv
index 6e6db161c8..7975f56faf 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-Axes1,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:40:30 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,roofline|SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+Axes1,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:40:30 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,roofline|SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/timestamps.csv
index 24cce178e4..d4282a38f4 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes1/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,202131,202131,33554432,256,0,0,4,32,4160,0x0,0x7f6701a04280,17250653592721,17250653618423,17250653858583,17250653922762
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,202131,202131,32768,256,0,0,12,24,13888,0x0,0x7f6701a23f80,17250658683504,17250658698896,17250658712016,17250658729223
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,202131,202131,4194304,256,0,0,12,24,14336,0x7f6708902380,0x7f6701a23fc0,17250658734943,17250658782576,17250658874896,17250658877159
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/SQ_IFETCH_LEVEL.csv
index eebe7559ab..daeff02f6c 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/SQ_IFETCH_LEVEL.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,904528,904533,33554432,256,0,0,8,32,6464,0x0,0x7f5a30e04180,506681,506681,524288,6291456,792562,101549256,12076012262816271,12076012503553792,12076012503879230,12076012503985002
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,904528,904533,32768,256,0,0,24,24,12480,0x0,0x7f5a30e35100,28104,28104,512,8192,9287,1183436,12076012518518923,12076012518830984,12076012518837384,12076012518847614
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,904528,904533,4194304,256,0,0,24,24,12928,0x7f5b3c9cb900,0x7f5a30e35140,226931,226931,65536,917504,143322,18380728,12076012518910841,12076012519146822,12076012519285861,12076012519290988
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/SQ_INST_LEVEL_LDS.csv
index 323e5a669d..ce3449b374 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/SQ_INST_LEVEL_LDS.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,906323,906328,33554432,256,0,0,8,32,6464,0x0,0x7fb332204180,0,0,0,12076038461953928,12076038708819104,12076038709143262,12076038709253764
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,906323,906328,32768,256,0,0,24,24,12480,0x0,0x7fb332235100,0,0,0,12076038723915542,12076038724221189,12076038724227589,12076038724233333
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,906323,906328,4194304,256,0,0,24,24,12928,0x7fb43df66900,0x7fb332235140,0,0,0,12076038724298003,12076038724512547,12076038724648707,12076038724652732
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/SQ_INST_LEVEL_SMEM.csv
index 26d40dc6dc..7f009c67e8 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/SQ_INST_LEVEL_SMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,905945,905950,33554432,256,0,0,8,32,6464,0x0,0x7fa7a3804180,4194304,3115600,398554112,12076035960858082,12076036205207063,12076036205529621,12076036205637263
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,905945,905950,32768,256,0,0,24,24,12480,0x0,0x7fa7a3835100,512,23496,3012432,12076036220285436,12076036220589739,12076036220596459,12076036220601744
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,905945,905950,4194304,256,0,0,24,24,12928,0x7fa8d3833900,0x7fa7a3835140,65536,168548,21509560,12076036220667026,12076036220889098,12076036221020937,12076036221025311
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/SQ_INST_LEVEL_VMEM.csv
index b4e548a9b0..22b9d8472e 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/SQ_INST_LEVEL_VMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,906135,906140,33554432,256,0,0,8,32,6464,0x0,0x7f7a6cc04180,1048576,11145971,1426713976,12076037205083380,12076037454134301,12076037454459899,12076037454571422
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,906135,906140,32768,256,0,0,24,24,12480,0x0,0x7f7a6cc35100,4096,113752,14543000,12076037468977485,12076037469293867,12076037469300107,12076037469309622
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,906135,906140,4194304,256,0,0,24,24,12928,0x7f7b7879e900,0x7f7a6cc35140,524288,10196555,1305198640,12076037469370506,12076037469587946,12076037469726985,12076037469731186
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/SQ_LEVEL_WAVES.csv
index 19887f01a2..2059e6af51 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/SQ_LEVEL_WAVES.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,906511,906516,33554432,256,0,0,8,32,6464,0x0,0x7f4586e04180,504246,504246,17548,4033976,524288,368605679,3827741,0,1489275812,12076039738087526,12076039982998365,12076039983322204,12076039983431627
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,906511,906516,32768,256,0,0,24,24,12480,0x0,0x7f4586e35100,28708,28708,21209,229672,512,1162927,78755,0,4666036,12076039998516141,12076039998845611,12076039998852011,12076039998860611
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,906511,906516,4194304,256,0,0,24,24,12928,0x7f46b6ef1900,0x7f4586e35140,226140,226140,22430,1809128,65536,121427759,1627144,0,487522204,12076039998932284,12076039999174090,12076039999311369,12076039999315967
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/pmc_dispatch_info.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/pmc_perf.csv
index c7d87b72e0..110fc36480 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBuffer.kd,0,0,0,905262,905267,33554432,256,0,0,8,32,6464,0x0,0x7f7ff0e04180,1048576,0,1048576,9437184,0,4194304,1048576,0,504257,504257,57826455,55265856,185,12533581,54411633,54303454,55230138,54048577,4034056,3839554,504257,0,504257,0,16136224,15273605,0,0,0,0,0,17398488,1048576,0,504952,0,0,0,504952,0,0,0,504952,0,0,0,504952,0,0,0,504952,0,0,0,504952,0,0,0,504952,0,0,0,504952,0,0,0,504952,0,0,0,504952,0,0,0,504952,0,0,0,504952,0,0,0,504952,0,0,0,504952,0,0,0,504952,0,0,0,504952,0,0,0,504952,0,0,0,504952,0,0,0,504952,0,0,0,504952,0,0,0,504952,0,0,0,504952,0,0,0,504952,0,0,0,504952,0,0,0,504952,0,0,0,504952,0,0,0,504952,0,0,0,504952,0,0,0,504952,0,0,0,504952,0,0,0,504952,0,0,0,504952,0,0,0,37559673,0,0,0,0,52,0,0,0,48,0,0,0,0,0,0,0,224,0,0,0,0,0,0,0,3,0,0,0,0,0,0,0,2563,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,2737,0,0,0,0,0,0,0,3,0,0,0,0,0,0,0,2172,0,0,0,2626,0,0,0,0,0,0,0,1,0,0,0,48,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,1048576,0,0,3046551,131076,131076,0,15357,131072,131072,0,0,131072,131072,0,0,131072,131072,0,3354772,131080,131080,0,0,131072,131072,0,0,131076,131076,0,21347,131080,131080,0,0,131080,131080,0,0,131072,131072,0,0,131072,131072,0,0,131076,131076,0,262,131076,131076,0,1752,131080,131080,0,0,131072,131072,0,0,131080,131080,0,262,131072,131072,0,1222,131072,131072,0,0,131072,131072,0,0,131072,131072,0,3736892,131072,131072,0,1504,131080,131080,0,0,131072,131072,0,0,131072,131072,0,3020964,131072,131072,0,0,131076,131076,0,0,131072,131072,0,0,131072,131072,0,6042,131072,131072,0,0,131080,131080,0,1083,131072,131072,0,0,131072,131072,1048576,0,804,0,0,17204890,863,0,0,17272050,829,0,0,17157840,1242,0,0,17238846,44754,0,0,29479462,938,0,0,17552021,809,0,0,17798573,1337,0,0,18643299,49308,0,0,30644672,1034,0,0,17420710,931,0,0,16965463,922,0,0,16850823,836,0,0,17274121,803,0,0,17481836,830,0,0,17927958,45453,0,0,30760948,789,0,0,16715474,1037,0,0,16946293,857,0,0,16909514,825,0,0,17129037,47621,0,0,30457075,1461,0,0,17712015,864,0,0,18144580,1416,0,0,18833288,1349,0,0,16912337,1716,0,0,16835874,1019,0,0,16975284,1053,0,0,16915706,1140,0,0,17552680,1856,0,0,17587467,924,0,0,18073426,841,0,0,18845391,1048576,131072,131072,0,262144,131260,131124,240,262384,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131120,48,262192,131072,131073,1,262145,131072,131122,50,262194,131072,133623,2551,264695,131072,131072,0,262144,131072,133600,2528,264672,131072,131076,4,262148,131072,131072,0,262144,131072,131073,1,262145,131213,133854,2923,265067,131119,131073,48,262192,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,133774,2702,264846,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131119,131094,69,262213,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,262144,0,262144,262336,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262288,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,0,0,3145728,524288,32505856,373516608,218751460,122259292,481972,0,0,0,1048576,52973371,52757625,1048576,1048576,131072,524288,698,503205,4195,0,96,10913,0,8388944,32505856,4033936,3825938,57258166,11534336,0,0,14155776,67108864,67108864,0,67108864,54599522,54266674,0,1048576,241919,766207,11487,2443,0,500193,8399739,0,4194727,4205012,13631488,0,3670016,1048576,1048576,0,4194304,9437184,0,0,360,33554432,54343417,4194304,0,0,2793,500293,0,11232,8388608,0,4194398,905969664,6291456,0,0,0,524288,524288,0,15351,16608476,0,16777216,4194304,4194304,0,0,0,16661,4194365,4194365,0,222143,0,0,0,33554432,0,0,0,0,648115772,0,2826091607,0,0,0,0,0,473866,0,0,221008,0,0,8388608,336,144,0,0,0,480,8388608,0,0,0,0,284530,0,0,0,10221,0,20424,0,6291456,6289498,96,2024,1903189,0,0,0,0,0,0,0,0,0,3145728,0,0,0,144460,4194304,4189871,144,4289,2097152,524288,1572864,0,0,0,0,0,0,524288,0,4128837,65531,4063249,0,0,8388608,0,42135585,0,1048576,10761,4194384,13235379,610459494,12076014382347416,12076040869166673,12076040869490510,12076014627745367
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,905262,905267,32768,256,0,0,24,24,12480,0x0,0x7f7ff0e35100,0,4096,4096,512,0,512,4096,0,29186,29186,1540067,628830,203,119096,151858,139807,620772,600386,233488,88491,29186,0,29186,0,933952,210460,0,0,0,0,0,60730,4096,0,27342,0,0,0,27342,0,0,0,27342,0,0,0,27342,0,0,0,27342,0,0,0,27342,0,0,0,27342,0,0,0,27342,0,0,0,27342,0,0,0,27342,0,0,0,27342,0,0,0,27342,0,0,0,27342,0,0,0,27342,0,0,0,27342,0,0,0,27342,0,0,0,27342,0,0,0,27342,0,0,0,27342,0,0,0,27342,0,0,0,27342,0,0,0,27342,0,0,0,27342,0,0,0,27342,0,0,0,27342,0,0,0,27342,0,0,0,27342,0,0,0,27342,0,0,0,27342,0,0,0,27342,0,0,0,27342,0,0,0,27342,0,0,0,0,256,0,0,0,304,0,0,0,256,0,0,0,256,0,0,0,377,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,261,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,304,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,4096,4096,0,91528,0,0,0,104807,0,0,0,93219,0,0,0,90296,0,0,0,92958,0,0,0,127171,0,0,0,131579,0,0,0,147551,0,0,0,85170,0,0,0,94251,0,0,0,74259,0,0,0,80411,0,0,0,79497,0,0,0,97905,0,0,0,69578,0,0,0,66616,0,0,0,125208,0,0,0,119449,0,0,0,85334,0,0,0,115080,0,0,0,123131,0,0,0,86331,0,0,0,85485,0,0,0,91928,0,0,0,82967,0,0,0,82620,0,0,0,80308,0,0,0,85926,0,0,0,173186,0,0,0,85052,0,0,0,83139,0,0,0,78908,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4096,0,256,256,256,0,304,304,304,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,304,304,304,0,257,257,257,0,258,258,258,0,256,256,256,0,256,256,256,0,256,256,256,188,260,448,448,0,256,256,256,0,257,257,257,0,256,256,256,188,260,448,448,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,47,377,424,424,0,256,256,256,0,256,256,256,47,257,304,304,0,256,256,256,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,304,0,0,256,0,0,0,0,512,512,35328,1055159,969905,48902,11312,0,0,0,4096,95902,93791,4096,4096,128,512,602,26719,4087,0,48,171,0,8624,36352,216880,67694,945699,26624,0,0,30208,65536,65536,65536,0,0,0,0,0,116,628,11466,2454,0,22994,8844,0,470,8374,1024,0,1024,4096,0,4096,512,512,0,0,360,16384,0,16384,0,0,2917,24019,0,8892,0,0,31,1933312,8192,0,0,0,512,512,0,120,15064,0,16384,16384,0,0,0,0,20249,0,0,0,0,0,0,0,32768,0,0,0,0,12966960,17659250,0,8192,0,0,0,0,695,0,0,0,0,0,1024,432,48,0,0,0,480,0,0,0,0,0,3087,0,0,0,8422,0,440,0,8192,6544,48,1600,1066,0,0,0,0,0,0,0,0,0,2560,0,0,0,53508,512,0,48,464,0,512,0,0,0,0,0,0,0,512,0,0,0,0,0,8192,0,0,324043,0,4096,8540,0,2924490,0,12076014642823910,12076040884512411,12076040884519291,12076014643830020
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,905262,905267,4194304,256,0,0,24,24,12928,0x7f80fca1f900,0x7f7ff0e35140,0,524288,524288,65536,0,65536,524288,0,229604,229604,25469447,24220989,29503,5576976,23605408,23512272,24210228,22052890,1836832,1681977,229604,0,229604,0,7347328,6618879,0,0,0,0,0,20600165,524288,0,221941,0,0,0,221941,0,0,0,221941,0,0,0,221941,0,0,0,221941,0,0,0,221941,0,0,0,221941,0,0,0,221941,0,0,0,221941,0,0,0,221941,0,0,0,221941,0,0,0,221941,0,0,0,221941,0,0,0,221941,0,0,0,221941,0,0,0,221941,0,0,0,221941,0,0,0,221941,0,0,0,221941,0,0,0,221941,0,0,0,221941,0,0,0,221941,0,0,0,221941,0,0,0,221941,0,0,0,221941,0,0,0,221941,0,0,0,221941,0,0,0,221941,0,0,0,221941,0,0,0,221941,0,0,0,221941,0,0,0,221941,0,0,0,0,65536,0,1080,0,65584,0,5420,0,65540,0,0,0,65536,0,4218,0,66027,0,13408,0,65536,0,22838,0,65536,0,6087,0,65536,0,4116,0,66613,0,32837,0,65536,0,2,0,65536,0,324,0,65536,0,2840,0,65536,0,3379,0,65536,0,1526,0,65537,0,3570,0,65536,0,5250,0,65536,0,2572,0,65536,0,264,0,65536,0,4902,0,65536,0,3860,0,67936,0,95187,0,65536,0,9292,0,65537,0,6348,0,65584,0,13924,0,65536,0,15723,0,65536,0,208,0,65536,0,11962,0,65536,0,0,0,65537,0,17222,0,65536,0,6486,0,65540,0,1827,0,65536,0,1822,0,524288,524288,0,43699019,0,0,0,41510716,0,0,0,37856861,0,0,0,38896658,0,0,0,37582135,0,0,0,44378163,0,0,0,37171128,0,0,0,36368214,0,0,0,35078423,0,0,0,36471933,0,0,0,37351404,0,0,0,39131945,0,0,0,30900534,0,0,0,40035905,0,0,0,41446946,0,0,0,44576443,0,0,0,36142895,0,0,0,34826766,0,0,0,34737148,0,0,0,41043766,0,0,0,39990282,0,0,0,35787828,0,0,0,40558515,0,0,0,41155353,0,0,0,49758419,0,0,0,40772881,0,0,0,33839271,0,0,0,39941370,0,0,0,33657981,0,0,0,42337217,0,0,0,36049176,0,0,0,40100377,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,524288,0,65536,65536,65536,0,65584,65584,65584,188,65540,65728,65728,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65584,65584,65584,0,65537,65537,65537,0,65538,65538,65538,0,67497,67497,67497,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65537,65537,65537,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,67431,67431,67431,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,47,65657,65704,65704,0,65536,65536,65536,0,65536,65536,65536,188,65540,65728,65728,0,65536,65536,65536,65536,0,0,65536,0,0,65728,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65728,0,0,65536,0,0,0,0,65536,65536,4128768,144901291,52776335,87865116,197730,0,0,0,524288,22023738,22017534,524288,524288,16384,65536,742,214363,3982,0,48,2368,0,2097536,4259840,1795496,1626198,24042140,3014656,0,0,3473408,8388608,8388608,8388608,0,0,0,0,0,156433,192038,11193,2468,0,220462,2102111,0,423,2101688,131072,0,131072,524288,0,524288,65536,65536,0,0,360,2097152,0,2097152,34799,0,2923,221418,0,2101792,0,0,31,222298112,917504,0,0,0,65536,65536,0,7606,2017793,0,2097152,2097152,0,630027,632061,0,20795,0,0,0,0,0,0,0,4194304,0,0,0,0,1096136272,1852270329,0,2097152,0,0,0,0,190666,0,0,0,0,0,131072,384,48,0,0,0,432,0,0,0,0,0,13398,0,0,0,2102330,0,10338,0,917504,914876,48,7402,178309,0,0,0,0,0,0,0,0,0,327680,0,0,154384,207371,65536,64048,48,1440,0,65536,0,0,0,0,0,0,0,65536,0,0,0,1966097,0,2097152,0,0,16554076,0,524288,2100395,0,1026948934,0,12076014644466463,12076040884584411,12076040884719290,12076014645729360
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/prev_analysis/1.csv
index 2ce416ce43..c63e416a56 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,6052433.0,6052433.0,6052433.0,9.171253897560876
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4524925.0,4524925.0,4524925.0,6.856620476826534
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 256u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,3048937.0,3048937.0,3048937.0,4.620055330586488
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/prev_analysis/1001.csv
index ca08330db0..0e3bf5267e 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,46.862275449101794,Instr per wave
 SMEM,1.8083832335329342,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/prev_analysis/101.csv
index 68532c0bf4..d1a9b7c842 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx908
 mi100
 48
 1228.8
-SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/prev_analysis/1202.csv
index f1bda85707..6c834ba1b6 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,33836.997512908754,2849.70556640625,547887.5590209961,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/prev_analysis/1901.csv
index d1dac074af..8a8fb3d838 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,2.0,smem_
 VALU,735.0,valu_
 MFMA,,mfma_
 VMEM,8.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,22.0,br_
 VGPR,24.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,67894.0,wavefronts_
 Workgroups,16973.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,163.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,0.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,44.0,hbm_rd_
 HBM Wr,0.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,70.0,vl1_coales_
 VL1 Stall,30.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,35.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/prev_analysis/2001.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/prev_analysis/201.csv
index 6a63f25dd9..08cc764555 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,59.5755905790845,Pct,100,59.5755905790845
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,63.96707393468963,Threads,64,99.94855302295255
 IPC - Issue,0.8437193943979889,Instr/cycle,5,16.874387887959777
-LDS BW,0.0,Gb/sec,23070.72,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,23070.72,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99338555945363,Pct,100,99.99338555945363
 Instr Cache BW,1406.7885614971879,Gb/s,4614.144,30.488614171928482
 Scalar L1D Cache Hit Rate,99.3562044853132,Pct,100,99.3562044853132
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/prev_analysis/602.csv
index f85f65ee42..72ee79c1e3 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,60911.161676646705,0,744296,Simd
 Insufficient SIMD VGPRs,664898.8263473054,0,39547083,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/prev_analysis/701.csv
index d3f1bff5a3..1071413faa 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,23.976047904191617,8,36,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/sysinfo.csv
index 2ae3865455..f3d56aef3d 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-Axes2,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 11:26:27 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+Axes2,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 11:26:27 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/timestamps.csv
index e89225b463..7eaaee7d78 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes2/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,906562,906567,33554432,256,0,0,8,32,6464,0x0,0x7f4385604180,12076040869119418,12076040869166673,12076040869490510,12076040869595163
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,906562,906567,32768,256,0,0,24,24,12480,0x0,0x7f4385635100,12076040884412370,12076040884512411,12076040884519291,12076040884525019
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,906562,906567,4194304,256,0,0,24,24,12928,0x7f44911b4900,0x7f4385635140,12076040884570664,12076040884584411,12076040884719290,12076040884722877
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/SQ_IFETCH_LEVEL.csv
index cc6d25a148..b1800528df 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/SQ_IFETCH_LEVEL.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,206291,206291,33554432,256,0,0,4,32,4160,0x0,0x7fb354204280,382773,382773,524288,4718592,681263,76371244,17335908726154,17335197539126,17336053148049,17336053256459
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,206291,206291,32768,256,0,0,12,24,13888,0x0,0x7fb354223f80,33913,33913,512,8192,6012,678776,17336058469361,17336053148049,17336058604217,17336058609087
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,206291,206291,4194304,256,0,0,12,24,14336,0x7fb3572f2380,0x7fb354223fc0,164212,164212,65536,917504,142050,15918288,17336058648376,17336058604217,17336058979578,17336058982747
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/SQ_INST_LEVEL_LDS.csv
index dddf5ca57a..1199933482 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/SQ_INST_LEVEL_LDS.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,208139,208139,33554432,256,0,0,4,32,4160,0x0,0x7fbdd4604280,0,0,0,17355253900417,17354557238840,17355396879913,17355396996993
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,208139,208139,32768,256,0,0,12,24,13888,0x0,0x7fbdd4623f80,0,0,0,17355402176137,17355396879913,17355402306797,17355402311693
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,208139,208139,4194304,256,0,0,12,24,14336,0x7fbdf30f6380,0x7fbdd4623fc0,0,0,0,17355402345302,17355402306797,17355402676558,17355402679014
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/SQ_INST_LEVEL_SMEM.csv
index ff07e04dcc..f473ba8daf 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/SQ_INST_LEVEL_SMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,206069,206069,33554432,256,0,0,4,32,4160,0x0,0x7fd4d7204280,3670016,3108234,348352984,17334968515481,17329900548710,17335117324819,17335117440069
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,206069,206069,32768,256,0,0,12,24,13888,0x0,0x7fd4d7223f80,512,95104,10667584,17335122621942,17335117324819,17335122750907,17335122755808
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,206069,206069,4194304,256,0,0,12,24,14336,0x7fd4da170380,0x7fd4d7223fc0,65536,625284,70022568,17335122790767,17335122750907,17335123118748,17335123121248
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/SQ_INST_LEVEL_VMEM.csv
index 1f0eadb278..66505920da 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/SQ_INST_LEVEL_VMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,207917,207917,33554432,256,0,0,4,32,4160,0x0,0x7ff54c204280,524288,5490003,614888704,17354329285041,17352075152262,17354476649922,17354476742662
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,207917,207917,32768,256,0,0,12,24,13888,0x0,0x7ff54c223f80,4096,38964,4359388,17354481900826,17354476649922,17354482028645,17354482033612
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,207917,207917,4194304,256,0,0,12,24,14336,0x7ff56a9d1380,0x7ff54c223fc0,524288,10857982,1216044208,17354482068181,17354482028645,17354482412005,17354482414992
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/SQ_LEVEL_WAVES.csv
index 5ae81f2d79..c7483f4e0d 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/SQ_LEVEL_WAVES.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,206513,206513,33554432,256,0,0,4,32,4160,0x0,0x7fd82ca04280,381343,381343,8981,3050752,524288,239919456,2962542,0,975899640,17336850338375,17336133839148,17336997386761,17336997497271
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,206513,206513,32768,256,0,0,12,24,13888,0x0,0x7fd82ca23f80,34251,34251,30792,274016,512,1814325,172534,0,7270928,17337002664734,17336997386761,17337002807885,17337002812960
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,206513,206513,4194304,256,0,0,12,24,14336,0x7fd82f967380,0x7fd82ca23fc0,164673,164673,13486,1317392,65536,85192702,1215418,0,342501352,17337002856539,17337002807885,17337003204845,17337003207389
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/pmc_perf.csv
index 20ab60be23..a87e365c89 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDI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],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBufferAligned.kd,0,0,0,207279,207279,33554432,256,0,0,4,32,4160,0x0,0x7fb03a804280,3064168,2977625,524288,38687083,241951559,392,224,0,383020,383020,38951216.0,38021451.0,10.0,4161835.0,31182477.0,30818505.0,38000368.0,37440822.0,3062457,2984023,383020,0,383020,0,12256640.0,9436523.0,0.0,0.0,0,0,616,0,4718592,4714953,112,3527,375133,0.0,0.0,0.0,524288.0,28509053.0,27784319.0,8025.0,524288.0,131072,524288,302,384144,2251,0,56.0,305.0,0.0,4194696.0,0,0,0,0,0,7340032,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,20156241.0,524288.0,0,384944,0,0,0,384944,0,0,0,384944,0,0,0,384944,0,0,0,384944,0,0,0,384944,0,0,0,384944,0,0,0,384944,0,0,0,384944,0,0,0,384944,0,0,0,384944,0,0,0,384944,0,0,0,384944,0,0,0,384944,0,0,0,384944,0,0,0,384944,0,0,0,384944,0,0,0,384944,0,0,0,384944,0,0,0,384944,0,0,0,384944,0,0,0,384944,0,0,0,384944,0,0,0,384944,0,0,0,384944,0,0,0,384944,0,0,0,384944,0,0,0,384944,0,0,0,384944,0,0,0,384944,0,0,0,384944,0,0,0,384944,0,0,0,0,0,0.0,21627107.0,168,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,34,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2,0,0,0,0,0,0,0,0,0,0,0,32,0,0,0,2,0,0,0,0,0,0,0,1,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,38,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,33,0,0,0,524288.0,0.0,0,43391,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,333,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,44805,129024,129024,0,0,129024,129024,0,0,129024,129024,0,184077,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,26796,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,1050,129024,129024,0,0,129024,129024,0,279786,129024,129024,0,0,129024,129024,0,0,129024,129024,0,44894,129024,129024,0,832,129024,129024,0,0,129024,129024,0,0,129024,129024,0,645,129024,129024,524288.0,0.0,43465,0,0,50497522,45029,0,0,50612938,44234,0,0,50091400,46794,0,0,51853174,45403,0,0,51408664,45779,0,0,51507088,45049,0,0,50948786,47709,0,0,52904366,44878,0,0,50881804,46420,0,0,51016847,44204,0,0,50164943,48028,0,0,52382394,45832,0,0,51494549,46208,0,0,51179712,45715,0,0,51197781,48558,0,0,53185756,44371,0,0,50450442,45571,0,0,50591601,43554,0,0,50098800,48089,0,0,52176186,46244,0,0,51803176,45091,0,0,51145103,45540,0,0,51050280,47684,0,0,52823269,45241,0,0,50831546,45917,0,0,51137759,45278,0,0,50441399,47296,0,0,52253248,46008,0,0,51645698,46741,0,0,51675917,46083,0,0,51286175,49513,0,0,53203695,0.0,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65568,32,131104,65646,65539,113,131185,65536,65537,1,131073,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65568,32,131104,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65571,35,131107,65758,65538,224,131296,65536,65593,57,131129,65591,65537,56,131128,65536,65536,0,131072,65536,65536,0,131072,65536,65648,112,131184,65536,65536,0,131072,65536,65536,0,131072,65536,65568,32,131104,65591,65537,56,131128,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131184,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131296,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131128,0,131072,1287592,0,524288,3670016,3663117,224,6675,1048576,33554432.0,33554432.0,0.0,33554432.0,30252779.0,28607477.0,0.0,524288.0,225684,536109,8527,920,0,386369,4195054.0,0.0,2097594.0,2097460.0,1048576,1048576,0,524288,0,524288,7340032,0,0.0,0.0,104.0,8388608.0,29790190.0,2097152.0,0.0,207477,0,1254,385498,0,751.0,4194304.0,0.0,2064387.0,25690112,9437184,0,0,0,0,0,0,13305.0,8242253.0,0.0,8388608.0,2097152.0,4194304.0,9795239,0,0,8687,4128768.0,4128768.0,0.0,1493819.0,0,0,0,0,0,0,5767168,1048576,320329506.0,0.0,1487910893.0,0.0,26.0,0.0,0,0,377929,0.0,0.0,1526955.0,0.0,3670016,524288,0,0,0,2621440,524288,179088581,4194304.0,0.0,0.0,0.0,0.0,1149845.0,0,0,0.0,308.0,0.0,600.0,42935015,24117248,0,0,9437184,11010048,0,3145728,0.0,0.0,0.0,0.0,0.0,0.0,0,1572864,0.0,0.0,0.0,198629.0,524288,524288,0,3670016,7340032,603979776,4718592,0,0.0,0.0,0.0,0.0,0.0,0.0,524288,0,2064384.0,0.0,2031623.0,0.0,0,0,524288,0,0,0,0,33554432,0.0,4194304.0,0.0,18878785.0,0.0,0.0,140.0,4128768.0,990634.0,1700961698.0,17338293408453,17356069295347,17356069536147,17338440433683
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,207279,207279,32768,256,0,0,12,24,13888,0x0,0x7fb03a823f80,265080,159164,512,1375199,1741481,504,56,0,33134,33134,2302229.0,166604.0,171.0,0.0,37756.0,34819.0,160348.0,141549.0,265072,166276,33134,0,33134,0,1060288.0,384260.0,0.0,0.0,0,0,560,0,8192,6230,56,1906,23011,0.0,0.0,0.0,4096.0,32027.0,30586.0,0.0,4096.0,128,512,302,32054,2222,0,0.0,60.0,0.0,4600.0,0,0,0,0,0,1024,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,12775.0,4096.0,0,33515,0,0,0,33515,0,0,0,33515,0,0,0,33515,0,0,0,33515,0,0,0,33515,0,0,0,33515,0,0,0,33515,0,0,0,33515,0,0,0,33515,0,0,0,33515,0,0,0,33515,0,0,0,33515,0,0,0,33515,0,0,0,33515,0,0,0,33515,0,0,0,33515,0,0,0,33515,0,0,0,33515,0,0,0,33515,0,0,0,33515,0,0,0,33515,0,0,0,33515,0,0,0,33515,0,0,0,33515,0,0,0,33515,0,0,0,33515,0,0,0,33515,0,0,0,33515,0,0,0,33515,0,0,0,33515,0,0,0,33515,0,0,0,0,0,0.0,0.0,312,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,261,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,258,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,258,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,4096.0,4096.0,0,113755,0,0,0,78894,0,0,0,78273,0,0,0,80225,0,0,0,79887,0,0,0,78866,0,0,0,103956,0,0,0,88479,0,0,0,78899,0,0,0,76703,0,0,0,76716,0,0,0,86171,0,0,0,677214,0,0,0,83008,0,0,0,78790,0,0,0,89615,0,0,0,80729,0,0,0,80352,0,0,0,78342,0,0,0,135052,0,0,0,80714,0,0,0,80520,0,0,0,81070,0,0,0,111973,0,0,0,103644,0,0,0,79040,0,0,0,74200,0,0,0,82310,0,0,0,78650,0,0,0,82887,0,0,0,86354,0,0,0,85665,0,0,0.0,0.0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4096.0,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,222,131,353,353,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,222,130,352,352,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,129,129,129,0,128,128,128,55,130,185,185,0,128,128,128,0,128,128,128,0,128,128,128,0,184,184,184,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,352,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,352,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,184,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,680,0,0,512,0,56,456,0,65536.0,65536.0,65536.0,0.0,0.0,0.0,0.0,0.0,4,516,11441,995,0,30773,4661.0,0.0,499.0,4162.0,512,0,0,0,4096,4096,512,0,0.0,0.0,104.0,16384.0,0.0,16384.0,4096.0,0,0,1349,31284,0,4660.0,0.0,0.0,31.0,35328,26112,0,0,0,0,0,0,104.0,15240.0,0.0,16384.0,16384.0,0.0,0,0,0,29982,0.0,0.0,0.0,0.0,0,0,0,0,0,0,10752,3584,4939712.0,6571415.0,0.0,8192.0,0.0,0.0,0,0,496,0.0,0.0,0.0,0.0,512,4096,0,0,0,512,512,1610588,0.0,0.0,0.0,0.0,0.0,1533.0,0,0,0.0,8262.0,0.0,122.0,14756,32256,0,0,26112,1024,0,1024,0.0,0.0,0.0,0.0,0.0,0.0,0,1024,0.0,0.0,0.0,36115.0,4096,0,4096,512,512,1671168,8192,0,0.0,0.0,0.0,0.0,0.0,0.0,512,0,0.0,0.0,0.0,0.0,0,0,512,0,0,0,0,32768,8192.0,0.0,0.0,127613.0,0.0,4096.0,8206.0,0.0,3281156.0,0.0,17338446690197,17356074359028,17356074372468,17338447167265
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,207279,207279,4194304,256,0,0,12,24,14336,0x7fb03d8e9380,0x7fb03a823fc0,1323104,1223513,65536,15806709,89208185,392,56,0,165387,165387,16136770.0,14601997.0,24402.0,639874.0,14358954.0,14307687.0,14595704.0,12460549.0,1323096,1230302,165387,0,165387,0,5292384.0,4758860.0,0.0,0.0,0,0,448,0,917504,913945,0,3559,153373,0.0,0.0,0.0,524288.0,14408121.0,14405199.0,2096.0,524288.0,16384,65536,302,164200,2295,0,0.0,181.0,0.0,1048968.0,0,0,0,0,0,131072,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,11705265.0,524288.0,0,164596,0,0,0,164596,0,0,0,164596,0,0,0,164596,0,0,0,164596,0,0,0,164596,0,0,0,164596,0,0,0,164596,0,0,0,164596,0,0,0,164596,0,0,0,164596,0,0,0,164596,0,0,0,164596,0,0,0,164596,0,0,0,164596,0,0,0,164596,0,0,0,164596,0,0,0,164596,0,0,0,164596,0,0,0,164596,0,0,0,164596,0,0,0,164596,0,0,0,164596,0,0,0,164596,0,0,0,164596,0,0,0,164596,0,0,0,164596,0,0,0,164596,0,0,0,164596,0,0,0,164596,0,0,0,164596,0,0,0,164596,0,0,0,0,0,0.0,0.0,65592,0,14366,0,65536,0,14304,0,65536,0,13292,0,65537,0,8985,0,65536,0,33470,0,65537,0,14089,0,65536,0,29614,0,65536,0,11775,0,65536,0,8533,0,65536,0,8513,0,65539,0,6419,0,65536,0,14175,0,65536,0,11199,0,65536,0,14014,0,65536,0,20314,0,65536,0,20880,0,65537,0,23438,0,65536,0,19257,0,65536,0,14070,0,65536,0,13247,0,65536,0,16433,0,65536,0,13383,0,65595,0,14981,0,65539,0,10711,0,65540,0,12366,0,65536,0,14280,0,65536,0,14648,0,65536,0,9180,0,65536,0,12041,0,65536,0,24877,0,65536,0,17960,0,65595,0,26835,0,524288.0,524288.0,0,39344217,0,0,0,38878406,0,0,0,44026455,0,0,0,47059530,0,0,0,41678538,0,0,0,46662210,0,0,0,49512951,0,0,0,46898371,0,0,0,40637834,0,0,0,38889701,0,0,0,37434923,0,0,0,46502468,0,0,0,41562503,0,0,0,47259184,0,0,0,45699678,0,0,0,46659818,0,0,0,45214885,0,0,0,40695233,0,0,0,39669876,0,0,0,46973625,0,0,0,47816252,0,0,0,46533716,0,0,0,48715327,0,0,0,40494669,0,0,0,39234750,0,0,0,41389203,0,0,0,41401403,0,0,0,41470696,0,0,0,41045946,0,0,0,45498618,0,0,0,46892323,0,0,0,44200603,0,0,0.0,0.0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,524288.0,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32769,32769,32769,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32769,32769,32769,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32769,32769,32769,0,32826,32826,32826,0,32768,32768,32768,166,32771,32937,32937,222,32770,32992,32992,0,32768,32768,32768,0,32768,32768,32768,0,32824,32824,32824,0,32768,32768,32768,0,32768,32768,32768,0,32830,32830,32830,0,32768,32768,32768,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32936,0,0,32992,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,903572,0,0,65536,63800,56,1680,0,8388608.0,8388608.0,8388608.0,0.0,0.0,0.0,0.0,0.0,125360,146659,10132,2549,0,162758,1049151.0,0.0,388.0,1048763.0,65536,0,0,0,524288,524288,131072,0,0.0,0.0,104.0,2097152.0,0.0,2097152.0,524288.0,58138,0,2843,161386,0,1049145.0,0.0,0.0,31.0,4063232,2883584,0,0,0,0,0,0,6603.0,2027040.0,0.0,2097152.0,2097152.0,0.0,1274298,0,0,13703,0.0,0.0,0.0,0.0,262144,0,0,0,0,0,1507328,458752,1006696037.0,2239140883.0,0.0,2097152.0,57.0,0.0,0,0,147990,0.0,0.0,0.0,0.0,65536,524288,0,0,0,65536,65536,48412312,0.0,0.0,0.0,0.0,0.0,12442.0,0,0,0.0,2097344.0,0.0,370.0,36964324,3735552,0,0,2883584,196608,0,131072,0.0,0.0,0.0,0.0,0.0,0.0,0,131072,0.0,0.0,686740.0,2036363.0,524288,0,524288,65536,131072,184549376,917504,0,0.0,0.0,0.0,0.0,0.0,0.0,65536,0,0.0,0.0,983048.0,0.0,0,0,65536,0,0,0,0,4194304,2097152.0,0.0,0.0,12338885.0,0.0,524288.0,2097288.0,0.0,1468985539.0,0.0,17338448263716,17356074454708,17356074547348,17338449048185
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/prev_analysis/1.csv
index 52e50540bd..ca5c1891af 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,3357121.0,3357121.0,3357121.0,7.844852680402149
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,1725121.0,1725121.0,1725121.0,4.031227978040719
 "void benchmark_func<double, 256, 8u, 512u>(double, double*) [clone .kd]",1,1715680.0,1715680.0,1715680.0,4.009166439551139
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/prev_analysis/1001.csv
index f475f954a6..fb5988001a 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,494.8622754491018,Instr per wave
 VMEM,7.958083832335329,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,0.0,Instr per wave
 SALU,24.520958083832337,Instr per wave
 SMEM,1.8023952095808384,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/prev_analysis/101.csv
index 61689dfb92..7b8c662962 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx90a
 mi200
 56
 1638.4
-roofline|SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+roofline|SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/prev_analysis/1202.csv
index 81cb1d07d1..1b50d6d348 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,18358.228336128646,1845.9439010620117,258547.47912597656,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/prev_analysis/1901.csv
index f28762af47..45741c83fe 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,2.0,smem_
 VALU,495.0,valu_
 MFMA,0.0,mfma_
 VMEM,8.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,10.0,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,67894.0,wavefronts_
 Workgroups,16973.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,128.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,0.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,44.0,hbm_rd_
 HBM Wr,0.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,70.0,vl1_coales_
 VL1 Stall,2.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,26.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/prev_analysis/201.csv
index ce6b8a3c34..bfe7d8d416 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,58.438695311565574,Pct,100,58.438695311565574
 MFMA Util,0.0,Pct,100,0.0
 VALU Active Threads/Wave,64.0,Threads,64,100.0
 IPC - Issue,1.0,Instr/cycle,5,20.0
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99262226771893,Pct,100,99.99262226771893
 Instr Cache BW,1674.3011342593545,Gb/s,6092.8,27.479994981935306
 Scalar L1D Cache Hit Rate,99.34855885867488,Pct,100,99.34855885867488
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/prev_analysis/602.csv
index cab4fdf941..955e352af6 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,12167920.431137724,0,375186637,Simd
 Insufficient SIMD VGPRs,0.0,0,0,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/prev_analysis/701.csv
index 12250d77c0..db0925a109 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/sysinfo.csv
index 1f929c9de9..2f60645e6f 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-Axes2,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:42:15 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,roofline|SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+Axes2,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:42:15 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,roofline|SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/timestamps.csv
index 8f7e94854e..cc8e0adcd4 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes2/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,208222,208222,33554432,256,0,0,4,32,4160,0x0,0x7f3476804280,17356069269547,17356069295347,17356069536147,17356069651727
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,208222,208222,32768,256,0,0,12,24,13888,0x0,0x7f3476823f80,17356074343033,17356074359028,17356074372468,17356074389822
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,208222,208222,4194304,256,0,0,12,24,14336,0x7f34797dd380,0x7f3476823fc0,17356074394882,17356074454708,17356074547348,17356074549478
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/SQ_IFETCH_LEVEL.csv
index 6077ecbc3b..084beb6279 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/SQ_IFETCH_LEVEL.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,909520,909525,33554432,256,0,0,8,32,6464,0x0,0x7fe829004180,503321,503321,524288,6291456,793537,101537344,12076108055286022,12076108302996961,12076108303320479,12076108303432952
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,909520,909525,32768,256,0,0,24,24,12480,0x0,0x7fe829035100,28673,28673,512,8192,8944,1142220,12076108317782961,12076108318107515,12076108318114555,12076108318122752
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,909520,909525,4194304,256,0,0,24,24,12928,0x7fe934bda900,0x7fe829035140,226268,226268,65536,917504,141153,18044408,12076108318186060,12076108318412154,12076108318550713,12076108318555196
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/SQ_INST_LEVEL_LDS.csv
index dd47d1b47e..86e351455a 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/SQ_INST_LEVEL_LDS.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,911318,911323,33554432,256,0,0,8,32,6464,0x0,0x7fd3d5804180,0,0,0,12076134384262348,12076134622186182,12076134622511940,12076134622624233
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,911318,911323,32768,256,0,0,24,24,12480,0x0,0x7fd3d5835100,0,0,0,12076134637155819,12076134637454058,12076134637461418,12076134637466817
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,911318,911323,4194304,256,0,0,24,24,12928,0x7fd4e1490900,0x7fd3d5835140,0,0,0,12076134637527059,12076134637740777,12076134637880296,12076134637884283
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/SQ_INST_LEVEL_SMEM.csv
index 3ff619e488..ca0c6748f1 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/SQ_INST_LEVEL_SMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,910940,910945,33554432,256,0,0,8,32,6464,0x0,0x7fbb29204180,4194304,3072326,393422784,12076131878204691,12076132121676698,12076132122000377,12076132122110910
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,910940,910945,32768,256,0,0,24,24,12480,0x0,0x7fbb29235100,512,21876,2797384,12076132136823112,12076132137121587,12076132137127667,12076132137132998
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,910940,910945,4194304,256,0,0,24,24,12928,0x7fbc34dd9900,0x7fbb29235140,65536,180780,23110632,12076132137192027,12076132137407986,12076132137546225,12076132137550373
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/SQ_INST_LEVEL_VMEM.csv
index 20c00a1f3e..be3c16e5d4 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/SQ_INST_LEVEL_VMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,911130,911135,33554432,256,0,0,8,32,6464,0x0,0x7fce0e804180,1048576,11191210,1432779132,12076133128428015,12076133372836595,12076133373159633,12076133373271216
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,911130,911135,32768,256,0,0,24,24,12480,0x0,0x7fce0e835100,4096,139531,17848416,12076133387891056,12076133388179520,12076133388186400,12076133388191895
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,911130,911135,4194304,256,0,0,24,24,12928,0x7fcf1a4b7900,0x7fce0e835140,524288,13108593,1678007364,12076133388256235,12076133388466559,12076133388596478,12076133388600154
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/SQ_LEVEL_WAVES.csv
index 48a5202a8a..464ef34b18 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/SQ_LEVEL_WAVES.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,911507,911514,33554432,256,0,0,8,32,6464,0x0,0x7f1631e04180,502997,502997,16972,4023984,524288,370817117,3823622,0,1498078928,12076135631582317,12076135876277375,12076135876600893,12076135876709715
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,911507,911514,32768,256,0,0,24,24,12480,0x0,0x7f1631e35100,27681,27681,20333,221456,512,1086316,73178,0,4359244,12076135891263753,12076135891585458,12076135891591698,12076135891600299
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,911507,911514,4194304,256,0,0,24,24,12928,0x7f173da09900,0x7f1631e35140,219780,219780,20940,1758248,65536,130207192,1588334,0,522643840,12076135891675879,12076135891912816,12076135892046576,12076135892050806
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/pmc_dispatch_info.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/pmc_perf.csv
index e21dbdff84..fc00521d9a 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBuffer.kd,0,0,0,910254,910259,33554432,256,0,0,8,32,6464,0x0,0x7fc3f4e04180,1048576,0,1048576,9437184,0,4194304,1048576,0,500389,500389,57469791,55024259,230,13434002,54212058,54119544,54983448,53800792,4003112,3815778,500389,0,500389,0,16012448,15164400,0,0,0,0,0,17382056,1048576,0,503901,0,0,0,503901,0,0,0,503901,0,0,0,503901,0,0,0,503901,0,0,0,503901,0,0,0,503901,0,0,0,503901,0,0,0,503901,0,0,0,503901,0,0,0,503901,0,0,0,503901,0,0,0,503901,0,0,0,503901,0,0,0,503901,0,0,0,503901,0,0,0,503901,0,0,0,503901,0,0,0,503901,0,0,0,503901,0,0,0,503901,0,0,0,503901,0,0,0,503901,0,0,0,503901,0,0,0,503901,0,0,0,503901,0,0,0,503901,0,0,0,503901,0,0,0,503901,0,0,0,503901,0,0,0,503901,0,0,0,503901,0,0,0,37697002,2741,0,0,0,7,0,0,0,0,0,0,0,48,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,2703,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,25,0,0,0,3,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,48,0,0,0,0,0,0,0,2418,0,0,0,0,0,0,0,0,0,0,0,48,0,0,0,2581,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1048576,0,0,0,131076,131076,0,1469,131080,131080,0,0,131076,131076,0,3236322,131076,131076,0,0,131072,131072,0,0,131072,131072,0,271,131072,131072,0,0,131072,131072,0,5212,131072,131072,0,1497,131076,131076,0,0,131076,131076,0,0,131076,131076,0,0,131072,131072,0,21520,131072,131072,0,0,131072,131072,0,3099787,131080,131080,0,0,131072,131072,0,783,131080,131080,0,536260,131072,131072,0,3066037,131072,131072,0,0,131080,131080,0,0,131076,131076,0,14590,131076,131076,0,0,131076,131076,0,258,131072,131072,0,0,131076,131076,0,0,131072,131072,0,0,131072,131072,0,0,131072,131072,0,0,131072,131072,0,0,131076,131076,0,3237110,131076,131076,1048576,0,1078,0,0,17222071,905,0,0,17304607,748,0,0,17533702,44794,0,0,29360160,999,0,0,17334788,1086,0,0,17232559,1025,0,0,18366472,50329,0,0,31723241,706,0,0,17140097,800,0,0,17093972,731,0,0,17583742,1005,0,0,16722336,1120,0,0,17271979,1363,0,0,17528946,1169,0,0,18161349,886,0,0,18470006,869,0,0,16575103,1822,0,0,17108845,912,0,0,17145945,1702,0,0,16793749,1183,0,0,17433426,1724,0,0,17334322,801,0,0,18262052,982,0,0,18393614,860,0,0,16802668,1010,0,0,16536714,1404,0,0,17240536,44673,0,0,29386279,964,0,0,17150649,998,0,0,17127402,1139,0,0,18628315,48222,0,0,31500395,1048576,131072,131072,0,262144,131260,131124,240,262384,131072,131072,0,262144,131072,133705,2633,264777,131072,131073,1,262145,131072,131072,0,262144,131072,131072,0,262144,131119,133658,2633,264777,131072,131073,1,262145,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131089,17,262161,131072,131072,0,262144,131213,131075,144,262288,131072,131072,0,262144,131072,133527,2455,264599,131072,131072,0,262144,131072,131072,0,262144,131119,131073,48,262192,131072,131072,0,262144,131072,131073,1,262145,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131075,3,262147,131072,131121,49,262193,131072,131072,0,262144,131072,133758,2686,264830,262144,0,262144,262336,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262288,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,0,0,3145728,524288,32505856,371347351,219043937,119797558,479800,0,0,0,1048576,52582505,52367756,1048576,1048576,131072,524288,728,502542,4468,0,96,10619,0,8388944,32505856,3994104,3798018,56848624,11534336,0,0,14155776,67108864,67108864,0,67108864,54215685,53921872,0,1048576,235541,759829,11651,1997,0,494986,8399572,0,4194727,4204845,13631488,0,3670016,1048576,1048576,0,4194304,9437184,0,0,360,33554432,54072815,4194304,0,0,3049,501374,0,11257,8388608,0,4194400,905969664,6291456,0,0,0,524288,524288,0,15329,16608714,0,16777216,4194304,4194304,0,0,0,16671,4194356,4194356,0,224030,0,0,0,33554432,0,0,0,0,627990253,0,2767737563,0,0,0,0,0,474231,0,0,219386,0,0,8388608,336,144,0,0,0,480,8388608,0,0,0,0,255632,0,0,0,10886,0,21754,0,6291456,6289390,96,2323,2026154,0,0,0,0,0,0,0,0,0,3145728,0,0,0,152186,4194304,4189863,144,4297,2097152,524288,1572864,0,0,0,0,0,0,524288,0,4128833,65536,4063247,0,0,8388608,0,42342903,0,1048576,10674,4194380,13014142,611484541,12076110187039381,12076136765433491,12076136765754608,12076110431736399
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,910254,910259,32768,256,0,0,24,24,12480,0x0,0x7fc3f4e35100,0,4096,4096,512,0,512,4096,0,29060,29060,1513847,602997,226,134722,86233,66377,594928,574431,232480,86743,29060,0,29060,0,929920,205083,0,0,0,0,0,111206,4096,0,28168,0,0,0,28168,0,0,0,28168,0,0,0,28168,0,0,0,28168,0,0,0,28168,0,0,0,28168,0,0,0,28168,0,0,0,28168,0,0,0,28168,0,0,0,28168,0,0,0,28168,0,0,0,28168,0,0,0,28168,0,0,0,28168,0,0,0,28168,0,0,0,28168,0,0,0,28168,0,0,0,28168,0,0,0,28168,0,0,0,28168,0,0,0,28168,0,0,0,28168,0,0,0,28168,0,0,0,28168,0,0,0,28168,0,0,0,28168,0,0,0,28168,0,0,0,28168,0,0,0,28168,0,0,0,28168,0,0,0,28168,0,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,304,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,261,0,0,0,256,0,0,0,377,0,0,0,256,0,0,0,261,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,304,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,4096,4096,0,205196,0,0,0,151238,0,0,0,123911,0,0,0,96802,0,0,0,134273,0,0,0,206844,0,0,0,110656,0,0,0,98294,0,0,0,165387,0,0,0,89549,0,0,0,89239,0,0,0,85552,0,0,0,80250,0,0,0,113576,0,0,0,64353,0,0,0,67195,0,0,0,155820,0,0,0,95692,0,0,0,75560,0,0,0,86793,0,0,0,168030,0,0,0,129937,0,0,0,122202,0,0,0,91957,0,0,0,82153,0,0,0,71839,0,0,0,84391,0,0,0,108023,0,0,0,81267,0,0,0,100898,0,0,0,129224,0,0,0,94239,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4096,0,256,256,256,0,304,304,304,0,256,256,256,0,256,256,256,0,257,257,257,0,256,256,256,0,256,256,256,47,257,304,304,0,257,257,257,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,188,260,448,448,0,376,376,376,0,256,256,256,0,256,256,256,188,260,448,448,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,257,257,257,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,257,257,257,47,257,304,304,0,256,256,256,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,304,0,0,256,0,0,0,0,512,512,35328,1086221,1004189,45680,11302,0,0,0,4096,121709,119090,4096,4096,128,512,638,27153,4319,0,48,173,0,8624,36352,219240,75449,1068241,26624,0,0,30208,65536,65536,65536,0,0,0,0,0,116,628,11734,1953,0,23194,8891,0,470,8421,1024,0,1024,4096,0,4096,512,512,0,0,360,16384,0,16384,0,0,2941,24801,0,8892,0,0,31,1933312,8192,0,0,0,512,512,0,120,15064,0,16384,16384,0,0,0,0,21052,0,0,0,0,0,0,0,32768,0,0,0,0,12148126,16912923,0,8192,0,0,0,0,696,0,0,0,0,0,1024,432,48,0,0,0,480,0,0,0,0,0,2336,0,0,0,8421,0,438,0,8192,6572,48,1572,1056,0,0,0,0,0,0,0,0,0,2560,0,0,0,50001,512,0,48,464,0,512,0,0,0,0,0,0,0,512,0,0,0,0,0,8192,0,0,431551,0,4096,8373,0,3416589,0,12076110446702223,12076136780918025,12076136780924425,12076110447700849
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,910254,910259,4194304,256,0,0,24,24,12928,0x7fc5009d1900,0x7fc3f4e35140,0,524288,524288,65536,0,65536,524288,0,222725,222725,24676697,23491106,30361,8426575,22037394,21808096,23475200,21311463,1781800,1629119,222725,0,222725,0,7127200,6407481,0,0,0,0,0,19466468,524288,0,213276,0,0,0,213276,0,0,0,213276,0,0,0,213276,0,0,0,213276,0,0,0,213276,0,0,0,213276,0,0,0,213276,0,0,0,213276,0,0,0,213276,0,0,0,213276,0,0,0,213276,0,0,0,213276,0,0,0,213276,0,0,0,213276,0,0,0,213276,0,0,0,213276,0,0,0,213276,0,0,0,213276,0,0,0,213276,0,0,0,213276,0,0,0,213276,0,0,0,213276,0,0,0,213276,0,0,0,213276,0,0,0,213276,0,0,0,213276,0,0,0,213276,0,0,0,213276,0,0,0,213276,0,0,0,213276,0,0,0,213276,0,0,0,0,65536,0,3008,0,65536,0,1430,0,65540,0,9903,0,65584,0,0,0,65536,0,4935,0,65536,0,1547,0,65537,0,6301,0,65536,0,2776,0,65536,0,2168,0,65536,0,4019,0,65536,0,2389,0,65536,0,4025,0,68002,0,82219,0,65536,0,4816,0,65537,0,5482,0,65536,0,2589,0,65771,0,8112,0,65536,0,1247,0,65537,0,2582,0,65536,0,3247,0,65536,0,4992,0,65536,0,2913,0,65584,0,2776,0,65536,0,3308,0,65536,0,252,0,65536,0,95,0,65536,0,3752,0,65536,0,259,0,67411,0,57656,0,65536,0,276,0,65540,0,1061,0,65536,0,480,0,524288,524288,0,36326311,0,0,0,36044121,0,0,0,34840193,0,0,0,40110412,0,0,0,31397591,0,0,0,36194966,0,0,0,37647029,0,0,0,39313450,0,0,0,34650943,0,0,0,33632310,0,0,0,32860172,0,0,0,33718520,0,0,0,31606244,0,0,0,33362338,0,0,0,33047349,0,0,0,39656906,0,0,0,38641251,0,0,0,33985973,0,0,0,33972120,0,0,0,53932702,0,0,0,40776779,0,0,0,39418825,0,0,0,30732173,0,0,0,38835216,0,0,0,34687203,0,0,0,33052801,0,0,0,32937903,0,0,0,31329126,0,0,0,34266702,0,0,0,35287774,0,0,0,35401965,0,0,0,31499889,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,524288,0,65536,65536,65536,0,65584,65584,65584,188,65540,65728,65728,0,66872,66872,66872,0,65537,65537,65537,0,65536,65536,65536,0,65536,65536,65536,47,65537,65584,65584,0,65537,65537,65537,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65656,65656,65656,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65971,65971,65971,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65537,65537,65537,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65537,65537,65537,188,65540,65728,65728,0,65536,65536,65536,65536,0,0,65536,0,0,65728,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65728,0,0,65536,0,0,0,0,65536,65536,4128768,149441047,51373183,93808024,199923,0,0,0,524288,22706042,22703259,524288,524288,16384,65536,778,217941,4145,0,48,2986,0,2097536,4259840,1737552,1562856,23207300,3014656,0,0,3473408,8388608,8388608,8388608,0,0,0,0,0,198781,222130,11865,2003,0,212906,2100178,0,423,2099755,131072,0,131072,524288,0,524288,65536,65536,0,0,360,2097152,0,2097152,33166,0,2784,223963,0,2102004,0,0,31,222298112,917504,0,0,0,65536,65536,0,7486,2016651,0,2097152,2097152,0,622478,624357,0,20738,0,0,0,0,0,0,0,4194304,0,0,0,0,895265231,1361701462,0,2097152,0,0,0,0,201240,0,0,0,0,0,131072,384,48,0,0,0,432,0,0,0,0,0,16542,0,0,0,2100254,0,6186,0,917504,914945,48,7255,200206,0,0,0,0,0,0,0,0,0,327680,0,0,648539,701723,65536,64048,48,1440,0,65536,0,0,0,0,0,0,0,65536,0,0,0,1966105,0,2097152,0,0,14091845,0,524288,2101782,0,880348049,0,12076110448330689,12076136780988904,12076136781126183,12076110449585040
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/prev_analysis/1.csv
index f9ce164aa1..7a69ccdce3 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,6051953.0,6051953.0,6051953.0,9.186186363820095
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4526685.0,4526685.0,4526685.0,6.871000488653658
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 256u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,3049736.0,3049736.0,3049736.0,4.629157439995196
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/prev_analysis/1001.csv
index ca08330db0..0e3bf5267e 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,46.862275449101794,Instr per wave
 SMEM,1.8083832335329342,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/prev_analysis/101.csv
index f8ca26222c..7b89a5ad0e 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx908
 mi100
 48
 1228.8
-SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/prev_analysis/1202.csv
index ed330bd4c8..e97539fd54 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,33594.84124093427,2833.155448913574,547895.4530029297,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/prev_analysis/1901.csv
index 11c865ee98..469a994125 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,2.0,smem_
 VALU,735.0,valu_
 MFMA,,mfma_
 VMEM,8.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,22.0,br_
 VGPR,24.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,67894.0,wavefronts_
 Workgroups,16973.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,163.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,0.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,44.0,hbm_rd_
 HBM Wr,0.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,70.0,vl1_coales_
 VL1 Stall,28.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,34.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/prev_analysis/2001.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/prev_analysis/201.csv
index 96e4e6fe8c..450bfe62bd 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,59.26121204471573,Pct,100,59.26121204471573
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,63.96764040562569,Threads,64,99.94943813379014
 IPC - Issue,0.8437242718470235,Instr/cycle,5,16.874485436940468
-LDS BW,0.0,Gb/sec,23070.72,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,23070.72,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99349012530601,Pct,100,99.99349012530601
 Instr Cache BW,1412.884356723283,Gb/s,4614.144,30.62072524661742
 Scalar L1D Cache Hit Rate,99.35620448527392,Pct,100,99.35620448527392
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/prev_analysis/602.csv
index 411aea9c54..fc78f2e84a 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,60134.077844311374,0,622478,Simd
 Insufficient SIMD VGPRs,601408.7185628742,0,40245662,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/prev_analysis/701.csv
index d3f1bff5a3..1071413faa 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,23.976047904191617,8,36,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/sysinfo.csv
index 51f32e775d..9d71b2e980 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-Axes3,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 11:28:03 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+Axes3,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 11:28:03 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/timestamps.csv
index c197fa6153..fbcf13f6fe 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes3/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,911558,911563,33554432,256,0,0,8,32,6464,0x0,0x7f7f1e004180,12076136765385269,12076136765433491,12076136765754608,12076136765859220
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,911558,911563,32768,256,0,0,24,24,12480,0x0,0x7f7f1e035100,12076136780811589,12076136780918025,12076136780924425,12076136780930219
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,911558,911563,4194304,256,0,0,24,24,12928,0x7f8029b71900,0x7f7f1e035140,12076136780976144,12076136780988904,12076136781126183,12076136781129860
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/SQ_IFETCH_LEVEL.csv
index 0bcc007f59..e4405a3285 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/SQ_IFETCH_LEVEL.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,211749,211749,33554432,256,0,0,4,32,4160,0x0,0x7f820be04280,388008,388008,524288,4718592,680254,76306380,17414252801873,17413542112156,17414401629608,17414401745256
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,211749,211749,32768,256,0,0,12,24,13888,0x0,0x7f820be23f80,33769,33769,512,8192,6030,677892,17414406916492,17414401629608,17414407048166,17414407053268
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,211749,211749,4194304,256,0,0,12,24,14336,0x7f821a71d380,0x7f820be23fc0,166703,166703,65536,917504,144491,16197228,17414407090447,17414407048166,17414407430086,17414407432618
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/SQ_INST_LEVEL_LDS.csv
index b1ff262068..26a19715a9 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/SQ_INST_LEVEL_LDS.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,213597,213597,33554432,256,0,0,4,32,4160,0x0,0x7f841a404280,0,0,0,17433664805251,17432957069157,17433807278554,17433807370573
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,213597,213597,32768,256,0,0,12,24,13888,0x0,0x7f841a423f80,0,0,0,17433812524319,17433807278554,17433812649591,17433812654015
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,213597,213597,4194304,256,0,0,12,24,14336,0x7f841d3ae380,0x7f841a423fc0,0,0,0,17433812688524,17433812649591,17433813013911,17433813016086
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/SQ_INST_LEVEL_SMEM.csv
index d65b451aeb..e93561dd4a 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/SQ_INST_LEVEL_SMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,211527,211527,33554432,256,0,0,4,32,4160,0x0,0x7f4688204280,3670016,3054154,341857152,17413315644610,17404579624633,17413463333343,17413463447223
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,211527,211527,32768,256,0,0,12,24,13888,0x0,0x7f4688223f80,512,96322,10800192,17413468616208,17413463333343,17413468744548,17413468748994
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,211527,211527,4194304,256,0,0,12,24,14336,0x7f468b1cd380,0x7f4688223fc0,65536,621694,69634176,17413468781314,17413468744548,17413469103109,17413469105425
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/SQ_INST_LEVEL_VMEM.csv
index 21eb470436..c0834ca5da 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/SQ_INST_LEVEL_VMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,213375,213375,33554432,256,0,0,4,32,4160,0x0,0x7f594ea04280,524288,5456862,611187468,17432727256629,17430416272901,17432876170783,17432876284272
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,213375,213375,32768,256,0,0,12,24,13888,0x0,0x7f594ea23f80,4096,47128,5279028,17432881448727,17432876170783,17432881577657,17432881582104
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,213375,213375,4194304,256,0,0,12,24,14336,0x7f5951a95380,0x7f594ea23fc0,524288,10541605,1180657360,17432881616473,17432881577657,17432881946617,17432881949174
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/SQ_LEVEL_WAVES.csv
index d6aade9ba9..9c7959a1cf 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/SQ_LEVEL_WAVES.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,211971,211971,33554432,256,0,0,4,32,4160,0x0,0x7fd3c5604280,387706,387706,8932,3101656,524288,245392945,3014196,0,997841304,17415188858019,17414483478312,17415335506950,17415335618980
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,211971,211971,32768,256,0,0,12,24,13888,0x0,0x7fd3c5623f80,33327,33327,29902,266624,512,1689948,155440,0,6773228,17415340755436,17415335506950,17415340894791,17415340899472
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,211971,211971,4194304,256,0,0,12,24,14336,0x7fd3c85c9380,0x7fd3c5623fc0,165887,165887,13893,1327104,65536,70614185,1216513,0,284194924,17415340943411,17415340894791,17415341281992,17415341284272
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/pmc_perf.csv
index d3d5093c94..81bc212bd7 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDI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],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBufferAligned.kd,0,0,0,212737,212737,33554432,256,0,0,4,32,4160,0x0,0x7ff178a04280,3129328,3040631,524288,39505030,249299708,392,224,0,391165,391165,39770437.0,38767774.0,7.0,4264582.0,31935921.0,31583213.0,38745213.0,38183824.0,3127617,3047031,391165,0,391165,0,12517280.0,9559975.0,0.0,0.0,0,0,616,0,4718592,4714743,112,3737,376714,0.0,0.0,0.0,524288.0,28872201.0,28179427.0,8012.0,524288.0,131072,524288,302,385948,2327,0,56.0,302.0,0.0,4194696.0,0,0,0,0,0,7340032,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,20904718.0,524288.0,0,390991,0,0,0,390991,0,0,0,390991,0,0,0,390991,0,0,0,390991,0,0,0,390991,0,0,0,390991,0,0,0,390991,0,0,0,390991,0,0,0,390991,0,0,0,390991,0,0,0,390991,0,0,0,390991,0,0,0,390991,0,0,0,390991,0,0,0,390991,0,0,0,390991,0,0,0,390991,0,0,0,390991,0,0,0,390991,0,0,0,390991,0,0,0,390991,0,0,0,390991,0,0,0,390991,0,0,0,390991,0,0,0,390991,0,0,0,390991,0,0,0,390991,0,0,0,390991,0,0,0,390991,0,0,0,390991,0,0,0,390991,0,0,0,0,0,0.0,21790126.0,0,0,0,0,0,0,0,0,0,0,0,0,33,0,0,0,2,0,0,0,0,0,0,0,0,0,0,0,56,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,112,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,35,0,0,0,7,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,0,0,1,0,0,0,524288.0,0.0,0,42654,129024,129024,0,0,129024,129024,0,0,129024,129024,0,383,129024,129024,0,331,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,321818,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,1083,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,32069,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,547476,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,46344,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,390,129024,129024,524288.0,0.0,44900,0,0,51822114,46377,0,0,52095073,44995,0,0,51270318,47810,0,0,53031671,46400,0,0,52537536,47314,0,0,52794521,45507,0,0,51860342,48205,0,0,53686124,45470,0,0,52001266,47240,0,0,52387241,46510,0,0,52066404,48890,0,0,53569841,47534,0,0,53031336,48984,0,0,53171044,47964,0,0,52672257,50207,0,0,54477322,44474,0,0,51413878,46728,0,0,51977611,45002,0,0,51465526,47960,0,0,53404612,45489,0,0,52260587,46847,0,0,52565569,45404,0,0,51881200,49000,0,0,54076369,46763,0,0,52179377,47447,0,0,52260221,47007,0,0,52025147,48289,0,0,53396710,47684,0,0,53075868,48086,0,0,52966227,47467,0,0,52575369,50949,0,0,54446770,0.0,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65569,33,131105,65646,65538,112,131184,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65648,112,131184,65536,65536,0,131072,65536,65536,0,131072,65536,65568,32,131104,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65537,1,131073,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65569,33,131105,65758,65538,224,131296,65536,65536,0,131072,65536,65536,0,131072,65536,65537,1,131073,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65591,65537,56,131128,65536,65568,32,131104,65591,65593,112,131184,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131184,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131296,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131128,0,131072,1130920,0,524288,3670016,3663348,224,6444,1048576,33554432.0,33554432.0,0.0,33554432.0,30385103.0,28810894.0,0.0,524288.0,219948,537476,8691,894,0,385058,4195056.0,0.0,2097594.0,2097462.0,1048576,1048576,0,524288,0,524288,7340032,0,0.0,0.0,104.0,8388608.0,30031628.0,2097152.0,0.0,208010,0,1217,387000,0,748.0,4194304.0,0.0,2064387.0,25690112,9437184,0,0,0,0,0,0,13287.0,8242451.0,0.0,8388608.0,2097152.0,4194304.0,10125918,0,0,8694,4128768.0,4128768.0,0.0,1546995.0,0,0,0,0,0,0,5767168,1048576,319727103.0,0.0,1484852332.0,0.0,24.0,0.0,0,0,378533,0.0,0.0,1533750.0,0.0,3670016,524288,0,0,0,2621440,524288,178098540,4194304.0,0.0,0.0,0.0,0.0,1202530.0,0,0,0.0,310.0,0.0,604.0,43685469,24117248,0,0,9437184,11010048,0,3145728,0.0,0.0,0.0,0.0,0.0,0.0,0,1572864,0.0,0.0,0.0,189376.0,524288,524288,0,3670016,7340032,603979776,4718592,0,0.0,0.0,0.0,0.0,0.0,0.0,524288,0,2064384.0,0.0,2031623.0,0.0,0,0,524288,0,0,0,0,33554432,0.0,4194304.0,0.0,19031473.0,0.0,0.0,139.0,4128768.0,890061.0,1671132118.0,17416623737047,17434480811769,17434481051609,17416770060950
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,212737,212737,32768,256,0,0,12,24,13888,0x0,0x7ff178a23f80,266888,161561,512,1386414,1742120,504,56,0,33360,33360,2331654.0,146864.0,190.0,0.0,34860.0,31429.0,140588.0,121770.0,266880,168536,33360,0,33360,0,1067520.0,353996.0,0.0,0.0,0,0,560,0,8192,6084,56,2052,23796,0.0,0.0,0.0,4096.0,30193.0,28607.0,0.0,4096.0,128,512,302,33420,2278,0,0.0,59.0,0.0,4600.0,0,0,0,0,0,1024,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,15962.0,4096.0,0,33195,0,0,0,33195,0,0,0,33195,0,0,0,33195,0,0,0,33195,0,0,0,33195,0,0,0,33195,0,0,0,33195,0,0,0,33195,0,0,0,33195,0,0,0,33195,0,0,0,33195,0,0,0,33195,0,0,0,33195,0,0,0,33195,0,0,0,33195,0,0,0,33195,0,0,0,33195,0,0,0,33195,0,0,0,33195,0,0,0,33195,0,0,0,33195,0,0,0,33195,0,0,0,33195,0,0,0,33195,0,0,0,33195,0,0,0,33195,0,0,0,33195,0,0,0,33195,0,0,0,33195,0,0,0,33195,0,0,0,33195,0,0,0,0,0,0.0,0.0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,312,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,258,0,0,0,257,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,4096.0,4096.0,0,75630,0,0,0,75590,0,0,0,76738,0,0,0,82911,0,0,0,75160,0,0,0,81064,0,0,0,82941,0,0,0,134397,0,0,0,75016,0,0,0,86847,0,0,0,86439,0,0,0,86052,0,0,0,84588,0,0,0,83375,0,0,0,74990,0,0,0,97976,0,0,0,107117,0,0,0,77692,0,0,0,73868,0,0,0,80006,0,0,0,98363,0,0,0,82780,0,0,0,653292,0,0,0,89194,0,0,0,75070,0,0,0,76198,0,0,0,71202,0,0,0,117653,0,0,0,75561,0,0,0,87387,0,0,0,79126,0,0,0,102064,0,0,0.0,0.0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4096.0,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,222,130,352,352,0,128,128,128,0,128,128,128,0,128,128,128,0,184,184,184,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,222,130,352,352,0,128,128,128,0,128,128,128,0,129,129,129,0,128,128,128,0,128,128,128,0,128,128,128,0,129,129,129,0,128,128,128,55,129,184,184,0,128,128,128,0,129,129,129,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,352,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,352,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,184,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,662,0,0,512,0,56,456,0,65536.0,65536.0,65536.0,0.0,0.0,0.0,0.0,0.0,4,516,11424,1015,0,31143,4659.0,0.0,499.0,4160.0,512,0,0,0,4096,4096,512,0,0.0,0.0,104.0,16384.0,0.0,16384.0,4096.0,0,0,1304,31327,0,4659.0,0.0,0.0,31.0,35328,26112,0,0,0,0,0,0,104.0,15240.0,0.0,16384.0,16384.0,0.0,0,0,0,29197,0.0,0.0,0.0,0.0,0,0,0,0,0,0,10752,3584,4668062.0,5736085.0,0.0,8192.0,0.0,0.0,0,0,498,0.0,0.0,0.0,0.0,512,4096,0,0,0,512,512,1583435,0.0,0.0,0.0,0.0,0.0,1459.0,0,0,0.0,8261.0,0.0,120.0,14989,32256,0,0,26112,1024,0,1024,0.0,0.0,0.0,0.0,0.0,0.0,0,1024,0.0,0.0,0.0,52952.0,4096,0,4096,512,512,1671168,8192,0,0.0,0.0,0.0,0.0,0.0,0.0,512,0,0.0,0.0,0.0,0.0,0,0,512,0,0,0,0,32768,8192.0,0.0,0.0,126970.0,0.0,4096.0,8204.0,0.0,3332333.0,0.0,17416776269298,17434485775291,17434485788571,17416776758726
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,212737,212737,4194304,256,0,0,12,24,14336,0x7ff17b912380,0x7ff178a23fc0,1306984,1204157,65536,15569026,79567362,392,56,0,163372,163372,15885090.0,14449361.0,24800.0,664530.0,13654488.0,13467220.0,14443068.0,12304588.0,1306976,1210910,163372,0,163372,0,5227904.0,4713476.0,0.0,0.0,0,0,448,0,917504,913827,0,3677,156741,0.0,0.0,0.0,524288.0,14617420.0,14613440.0,2261.0,524288.0,16384,65536,302,167493,2287,0,0.0,163.0,0.0,1048968.0,0,0,0,0,0,131072,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,10309653.0,524288.0,0,174196,0,0,0,174196,0,0,0,174196,0,0,0,174196,0,0,0,174196,0,0,0,174196,0,0,0,174196,0,0,0,174196,0,0,0,174196,0,0,0,174196,0,0,0,174196,0,0,0,174196,0,0,0,174196,0,0,0,174196,0,0,0,174196,0,0,0,174196,0,0,0,174196,0,0,0,174196,0,0,0,174196,0,0,0,174196,0,0,0,174196,0,0,0,174196,0,0,0,174196,0,0,0,174196,0,0,0,174196,0,0,0,174196,0,0,0,174196,0,0,0,174196,0,0,0,174196,0,0,0,174196,0,0,0,174196,0,0,0,174196,0,0,0,0,0,0.0,0.0,65536,0,25808,0,65536,0,39401,0,65537,0,12474,0,65538,0,14278,0,65537,0,21443,0,65536,0,5732,0,65536,0,26760,0,65536,0,29599,0,65536,0,22625,0,65536,0,21998,0,65536,0,17177,0,65536,0,12701,0,65536,0,18838,0,65536,0,14294,0,65536,0,15249,0,65536,0,36830,0,65592,0,37560,0,65536,0,28531,0,65536,0,30684,0,65537,0,27185,0,65536,0,13536,0,65595,0,4062,0,65537,0,22872,0,65539,0,11725,0,65540,0,8293,0,65536,0,25969,0,65536,0,8677,0,65536,0,10182,0,65536,0,11639,0,65536,0,21631,0,65599,0,16659,0,65537,0,28245,0,524288.0,524288.0,0,43500072,0,0,0,36699383,0,0,0,49907358,0,0,0,41435105,0,0,0,54581738,0,0,0,48536528,0,0,0,48475794,0,0,0,43927300,0,0,0,45548006,0,0,0,37409527,0,0,0,37152642,0,0,0,49391665,0,0,0,38532315,0,0,0,46624251,0,0,0,49490115,0,0,0,48858732,0,0,0,44754391,0,0,0,42756951,0,0,0,38550893,0,0,0,39217539,0,0,0,44847572,0,0,0,46739264,0,0,0,37246847,0,0,0,38374058,0,0,0,35565824,0,0,0,40802874,0,0,0,38127029,0,0,0,37802826,0,0,0,38681237,0,0,0,48270778,0,0,0,46999408,0,0,0,46122442,0,0,0.0,0.0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,524288.0,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32769,32769,32769,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32824,32824,32824,0,32769,32769,32769,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32769,32769,32769,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32829,32829,32829,0,32768,32768,32768,166,32770,32936,32936,222,32770,32992,32992,0,32769,32769,32769,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32831,32831,32831,0,32768,32768,32768,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32936,0,0,32992,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,918023,0,0,65536,63800,56,1680,0,8388608.0,8388608.0,8388608.0,0.0,0.0,0.0,0.0,0.0,124108,147561,9981,2448,0,162739,1049156.0,0.0,388.0,1048768.0,65536,0,0,0,524288,524288,131072,0,0.0,0.0,104.0,2097152.0,0.0,2097152.0,524288.0,59173,0,2454,161919,0,1049152.0,0.0,0.0,31.0,4063232,2883584,0,0,0,0,0,0,6609.0,2027855.0,0.0,2097152.0,2097152.0,0.0,1213505,0,0,13703,0.0,0.0,0.0,0.0,262144,0,0,0,0,0,1507328,458752,995244227.0,2435481436.0,0.0,2097152.0,74.0,0.0,0,0,147965,0.0,0.0,0.0,0.0,65536,524288,0,0,0,65536,65536,48779443,0.0,0.0,0.0,0.0,0.0,18385.0,0,0,0.0,2097345.0,0.0,372.0,33603990,3735552,0,0,2883584,196608,0,131072,0.0,0.0,0.0,0.0,0.0,0.0,0,131072,0.0,0.0,467600.0,1451109.0,524288,0,524288,65536,131072,184549376,917504,0,0.0,0.0,0.0,0.0,0.0,0.0,65536,0,0.0,0.0,983047.0,0.0,0,0,65536,0,0,0,0,4194304,2097152.0,0.0,0.0,12389420.0,0.0,524288.0,2097285.0,0.0,1389355477.0,0.0,17416777855447,17434485856091,17434485948571,17416778653796
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/prev_analysis/1.csv
index 5641c35015..0db7012004 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,3357122.0,3357122.0,3357122.0,7.843415692980662
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,1724161.0,1724161.0,1724161.0,4.028245456860141
 "void benchmark_func<double, 256, 8u, 512u>(double, double*) [clone .kd]",1,1715521.0,1715521.0,1715521.0,4.008059383316388
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/prev_analysis/1001.csv
index f475f954a6..fb5988001a 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,494.8622754491018,Instr per wave
 VMEM,7.958083832335329,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,0.0,Instr per wave
 SALU,24.520958083832337,Instr per wave
 SMEM,1.8023952095808384,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/prev_analysis/101.csv
index 06d8eebf3c..2b25e009a3 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx90a
 mi200
 56
 1638.4
-roofline|SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+roofline|SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/prev_analysis/1202.csv
index 4af8b2c1de..5b2e1d2c79 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,18286.63964606188,1902.0058288574219,258291.54821777344,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/prev_analysis/1901.csv
index 8c4f262c0a..d5319ace44 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,2.0,smem_
 VALU,495.0,valu_
 MFMA,0.0,mfma_
 VMEM,8.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,10.0,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,67894.0,wavefronts_
 Workgroups,16973.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,128.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,0.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,44.0,hbm_rd_
 HBM Wr,0.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,70.0,vl1_coales_
 VL1 Stall,2.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,25.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/prev_analysis/201.csv
index 7d0bb50ec6..007148ae31 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,58.43551248717028,Pct,100,58.43551248717028
 MFMA Util,0.0,Pct,100,0.0
 VALU Active Threads/Wave,64.0,Threads,64,100.0
 IPC - Issue,1.0,Instr/cycle,5,20.0
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.9924972311537,Pct,100,99.9924972311537
 Instr Cache BW,1673.9106929243687,Gb/s,6092.8,27.47358674048662
 Scalar L1D Cache Hit Rate,99.34855886098354,Pct,100,99.34855886098354
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/prev_analysis/602.csv
index 8a0d32a4f3..a6d54229e3 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,12243243.766467066,0,361868732,Simd
 Insufficient SIMD VGPRs,0.0,0,0,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/prev_analysis/701.csv
index 12250d77c0..db0925a109 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/sysinfo.csv
index c9031f0b6a..4afa4ca93c 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-Axes3,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:43:33 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,roofline|SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+Axes3,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:43:33 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,roofline|SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/timestamps.csv
index 527ae751d3..d0690e6bc3 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes3/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,213680,213680,33554432,256,0,0,4,32,4160,0x0,0x7f74dee04280,17434480786238,17434480811769,17434481051609,17434481140839
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,213680,213680,32768,256,0,0,12,24,13888,0x0,0x7f74dee23f80,17434485759828,17434485775291,17434485788571,17434485806437
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,213680,213680,4194304,256,0,0,12,24,14336,0x7f74e1b36380,0x7f74dee23fc0,17434485810857,17434485856091,17434485948571,17434485950813
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/SQ_IFETCH_LEVEL.csv
index c2ab22dcf2..2c1d94e9ea 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/SQ_IFETCH_LEVEL.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,914526,914531,33554432,256,0,0,8,32,6464,0x0,0x7f97e3204180,505169,505169,524288,6291456,793371,101481564,12076203877789763,12076204123558426,12076204123882264,12076204123990967
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,914526,914531,32768,256,0,0,24,24,12480,0x0,0x7f97e3235100,28304,28304,512,8192,9215,1191988,12076204138617189,12076204138932462,12076204138939022,12076204138947362
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,914526,914531,4194304,256,0,0,24,24,12928,0x7f991354f900,0x7f97e3235140,212707,212707,65536,917504,139628,17881924,12076204139016551,12076204139248300,12076204139377580,12076204139381850
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/SQ_INST_LEVEL_LDS.csv
index 0582e715ec..bc597b9fd3 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/SQ_INST_LEVEL_LDS.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,916321,916326,33554432,256,0,0,8,32,6464,0x0,0x7f78de804180,0,0,0,12076230351865750,12076230599436962,12076230599760800,12076230599868612
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,916321,916326,32768,256,0,0,24,24,12480,0x0,0x7f78de835100,0,0,0,12076230614261882,12076230614563327,12076230614569887,12076230614575334
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,916321,916326,4194304,256,0,0,24,24,12928,0x7f7a0e8e2900,0x7f78de835140,0,0,0,12076230614633973,12076230614849245,12076230614981405,12076230614985526
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/SQ_INST_LEVEL_SMEM.csv
index 39f049446a..00bd8b0fd2 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/SQ_INST_LEVEL_SMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,915943,915948,33554432,256,0,0,8,32,6464,0x0,0x7f5764c04180,4194304,3117314,398853480,12076227848839156,12076228092832930,12076228093156769,12076228093271172
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,915943,915948,32768,256,0,0,24,24,12480,0x0,0x7f5764c35100,512,20536,2616448,12076228108114247,12076228108407501,12076228108414061,12076228108419344
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,915943,915948,4194304,256,0,0,24,24,12928,0x7f587084d900,0x7f5764c35140,65536,169396,21711720,12076228108485006,12076228108702060,12076228108839180,12076228108842811
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/SQ_INST_LEVEL_VMEM.csv
index 3da585d5d4..bc2ed17b8d 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/SQ_INST_LEVEL_VMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,916133,916138,33554432,256,0,0,8,32,6464,0x0,0x7f2c58204180,1048576,11071218,1417559124,12076229102193079,12076229347601758,12076229347925596,12076229348031549
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,916133,916138,32768,256,0,0,24,24,12480,0x0,0x7f2c58235100,4096,124799,15966260,12076229362593942,12076229362887403,12076229362893803,12076229362899400
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,916133,916138,4194304,256,0,0,24,24,12928,0x7f2d63712900,0x7f2c58235140,524288,13143746,1682249336,12076229362964371,12076229363174762,12076229363303401,12076229363307679
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/SQ_LEVEL_WAVES.csv
index 90e48b2111..3aed1d8193 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/SQ_LEVEL_WAVES.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,916511,916516,33554432,256,0,0,8,32,6464,0x0,0x7f90e3204180,503889,503889,16730,4031120,524288,372250580,3826469,0,1503761888,12076231611374211,12076231851829714,12076231852153232,12076231852264555
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,916511,916516,32768,256,0,0,24,24,12480,0x0,0x7f90e3235100,27559,27559,20321,220480,512,1112827,76221,0,4465564,12076231866848879,12076231867193881,12076231867200281,12076231867210551
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,916511,916516,4194304,256,0,0,24,24,12928,0x7f921323b900,0x7f90e3235140,216436,216436,21011,1731496,65536,154594617,1558880,0,620189568,12076231867277295,12076231867515959,12076231867647959,12076231867651741
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/pmc_dispatch_info.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/pmc_perf.csv
index cf8cfc705c..d61df0e2fd 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBuffer.kd,0,0,0,915261,915266,33554432,256,0,0,8,32,6464,0x0,0x7fa217a04180,1048576,0,1048576,9437184,0,4194304,1048576,0,502584,502584,57683235,55232064,169,12555038,54353728,54256640,55176109,53987174,4020672,3830006,502584,0,502584,0,16082688,15219815,0,0,0,0,0,17308107,1048576,0,501354,0,0,0,501354,0,0,0,501354,0,0,0,501354,0,0,0,501354,0,0,0,501354,0,0,0,501354,0,0,0,501354,0,0,0,501354,0,0,0,501354,0,0,0,501354,0,0,0,501354,0,0,0,501354,0,0,0,501354,0,0,0,501354,0,0,0,501354,0,0,0,501354,0,0,0,501354,0,0,0,501354,0,0,0,501354,0,0,0,501354,0,0,0,501354,0,0,0,501354,0,0,0,501354,0,0,0,501354,0,0,0,501354,0,0,0,501354,0,0,0,501354,0,0,0,501354,0,0,0,501354,0,0,0,501354,0,0,0,501354,0,0,0,37558788,48,0,0,0,52,0,0,0,0,0,0,0,2649,0,0,0,0,0,0,0,0,0,0,0,3,0,0,0,0,0,0,0,21,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,49,0,0,0,1,0,0,0,2606,0,0,0,0,0,0,0,3,0,0,0,0,0,0,0,2721,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2560,0,0,0,1048576,0,0,3257136,131076,131076,0,19637,131072,131072,0,0,131072,131072,0,0,131076,131076,0,3155312,131072,131072,0,0,131076,131076,0,0,131076,131076,0,365,131076,131076,0,548013,131072,131072,0,0,131076,131076,0,0,131072,131072,0,0,131076,131076,0,0,131080,131080,0,0,131072,131072,0,0,131080,131080,0,0,131072,131072,0,0,131080,131080,0,782,131076,131076,0,1479,131076,131076,0,0,131076,131076,0,2937441,131076,131076,0,0,131072,131072,0,850,131076,131076,0,0,131076,131076,0,3019827,131072,131072,0,0,131072,131072,0,0,131072,131072,0,0,131076,131076,0,58416,131076,131076,0,0,131072,131072,0,0,131072,131072,0,0,131076,131076,1048576,0,47843,0,0,30111624,979,0,0,17245669,1577,0,0,17089260,1083,0,0,17100147,1051,0,0,16986765,963,0,0,17424835,882,0,0,17877655,1108,0,0,18483973,1594,0,0,17220770,1273,0,0,17234208,883,0,0,16934314,859,0,0,16720244,48724,0,0,30032832,1630,0,0,17348358,1127,0,0,17717595,1676,0,0,18646658,1694,0,0,16747614,1841,0,0,17074394,1786,0,0,16974416,1063,0,0,16785133,1764,0,0,17236869,1136,0,0,17182104,793,0,0,17762238,1458,0,0,18740171,47908,0,0,29505159,810,0,0,16783173,1024,0,0,16851414,1727,0,0,16914788,50358,0,0,30613713,1546,0,0,17392374,905,0,0,17811548,1889,0,0,18596528,1048576,131072,131072,0,262144,131260,131076,192,262336,131072,131072,0,262144,131072,131072,0,262144,131072,131141,69,262213,131072,131072,0,262144,131072,131073,1,262145,131072,131072,0,262144,131072,133795,2723,264867,131072,131072,0,262144,131072,131073,1,262145,131072,131072,0,262144,131119,131073,48,262192,131072,131072,0,262144,131072,131076,4,262148,131072,133716,2644,264788,131072,131072,0,262144,131213,131075,144,262288,131119,131073,48,262192,131072,133651,2579,264723,131072,133604,2532,264676,131072,131072,0,262144,131072,131120,48,262192,131072,131121,49,262193,131072,131073,1,262145,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,262144,0,262144,262336,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262288,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,0,0,3145728,524288,32505856,370962940,217532571,120924513,480060,0,0,0,1048576,52459063,52231210,1048576,1048576,131072,524288,698,502187,4463,0,96,10682,0,8388944,32505856,3992376,3796211,56684360,11534336,0,0,14155776,67108864,67108864,0,67108864,54138516,53849578,0,1048576,240040,764328,11499,2004,0,494990,8399571,0,4194727,4204844,13631488,0,3670016,1048576,1048576,0,4194304,9437184,0,0,360,33554432,53736915,4194304,0,0,2420,498280,0,11008,8388608,0,4194370,905969664,6291456,0,0,0,524288,524288,0,15323,16608795,0,16777216,4194304,4194304,0,0,0,17257,4194376,4194376,0,228788,0,0,0,33554432,0,0,0,0,633752710,0,2777180069,0,0,0,0,0,476812,0,0,218024,0,0,8388608,336,144,0,0,0,480,8388608,0,0,0,0,352340,0,0,0,10616,0,21214,0,6291456,6289546,96,2018,1831067,0,0,0,0,0,0,0,0,0,3145728,0,0,0,149818,4194304,4189856,144,4304,2097152,524288,1572864,0,0,0,0,0,0,524288,0,4128830,65534,4063249,0,0,8388608,0,42283770,0,1048576,10648,4194349,12863087,609918750,12076205980717040,12076232743488694,12076232743813811,12076206226186444
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,915261,915266,32768,256,0,0,24,24,12480,0x0,0x7fa217a35100,0,4096,4096,512,0,512,4096,0,29154,29154,1512527,589745,163,107771,66026,38955,581548,561124,233232,86653,29154,0,29154,0,932928,200729,0,0,0,0,0,55005,4096,0,28527,0,0,0,28527,0,0,0,28527,0,0,0,28527,0,0,0,28527,0,0,0,28527,0,0,0,28527,0,0,0,28527,0,0,0,28527,0,0,0,28527,0,0,0,28527,0,0,0,28527,0,0,0,28527,0,0,0,28527,0,0,0,28527,0,0,0,28527,0,0,0,28527,0,0,0,28527,0,0,0,28527,0,0,0,28527,0,0,0,28527,0,0,0,28527,0,0,0,28527,0,0,0,28527,0,0,0,28527,0,0,0,28527,0,0,0,28527,0,0,0,28527,0,0,0,28527,0,0,0,28527,0,0,0,28527,0,0,0,28527,0,0,0,0,256,0,0,0,304,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,376,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,305,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,4096,4096,0,119650,0,0,0,99336,0,0,0,88912,0,0,0,101400,0,0,0,74418,0,0,0,96918,0,0,0,102851,0,0,0,108947,0,0,0,77130,0,0,0,82477,0,0,0,69880,0,0,0,79385,0,0,0,87977,0,0,0,87542,0,0,0,68551,0,0,0,70897,0,0,0,136939,0,0,0,109990,0,0,0,78463,0,0,0,107029,0,0,0,96108,0,0,0,121218,0,0,0,75787,0,0,0,93098,0,0,0,103583,0,0,0,82969,0,0,0,74273,0,0,0,76737,0,0,0,165296,0,0,0,89559,0,0,0,107308,0,0,0,121312,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4096,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,376,376,376,0,256,256,256,0,257,257,257,0,256,256,256,0,256,256,256,0,256,256,256,0,257,257,257,0,256,256,256,47,257,304,304,0,256,256,256,188,260,448,448,0,256,256,256,0,256,256,256,0,256,256,256,188,260,448,448,0,256,256,256,0,256,256,256,0,256,256,256,0,304,304,304,0,305,305,305,0,257,257,257,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,47,257,304,304,0,256,256,256,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,304,0,0,256,0,0,0,0,512,512,35328,1107397,1054196,16849,11568,0,0,0,4096,65365,62365,4096,4096,128,512,607,27782,4311,0,48,220,0,8624,36352,221896,75082,1030373,26624,0,0,30208,65536,65536,65536,0,0,0,0,0,115,627,11610,2009,0,23600,8843,0,470,8373,1024,0,1024,4096,0,4096,512,512,0,0,360,16384,0,16384,0,0,2424,24717,0,8891,0,0,31,1933312,8192,0,0,0,512,512,0,120,15064,0,16384,16384,0,0,0,0,19817,0,0,0,0,0,0,0,32768,0,0,0,0,12762686,17789980,0,8192,0,0,0,0,697,0,0,0,0,0,1024,432,48,0,0,0,480,0,0,0,0,0,2876,0,0,0,8373,0,342,0,8192,6577,48,1567,1046,0,0,0,0,0,0,0,0,0,2560,0,0,0,50695,512,0,48,464,0,512,0,0,0,0,0,0,0,512,0,0,0,0,0,8192,0,0,460460,0,4096,8420,0,3285294,0,12076206241113184,12076232758383433,12076232758389833,12076206242105829
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,915261,915266,4194304,256,0,0,24,24,12928,0x7fa347ca6900,0x7fa217a35140,0,524288,524288,65536,0,65536,524288,0,220770,220770,24135887,22965921,30003,10448375,22366116,22241434,22953556,20790268,1766160,1593073,220770,0,220770,0,7064640,6275433,0,0,0,0,0,19524396,524288,0,215036,0,0,0,215036,0,0,0,215036,0,0,0,215036,0,0,0,215036,0,0,0,215036,0,0,0,215036,0,0,0,215036,0,0,0,215036,0,0,0,215036,0,0,0,215036,0,0,0,215036,0,0,0,215036,0,0,0,215036,0,0,0,215036,0,0,0,215036,0,0,0,215036,0,0,0,215036,0,0,0,215036,0,0,0,215036,0,0,0,215036,0,0,0,215036,0,0,0,215036,0,0,0,215036,0,0,0,215036,0,0,0,215036,0,0,0,215036,0,0,0,215036,0,0,0,215036,0,0,0,215036,0,0,0,215036,0,0,0,215036,0,0,0,0,65536,0,21951,0,65584,0,7897,0,65540,0,2556,0,65536,0,13914,0,65536,0,6506,0,65536,0,40746,0,65536,0,4505,0,65536,0,19283,0,65656,0,12759,0,65536,0,439,0,65536,0,23625,0,65536,0,13842,0,65537,0,0,0,65585,0,5298,0,65536,0,5567,0,66250,0,45627,0,65536,0,24305,0,65536,0,7034,0,65536,0,5619,0,68014,0,64546,0,65536,0,27530,0,65536,0,12000,0,65537,0,22625,0,65536,0,13147,0,65536,0,4183,0,65537,0,7370,0,65536,0,18089,0,65536,0,23559,0,65536,0,19047,0,65536,0,2775,0,65540,0,3030,0,65536,0,883,0,524288,524288,0,58805758,0,0,0,28069203,0,0,0,28936673,0,0,0,28819478,0,0,0,31549783,0,0,0,31968777,0,0,0,28913846,0,0,0,31006547,0,0,0,25968828,0,0,0,27003068,0,0,0,29711222,0,0,0,30247159,0,0,0,29921188,0,0,0,30421848,0,0,0,30789356,0,0,0,28065445,0,0,0,28355235,0,0,0,30901019,0,0,0,29208207,0,0,0,30967497,0,0,0,32109304,0,0,0,30443561,0,0,0,27710722,0,0,0,27578766,0,0,0,36712305,0,0,0,29553552,0,0,0,31445818,0,0,0,32981969,0,0,0,28891977,0,0,0,32515607,0,0,0,29553811,0,0,0,30825576,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,524288,0,65536,65536,65536,0,65536,65536,65536,188,65540,65728,65728,0,65536,65536,65536,0,65656,65656,65656,0,65536,65536,65536,0,65537,65537,65537,0,65536,65536,65536,0,67032,67032,67032,0,65536,65536,65536,0,65537,65537,65537,0,65536,65536,65536,47,65537,65584,65584,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,67519,67519,67519,0,65536,65536,65536,0,65584,65584,65584,0,65585,65585,65585,0,65537,65537,65537,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,188,65540,65728,65728,0,65536,65536,65536,65536,0,0,65536,0,0,65728,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65728,0,0,65536,0,0,0,0,65536,65536,4128768,140204200,53222594,82721766,197609,0,0,0,524288,21938490,21931589,524288,524288,16384,65536,770,215223,4251,0,48,2513,0,2097536,4259840,1827112,1644184,24356194,3014656,0,0,3473408,8388608,8388608,8388608,0,0,0,0,0,174713,205067,12395,2044,0,224267,2102442,0,423,2102019,131072,0,131072,524288,0,524288,65536,65536,0,0,360,2097152,0,2097152,39254,0,2425,216189,0,2100664,0,0,31,222298112,917504,0,0,0,65536,65536,0,7592,2015197,0,2097152,2097152,0,579327,581098,0,21912,0,0,0,0,0,0,0,4194304,0,0,0,0,1118938175,1945229457,0,2097152,0,0,0,0,192929,0,0,0,0,0,131072,384,48,0,0,0,432,0,0,0,0,0,9906,0,0,0,2099768,0,5214,0,917504,914817,69,5167,228699,0,0,0,0,0,0,0,0,0,327680,0,0,260331,313434,65536,64048,48,1440,0,65536,0,0,0,0,0,0,0,65536,0,0,0,1966099,0,2097152,0,0,16665195,0,524288,2099991,0,1088103923,0,12076206242739186,12076232758455752,12076232758594791,12076206243968521
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/prev_analysis/1.csv
index 78d1c124f8..ccc7f3aa9a 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,6056109.0,6056109.0,6056109.0,9.1809465133838
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4525402.0,4525402.0,4525402.0,6.86042370002919
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 256u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,3050374.0,3050374.0,3050374.0,4.624309195857703
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/prev_analysis/1001.csv
index ca08330db0..0e3bf5267e 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,46.862275449101794,Instr per wave
 SMEM,1.8083832335329342,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/prev_analysis/101.csv
index 17b7a1a260..b369a3562e 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx908
 mi100
 48
 1228.8
-SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/prev_analysis/1202.csv
index a78dc46da8..c492d2e20f 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,33912.535498522,2830.222625732422,547973.1409301758,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/prev_analysis/1901.csv
index 0bc1e1b2b7..dbf10092f6 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,2.0,smem_
 VALU,735.0,valu_
 MFMA,,mfma_
 VMEM,8.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,22.0,br_
 VGPR,24.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,67894.0,wavefronts_
 Workgroups,16973.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,163.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,0.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,44.0,hbm_rd_
 HBM Wr,0.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,70.0,vl1_coales_
 VL1 Stall,29.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,35.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/prev_analysis/2001.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/prev_analysis/201.csv
index e6cfd198fd..0903273809 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,59.23170182173713,Pct,100,59.23170182173713
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,63.967701311913,Threads,64,99.94953329986406
 IPC - Issue,0.8437250831887582,Instr/cycle,5,16.874501663775163
-LDS BW,0.0,Gb/sec,23070.72,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,23070.72,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99344038252147,Pct,100,99.99344038252147
 Instr Cache BW,1409.8925710298083,Gb/s,4614.144,30.55588579441405
 Scalar L1D Cache Hit Rate,99.35620448523953,Pct,100,99.35620448523953
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/prev_analysis/602.csv
index c2bcae3ec6..9b1f51d7e0 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,60123.35329341317,0,764182,Simd
 Insufficient SIMD VGPRs,603042.0119760479,0,31191816,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/prev_analysis/701.csv
index d3f1bff5a3..1071413faa 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,23.976047904191617,8,36,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/sysinfo.csv
index 23c743b78a..bcbc42304d 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-Axes4,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 11:29:39 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+Axes4,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 11:29:39 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/timestamps.csv
index c50dc4609d..fb8f30ce85 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes4/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,916560,916565,33554432,256,0,0,8,32,6464,0x0,0x7f86ad004180,12076232743442339,12076232743488694,12076232743813811,12076232743923273
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,916560,916565,32768,256,0,0,24,24,12480,0x0,0x7f86ad035100,12076232758271248,12076232758383433,12076232758389833,12076232758396250
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,916560,916565,4194304,256,0,0,24,24,12928,0x7f87b8cf5900,0x7f86ad035140,12076232758439340,12076232758455752,12076232758594791,12076232758598887
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/SQ_IFETCH_LEVEL.csv
index c34b0122c8..5dacf28aa5 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/SQ_IFETCH_LEVEL.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,217839,217839,33554432,256,0,0,4,32,4160,0x0,0x7f57fd404280,380706,380706,524288,4718592,683300,76430472,17520169087269,17519462538947,17520320714244,17520320824664
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,217839,217839,32768,256,0,0,12,24,13888,0x0,0x7f57fd423f80,33444,33444,512,8192,6064,677308,17520325979931,17520320714244,17520326123533,17520326128288
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,217839,217839,4194304,256,0,0,12,24,14336,0x7f58004a4380,0x7f57fd423fc0,167781,167781,65536,917504,140890,15703316,17520326166047,17520326123533,17520326504334,17520326506818
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/SQ_INST_LEVEL_LDS.csv
index 86c86719ce..b32b5138b7 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/SQ_INST_LEVEL_LDS.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,219687,219687,33554432,256,0,0,4,32,4160,0x0,0x7f2c5ee04280,0,0,0,17539642547842,17538932225326,17539789562305,17539789674205
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,219687,219687,32768,256,0,0,12,24,13888,0x0,0x7f2c5ee23f80,0,0,0,17539794859632,17539789562305,17539794984229,17539794988729
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,219687,219687,4194304,256,0,0,12,24,14336,0x7f2c61e2c380,0x7f2c5ee23fc0,0,0,0,17539795023528,17539794984229,17539795344229,17539795346589
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/SQ_INST_LEVEL_SMEM.csv
index 61cf55a4e3..bc7f11d407 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/SQ_INST_LEVEL_SMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,217617,217617,33554432,256,0,0,4,32,4160,0x0,0x7f3416804280,3670016,2900946,325288488,17519240137891,17514040785310,17519383484057,17519383597957
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,217617,217617,32768,256,0,0,12,24,13888,0x0,0x7f3416823f80,512,97956,10984232,17519388715876,17519383484057,17519388846306,17519388850993
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,217617,217617,4194304,256,0,0,12,24,14336,0x7f3419866380,0x7f3416823fc0,65536,605048,67828144,17519388884212,17519388846306,17519389210147,17519389212713
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/SQ_INST_LEVEL_VMEM.csv
index ed3e01157a..89fff3fde7 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/SQ_INST_LEVEL_VMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,219465,219465,33554432,256,0,0,4,32,4160,0x0,0x7f435e404280,524288,5494002,615233648,17538702437295,17536412103589,17538851562764,17538851655314
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,219465,219465,32768,256,0,0,12,24,13888,0x0,0x7f435e423f80,4096,38020,4263044,17538856858391,17538851562764,17538856986452,17538856991047
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,219465,219465,4194304,256,0,0,12,24,14336,0x7f436130f380,0x7f435e423fc0,524288,10652073,1193013832,17538857025677,17538856986452,17538857355252,17538857357628
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/SQ_LEVEL_WAVES.csv
index a62ac38b9e..57759a2632 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/SQ_LEVEL_WAVES.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,218061,218061,33554432,256,0,0,4,32,4160,0x0,0x7fba6d404280,385123,385123,8981,3080992,524288,242386181,2992283,0,985781684,17521113721029,17520402632317,17521263507621,17521263620361
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,218061,218061,32768,256,0,0,12,24,13888,0x0,0x7fba6d423f80,33238,33238,29337,265912,512,1704520,165163,0,6831576,17521268762179,17521263507621,17521268903467,17521268908505
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,218061,218061,4194304,256,0,0,12,24,14336,0x7fba704e8380,0x7fba6d423fc0,165709,165709,14915,1325680,65536,82247418,1216131,0,330719736,17521268951944,17521268903467,17521269295148,17521269297865
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/pmc_perf.csv
index 07646bd6e6..d6d2650f03 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDI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],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBufferAligned.kd,0,0,0,218827,218827,33554432,256,0,0,4,32,4160,0x0,0x7f676ee04280,3090448,3003309,524288,38998688,244041473,392,224,0,386305,386305,39285186.0,38232467.0,13.0,4213199.0,31344065.0,30978675.0,38202630.0,37639538.0,3088737,3009701,386305,0,386305,0,12361760.0,9503331.0,0.0,0.0,0,0,616,0,4718592,4714920,112,3560,375370,0.0,0.0,0.0,524288.0,28515203.0,27785944.0,7748.0,524288.0,131072,524288,301,384552,2365,0,56.0,305.0,0.0,4194696.0,0,0,0,0,0,7340032,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,19930242.0,524288.0,0,382434,0,0,0,382434,0,0,0,382434,0,0,0,382434,0,0,0,382434,0,0,0,382434,0,0,0,382434,0,0,0,382434,0,0,0,382434,0,0,0,382434,0,0,0,382434,0,0,0,382434,0,0,0,382434,0,0,0,382434,0,0,0,382434,0,0,0,382434,0,0,0,382434,0,0,0,382434,0,0,0,382434,0,0,0,382434,0,0,0,382434,0,0,0,382434,0,0,0,382434,0,0,0,382434,0,0,0,382434,0,0,0,382434,0,0,0,382434,0,0,0,382434,0,0,0,382434,0,0,0,382434,0,0,0,382434,0,0,0,382434,0,0,0,0,0,0.0,21271614.0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2,0,0,0,0,0,0,0,34,0,0,0,56,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,112,0,0,0,0,0,0,0,0,0,0,0,32,0,0,0,32,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,4,0,0,0,0,0,0,0,0,0,0,0,32,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,1,0,0,0,524288.0,0.0,0,0,129024,129024,0,0,129024,129024,0,344,129024,129024,0,44034,129024,129024,0,328,129024,129024,0,203673,129024,129024,0,191,129024,129024,0,0,129024,129024,0,0,129024,129024,0,281807,129024,129024,0,0,129024,129024,0,0,129024,129024,0,44459,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,816,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,164,129024,129024,0,27095,129024,129024,0,870,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,46075,129024,129024,0,512,129024,129024,524288.0,0.0,43512,0,0,49894371,44852,0,0,50060372,43744,0,0,49495022,47570,0,0,51787608,44073,0,0,50627533,46356,0,0,51085883,45400,0,0,50605024,48064,0,0,52471829,44807,0,0,50285975,47052,0,0,50983158,44528,0,0,49789867,46767,0,0,51564672,45625,0,0,50939336,45185,0,0,50767752,45566,0,0,50562627,48909,0,0,52603449,44494,0,0,50090140,44661,0,0,49904322,43094,0,0,49272060,47440,0,0,51620104,44273,0,0,50554105,45954,0,0,51040242,43580,0,0,49952738,47094,0,0,52111281,43932,0,0,50098570,46303,0,0,50450011,45185,0,0,49790403,46986,0,0,51369230,45897,0,0,51243317,45717,0,0,50813800,46824,0,0,51011275,49183,0,0,53011733,0.0,65536,65536,0,131072,65536,65536,0,131072,65536,65537,1,131073,65536,65568,32,131104,65646,65538,112,131184,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65568,32,131104,65536,65536,0,131072,65536,65536,0,131072,65591,65537,56,131128,65536,65536,0,131072,65536,65537,1,131073,65536,65536,0,131072,65536,65536,0,131072,65536,65592,56,131128,65536,65572,36,131108,65758,65538,224,131296,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65648,112,131184,65536,65536,0,131072,65536,65536,0,131072,65536,65568,32,131104,65591,65537,56,131128,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131184,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131296,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131128,0,131072,1149232,0,524288,3670016,3663135,224,6657,1048576,33554432.0,33554432.0,0.0,33554432.0,29834706.0,28150181.0,0.0,524288.0,213115,538656,9009,923,0,381566,4195055.0,0.0,2097594.0,2097461.0,1048576,1048576,0,524288,0,524288,7340032,0,0.0,0.0,104.0,8388608.0,29531799.0,2097152.0,0.0,204636,0,1227,383533,0,754.0,4194304.0,0.0,2064387.0,25690112,9437184,0,0,0,0,0,0,13287.0,8242451.0,0.0,8388608.0,2097152.0,4194304.0,9673679,0,0,8764,4128768.0,4128768.0,0.0,1485147.0,0,0,0,0,0,0,5767168,1048576,319445217.0,0.0,1484440928.0,0.0,34.0,0.0,0,0,376805,0.0,0.0,1541121.0,0.0,3670016,524288,0,0,0,2621440,524288,180924464,4194304.0,0.0,0.0,0.0,0.0,1151428.0,0,0,0.0,311.0,0.0,606.0,43093559,24117248,0,0,9437184,11010048,0,3145728,0.0,0.0,0.0,0.0,0.0,0.0,0,1572864,0.0,0.0,0.0,188138.0,524288,524288,0,3670016,7340032,603979776,4718592,0,0.0,0.0,0.0,0.0,0.0,0.0,524288,0,2064384.0,0.0,2031623.0,0.0,0,0,524288,0,0,0,0,33554432,0.0,4194304.0,0.0,18892697.0,0.0,0.0,141.0,4128768.0,654265.0,1699911385.0,17522557971048,17540461094816,17540461334336,17522706113366
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,218827,218827,32768,256,0,0,12,24,13888,0x0,0x7f676ee23f80,256952,153986,512,1318074,1584167,504,56,0,32118,32118,2236056.0,150897.0,185.0,0.0,35515.0,32429.0,144648.0,125850.0,256944,161208,32118,0,32118,0,1027776.0,355759.0,0.0,0.0,0,0,560,0,8192,6221,56,1915,23464,0.0,0.0,0.0,4096.0,34127.0,32746.0,0.0,4096.0,128,512,302,32983,2400,0,0.0,60.0,0.0,4600.0,0,0,0,0,0,1024,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,11744.0,4096.0,0,34049,0,0,0,34049,0,0,0,34049,0,0,0,34049,0,0,0,34049,0,0,0,34049,0,0,0,34049,0,0,0,34049,0,0,0,34049,0,0,0,34049,0,0,0,34049,0,0,0,34049,0,0,0,34049,0,0,0,34049,0,0,0,34049,0,0,0,34049,0,0,0,34049,0,0,0,34049,0,0,0,34049,0,0,0,34049,0,0,0,34049,0,0,0,34049,0,0,0,34049,0,0,0,34049,0,0,0,34049,0,0,0,34049,0,0,0,34049,0,0,0,34049,0,0,0,34049,0,0,0,34049,0,0,0,34049,0,0,0,34049,0,0,0,0,0,0.0,0.0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,260,0,0,0,257,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,312,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,4096.0,4096.0,0,80402,0,0,0,85223,0,0,0,80199,0,0,0,86656,0,0,0,77742,0,0,0,658041,0,0,0,76032,0,0,0,84138,0,0,0,81644,0,0,0,83052,0,0,0,80578,0,0,0,106291,0,0,0,81911,0,0,0,77958,0,0,0,76241,0,0,0,87252,0,0,0,76165,0,0,0,77592,0,0,0,80096,0,0,0,84101,0,0,0,83559,0,0,0,89907,0,0,0,86149,0,0,0,98831,0,0,0,75360,0,0,0,77198,0,0,0,74388,0,0,0,86101,0,0,0,79731,0,0,0,85690,0,0,0,116746,0,0,0,82053,0,0,0.0,0.0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4096.0,0,128,128,128,0,128,128,128,0,129,129,129,0,128,128,128,0,128,128,128,222,130,352,352,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,222,130,352,352,0,128,128,128,0,128,128,128,0,129,129,129,0,128,128,128,0,128,128,128,0,128,128,128,0,129,129,129,0,128,128,128,55,129,184,184,0,128,128,128,0,128,128,128,0,128,128,128,0,184,184,184,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,352,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,352,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,184,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,658,0,0,512,0,56,456,0,65536.0,65536.0,65536.0,0.0,0.0,0.0,0.0,0.0,6,518,11443,999,0,30829,4661.0,0.0,499.0,4162.0,512,0,0,0,4096,4096,512,0,0.0,0.0,104.0,16384.0,0.0,16384.0,4096.0,0,0,2058,30555,0,4661.0,0.0,0.0,31.0,35328,26112,0,0,0,0,0,0,104.0,15240.0,0.0,16384.0,16384.0,0.0,0,0,0,29908,0.0,0.0,0.0,0.0,0,0,0,0,0,0,10752,3584,3858585.0,5275475.0,0.0,8192.0,0.0,0.0,0,0,499,0.0,0.0,0.0,0.0,512,4096,0,0,0,512,512,1652884,0.0,0.0,0.0,0.0,0.0,1522.0,0,0,0.0,8262.0,0.0,122.0,12490,32256,0,0,26112,1024,0,1024,0.0,0.0,0.0,0.0,0.0,0.0,0,1024,0.0,0.0,0.0,46149.0,4096,0,4096,512,512,1671168,8192,0,0.0,0.0,0.0,0.0,0.0,0.0,512,0,0.0,0.0,0.0,0.0,0,0,512,0,0,0,0,32768,8192.0,0.0,0.0,98190.0,0.0,4096.0,8206.0,0.0,3384182.0,0.0,17522712287918,17540466151782,17540466164902,17522712761305
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,218827,218827,4194304,256,0,0,12,24,14336,0x7f6771e74380,0x7f676ee23fc0,1313528,1210260,65536,15639070,76321199,392,56,0,164190,164190,15964416.0,14546470.0,24053.0,724274.0,13386944.0,13060455.0,14539852.0,12406008.0,1313520,1216884,164190,0,164190,0,5254080.0,4751053.0,0.0,0.0,0,0,448,0,917504,913707,0,3797,154056,0.0,0.0,0.0,524288.0,13625463.0,13608024.0,2251.0,524288.0,16384,65536,302,164906,2361,0,0.0,182.0,0.0,1048968.0,0,0,0,0,0,131072,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,9419776.0,524288.0,0,173754,0,0,0,173754,0,0,0,173754,0,0,0,173754,0,0,0,173754,0,0,0,173754,0,0,0,173754,0,0,0,173754,0,0,0,173754,0,0,0,173754,0,0,0,173754,0,0,0,173754,0,0,0,173754,0,0,0,173754,0,0,0,173754,0,0,0,173754,0,0,0,173754,0,0,0,173754,0,0,0,173754,0,0,0,173754,0,0,0,173754,0,0,0,173754,0,0,0,173754,0,0,0,173754,0,0,0,173754,0,0,0,173754,0,0,0,173754,0,0,0,173754,0,0,0,173754,0,0,0,173754,0,0,0,173754,0,0,0,173754,0,0,0,0,0,0.0,0.0,65536,0,20901,0,65536,0,16857,0,65536,0,19749,0,65537,0,20862,0,65536,0,26460,0,65536,0,22690,0,65588,0,23255,0,65536,0,22346,0,65537,0,21364,0,65536,0,18195,0,65536,0,19519,0,65536,0,20481,0,65592,0,16223,0,65536,0,22112,0,65536,0,17649,0,65581,0,26751,0,65536,0,17629,0,65536,0,17122,0,65536,0,14776,0,65536,0,23916,0,65536,0,20020,0,65537,0,21518,0,65536,0,23866,0,65539,0,19577,0,65540,0,13380,0,65536,0,18766,0,65536,0,16471,0,65536,0,15310,0,65537,0,21514,0,65536,0,16153,0,65536,0,31775,0,65537,0,18807,0,524288.0,524288.0,0,40053039,0,0,0,41931889,0,0,0,41251034,0,0,0,49409116,0,0,0,46616203,0,0,0,49669740,0,0,0,42113760,0,0,0,50032406,0,0,0,44725553,0,0,0,39715045,0,0,0,43992701,0,0,0,41642361,0,0,0,41500361,0,0,0,45589938,0,0,0,42832009,0,0,0,48426291,0,0,0,48363261,0,0,0,46943978,0,0,0,48975997,0,0,0,49434724,0,0,0,48090109,0,0,0,42535335,0,0,0,40618992,0,0,0,42654258,0,0,0,41132520,0,0,0,46194618,0,0,0,40410651,0,0,0,42220725,0,0,0,46890493,0,0,0,52414143,0,0,0,44217684,0,0,0,50215442,0,0,0.0,0.0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,524288.0,0,32768,32768,32768,0,32768,32768,32768,0,32771,32771,32771,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32769,32769,32769,0,32768,32768,32768,0,32769,32769,32769,0,32768,32768,32768,0,32827,32827,32827,0,32768,32768,32768,166,32770,32936,32936,222,32770,32992,32992,0,32768,32768,32768,0,32768,32768,32768,0,32824,32824,32824,0,32768,32768,32768,0,32768,32768,32768,0,32830,32830,32830,0,32768,32768,32768,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32936,0,0,32992,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,900562,0,0,65536,63800,56,1680,0,8388608.0,8388608.0,8388608.0,0.0,0.0,0.0,0.0,0.0,123951,145870,10045,2540,0,162569,1049150.0,0.0,388.0,1048762.0,65536,0,0,0,524288,524288,131072,0,0.0,0.0,104.0,2097152.0,0.0,2097152.0,524288.0,41357,0,2865,161483,0,1049149.0,0.0,0.0,31.0,4063232,2883584,0,0,0,0,0,0,6599.0,2027124.0,0.0,2097152.0,2097152.0,0.0,1364599,0,0,13870,0.0,0.0,0.0,0.0,262144,0,0,0,0,0,1507328,458752,997867159.0,2243867762.0,0.0,2097152.0,58.0,0.0,0,0,147715,0.0,0.0,0.0,0.0,65536,524288,0,0,0,65536,65536,49018329,0.0,0.0,0.0,0.0,0.0,12300.0,0,0,0.0,2097344.0,0.0,370.0,33049408,3735552,0,0,2883584,196608,0,131072,0.0,0.0,0.0,0.0,0.0,0.0,0,131072,0.0,0.0,370858.0,1217984.0,524288,0,524288,65536,131072,184549376,917504,0,0.0,0.0,0.0,0.0,0.0,0.0,65536,0,0.0,0.0,983047.0,0.0,0,0,65536,0,0,0,0,4194304,2097152.0,0.0,0.0,12389081.0,0.0,524288.0,2097291.0,0.0,1473351529.0,0.0,17522713855337,17540466236742,17540466329542,17522714646717
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/prev_analysis/1.csv
index 0dae1c4965..0f4ac58c88 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,3358084.0,3358084.0,3358084.0,7.845540085571721
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,1724482.0,1724482.0,1724482.0,4.02893217020387
 "void benchmark_func<double, 256, 8u, 512u>(double, double*) [clone .kd]",1,1715523.0,1715523.0,1715523.0,4.00800112928094
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/prev_analysis/1001.csv
index f475f954a6..fb5988001a 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,494.8622754491018,Instr per wave
 VMEM,7.958083832335329,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,0.0,Instr per wave
 SALU,24.520958083832337,Instr per wave
 SMEM,1.8023952095808384,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/prev_analysis/101.csv
index a434c220a6..60a594d56f 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx90a
 mi200
 56
 1638.4
-roofline|SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+roofline|SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/prev_analysis/1202.csv
index 6e4e312ddf..963d04cbb2 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,18333.538023486108,1861.8886795043945,258448.04522705078,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/prev_analysis/1901.csv
index f97102642d..6dc9404f91 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,2.0,smem_
 VALU,495.0,valu_
 MFMA,0.0,mfma_
 VMEM,8.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,10.0,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,67894.0,wavefronts_
 Workgroups,16973.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,128.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,0.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,44.0,hbm_rd_
 HBM Wr,0.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,70.0,vl1_coales_
 VL1 Stall,2.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,26.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/prev_analysis/201.csv
index 8edbc52900..6c33d1c30b 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,58.38800586549404,Pct,100,58.38800586549404
 MFMA Util,0.0,Pct,100,0.0
 VALU Active Threads/Wave,64.0,Threads,64,100.0
 IPC - Issue,1.0,Instr/cycle,5,20.0
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99260915175003,Pct,100,99.99260915175003
 Instr Cache BW,1674.7116329920113,Gb/s,6092.8,27.486732421743884
 Scalar L1D Cache Hit Rate,99.3485588588548,Pct,100,99.3485588588548
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/prev_analysis/602.csv
index d8404ab8d5..b04f81e047 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,12356304.688622754,0,390664635,Simd
 Insufficient SIMD VGPRs,0.0,0,0,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/prev_analysis/701.csv
index 12250d77c0..db0925a109 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/sysinfo.csv
index 522ee34c81..106b1772dd 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-Axes4,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:45:19 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,roofline|SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+Axes4,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:45:19 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,roofline|SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/timestamps.csv
index 5b917e650f..cc4d2f6669 100644
--- a/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Axes4/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,219770,219770,33554432,256,0,0,4,32,4160,0x0,0x7f9b03c04280,17540461070125,17540461094816,17540461334336,17540461397826
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,219770,219770,32768,256,0,0,12,24,13888,0x0,0x7f9b03c23f80,17540466136625,17540466151782,17540466164902,17540466183754
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,219770,219770,4194304,256,0,0,12,24,14336,0x7f9b262db380,0x7f9b03c23fc0,17540466185613,17540466236742,17540466329542,17540466331590
diff --git a/projects/rocprofiler-compute/tests/workloads/CMD_INV/mi100/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/CMD_INV/mi100/SQ_IFETCH_LEVEL.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/CMD_INV/mi100/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/CMD_INV/mi100/SQ_IFETCH_LEVEL.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/CMD_INV/mi100/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/CMD_INV/mi100/SQ_INST_LEVEL_LDS.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/CMD_INV/mi100/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/CMD_INV/mi100/SQ_INST_LEVEL_LDS.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/CMD_INV/mi100/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/CMD_INV/mi100/SQ_INST_LEVEL_SMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/CMD_INV/mi100/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/CMD_INV/mi100/SQ_INST_LEVEL_SMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/CMD_INV/mi100/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/CMD_INV/mi100/SQ_INST_LEVEL_VMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/CMD_INV/mi100/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/CMD_INV/mi100/SQ_INST_LEVEL_VMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/CMD_INV/mi100/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/CMD_INV/mi100/SQ_LEVEL_WAVES.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/CMD_INV/mi100/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/CMD_INV/mi100/SQ_LEVEL_WAVES.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/CMD_INV/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/CMD_INV/mi100/pmc_perf.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/CMD_INV/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/CMD_INV/mi100/pmc_perf.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/CMD_INV/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/CMD_INV/mi100/timestamps.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/CMD_INV/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/CMD_INV/mi100/timestamps.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/CPC/mi100/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/CPC/mi100/pmc_dispatch_info.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/CPC/mi100/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/CPC/mi100/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/CPC/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/CPC/mi100/pmc_perf.csv
index cad6f22e67..70ee5e6ea6 100644
--- a/projects/rocprofiler-compute/tests/workloads/CPC/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/CPC/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,CPC_ME1_DC0_SPI_BUSY,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,CPC_ME1_DC0_SPI_BUSY,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBuffer.kd,0,0,0,868078,868083,33554432,256,0,0,8,32,6464,0x0,0x7f6d9ea04180,4014416,3802798,524288,501801,501801,501801,0,712,503497,10906,2411,2659,497544,0,17567,478093,12075272861084152,12075279053995252,12075279054317649,12075273110476365
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,868078,868083,32768,256,0,0,24,24,12480,0x0,0x7f6d9ea35100,223232,76342,512,27903,27903,27903,0,664,27117,10999,2504,2414,23380,0,21415,697,12075273125360972,12075279069200263,12075279069206983,12075273125740708
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,868078,868083,4194304,256,0,0,24,24,12928,0x7f6eceb23900,0x7f6d9ea35140,1741728,1576552,65536,217715,217715,217715,0,719,216050,10980,2531,2449,219989,0,21757,190896,12075273125788967,12075279069270663,12075279069401861,12075273126271604
diff --git a/projects/rocprofiler-compute/tests/workloads/CPC/mi100/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/CPC/mi100/prev_analysis/1.csv
index 087e13f120..4798c89a4e 100644
--- a/projects/rocprofiler-compute/tests/workloads/CPC/mi100/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/CPC/mi100/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,6053709.0,6053709.0,6053709.0,9.176106682718602
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4526682.0,4526682.0,4526682.0,6.861465747815432
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 256u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,3049414.0,3049414.0,3049414.0,4.6222486386074495
diff --git a/projects/rocprofiler-compute/tests/workloads/CPC/mi100/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/CPC/mi100/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/CPC/mi100/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/CPC/mi100/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/CPC/mi100/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/CPC/mi100/prev_analysis/1202.csv
index d92c0479fa..2d4898d1f7 100644
--- a/projects/rocprofiler-compute/tests/workloads/CPC/mi100/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/CPC/mi100/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,,,,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/CPC/mi100/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/CPC/mi100/prev_analysis/1901.csv
index 13c557f6ef..85c7cb0291 100644
--- a/projects/rocprofiler-compute/tests/workloads/CPC/mi100/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/CPC/mi100/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,24.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,,il1_fetch_
 IL1 Hit,,il1_hit_
 IL1_L2 Rd,,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/CPC/mi100/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/CPC/mi100/prev_analysis/2001.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/CPC/mi100/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/CPC/mi100/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/CPC/mi100/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/CPC/mi100/prev_analysis/201.csv
index 52e9f5bf0c..91625c4b2e 100644
--- a/projects/rocprofiler-compute/tests/workloads/CPC/mi100/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/CPC/mi100/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,,Gb/sec,23070.72,
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,,Gb/sec,23070.72,
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,,Pct,100,
 Instr Cache BW,,Gb/s,4614.144,
 Scalar L1D Cache Hit Rate,,Pct,100,
diff --git a/projects/rocprofiler-compute/tests/workloads/CPC/mi100/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/CPC/mi100/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/CPC/mi100/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/CPC/mi100/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/CPC/mi100/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/CPC/mi100/prev_analysis/701.csv
index 8fb0971b0c..b6e142aea6 100644
--- a/projects/rocprofiler-compute/tests/workloads/CPC/mi100/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/CPC/mi100/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,23.976047904191617,8,36,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/CPC/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/CPC/mi100/timestamps.csv
index 9e241ac223..98e04d670b 100644
--- a/projects/rocprofiler-compute/tests/workloads/CPC/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/CPC/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,868283,868288,33554432,256,0,0,8,32,6464,0x0,0x7f5a48204180,12075279053950779,12075279053995252,12075279054317649,12075279054425581
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,868283,868288,32768,256,0,0,24,24,12480,0x0,0x7f5a48235100,12075279069097283,12075279069200263,12075279069206983,12075279069213048
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,868283,868288,4194304,256,0,0,24,24,12928,0x7f5b53d76900,0x7f5a48235140,12075279069257901,12075279069270663,12075279069401861,12075279069405856
diff --git a/projects/rocprofiler-compute/tests/workloads/CPC/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/CPC/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/CPC/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/CPC/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/CPC/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/CPC/mi200/pmc_perf.csv
index f0f2266a2c..42aa6775b2 100644
--- a/projects/rocprofiler-compute/tests/workloads/CPC/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/CPC/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,CPC_ME1_DC0_SPI_BUSY,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,CPC_ME1_DC0_SPI_BUSY,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBufferAligned.kd,0,0,0,160404,160404,33554432,256,0,0,4,32,4160,0x0,0x7fa4dea04280,3054296,2965383,524288,381786,381786,381786,0,302,381283,8404,518,1217,380421,0,8701,369195,16455596020581,16459814018450,16459814257808,16455745747285
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,160404,160404,32768,256,0,0,12,24,13888,0x0,0x7fa4dea23f80,267264,159891,512,33407,33407,33407,0,302,32864,11021,515,1348,32461,0,29902,496,16455750923166,16459819051039,16459819064319,16455751060640
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,160404,160404,4194304,256,0,0,12,24,14336,0x7fa4e1915380,0x7fa4dea23fc0,1319368,1215750,65536,164920,164920,164920,0,302,164718,9883,1995,2856,161253,0,14318,148256,16455751096469,16459819137118,16459819229437,16455751438626
diff --git a/projects/rocprofiler-compute/tests/workloads/CPC/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/CPC/mi200/prev_analysis/1.csv
index 43e12d638b..5b3d977f51 100644
--- a/projects/rocprofiler-compute/tests/workloads/CPC/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/CPC/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,3359807.0,3359807.0,3359807.0,7.8432640011997155
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,1726223.0,1726223.0,1726223.0,4.029762041076459
 "void benchmark_func<double, 256, 8u, 512u>(double, double*) [clone .kd]",1,1715503.0,1715503.0,1715503.0,4.004736856566497
diff --git a/projects/rocprofiler-compute/tests/workloads/CPC/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/CPC/mi200/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/CPC/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/CPC/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/CPC/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/CPC/mi200/prev_analysis/1202.csv
index d92c0479fa..2d4898d1f7 100644
--- a/projects/rocprofiler-compute/tests/workloads/CPC/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/CPC/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,,,,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/CPC/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/CPC/mi200/prev_analysis/1901.csv
index bf48a8d6b0..fea0ee3201 100644
--- a/projects/rocprofiler-compute/tests/workloads/CPC/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/CPC/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,,il1_fetch_
 IL1 Hit,,il1_hit_
 IL1_L2 Rd,,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/CPC/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/CPC/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/CPC/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/CPC/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/CPC/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/CPC/mi200/prev_analysis/201.csv
index b4d9ea9d64..2086c73dba 100644
--- a/projects/rocprofiler-compute/tests/workloads/CPC/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/CPC/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,,Gb/sec,22630.4,
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,,Gb/sec,22630.4,
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,,Pct,100,
 Instr Cache BW,,Gb/s,6092.8,
 Scalar L1D Cache Hit Rate,,Pct,100,
diff --git a/projects/rocprofiler-compute/tests/workloads/CPC/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/CPC/mi200/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/CPC/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/CPC/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/CPC/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/CPC/mi200/prev_analysis/701.csv
index d28098ed25..9d9e3a3dab 100644
--- a/projects/rocprofiler-compute/tests/workloads/CPC/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/CPC/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/CPC/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/CPC/mi200/timestamps.csv
index a09b3d76e7..607b135dd9 100644
--- a/projects/rocprofiler-compute/tests/workloads/CPC/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/CPC/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,160617,160617,33554432,256,0,0,4,32,4160,0x0,0x7fa448004280,16459813992280,16459814018450,16459814257808,16459814365925
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,160617,160617,32768,256,0,0,12,24,13888,0x0,0x7fa448023f80,16459819035296,16459819051039,16459819064319,16459819082824
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,160617,160617,4194304,256,0,0,12,24,14336,0x7fa46684d380,0x7fa448023fc0,16459819086954,16459819137118,16459819229437,16459819231499
diff --git a/projects/rocprofiler-compute/tests/workloads/CPF/mi100/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/CPF/mi100/pmc_dispatch_info.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/CPF/mi100/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/CPF/mi100/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/CPF/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/CPF/mi100/pmc_perf.csv
index 28327b2ab9..a3c29ab1e0 100644
--- a/projects/rocprofiler-compute/tests/workloads/CPF/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/CPF/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,GRBM_COUNT,GRBM_GUI_ACTIVE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,GRBM_COUNT,GRBM_GUI_ACTIVE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBuffer.kd,0,0,0,869685,869690,33554432,256,0,0,8,32,6464,0x0,0x7fdec2404180,4040784,3830766,524288,505097,505097,505097,0,4178,0,0,482832,0,12075315587403796,12075319737980510,12075319738305467,12075315835499200
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,869685,869690,32768,256,0,0,24,24,12480,0x0,0x7fdec2435100,219112,74883,512,27388,27388,27388,0,2343,0,0,26941,0,12075315849868370,12075319753341463,12075319753348183,12075315850220494
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,869685,869690,4194304,256,0,0,24,24,12928,0x7fdfcdfa6900,0x7fdec2435140,1809384,1646053,65536,226172,226172,226172,0,2355,0,0,215251,0,12075315850313286,12075319753399863,12075319753530422,12075315850719822
diff --git a/projects/rocprofiler-compute/tests/workloads/CPF/mi100/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/CPF/mi100/prev_analysis/1.csv
index 6abbf5630f..ed4e113363 100644
--- a/projects/rocprofiler-compute/tests/workloads/CPF/mi100/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/CPF/mi100/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,6056598.0,6056598.0,6056598.0,9.176978573582865
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4526368.0,4526368.0,4526368.0,6.858368700077359
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 256u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,3051019.0,3051019.0,3051019.0,4.62291471063363
diff --git a/projects/rocprofiler-compute/tests/workloads/CPF/mi100/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/CPF/mi100/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/CPF/mi100/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/CPF/mi100/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/CPF/mi100/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/CPF/mi100/prev_analysis/1202.csv
index d92c0479fa..2d4898d1f7 100644
--- a/projects/rocprofiler-compute/tests/workloads/CPF/mi100/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/CPF/mi100/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,,,,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/CPF/mi100/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/CPF/mi100/prev_analysis/1901.csv
index 13c557f6ef..85c7cb0291 100644
--- a/projects/rocprofiler-compute/tests/workloads/CPF/mi100/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/CPF/mi100/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,24.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,,il1_fetch_
 IL1 Hit,,il1_hit_
 IL1_L2 Rd,,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/CPF/mi100/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/CPF/mi100/prev_analysis/2001.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/CPF/mi100/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/CPF/mi100/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/CPF/mi100/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/CPF/mi100/prev_analysis/201.csv
index 52e9f5bf0c..91625c4b2e 100644
--- a/projects/rocprofiler-compute/tests/workloads/CPF/mi100/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/CPF/mi100/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,,Gb/sec,23070.72,
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,,Gb/sec,23070.72,
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,,Pct,100,
 Instr Cache BW,,Gb/s,4614.144,
 Scalar L1D Cache Hit Rate,,Pct,100,
diff --git a/projects/rocprofiler-compute/tests/workloads/CPF/mi100/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/CPF/mi100/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/CPF/mi100/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/CPF/mi100/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/CPF/mi100/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/CPF/mi100/prev_analysis/701.csv
index 8fb0971b0c..b6e142aea6 100644
--- a/projects/rocprofiler-compute/tests/workloads/CPF/mi100/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/CPF/mi100/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,23.976047904191617,8,36,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/CPF/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/CPF/mi100/timestamps.csv
index f0f2d70821..cd39ffe374 100644
--- a/projects/rocprofiler-compute/tests/workloads/CPF/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/CPF/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,869828,869833,33554432,256,0,0,8,32,6464,0x0,0x7fad6ec04180,12075319737934279,12075319737980510,12075319738305467,12075319738413559
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,869828,869833,32768,256,0,0,24,24,12480,0x0,0x7fad6ec35100,12075319753241562,12075319753341463,12075319753348183,12075319753353820
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,869828,869833,4194304,256,0,0,24,24,12928,0x7fae9ecce900,0x7fad6ec35140,12075319753387052,12075319753399863,12075319753530422,12075319753533925
diff --git a/projects/rocprofiler-compute/tests/workloads/CPF/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/CPF/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/CPF/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/CPF/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/CPF/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/CPF/mi200/pmc_perf.csv
index 9fc446aa13..1a60406e22 100644
--- a/projects/rocprofiler-compute/tests/workloads/CPF/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/CPF/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,GRBM_COUNT,GRBM_GUI_ACTIVE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,GRBM_COUNT,GRBM_GUI_ACTIVE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBufferAligned.kd,0,0,0,162887,162887,33554432,256,0,0,4,32,4160,0x0,0x7f0b90204280,3066680,2977166,524288,383334,383334,383334,0,2896,0,0,380125,0,16527598245916,16530446836344,16530447076822,16527746399726
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,162887,162887,32768,256,0,0,12,24,13888,0x0,0x7f0b90223f80,269736,161104,512,33716,33716,33716,0,1798,0,0,31489,0,16527751557277,16530451863499,16530451877259,16527751693352
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,162887,162887,4194304,256,0,0,12,24,14336,0x7f0baea38380,0x7f0b90223fc0,1323456,1214693,65536,165431,165431,165431,0,1855,0,0,162564,0,16527751728691,16530451947178,16530452039817,16527752064919
diff --git a/projects/rocprofiler-compute/tests/workloads/CPF/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/CPF/mi200/prev_analysis/1.csv
index c9405fabe2..f37a242d41 100644
--- a/projects/rocprofiler-compute/tests/workloads/CPF/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/CPF/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,3358850.0,3358850.0,3358850.0,7.843042113553034
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,1726544.0,1726544.0,1726544.0,4.031545708472337
 "void benchmark_func<double, 256, 8u, 512u>(double, double*) [clone .kd]",1,1716784.0,1716784.0,1716784.0,4.008755738384873
diff --git a/projects/rocprofiler-compute/tests/workloads/CPF/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/CPF/mi200/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/CPF/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/CPF/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/CPF/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/CPF/mi200/prev_analysis/1202.csv
index d92c0479fa..2d4898d1f7 100644
--- a/projects/rocprofiler-compute/tests/workloads/CPF/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/CPF/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,,,,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/CPF/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/CPF/mi200/prev_analysis/1901.csv
index bf48a8d6b0..fea0ee3201 100644
--- a/projects/rocprofiler-compute/tests/workloads/CPF/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/CPF/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,,il1_fetch_
 IL1 Hit,,il1_hit_
 IL1_L2 Rd,,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/CPF/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/CPF/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/CPF/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/CPF/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/CPF/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/CPF/mi200/prev_analysis/201.csv
index b4d9ea9d64..2086c73dba 100644
--- a/projects/rocprofiler-compute/tests/workloads/CPF/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/CPF/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,,Gb/sec,22630.4,
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,,Gb/sec,22630.4,
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,,Pct,100,
 Instr Cache BW,,Gb/s,6092.8,
 Scalar L1D Cache Hit Rate,,Pct,100,
diff --git a/projects/rocprofiler-compute/tests/workloads/CPF/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/CPF/mi200/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/CPF/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/CPF/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/CPF/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/CPF/mi200/prev_analysis/701.csv
index d28098ed25..9d9e3a3dab 100644
--- a/projects/rocprofiler-compute/tests/workloads/CPF/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/CPF/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/CPF/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/CPF/mi200/timestamps.csv
index 44281c13c4..104c177483 100644
--- a/projects/rocprofiler-compute/tests/workloads/CPF/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/CPF/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,163048,163048,33554432,256,0,0,4,32,4160,0x0,0x7f20e6604280,16530446811403,16530446836344,16530447076822,16530447164691
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,163048,163048,32768,256,0,0,12,24,13888,0x0,0x7f20e6623f80,16530451847800,16530451863499,16530451877259,16530451894228
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,163048,163048,4194304,256,0,0,12,24,14336,0x7f20e952d380,0x7f20e6623fc0,16530451899078,16530451947178,16530452039817,16530452042063
diff --git a/projects/rocprofiler-compute/tests/workloads/D_int_inv1/mi100/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/D_int_inv1/mi100/SQ_IFETCH_LEVEL.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_int_inv1/mi100/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_int_inv1/mi100/SQ_IFETCH_LEVEL.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/D_int_inv1/mi100/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/D_int_inv1/mi100/SQ_INST_LEVEL_LDS.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_int_inv1/mi100/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_int_inv1/mi100/SQ_INST_LEVEL_LDS.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/D_int_inv1/mi100/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/D_int_inv1/mi100/SQ_INST_LEVEL_SMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_int_inv1/mi100/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_int_inv1/mi100/SQ_INST_LEVEL_SMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/D_int_inv1/mi100/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/D_int_inv1/mi100/SQ_INST_LEVEL_VMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_int_inv1/mi100/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_int_inv1/mi100/SQ_INST_LEVEL_VMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/D_int_inv1/mi100/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/D_int_inv1/mi100/SQ_LEVEL_WAVES.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_int_inv1/mi100/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_int_inv1/mi100/SQ_LEVEL_WAVES.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/D_int_inv1/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/D_int_inv1/mi100/pmc_perf.csv
index 770051c4a2..25b1b98ff3 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_int_inv1/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_int_inv1/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,BeginNs,EndNs
+Dispatch_ID,Kernel_Name,Start_Timestamp,End_Timestamp
 ,,12074318637816165,12074318638140962
 ,,12074318652705076,12074318652712756
 ,,12074318652775956,12074318652910994
diff --git a/projects/rocprofiler-compute/tests/workloads/D_int_inv1/mi100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/D_int_inv1/mi100/sysinfo.csv
index d179b84906..f39bc5325a 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_int_inv1/mi100/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_int_inv1/mi100/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-D_int_inv1,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 10:57:44 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+D_int_inv1,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 10:57:44 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/D_int_inv1/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/D_int_inv1/mi100/timestamps.csv
index 5b9760a7ad..4ca43f2b76 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_int_inv1/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_int_inv1/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,820647,820652,33554432,256,0,0,8,32,6464,0x0,0x7f2e0de04180,12074318637769159,12074318637816165,12074318638140962,12074318638250614
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,820647,820652,32768,256,0,0,24,24,12480,0x0,0x7f2e0de35100,12074318652600197,12074318652705076,12074318652712756,12074318652718486
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,820647,820652,4194304,256,0,0,24,24,12928,0x7f2f19a4a900,0x7f2e0de35140,12074318652763109,12074318652775956,12074318652910994,12074318652914310
diff --git a/projects/rocprofiler-compute/tests/workloads/D_int_inv1/mi200/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/D_int_inv1/mi200/SQ_IFETCH_LEVEL.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_int_inv1/mi200/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_int_inv1/mi200/SQ_IFETCH_LEVEL.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/D_int_inv1/mi200/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/D_int_inv1/mi200/SQ_INST_LEVEL_LDS.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_int_inv1/mi200/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_int_inv1/mi200/SQ_INST_LEVEL_LDS.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/D_int_inv1/mi200/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/D_int_inv1/mi200/SQ_INST_LEVEL_SMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_int_inv1/mi200/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_int_inv1/mi200/SQ_INST_LEVEL_SMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/D_int_inv1/mi200/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/D_int_inv1/mi200/SQ_INST_LEVEL_VMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_int_inv1/mi200/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_int_inv1/mi200/SQ_INST_LEVEL_VMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/D_int_inv1/mi200/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/D_int_inv1/mi200/SQ_LEVEL_WAVES.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_int_inv1/mi200/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_int_inv1/mi200/SQ_LEVEL_WAVES.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/D_int_inv1/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/D_int_inv1/mi200/pmc_perf.csv
index 1ea37dfc29..27b53314e7 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_int_inv1/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_int_inv1/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,BeginNs,EndNs
+Dispatch_ID,Kernel_Name,Start_Timestamp,End_Timestamp
 ,,15261234340777,15261234576778
 ,,15261239478560,15261239486720
 ,,15261239563040,15261239655200
diff --git a/projects/rocprofiler-compute/tests/workloads/D_int_inv1/mi200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/D_int_inv1/mi200/sysinfo.csv
index 29f43307e3..a87e0e73ae 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_int_inv1/mi200/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_int_inv1/mi200/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-D_int_inv1,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:07:20 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,roofline|SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+D_int_inv1,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:07:20 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,roofline|SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/D_int_inv1/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/D_int_inv1/mi200/timestamps.csv
index 4cd6761c74..7a58629ed3 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_int_inv1/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_int_inv1/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,98949,98949,33554432,256,0,0,4,32,4160,0x0,0x7f4fd1a04280,15261234311167,15261234340777,15261234576778,15261234681208
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,98949,98949,32768,256,0,0,12,24,13888,0x0,0x7f4fd1a23f80,15261239462877,15261239478560,15261239486720,15261239510036
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,98949,98949,4194304,256,0,0,12,24,14336,0x7f4fd4ad9380,0x7f4fd1a23fc0,15261239511466,15261239563040,15261239655200,15261239657742
diff --git a/projects/rocprofiler-compute/tests/workloads/D_int_inv2/mi100/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/D_int_inv2/mi100/SQ_IFETCH_LEVEL.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_int_inv2/mi100/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_int_inv2/mi100/SQ_IFETCH_LEVEL.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/D_int_inv2/mi100/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/D_int_inv2/mi100/SQ_INST_LEVEL_LDS.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_int_inv2/mi100/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_int_inv2/mi100/SQ_INST_LEVEL_LDS.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/D_int_inv2/mi100/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/D_int_inv2/mi100/SQ_INST_LEVEL_SMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_int_inv2/mi100/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_int_inv2/mi100/SQ_INST_LEVEL_SMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/D_int_inv2/mi100/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/D_int_inv2/mi100/SQ_INST_LEVEL_VMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_int_inv2/mi100/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_int_inv2/mi100/SQ_INST_LEVEL_VMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/D_int_inv2/mi100/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/D_int_inv2/mi100/SQ_LEVEL_WAVES.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_int_inv2/mi100/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_int_inv2/mi100/SQ_LEVEL_WAVES.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/D_int_inv2/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/D_int_inv2/mi100/pmc_perf.csv
index 69ae909ac1..fadd4d7544 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_int_inv2/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_int_inv2/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,BeginNs,EndNs
+Dispatch_ID,Kernel_Name,Start_Timestamp,End_Timestamp
 ,,12074387702319716,12074387702643873
 ,,12074387717568261,12074387717574821
 ,,12074387717642980,12074387717777059
diff --git a/projects/rocprofiler-compute/tests/workloads/D_int_inv2/mi100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/D_int_inv2/mi100/sysinfo.csv
index 6b3f4a81a9..9ef93b4936 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_int_inv2/mi100/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_int_inv2/mi100/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-D_int_inv2,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 10:58:53 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+D_int_inv2,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 10:58:53 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/D_int_inv2/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/D_int_inv2/mi100/timestamps.csv
index abde94fbdc..66a5cbd4bb 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_int_inv2/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_int_inv2/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,825649,825654,33554432,256,0,0,8,32,6464,0x0,0x7fc02b204180,12074387702272847,12074387702319716,12074387702643873,12074387702729034
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,825649,825654,32768,256,0,0,24,24,12480,0x0,0x7fc02b235100,12074387717454209,12074387717568261,12074387717574821,12074387717580784
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,825649,825654,4194304,256,0,0,24,24,12928,0x7fc15b1a3900,0x7fc02b235140,12074387717628603,12074387717642980,12074387717777059,12074387717780556
diff --git a/projects/rocprofiler-compute/tests/workloads/D_int_inv2/mi200/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/D_int_inv2/mi200/SQ_IFETCH_LEVEL.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_int_inv2/mi200/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_int_inv2/mi200/SQ_IFETCH_LEVEL.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/D_int_inv2/mi200/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/D_int_inv2/mi200/SQ_INST_LEVEL_LDS.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_int_inv2/mi200/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_int_inv2/mi200/SQ_INST_LEVEL_LDS.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/D_int_inv2/mi200/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/D_int_inv2/mi200/SQ_INST_LEVEL_SMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_int_inv2/mi200/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_int_inv2/mi200/SQ_INST_LEVEL_SMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/D_int_inv2/mi200/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/D_int_inv2/mi200/SQ_INST_LEVEL_VMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_int_inv2/mi200/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_int_inv2/mi200/SQ_INST_LEVEL_VMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/D_int_inv2/mi200/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/D_int_inv2/mi200/SQ_LEVEL_WAVES.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_int_inv2/mi200/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_int_inv2/mi200/SQ_LEVEL_WAVES.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/D_int_inv2/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/D_int_inv2/mi200/pmc_perf.csv
index fda82d989a..202f7de096 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_int_inv2/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_int_inv2/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,BeginNs,EndNs
+Dispatch_ID,Kernel_Name,Start_Timestamp,End_Timestamp
 ,,15350964930274,15350965168355
 ,,15350969986294,15350969999414
 ,,15350970065654,15350970158295
diff --git a/projects/rocprofiler-compute/tests/workloads/D_int_inv2/mi200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/D_int_inv2/mi200/sysinfo.csv
index 8bbacc36af..5411c0c960 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_int_inv2/mi200/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_int_inv2/mi200/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-D_int_inv2,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:08:50 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,roofline|SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+D_int_inv2,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:08:50 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,roofline|SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/D_int_inv2/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/D_int_inv2/mi200/timestamps.csv
index d2f4184ab1..a39856243a 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_int_inv2/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_int_inv2/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,105051,105051,33554432,256,0,0,4,32,4160,0x0,0x7fd7b5204280,15350964905154,15350964930274,15350965168355,15350965259645
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,105051,105051,32768,256,0,0,12,24,13888,0x0,0x7fd7b5223f80,15350969971296,15350969986294,15350969999414,15350970017035
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,105051,105051,4194304,256,0,0,12,24,14336,0x7fd7b8146380,0x7fd7b5223fc0,15350970021885,15350970065654,15350970158295,15350970160642
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/SQ_IFETCH_LEVEL.csv
index 450d1c639e..680c6a78bd 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/SQ_IFETCH_LEVEL.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,828617,828622,33554432,256,0,0,8,32,6464,0x0,0x7fa1bc204180,502377,502377,524288,6291456,799211,102216136,12074439140768879,12074439387663423,12074439387986781,12074439388101603
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/SQ_INST_LEVEL_LDS.csv
index f2c47678c9..e2df009a4d 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/SQ_INST_LEVEL_LDS.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,830432,830437,33554432,256,0,0,8,32,6464,0x0,0x7fb6eb804180,0,0,0,12074460772318279,12074461018701263,12074461019025581,12074461019139814
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/SQ_INST_LEVEL_SMEM.csv
index 49b2230e33..283d0a7f94 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/SQ_INST_LEVEL_SMEM.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,830052,830057,33554432,256,0,0,8,32,6464,0x0,0x7faaf2804180,4194304,3093786,395977992,12074458306912753,12074458552451946,12074458552773704,12074458552888616
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/SQ_INST_LEVEL_VMEM.csv
index 56e0c0bb43..63064c900b 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/SQ_INST_LEVEL_VMEM.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,830241,830246,33554432,256,0,0,8,32,6464,0x0,0x7f40c8404180,1048576,11249024,1440229340,12074459540948944,12074459785586897,12074459785910735,12074459786026618
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/SQ_LEVEL_WAVES.csv
index 011e0f5402..624ff17379 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/SQ_LEVEL_WAVES.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,830630,830635,33554432,256,0,0,8,32,6464,0x0,0x7fe72f204180,504593,504593,15883,4036752,524288,372852983,3832144,0,1506200888,12074462007675194,12074462247745327,12074462248070286,12074462248184509
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/pmc_dispatch_info.csv
index 90cd5504cd..5794a6cd05 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/pmc_dispatch_info.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/pmc_perf.csv
index 48867c3d8d..01d2f325ba 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/pmc_perf.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBuffer.kd,0,0,0,829353,829358,33554432,256,0,0,8,32,6464,0x0,0x7f1b3b204180,1048576,0,1048576,9437184,0,4194304,1048576,0,501697,501697,57631611,55286777,117,12696122,54513558,54419993,55253340,54084224,4013576,3826562,501697,0,501697,0,16054304,15208621,0,0,0,0,0,17379683,1048576,0,506617,0,0,0,506617,0,0,0,506617,0,0,0,506617,0,0,0,506617,0,0,0,506617,0,0,0,506617,0,0,0,506617,0,0,0,506617,0,0,0,506617,0,0,0,506617,0,0,0,506617,0,0,0,506617,0,0,0,506617,0,0,0,506617,0,0,0,506617,0,0,0,506617,0,0,0,506617,0,0,0,506617,0,0,0,506617,0,0,0,506617,0,0,0,506617,0,0,0,506617,0,0,0,506617,0,0,0,506617,0,0,0,506617,0,0,0,506617,0,0,0,506617,0,0,0,506617,0,0,0,506617,0,0,0,506617,0,0,0,506617,0,0,0,37566095,90,0,0,0,52,0,0,0,0,0,0,0,0,0,0,0,2684,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2566,0,0,0,0,0,0,0,3,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,3,0,0,0,0,0,0,0,0,0,0,0,2651,0,0,0,0,0,0,0,1,0,0,0,50,0,0,0,2565,0,0,0,0,0,0,0,0,0,0,0,48,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1048576,0,0,3046050,131072,131072,0,2136,131072,131072,0,0,131076,131076,0,21429,131072,131072,0,0,131080,131080,0,0,131072,131072,0,567242,131076,131076,0,0,131072,131072,0,751,131076,131076,0,0,131072,131072,0,1714,131072,131072,0,0,131072,131072,0,2974650,131072,131072,0,0,131072,131072,0,1566,131072,131072,0,0,131072,131072,0,7169,131072,131072,0,782,131072,131072,0,0,131072,131072,0,0,131072,131072,0,0,131076,131076,0,0,131072,131072,0,19162,131072,131072,0,0,131072,131072,0,3117564,131072,131072,0,0,131072,131072,0,0,131072,131072,0,0,131072,131072,0,2928947,131072,131072,0,0,131072,131072,0,0,131072,131072,0,0,131072,131072,1048576,0,1020,0,0,16920145,943,0,0,17096189,1067,0,0,17275363,795,0,0,17268927,1369,0,0,17191826,1183,0,0,17202036,1212,0,0,18133394,1207,0,0,18669752,45711,0,0,29912496,1908,0,0,17631683,1426,0,0,17533552,843,0,0,17039755,1540,0,0,17167551,1934,0,0,17646094,1652,0,0,18329241,50775,0,0,31873461,839,0,0,16441277,1175,0,0,16978889,926,0,0,17179358,42074,0,0,29228102,44585,0,0,29095657,946,0,0,17315904,854,0,0,18153803,1489,0,0,18948816,1232,0,0,16483443,849,0,0,16820459,1404,0,0,17394104,933,0,0,16917554,1059,0,0,17019862,1060,0,0,17319789,1132,0,0,18097699,801,0,0,18558839,1048576,131072,131072,0,262144,131260,131124,240,262384,131072,131072,0,262144,131072,131072,0,262144,131072,131073,1,262145,131072,131120,48,262192,131072,131072,0,262144,131072,133686,2614,264758,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,133669,2597,264741,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131119,131073,48,262192,131213,131123,192,262336,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,133629,2557,264701,131072,131072,0,262144,131072,131072,0,262144,131119,131076,51,262195,131072,133783,2711,264855,131072,131073,1,262145,131072,131072,0,262144,131072,131072,0,262144,131072,131093,21,262165,262144,0,262144,262336,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262288,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,0,0,3145728,524288,32505856,367520449,217416822,117597771,482108,0,0,0,1048576,52510071,52273200,1048576,1048576,131072,524288,739,504094,4007,0,96,10791,0,8388944,32505856,3986512,3789178,56707232,11534336,0,0,14155776,67108864,67108864,0,67108864,54024008,53689234,0,1048576,237742,762030,11150,2132,0,494225,8399532,0,4194727,4204805,13631488,0,3670016,1048576,1048576,0,4194304,9437184,0,0,360,33554432,54540189,4194304,0,0,2375,501266,0,11224,8388608,0,4194401,905969664,6291456,0,0,0,524288,524288,0,15326,16608723,0,16777216,4194304,4194304,0,0,0,18076,4194335,4194335,0,228445,0,0,0,33554432,0,0,0,0,644878631,0,2822502661,0,0,0,0,0,473932,0,0,220940,0,0,8388608,336,144,0,0,0,480,8388608,0,0,0,0,311963,0,0,0,10550,0,21082,0,6291456,6289286,96,2729,1864830,0,0,0,0,0,0,0,0,0,3145728,0,0,0,144954,4194304,4189859,144,4301,2097152,524288,1572864,0,0,0,0,0,0,524288,0,4128835,65534,4063245,0,0,8388608,0,42567134,0,1048576,10449,4194344,12587038,604683202,12074441274958565,12074463093264885,12074463093587922,12074441521071863
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/prev_analysis/1.csv
index 222a4e7eab..95734ae62d 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/prev_analysis/1.csv
@@ -1,2 +1,2 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 __amd_rocclr_fillBuffer.kd,1,323037.0,323037.0,323037.0,100.0
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/prev_analysis/1001.csv
index 2923ed58d3..25f1221e3b 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,18.0,Instr per wave
 SMEM,8.0,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/prev_analysis/101.csv
index 4a1cb8323c..f1fedb2866 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx908
 mi100
 48
 1228.8
-SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/prev_analysis/1202.csv
index 04b9a4d205..f0ae3d2a86 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,2803.9585037231445,2803.9585037231445,2803.9585037231445,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/prev_analysis/1901.csv
index 0ccb0b5c06..e476fd3d94 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,8.0,smem_
 VALU,22.0,valu_
 MFMA,,mfma_
 VMEM,2.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,6.0,br_
 VGPR,8.0,vgpr_
 SGPR,32.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,524288.0,wavefronts_
 Workgroups,131072.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,12.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,8.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,0.0,hbm_rd_
 HBM Wr,8.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,25.0,vl1_coales_
 VL1 Stall,22.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,30.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/prev_analysis/2001.csv
index 90cd5504cd..5794a6cd05 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/prev_analysis/2001.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/prev_analysis/201.csv
index 2ce19a46d7..ed8751eba8 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,23.51315634735707,Pct,100,23.51315634735707
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,64.0,Threads,64,100.0
 IPC - Issue,0.9193548387096774,Instr/cycle,5,18.387096774193548
-LDS BW,0.0,Gb/sec,23070.72,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,23070.72,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99847361791667,Pct,100,99.99847361791667
 Instr Cache BW,1246.461501314091,Gb/s,4614.144,27.013927205438126
 Scalar L1D Cache Hit Rate,99.99656324828408,Pct,100,99.99656324828408
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/prev_analysis/602.csv
index 26498a82b0..685a022cff 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,0.0,0,0,Simd
 Insufficient SIMD VGPRs,0.0,0,0,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/prev_analysis/701.csv
index ebf5f22ba4..1d3a71c87a 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,8.0,8,8,Registers
 SGPRs,32.0,32,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/sysinfo.csv
index 04ab9d5580..36b15adf90 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-D_str_inv1,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 11:00:09 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+D_str_inv1,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 11:00:09 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/timestamps.csv
index a6c58ac596..c39d4dfca0 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,830681,830686,33554432,256,0,0,8,32,6464,0x0,0x7fbf15604180,12074463093222399,12074463093264885,12074463093587922,12074463093698343
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,830681,830686,32768,256,0,0,24,24,12480,0x0,0x7fbf15635100,12074463108256507,12074463108356859,12074463108363579,12074463108368686
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,830681,830686,4194304,256,0,0,24,24,12928,0x7fc021203900,0x7fbf15635140,12074463108410934,12074463108424379,12074463108559737,12074463108562777
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/SQ_IFETCH_LEVEL.csv
index 32c6d5545e..7c06b2e0a9 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/SQ_IFETCH_LEVEL.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,109218,109218,33554432,256,0,0,4,32,4160,0x0,0x7f241e004280,384814,384814,524288,4718592,680569,76276932,15428835647708,15428078775885,15428979437892,15428979551052
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/SQ_INST_LEVEL_LDS.csv
index de14d7c613..55173aeba7 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/SQ_INST_LEVEL_LDS.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,111070,111070,33554432,256,0,0,4,32,4160,0x0,0x7f3614204280,0,0,0,15443413743731,15442664486442,15443560442203,15443560533493
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/SQ_INST_LEVEL_SMEM.csv
index df53b425e5..2c7029840d 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/SQ_INST_LEVEL_SMEM.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,108995,108995,33554432,256,0,0,4,32,4160,0x0,0x7f94bd804280,3670016,2922022,327140336,15427931737573,15422297108553,15428078776212,15428078891282
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/SQ_INST_LEVEL_VMEM.csv
index b08ac7297e..fbd2ffccbc 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/SQ_INST_LEVEL_VMEM.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,110847,110847,33554432,256,0,0,4,32,4160,0x0,0x7f8db6e04280,524288,5457086,611162336,15442516251984,15441505225065,15442664485380,15442664573160
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/SQ_LEVEL_WAVES.csv
index 6d38e51f5e..3d25887564 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/SQ_LEVEL_WAVES.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,109441,109441,33554432,256,0,0,4,32,4160,0x0,0x7efd0c204280,381889,381889,8617,3055120,524288,240997938,2970095,0,980220332,15429744263467,15428979438109,15429888563599,15429888676869
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/pmc_dispatch_info.csv
index 8226fe9c0f..63bb17b9f9 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/pmc_dispatch_info.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/pmc_perf.csv
index e16c8adc83..b0a2c3790d 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/pmc_perf.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDI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],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBufferAligned.kd,0,0,0,110208,110208,33554432,256,0,0,4,32,4160,0x0,0x7f7d1a804280,3084520,2998628,524288,38959158,244412198,392,224,0,385564,385564,39224203.0,38202085.0,5.0,4192492.0,31367065.0,31006019.0,38182960.0,37623900.0,3082809,3005031,385564,0,385564,0,12338048.0,9464963.0,0.0,0.0,0,0,616,0,4718592,4714824,112,3656,377941,0.0,0.0,0.0,524288.0,28614170.0,27895862.0,7709.0,524288.0,131072,524288,301,387500,2590,0,56.0,302.0,0.0,4194696.0,0,0,0,0,0,7340032,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,20276977.0,524288.0,0,385436,0,0,0,385436,0,0,0,385436,0,0,0,385436,0,0,0,385436,0,0,0,385436,0,0,0,385436,0,0,0,385436,0,0,0,385436,0,0,0,385436,0,0,0,385436,0,0,0,385436,0,0,0,385436,0,0,0,385436,0,0,0,385436,0,0,0,385436,0,0,0,385436,0,0,0,385436,0,0,0,385436,0,0,0,385436,0,0,0,385436,0,0,0,385436,0,0,0,385436,0,0,0,385436,0,0,0,385436,0,0,0,385436,0,0,0,385436,0,0,0,385436,0,0,0,385436,0,0,0,385436,0,0,0,385436,0,0,0,385436,0,0,0,0,0,0.0,21515620.0,0,0,0,0,1,0,0,0,36,0,0,0,0,0,0,0,2,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,168,0,0,0,2,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,0,0,0,0,0,0,4,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,0,0,0,0,0,0,1,0,0,0,524288.0,0.0,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,43934,129024,129024,0,333,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,551111,129024,129024,0,44993,129024,129024,0,509,129024,129024,0,0,129024,129024,0,186,129024,129024,0,1060,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,278388,129024,129024,0,27630,129024,129024,0,874,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,45638,129024,129024,0,390,129024,129024,524288.0,0.0,43344,0,0,50316636,44847,0,0,50561990,44518,0,0,50167861,46416,0,0,51696966,44439,0,0,51185939,46282,0,0,51619722,44939,0,0,50832863,47950,0,0,52925361,44806,0,0,50798496,46722,0,0,51106945,44904,0,0,50298159,48882,0,0,52424747,45581,0,0,51377134,46625,0,0,51514809,45745,0,0,51286079,48833,0,0,53206603,43946,0,0,50496247,46296,0,0,50811788,44730,0,0,50273217,46564,0,0,51905443,44824,0,0,51040362,46831,0,0,51514902,45313,0,0,50981512,47666,0,0,52742601,45139,0,0,50888727,46059,0,0,50914824,44897,0,0,50256287,48442,0,0,52358347,45123,0,0,51643942,46963,0,0,51591901,46122,0,0,51122173,49322,0,0,53298400,0.0,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65568,32,131104,65646,65538,112,131184,65536,65537,1,131073,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65591,65537,56,131128,65536,65536,0,131072,65536,65568,32,131104,65536,65648,112,131184,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65538,2,131074,65536,65571,35,131107,65758,65538,224,131296,65536,65536,0,131072,65536,65536,0,131072,65536,65592,56,131128,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65568,32,131104,65591,65537,56,131128,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131184,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131296,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131128,0,131072,1036821,0,524288,3670016,3663353,224,6439,1048576,33554432.0,33554432.0,0.0,33554432.0,30142327.0,28489558.0,0.0,524288.0,216596,535781,8614,883,0,382281,4195056.0,0.0,2097594.0,2097462.0,1048576,1048576,0,524288,0,524288,7340032,0,0.0,0.0,104.0,8388608.0,29445401.0,2097152.0,0.0,201081,0,1208,381761,0,751.0,4194304.0,0.0,2064387.0,25690112,9437184,0,0,0,0,0,0,13283.0,8242495.0,0.0,8388608.0,2097152.0,4194304.0,9538513,0,0,8841,4128768.0,4128768.0,0.0,1477480.0,0,0,0,0,0,0,5767168,1048576,315211156.0,0.0,1471367434.0,0.0,40.0,0.0,0,0,371437,0.0,0.0,1476646.0,0.0,3670016,524288,0,0,0,2621440,524288,175606413,4194304.0,0.0,0.0,0.0,0.0,1253961.0,0,0,0.0,309.0,0.0,602.0,42153876,24117248,0,0,9437184,11010048,0,3145728,0.0,0.0,0.0,0.0,0.0,0.0,0,1572864,0.0,0.0,0.0,195567.0,524288,524288,0,3670016,7340032,603979776,4718592,0,0.0,0.0,0.0,0.0,0.0,0.0,524288,0,2064384.0,0.0,2031623.0,0.0,0,0,524288,0,0,0,0,33554432,0.0,4194304.0,0.0,18958769.0,0.0,0.0,143.0,4128768.0,896072.0,1694413436.0,15431139136981,15444196327800,15444196567481,15431289319032
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/prev_analysis/1.csv
index 9633324915..1576be7e05 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/prev_analysis/1.csv
@@ -1,2 +1,2 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 __amd_rocclr_fillBufferAligned.kd,1,239681.0,239681.0,239681.0,100.0
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/prev_analysis/1001.csv
index e34ed0c6f6..0850fc4acd 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,18.0,Instr per wave
 VMEM,1.0,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,0.0,Instr per wave
 SALU,14.0,Instr per wave
 SMEM,7.0,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/prev_analysis/101.csv
index 86e6d9ee85..0072f8509e 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx90a
 mi200
 56
 1638.4
-roofline|SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+roofline|SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/prev_analysis/1202.csv
index beb521b61b..619d5df73f 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,1864.7170867919922,1864.7170867919922,1864.7170867919922,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/prev_analysis/1901.csv
index 30246483bd..ea12394ca7 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,7.0,smem_
 VALU,18.0,valu_
 MFMA,0.0,mfma_
 VMEM,1.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,5.0,br_
 VGPR,4.0,vgpr_
 SGPR,32.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,524288.0,wavefronts_
 Workgroups,131072.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,9.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,8.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,0.0,hbm_rd_
 HBM Wr,8.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,25.0,vl1_coales_
 VL1 Stall,11.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,25.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/prev_analysis/2001.csv
index 8226fe9c0f..63bb17b9f9 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/prev_analysis/2001.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/prev_analysis/201.csv
index ea962a35c5..c8a24c7d80 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,23.534913489369817,Pct,100,23.534913489369817
 MFMA Util,0.0,Pct,100,0.0
 VALU Active Threads/Wave,64.0,Threads,64,100.0
 IPC - Issue,1.0,Instr/cycle,5,20.0
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.9976245700896,Pct,100,99.9976245700896
 Instr Cache BW,1259.9659046816394,Gb/s,6092.8,20.67958745866661
 Scalar L1D Cache Hit Rate,99.99388575700743,Pct,100,99.99388575700743
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/prev_analysis/602.csv
index 65e1fe7a80..8a8d1a622a 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,9538513.0,9538513,9538513,Simd
 Insufficient SIMD VGPRs,0.0,0,0,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/prev_analysis/701.csv
index c47e77a25f..f8ed8cd0d3 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,4.0,4,4,Registers
 SGPRs,32.0,32,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/sysinfo.csv
index 51baa4a65a..67b27904ea 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-D_str_inv1,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:10:23 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,roofline|SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+D_str_inv1,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:10:23 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,roofline|SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/timestamps.csv
index 036058157a..7aca890d2f 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv1/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,111153,111153,33554432,256,0,0,4,32,4160,0x0,0x7ff5c8604280,15444196302369,15444196327800,15444196567481,15444196654711
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,111153,111153,32768,256,0,0,12,24,13888,0x0,0x7ff5c8623f80,15444201320695,15444201335821,15444201348941,15444201366234
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,111153,111153,4194304,256,0,0,12,24,14336,0x7ff5d6ded380,0x7ff5c8623fc0,15444201370974,15444201416301,15444201508942,15444201511020
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/SQ_IFETCH_LEVEL.csv
index 3a095c10ab..d6bf2e803e 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/SQ_IFETCH_LEVEL.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,833668,833673,33554432,256,0,0,8,32,6464,0x0,0x7f6b11004180,506089,506089,524288,6291456,799158,102231340,12074521253791684,12074521496435173,12074521496760291,12074521496870754
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/SQ_INST_LEVEL_LDS.csv
index 1d268ad6f2..ca1c6deeb7 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/SQ_INST_LEVEL_LDS.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,835464,835469,33554432,256,0,0,8,32,6464,0x0,0x7f8aa2a04180,0,0,0,12074542709022891,12074542955697078,12074542956019796,12074542956131198
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/SQ_INST_LEVEL_SMEM.csv
index 20c01ca9eb..ad15d4f7be 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/SQ_INST_LEVEL_SMEM.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,835085,835090,33554432,256,0,0,8,32,6464,0x0,0x7f0daee04180,4194304,3194932,409201880,12074540250788010,12074540497238393,12074540497562551,12074540497668294
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/SQ_INST_LEVEL_VMEM.csv
index 0c3de78892..435f09f4bd 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/SQ_INST_LEVEL_VMEM.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,835274,835279,33554432,256,0,0,8,32,6464,0x0,0x7f4162604180,1048576,11225573,1436771232,12074541473844928,12074541722775338,12074541723097097,12074541723210360
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/SQ_LEVEL_WAVES.csv
index 9cc2e185d0..889f434880 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/SQ_LEVEL_WAVES.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,835655,835660,33554432,256,0,0,8,32,6464,0x0,0x7ff5ace04180,499729,499729,17513,3997840,524288,366071030,3788815,0,1479052348,12074543940502982,12074544184880067,12074544185201185,12074544185312297
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/pmc_dispatch_info.csv
index 90cd5504cd..5794a6cd05 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/pmc_dispatch_info.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/pmc_perf.csv
index 8e5ca7fa41..cdc18704b5 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/pmc_perf.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBuffer.kd,0,0,0,834403,834408,33554432,256,0,0,8,32,6464,0x0,0x7fc4f7a04180,1048576,0,1048576,9437184,0,4194304,1048576,0,504481,504481,57803099,55334214,146,13426210,54551949,54465822,55289251,54099673,4035848,3837990,504481,0,504481,0,16143392,15277648,0,0,0,0,0,17544609,1048576,0,505129,0,0,0,505129,0,0,0,505129,0,0,0,505129,0,0,0,505129,0,0,0,505129,0,0,0,505129,0,0,0,505129,0,0,0,505129,0,0,0,505129,0,0,0,505129,0,0,0,505129,0,0,0,505129,0,0,0,505129,0,0,0,505129,0,0,0,505129,0,0,0,505129,0,0,0,505129,0,0,0,505129,0,0,0,505129,0,0,0,505129,0,0,0,505129,0,0,0,505129,0,0,0,505129,0,0,0,505129,0,0,0,505129,0,0,0,505129,0,0,0,505129,0,0,0,505129,0,0,0,505129,0,0,0,505129,0,0,0,505129,0,0,0,37392329,0,0,0,0,52,0,0,0,0,0,0,0,2455,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2590,0,0,0,0,0,0,0,3,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2643,0,0,0,0,0,0,0,51,0,0,0,0,0,0,0,2704,0,0,0,66,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,48,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,1048576,0,0,3143813,131076,131076,0,16013,131072,131072,0,0,131076,131076,0,20232,131072,131072,0,563091,131076,131076,0,0,131072,131072,0,798,131076,131076,0,0,131072,131072,0,0,131076,131076,0,0,131076,131076,0,0,131072,131072,0,0,131072,131072,0,3045136,131072,131072,0,0,131076,131076,0,0,131072,131072,0,0,131072,131072,0,5824,131072,131072,0,781,131072,131072,0,0,131072,131072,0,0,131076,131076,0,0,131072,131072,0,0,131076,131076,0,276,131072,131072,0,0,131076,131076,0,3124966,131072,131072,0,0,131072,131072,0,1500,131072,131072,0,0,131076,131076,0,3058821,131077,131077,0,0,131072,131072,0,0,131076,131076,0,0,131076,131076,1048576,0,49057,0,0,30166629,1281,0,0,17548270,1436,0,0,17348305,1758,0,0,17304678,1639,0,0,17293752,884,0,0,17501955,1712,0,0,17969063,1870,0,0,18735802,1081,0,0,17160090,862,0,0,17482760,998,0,0,16822884,767,0,0,16807872,48422,0,0,30136827,1071,0,0,17533770,1011,0,0,17843964,1102,0,0,18575175,46814,0,0,29448934,885,0,0,17112059,1996,0,0,17008388,800,0,0,16727767,904,0,0,17151434,880,0,0,17682623,1874,0,0,17940742,831,0,0,18590823,1049,0,0,16911038,753,0,0,16973063,887,0,0,16599657,1019,0,0,16734751,48022,0,0,30018109,914,0,0,17662152,814,0,0,17821216,1171,0,0,18530560,1048576,131072,131120,48,262192,131260,131097,213,262357,131072,131073,1,262145,131072,131072,0,262144,131072,131072,0,262144,131072,133707,2635,264779,131072,131072,0,262144,131119,131073,48,262192,131072,131072,0,262144,131072,133536,2464,264608,131072,131072,0,262144,131119,131073,48,262192,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131120,48,262192,131213,131075,144,262288,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,133816,2744,264888,131072,131073,1,262145,131072,131072,0,262144,131072,131072,0,262144,131072,133679,2607,264751,131072,131120,48,262192,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,262144,0,262144,262336,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262288,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,0,0,3145728,524288,32505856,369062752,217634028,118922868,482617,0,0,0,1048576,52784409,52546767,1048576,1048576,131072,524288,725,505524,4441,0,96,10836,0,8388944,32505856,4011664,3801814,56894352,11534336,0,0,14155776,67108864,67108864,0,67108864,54133226,53795461,0,1048576,231882,756170,11831,1981,0,496826,8399651,0,4194727,4204924,13631488,0,3670016,1048576,1048576,0,4194304,9437184,0,0,360,33554432,54536465,4194304,0,0,2889,503328,0,11245,8388608,0,4194358,905969664,6291456,0,0,0,524288,524288,0,15344,16608589,0,16777216,4194304,4194304,0,0,0,16376,4194348,4194348,0,219634,0,0,0,33554432,0,0,0,0,636171344,0,2778572087,0,0,0,0,0,475458,0,0,222435,0,0,8388608,336,144,0,0,0,480,8388608,0,0,0,0,370002,0,0,0,10865,0,21712,0,6291456,6289425,96,2164,1906988,0,0,0,0,0,0,0,0,0,3145728,0,0,0,156405,4194304,4189861,144,4299,2097152,524288,1572864,0,0,0,0,0,0,524288,0,4128833,65535,4063248,0,0,8388608,0,41856931,0,1048576,10691,4194367,13325185,612800922,12074523331941628,12074545028345137,12074545028669134,12074523579742883
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/prev_analysis/1.csv
index b6df33fdd1..e606f2439e 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/prev_analysis/1.csv
@@ -1,2 +1,2 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 __amd_rocclr_fillBuffer.kd,1,323997.0,323997.0,323997.0,100.0
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/prev_analysis/1001.csv
index 2923ed58d3..25f1221e3b 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,18.0,Instr per wave
 SMEM,8.0,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/prev_analysis/101.csv
index ef67ac8820..f4f399f24d 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx908
 mi100
 48
 1228.8
-SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/prev_analysis/1202.csv
index 088fca8167..1541751f7f 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,2815.725341796875,2815.725341796875,2815.725341796875,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/prev_analysis/1901.csv
index 96c7ea0db4..177a16b1fd 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,8.0,smem_
 VALU,22.0,valu_
 MFMA,,mfma_
 VMEM,2.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,6.0,br_
 VGPR,8.0,vgpr_
 SGPR,32.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,524288.0,wavefronts_
 Workgroups,131072.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,12.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,8.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,0.0,hbm_rd_
 HBM Wr,8.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,25.0,vl1_coales_
 VL1 Stall,23.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,30.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/prev_analysis/2001.csv
index 90cd5504cd..5794a6cd05 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/prev_analysis/2001.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/prev_analysis/201.csv
index c0f6c52b94..2b3448bb4f 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,23.38339798723837,Pct,100,23.38339798723837
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,64.0,Threads,64,100.0
 IPC - Issue,0.9193548387096774,Instr/cycle,5,18.387096774193548
-LDS BW,0.0,Gb/sec,23070.72,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,23070.72,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.9984736516501,Pct,100,99.9984736516501
 Instr Cache BW,1242.7682478541467,Gb/s,4614.144,26.933885198514538
 Scalar L1D Cache Hit Rate,99.99656324992452,Pct,100,99.99656324992452
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/prev_analysis/602.csv
index 0a4f684335..f6fe6c3603 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,0.0,0,0,Simd
 Insufficient SIMD VGPRs,0.0,0,0,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/prev_analysis/701.csv
index ebf5f22ba4..1d3a71c87a 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,8.0,8,8,Registers
 SGPRs,32.0,32,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/sysinfo.csv
index e0a6d2b899..6ef79e870b 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-D_str_inv2,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 11:01:31 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+D_str_inv2,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 11:01:31 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/timestamps.csv
index ecb5fa0042..76eb9f1dc9 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,835704,835709,33554432,256,0,0,8,32,6464,0x0,0x7f84a8604180,12074545028298223,12074545028345137,12074545028669134,12074545028757136
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,835704,835709,32768,256,0,0,24,24,12480,0x0,0x7f84a8635100,12074545043676542,12074545043776525,12074545043783725,12074545043804580
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,835704,835709,4194304,256,0,0,24,24,12928,0x7f85b427c900,0x7f84a8635140,12074545043837120,12074545043850605,12074545043987884,12074545043991067
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/SQ_IFETCH_LEVEL.csv
index 12d462613b..182c2bf730 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/SQ_IFETCH_LEVEL.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,115320,115320,33554432,256,0,0,4,32,4160,0x0,0x7f6a30e04280,381074,381074,524288,4718592,682157,76382296,15525307942314,15524542112946,15525458166097,15525458279887
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/SQ_INST_LEVEL_LDS.csv
index 7f4f6211c4..d57f8427c5 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/SQ_INST_LEVEL_LDS.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,117172,117172,33554432,256,0,0,4,32,4160,0x0,0x7f9d1c204280,0,0,0,15539871294476,15539112749109,15540020123353,15540020237843
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/SQ_INST_LEVEL_SMEM.csv
index 79d64dcaa2..5795d032cc 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/SQ_INST_LEVEL_SMEM.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,115097,115097,33554432,256,0,0,4,32,4160,0x0,0x7f0ed7e04280,3670016,3072816,344543280,15524395875898,15518833176077,15524542113201,15524542226661
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/SQ_INST_LEVEL_VMEM.csv
index 873250ed33..ea4588e353 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/SQ_INST_LEVEL_VMEM.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,116949,116949,33554432,256,0,0,4,32,4160,0x0,0x7f9e6ae04280,524288,5468427,612409540,15538960446480,15537948802091,15539112749268,15539112863508
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/SQ_LEVEL_WAVES.csv
index e6a18719b6..dee7e2ae21 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/SQ_LEVEL_WAVES.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,115543,115543,33554432,256,0,0,4,32,4160,0x0,0x7f3bd2604280,379539,379539,8820,3036320,524288,238562609,2949146,0,970513160,15526219525683,15525458166031,15526363286923,15526363401313
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/pmc_dispatch_info.csv
index 8226fe9c0f..63bb17b9f9 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/pmc_dispatch_info.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/pmc_perf.csv
index 59b7a79667..c6653f9f78 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/pmc_perf.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDI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],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBufferAligned.kd,0,0,0,116310,116310,33554432,256,0,0,4,32,4160,0x0,0x7fb649004280,3088392,3000704,524288,38956150,243829857,392,224,0,386048,386048,39250619.0,38218653.0,3.0,4166013.0,31358724.0,30993438.0,38197639.0,37639265.0,3086681,3007107,386048,0,386048,0,12353536.0,9476793.0,0.0,0.0,0,0,616,0,4718592,4714761,112,3719,373130,0.0,0.0,0.0,524288.0,28298496.0,27555509.0,7837.0,524288.0,131072,524288,301,382678,2632,0,56.0,304.0,0.0,4194696.0,0,0,0,0,0,7340032,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,19893508.0,524288.0,0,381718,0,0,0,381718,0,0,0,381718,0,0,0,381718,0,0,0,381718,0,0,0,381718,0,0,0,381718,0,0,0,381718,0,0,0,381718,0,0,0,381718,0,0,0,381718,0,0,0,381718,0,0,0,381718,0,0,0,381718,0,0,0,381718,0,0,0,381718,0,0,0,381718,0,0,0,381718,0,0,0,381718,0,0,0,381718,0,0,0,381718,0,0,0,381718,0,0,0,381718,0,0,0,381718,0,0,0,381718,0,0,0,381718,0,0,0,381718,0,0,0,381718,0,0,0,381718,0,0,0,381718,0,0,0,381718,0,0,0,381718,0,0,0,0,0,0.0,21330067.0,32,0,0,0,0,0,0,0,56,0,0,0,1,0,0,0,2,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,35,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4,0,0,0,112,0,0,0,1,0,0,0,1,0,0,0,0,0,0,0,32,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,1,0,0,0,524288.0,0.0,0,43937,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,333,129024,129024,0,198,129024,129024,0,0,129024,129024,0,555350,129024,129024,0,0,129024,129024,0,44804,129024,129024,0,502,129024,129024,0,0,129024,129024,0,852,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,28189,129024,129024,0,0,129024,129024,0,165,129024,129024,0,287390,129024,129024,0,886,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,44376,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,187,129024,129024,524288.0,0.0,44259,0,0,50415367,44957,0,0,50585818,43224,0,0,49746550,46832,0,0,51823920,44294,0,0,50895068,45785,0,0,51274157,45171,0,0,50887289,48165,0,0,52890252,45159,0,0,50929720,46190,0,0,51058842,46118,0,0,50521546,47576,0,0,52206197,46076,0,0,51506362,46523,0,0,51408603,45934,0,0,51067208,49347,0,0,53096973,43960,0,0,50349571,46194,0,0,50686978,45303,0,0,50334749,47309,0,0,52000806,44976,0,0,51023814,45590,0,0,51163702,46893,0,0,51403185,48083,0,0,52651510,44540,0,0,50583797,45962,0,0,51043855,45217,0,0,50245878,47929,0,0,52134281,45577,0,0,51472780,46696,0,0,51554420,45983,0,0,51034438,48776,0,0,52969870,0.0,65536,65536,0,131072,65536,65536,0,131072,65536,65570,34,131106,65536,65536,0,131072,65646,65538,112,131184,65536,65536,0,131072,65536,65592,56,131128,65591,65538,57,131129,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65568,32,131104,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65537,1,131073,65536,65536,0,131072,65536,65569,33,131105,65536,65536,0,131072,65758,65650,336,131408,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65568,32,131104,65536,65536,0,131072,65591,65537,56,131128,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131184,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131296,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131128,0,131072,1114262,0,524288,3670016,3663238,224,6554,1048576,33554432.0,33554432.0,0.0,33554432.0,30290409.0,28666348.0,0.0,524288.0,222118,537388,8638,919,0,385462,4195056.0,0.0,2097594.0,2097462.0,1048576,1048576,0,524288,0,524288,7340032,0,0.0,0.0,104.0,8388608.0,29598584.0,2097152.0,0.0,205613,0,1216,384036,0,751.0,4194304.0,0.0,2064387.0,25690112,9437184,0,0,0,0,0,0,13291.0,8242407.0,0.0,8388608.0,2097152.0,4194304.0,9773647,0,0,8834,4128768.0,4128768.0,0.0,1468669.0,0,0,0,0,0,0,5767168,1048576,316630081.0,0.0,1476139155.0,0.0,44.0,0.0,0,0,374127,0.0,0.0,1490820.0,0.0,3670016,524288,0,0,0,2621440,524288,177486158,4194304.0,0.0,0.0,0.0,0.0,1221449.0,0,0,0.0,312.0,0.0,608.0,43200946,24117248,0,0,9437184,11010048,0,3145728,0.0,0.0,0.0,0.0,0.0,0.0,0,1572864,0.0,0.0,0.0,202271.0,524288,524288,0,3670016,7340032,603979776,4718592,0,0.0,0.0,0.0,0.0,0.0,0.0,524288,0,2064384.0,0.0,2031623.0,0.0,0,0,524288,0,0,0,0,33554432,0.0,4194304.0,0.0,18879980.0,0.0,0.0,144.0,4128768.0,675419.0,1692352412.0,15527615148362,15540660385679,15540660626800,15527763776554
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/prev_analysis/1.csv
index 3f74103448..64cc3961ae 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/prev_analysis/1.csv
@@ -1,2 +1,2 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 __amd_rocclr_fillBufferAligned.kd,1,241121.0,241121.0,241121.0,100.0
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/prev_analysis/1001.csv
index e34ed0c6f6..0850fc4acd 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,18.0,Instr per wave
 VMEM,1.0,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,0.0,Instr per wave
 SALU,14.0,Instr per wave
 SMEM,7.0,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/prev_analysis/101.csv
index 8c36ad3835..ad0cdf7b90 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx90a
 mi200
 56
 1638.4
-roofline|SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+roofline|SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/prev_analysis/1202.csv
index e01f163637..7d91bb84da 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,1860.2741775512695,1860.2741775512695,1860.2741775512695,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/prev_analysis/1901.csv
index 093e35f1ff..1fdaf2d857 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,7.0,smem_
 VALU,18.0,valu_
 MFMA,0.0,mfma_
 VMEM,1.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,5.0,br_
 VGPR,4.0,vgpr_
 SGPR,32.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,524288.0,wavefronts_
 Workgroups,131072.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,9.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,8.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,0.0,hbm_rd_
 HBM Wr,8.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,25.0,vl1_coales_
 VL1 Stall,11.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,25.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/prev_analysis/2001.csv
index 8226fe9c0f..63bb17b9f9 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/prev_analysis/2001.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/prev_analysis/201.csv
index a149d7f1cb..cc76cd8f2c 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,23.505407059783717,Pct,100,23.505407059783717
 MFMA Util,0.0,Pct,100,0.0
 VALU Active Threads/Wave,64.0,Threads,64,100.0
 IPC - Issue,1.0,Instr/cycle,5,20.0
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99762453834917,Pct,100,99.99762453834917
 Instr Cache BW,1252.4412556351376,Gb/s,6092.8,20.556086784977968
 Scalar L1D Cache Hit Rate,99.99388556507479,Pct,100,99.99388556507479
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/prev_analysis/602.csv
index 46712e81a2..5be7ca590d 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,9773647.0,9773647,9773647,Simd
 Insufficient SIMD VGPRs,0.0,0,0,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/prev_analysis/701.csv
index c47e77a25f..f8ed8cd0d3 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,4.0,4,4,Registers
 SGPRs,32.0,32,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/sysinfo.csv
index e426a8b824..cb7dd709e5 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-D_str_inv2,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:12:00 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,roofline|SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+D_str_inv2,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:12:00 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,roofline|SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/timestamps.csv
index 2488eff827..8ac77a16ac 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv2/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,117255,117255,33554432,256,0,0,4,32,4160,0x0,0x7ff19e604280,15540660360598,15540660385679,15540660626800,15540660677970
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,117255,117255,32768,256,0,0,12,24,13888,0x0,0x7ff19e623f80,15540665383634,15540665398658,15540665412258,15540665430013
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,117255,117255,4194304,256,0,0,12,24,14336,0x7ff1a152a380,0x7ff19e623fc0,15540665434283,15540665478659,15540665571139,15540665573279
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/SQ_IFETCH_LEVEL.csv
index 1d9ae5985c..4710eace1b 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/SQ_IFETCH_LEVEL.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,838678,838683,33554432,256,0,0,8,32,6464,0x0,0x7f688ba04180,502129,502129,524288,6291456,791982,101387712,12074606251087586,12074606493922782,12074606494245660,12074606494368661
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/SQ_INST_LEVEL_LDS.csv
index 4fc6930ec9..3869bf7967 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/SQ_INST_LEVEL_LDS.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,840474,840479,33554432,256,0,0,8,32,6464,0x0,0x7f41ea804180,0,0,0,12074627641541703,12074627885800295,12074627886123493,12074627886225846
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/SQ_INST_LEVEL_SMEM.csv
index 20891189cc..f66a5ef83d 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/SQ_INST_LEVEL_SMEM.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,840095,840100,33554432,256,0,0,8,32,6464,0x0,0x7fd005004180,4194304,3157320,403932688,12074625196773238,12074625435294704,12074625435619342,12074625435728314
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/SQ_INST_LEVEL_VMEM.csv
index 69c738ecb9..b05814e9c0 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/SQ_INST_LEVEL_VMEM.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,840285,840290,33554432,256,0,0,8,32,6464,0x0,0x7ff3e6c04180,1048576,11060940,1415938316,12074626416286070,12074626661345573,12074626661669251,12074626661777963
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/SQ_LEVEL_WAVES.csv
index 3795db1460..c6db18de65 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/SQ_LEVEL_WAVES.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,840665,840670,33554432,256,0,0,8,32,6464,0x0,0x7f95ef004180,507161,507161,18295,4057296,524288,373646433,3845835,0,1509428396,12074628863738112,12074629107904203,12074629108229641,12074629108341314
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/pmc_dispatch_info.csv
index 90cd5504cd..5794a6cd05 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/pmc_dispatch_info.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/pmc_perf.csv
index d873716a6e..3cc6bb7a5c 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/pmc_perf.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBuffer.kd,0,0,0,839413,839418,33554432,256,0,0,8,32,6464,0x0,0x7f01e2004180,1048576,0,1048576,9437184,0,4194304,1048576,0,500881,500881,57404815,55151275,154,12162273,54357132,54271421,55116369,53933641,4007048,3811438,500881,0,500881,0,16028192,15187738,0,0,0,0,0,17406746,1048576,0,502945,0,0,0,502945,0,0,0,502945,0,0,0,502945,0,0,0,502945,0,0,0,502945,0,0,0,502945,0,0,0,502945,0,0,0,502945,0,0,0,502945,0,0,0,502945,0,0,0,502945,0,0,0,502945,0,0,0,502945,0,0,0,502945,0,0,0,502945,0,0,0,502945,0,0,0,502945,0,0,0,502945,0,0,0,502945,0,0,0,502945,0,0,0,502945,0,0,0,502945,0,0,0,502945,0,0,0,502945,0,0,0,502945,0,0,0,502945,0,0,0,502945,0,0,0,502945,0,0,0,502945,0,0,0,502945,0,0,0,502945,0,0,0,37483877,0,0,0,0,4,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,48,0,0,0,0,0,0,0,2529,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,2643,0,0,0,0,0,0,0,0,0,0,0,3,0,0,0,0,0,0,0,0,0,0,0,4,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,96,0,0,0,2705,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2707,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,18,0,0,0,1048576,0,0,0,131072,131072,0,15436,131076,131076,0,0,131072,131072,0,3145168,131072,131072,0,0,131072,131072,0,0,131072,131072,0,0,131072,131072,0,0,131076,131076,0,8581,131072,131072,0,0,131080,131080,0,259,131076,131076,0,0,131072,131072,0,0,131076,131076,0,20988,131072,131072,0,833,131072,131072,0,2904853,131075,131075,0,1722,131076,131076,0,784,131076,131076,0,0,131076,131076,0,2907802,131072,131072,0,0,131072,131072,0,0,131072,131072,0,0,131072,131072,0,563205,131076,131076,0,0,131072,131072,0,0,131072,131072,0,0,131072,131072,0,0,131072,131072,0,0,131072,131072,0,0,131072,131072,0,0,131072,131072,0,2979778,131076,131076,1048576,0,838,0,0,17051124,1621,0,0,17165910,1008,0,0,17138245,863,0,0,17279670,44900,0,0,29645295,893,0,0,17501621,1083,0,0,17941522,1076,0,0,18910940,46849,0,0,29945560,716,0,0,17210210,1058,0,0,16775600,1198,0,0,17166274,945,0,0,17144046,1136,0,0,17395220,1318,0,0,17920482,1045,0,0,18827964,789,0,0,16777448,733,0,0,16787235,784,0,0,17009335,1004,0,0,17031544,50038,0,0,30282530,773,0,0,17129751,857,0,0,17912457,825,0,0,18778792,38699,0,0,28277325,1088,0,0,17159865,1064,0,0,16709669,749,0,0,17034802,789,0,0,17167904,1573,0,0,17434645,700,0,0,17905454,1474,0,0,18894322,1048576,131072,131073,1,262145,131260,131124,240,262384,131072,131072,0,262144,131072,131072,0,262144,131072,131073,1,262145,131072,131121,49,262193,131072,131072,0,262144,131072,133594,2522,264666,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,133790,2718,264862,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131119,131073,48,262192,131072,131072,0,262144,131213,131075,144,262288,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,133667,2595,264739,131072,131072,0,262144,131072,131120,48,262192,131072,131075,3,262147,131072,133770,2698,264842,131119,131073,48,262192,131072,131072,0,262144,131072,131072,0,262144,131072,131097,25,262169,262144,0,262144,262336,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262288,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,0,0,3145728,524288,32505856,368465451,216267374,119692221,478652,0,0,0,1048576,52202240,51968629,1048576,1048576,131072,524288,731,500054,4078,0,96,10601,0,8388944,32505856,4059792,3851493,57629374,11534336,0,0,14155776,67108864,67108864,0,67108864,54647435,54283627,0,1048576,249550,773838,11647,3115,0,503107,8399721,0,4194727,4204994,13631488,0,3670016,1048576,1048576,0,4194304,9437184,0,0,360,33554432,54433031,4194304,0,0,3321,498504,0,11113,8388608,0,4194374,905969664,6291456,0,0,0,524288,524288,0,15331,16608646,0,16777216,4194304,4194304,0,0,0,16700,4194366,4194366,0,217960,0,0,0,33554432,0,0,0,0,647973875,0,2824014476,0,0,0,0,0,478533,0,0,218244,0,0,8388608,336,144,0,0,0,480,8388608,0,0,0,0,286513,0,0,0,10568,0,21118,0,6291456,6289565,96,2096,1994360,0,0,0,0,0,0,0,0,0,3145728,0,0,0,145120,4194304,4189867,144,4293,2097152,524288,1572864,0,0,0,0,0,0,524288,0,4128848,65531,4063249,0,0,8388608,0,42292956,0,1048576,10484,4194353,12798488,602607808,12074608332402762,12074629942046408,12074629942371205,12074608577846146
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/prev_analysis/1.csv
index 0b2c87c8c4..4e31a5ad32 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/prev_analysis/1.csv
@@ -1,2 +1,2 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 __amd_rocclr_fillBuffer.kd,1,324797.0,324797.0,324797.0,100.0
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/prev_analysis/1001.csv
index 2923ed58d3..25f1221e3b 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,18.0,Instr per wave
 SMEM,8.0,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/prev_analysis/101.csv
index 59fb4161dc..35e0eb7798 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx908
 mi100
 48
 1228.8
-SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/prev_analysis/1202.csv
index 04e45b4fcb..bc3059a54f 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,2811.168296813965,2811.168296813965,2811.168296813965,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/prev_analysis/1901.csv
index 38cc8c7bbe..009f92a3dc 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,8.0,smem_
 VALU,22.0,valu_
 MFMA,,mfma_
 VMEM,2.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,6.0,br_
 VGPR,8.0,vgpr_
 SGPR,32.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,524288.0,wavefronts_
 Workgroups,131072.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,12.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,8.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,0.0,hbm_rd_
 HBM Wr,8.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,25.0,vl1_coales_
 VL1 Stall,21.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,30.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/prev_analysis/2001.csv
index 90cd5504cd..5794a6cd05 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/prev_analysis/2001.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/prev_analysis/201.csv
index 988d1fd5df..ed14ea8761 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,23.551462323386193,Pct,100,23.551462323386193
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,64.0,Threads,64,100.0
 IPC - Issue,0.9193548387096774,Instr/cycle,5,18.387096774193548
-LDS BW,0.0,Gb/sec,23070.72,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,23070.72,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99847368562472,Pct,100,99.99847368562472
 Instr Cache BW,1239.7072140444648,Gb/s,4614.144,26.867544967050545
 Scalar L1D Cache Hit Rate,99.99656325484587,Pct,100,99.99656325484587
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/prev_analysis/602.csv
index b31043c111..09f0068672 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,0.0,0,0,Simd
 Insufficient SIMD VGPRs,0.0,0,0,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/prev_analysis/701.csv
index ebf5f22ba4..1d3a71c87a 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,8.0,8,8,Registers
 SGPRs,32.0,32,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/sysinfo.csv
index 50d110b2ef..318d1ae981 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-D_str_inv3,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 11:02:56 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+D_str_inv3,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 11:02:56 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/timestamps.csv
index c09bdf084b..464e662054 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,840714,840719,33554432,256,0,0,8,32,6464,0x0,0x7f3b9c404180,12074629941989808,12074629942046408,12074629942371205,12074629942479097
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,840714,840719,32768,256,0,0,24,24,12480,0x0,0x7f3b9c435100,12074629956915505,12074629957014277,12074629957021157,12074629957026963
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,840714,840719,4194304,256,0,0,24,24,12928,0x7f3ca7fca900,0x7f3b9c435140,12074629957069662,12074629957084356,12074629957218435,12074629957221865
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/SQ_IFETCH_LEVEL.csv
index 027514ee5f..f69cbee40d 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/SQ_IFETCH_LEVEL.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,121422,121422,33554432,256,0,0,4,32,4160,0x0,0x7f8469a04280,378422,378422,524288,4718592,682762,76445760,15622029836638,15621264198394,15622178380001,15622178466351
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/SQ_INST_LEVEL_LDS.csv
index 273771ebdc..4e48a72193 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/SQ_INST_LEVEL_LDS.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,123274,123274,33554432,256,0,0,4,32,4160,0x0,0x7ff34cc04280,0,0,0,15636583633052,15635831530541,15636733321351,15636733436191
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/SQ_INST_LEVEL_SMEM.csv
index 30d77e4f80..f623a45050 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/SQ_INST_LEVEL_SMEM.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,121199,121199,33554432,256,0,0,4,32,4160,0x0,0x7f80dae04280,3670016,3089222,345647832,15621116061039,15615538549687,15621264198861,15621264309180
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/SQ_INST_LEVEL_VMEM.csv
index 35d5ad4cde..1a9cf9afa4 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/SQ_INST_LEVEL_VMEM.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,123051,123051,33554432,256,0,0,4,32,4160,0x0,0x7fd76e804280,524288,5467045,612257752,15635679594585,15634672863637,15635831530414,15635831618744
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/SQ_LEVEL_WAVES.csv
index aa273d62f0..9cffe9cff0 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/SQ_LEVEL_WAVES.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,121645,121645,33554432,256,0,0,4,32,4160,0x0,0x7feed0a04280,380068,380068,9079,3040552,524288,238047653,2952227,0,968436988,15622938181641,15622178380185,15623086387871,15623086502721
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/pmc_dispatch_info.csv
index 8226fe9c0f..63bb17b9f9 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/pmc_dispatch_info.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/pmc_perf.csv
index 6f5a715467..4315c6a72c 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/pmc_perf.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDI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],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBufferAligned.kd,0,0,0,122412,122412,33554432,256,0,0,4,32,4160,0x0,0x7f51ad004280,3079536,2990885,524288,38855509,242806577,392,224,0,384941,384941,39123349.0,38188949.0,0.0,4185973.0,31287821.0,30923614.0,38161839.0,37600396.0,3077825,2997287,384941,0,384941,0,12318112.0,9476961.0,0.0,0.0,0,0,616,0,4718592,4714940,112,3540,375370,0.0,0.0,0.0,524288.0,28433996.0,27709423.0,7737.0,524288.0,131072,524288,302,384556,2301,0,56.0,302.0,0.0,4194696.0,0,0,0,0,0,7340032,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,20118996.0,524288.0,0,385167,0,0,0,385167,0,0,0,385167,0,0,0,385167,0,0,0,385167,0,0,0,385167,0,0,0,385167,0,0,0,385167,0,0,0,385167,0,0,0,385167,0,0,0,385167,0,0,0,385167,0,0,0,385167,0,0,0,385167,0,0,0,385167,0,0,0,385167,0,0,0,385167,0,0,0,385167,0,0,0,385167,0,0,0,385167,0,0,0,385167,0,0,0,385167,0,0,0,385167,0,0,0,385167,0,0,0,385167,0,0,0,385167,0,0,0,385167,0,0,0,385167,0,0,0,385167,0,0,0,385167,0,0,0,385167,0,0,0,385167,0,0,0,0,0,0.0,20571325.0,32,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,2,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,38,0,0,0,0,0,0,0,57,0,0,0,0,0,0,0,4,0,0,0,0,0,0,0,112,0,0,0,0,0,0,0,0,0,0,0,32,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,524288.0,0.0,0,0,129024,129024,0,0,129024,129024,0,27938,129024,129024,0,0,129024,129024,0,333,129024,129024,0,198,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,45606,129024,129024,0,0,129024,129024,0,857,129024,129024,0,499681,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,178,129024,129024,0,324136,129024,129024,0,0,129024,129024,0,879,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,177,129024,129024,0,0,129024,129024,0,44361,129024,129024,0,0,129024,129024,0,184,129024,129024,524288.0,0.0,44702,0,0,50595208,44461,0,0,50527231,43204,0,0,49691291,45847,0,0,51454259,44297,0,0,51004366,45798,0,0,51423974,44969,0,0,50856202,47949,0,0,52847255,45413,0,0,50832277,46042,0,0,51004325,45188,0,0,50569804,47805,0,0,52251698,44364,0,0,51124656,47693,0,0,51801218,46382,0,0,51345117,48951,0,0,53034810,44143,0,0,50577621,46206,0,0,50828775,42748,0,0,49806759,45713,0,0,51636516,44518,0,0,50999422,45647,0,0,51195141,45341,0,0,50943923,46659,0,0,52695848,45467,0,0,50751157,46280,0,0,50997663,46040,0,0,50669113,48102,0,0,52315468,45604,0,0,51504898,47175,0,0,51823318,46222,0,0,51249056,48307,0,0,52943730,0.0,65536,65568,32,131104,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65646,65538,112,131184,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65568,32,131104,65536,65592,56,131128,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65539,3,131075,65536,65536,0,131072,65536,65648,112,131184,65536,65536,0,131072,65591,65570,89,131161,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65758,65538,224,131296,65536,65537,1,131073,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65568,32,131104,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65591,65537,56,131128,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131184,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131296,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131128,0,131072,1068133,0,524288,3670016,3663319,224,6473,1048576,33554432.0,33554432.0,0.0,33554432.0,30353415.0,28710885.0,0.0,524288.0,220590,538923,8565,949,0,384873,4195054.0,0.0,2097594.0,2097460.0,1048576,1048576,0,524288,0,524288,7340032,0,0.0,0.0,104.0,8388608.0,29728300.0,2097152.0,0.0,213405,0,1206,387145,0,749.0,4194304.0,0.0,2064387.0,25690112,9437184,0,0,0,0,0,0,13291.0,8242407.0,0.0,8388608.0,2097152.0,4194304.0,9833881,0,0,8974,4128768.0,4128768.0,0.0,1484433.0,0,0,0,0,0,0,5767168,1048576,316467378.0,0.0,1473905488.0,0.0,46.0,0.0,0,0,374361,0.0,0.0,1486125.0,0.0,3670016,524288,0,0,0,2621440,524288,176728168,4194304.0,0.0,0.0,0.0,0.0,1210498.0,0,0,0.0,309.0,0.0,602.0,41918949,24117248,0,0,9437184,11010048,0,3145728,0.0,0.0,0.0,0.0,0.0,0.0,0,1572864,0.0,0.0,0.0,196770.0,524288,524288,0,3670016,7340032,603979776,4718592,0,0.0,0.0,0.0,0.0,0.0,0.0,524288,0,2064384.0,0.0,2031623.0,0.0,0,0,524288,0,0,0,0,33554432,0.0,4194304.0,0.0,18913192.0,0.0,0.0,142.0,4128768.0,1009826.0,1693248639.0,15624327812666,15637372446181,15637372686822,15624471348034
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/prev_analysis/1.csv
index 7654c8dfd3..74723b6872 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/prev_analysis/1.csv
@@ -1,2 +1,2 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 __amd_rocclr_fillBufferAligned.kd,1,240641.0,240641.0,240641.0,100.0
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/prev_analysis/1001.csv
index e34ed0c6f6..0850fc4acd 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,18.0,Instr per wave
 VMEM,1.0,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,0.0,Instr per wave
 SALU,14.0,Instr per wave
 SMEM,7.0,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/prev_analysis/101.csv
index ce163da234..948f8547bc 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx90a
 mi200
 56
 1638.4
-roofline|SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+roofline|SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/prev_analysis/1202.csv
index 77c052d3c6..8fd915388d 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,1852.467170715332,1852.467170715332,1852.467170715332,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/prev_analysis/1901.csv
index e113a02474..5f04b048c7 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,7.0,smem_
 VALU,18.0,valu_
 MFMA,0.0,mfma_
 VMEM,1.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,5.0,br_
 VGPR,4.0,vgpr_
 SGPR,32.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,524288.0,wavefronts_
 Workgroups,131072.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,9.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,8.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,0.0,hbm_rd_
 HBM Wr,8.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,25.0,vl1_coales_
 VL1 Stall,11.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,25.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/prev_analysis/2001.csv
index 8226fe9c0f..63bb17b9f9 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/prev_analysis/2001.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/prev_analysis/201.csv
index 5d611f04f7..1b20d6eb3a 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,23.57300309557928,Pct,100,23.57300309557928
 MFMA Util,0.0,Pct,100,0.0
 VALU Active Threads/Wave,64.0,Threads,64,100.0
 IPC - Issue,1.0,Instr/cycle,5,20.0
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99762462853008,Pct,100,99.99762462853008
 Instr Cache BW,1254.9394658433102,Gb/s,6092.8,20.597089447270715
 Scalar L1D Cache Hit Rate,99.99388570026338,Pct,100,99.99388570026338
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/prev_analysis/602.csv
index 230f7bf801..2b811f6d23 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,9833881.0,9833881,9833881,Simd
 Insufficient SIMD VGPRs,0.0,0,0,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/prev_analysis/701.csv
index c47e77a25f..f8ed8cd0d3 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,4.0,4,4,Registers
 SGPRs,32.0,32,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/sysinfo.csv
index a1d8bc7a97..6c20c1d338 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-D_str_inv3,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:13:36 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,roofline|SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+D_str_inv3,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:13:36 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,roofline|SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/timestamps.csv
index 18fb9de0a6..f7a6721b36 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv3/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,123357,123357,33554432,256,0,0,4,32,4160,0x0,0x7fafa1004280,15637372419940,15637372446181,15637372686822,15637372777182
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,123357,123357,32768,256,0,0,12,24,13888,0x0,0x7fafa1023f80,15637377518555,15637377534037,15637377547477,15637377564584
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,123357,123357,4194304,256,0,0,12,24,14336,0x7fafa3fb4380,0x7fafa1023fc0,15637377570134,15637377613717,15637377706678,15637377709121
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/SQ_IFETCH_LEVEL.csv
index c8efe42498..2d9a691107 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/SQ_IFETCH_LEVEL.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,843696,843701,33554432,256,0,0,8,32,6464,0x0,0x7f9255e04180,506353,506353,524288,6291456,792725,101518120,12074689170432073,12074689413795516,12074689414120954,12074689414229077
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/SQ_INST_LEVEL_LDS.csv
index b68dc626cb..edcdf7e936 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/SQ_INST_LEVEL_LDS.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,845494,845499,33554432,256,0,0,8,32,6464,0x0,0x7fdc94604180,0,0,0,12074710645676521,12074710890657778,12074710890985296,12074710891099977
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/SQ_INST_LEVEL_SMEM.csv
index 1588c407d9..bc99f94477 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/SQ_INST_LEVEL_SMEM.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,845116,845121,33554432,256,0,0,8,32,6464,0x0,0x7fccbf804180,4194304,3182164,407509952,12074708175082302,12074708419046864,12074708419372142,12074708419481155
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/SQ_INST_LEVEL_VMEM.csv
index 2c6729905b..c382859214 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/SQ_INST_LEVEL_VMEM.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,845305,845310,33554432,256,0,0,8,32,6464,0x0,0x7f1934204180,1048576,11125112,1424804012,12074709399079347,12074709644603615,12074709644926174,12074709645037006
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/SQ_LEVEL_WAVES.csv
index e8e355d3d5..a68537c01a 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/SQ_LEVEL_WAVES.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,845687,845692,33554432,256,0,0,8,32,6464,0x0,0x7fa68d804180,502145,502145,16559,4017168,524288,371921779,3806507,0,1502483424,12074711859364417,12074712107494697,12074712107816775,12074712107937978
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/pmc_dispatch_info.csv
index 90cd5504cd..5794a6cd05 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/pmc_dispatch_info.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/pmc_perf.csv
index 3e9a709c6a..aa53f6491d 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/pmc_perf.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBuffer.kd,0,0,0,844431,844436,33554432,256,0,0,8,32,6464,0x0,0x7fd9efa04180,1048576,0,1048576,9437184,0,4194304,1048576,0,509041,509041,58361415,55803763,84,12216249,54741253,54621978,55743975,54552601,4072328,3875218,509041,0,509041,0,16289312,15427392,0,0,0,0,0,17153928,1048576,0,500657,0,0,0,500657,0,0,0,500657,0,0,0,500657,0,0,0,500657,0,0,0,500657,0,0,0,500657,0,0,0,500657,0,0,0,500657,0,0,0,500657,0,0,0,500657,0,0,0,500657,0,0,0,500657,0,0,0,500657,0,0,0,500657,0,0,0,500657,0,0,0,500657,0,0,0,500657,0,0,0,500657,0,0,0,500657,0,0,0,500657,0,0,0,500657,0,0,0,500657,0,0,0,500657,0,0,0,500657,0,0,0,500657,0,0,0,500657,0,0,0,500657,0,0,0,500657,0,0,0,500657,0,0,0,500657,0,0,0,500657,0,0,0,37235982,0,0,0,0,4,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,1,0,0,0,2594,0,0,0,0,0,0,0,1,0,0,0,1,0,0,0,2695,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,3,0,0,0,1,0,0,0,0,0,0,0,48,0,0,0,3,0,0,0,0,0,0,0,2600,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2575,0,0,0,48,0,0,0,0,0,0,0,0,0,0,0,22,0,0,0,1048576,0,0,3265898,131076,131076,0,21593,131072,131072,0,0,131072,131072,0,358,131076,131076,0,0,131072,131072,0,0,131072,131072,0,0,131076,131076,0,0,131076,131076,0,0,131072,131072,0,0,131072,131072,0,973,131072,131072,0,0,131072,131072,0,3000487,131077,131077,0,0,131072,131072,0,0,131072,131072,0,0,131072,131072,0,4987,131072,131072,0,783,131072,131072,0,0,131076,131076,0,0,131076,131076,0,262,131072,131072,0,0,131072,131072,0,0,131076,131076,0,0,131076,131076,0,3092199,131076,131076,0,0,131072,131072,0,0,131072,131072,0,0,131072,131072,0,3021088,131072,131072,0,546199,131072,131072,0,267,131072,131072,0,0,131072,131072,1048576,0,891,0,0,17013977,952,0,0,17082500,874,0,0,17211021,1267,0,0,17092734,786,0,0,17173888,891,0,0,17148717,1028,0,0,17978566,44470,0,0,30349027,1084,0,0,17269041,1499,0,0,17281635,1480,0,0,17190165,49000,0,0,30271451,1094,0,0,17179357,1050,0,0,17091690,745,0,0,18151675,853,0,0,18315761,819,0,0,16756758,1075,0,0,16604687,1149,0,0,16886722,758,0,0,16834421,1213,0,0,17261633,1087,0,0,17333124,1205,0,0,18016140,49090,0,0,31244729,1078,0,0,16664469,1597,0,0,16592661,1784,0,0,17080565,45386,0,0,30343830,1513,0,0,17274943,1526,0,0,17260957,867,0,0,18089141,1658,0,0,18488097,1048576,131072,131120,48,262192,131260,133668,2784,264928,131072,131120,48,262192,131072,131072,0,262144,131072,131072,0,262144,131072,133743,2671,264815,131072,131120,48,262192,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131073,1,262145,131119,131073,48,262192,131072,131072,0,262144,131213,131075,144,262288,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,133680,2608,264752,131119,131073,48,262192,131072,131072,0,262144,131072,131072,0,262144,131072,133646,2574,264718,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131101,29,262173,131072,131072,0,262144,131072,131072,0,262144,262144,0,262144,262336,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262288,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,0,0,3145728,524288,32505856,363344131,217570877,113267398,479801,0,0,0,1048576,52461052,52211651,1048576,1048576,131072,524288,725,501972,4038,0,96,10602,0,8388944,32505856,4026448,3824006,57181337,11534336,0,0,14155776,67108864,67108864,0,67108864,54202656,53827959,0,1048576,249947,774235,11752,2029,0,499062,8399783,0,4194727,4205056,13631488,0,3670016,1048576,1048576,0,4194304,9437184,0,0,360,33554432,54332630,4194304,0,0,2474,498751,0,11149,8388608,0,4194383,905969664,6291456,0,0,0,524288,524288,0,15324,16608752,0,16777216,4194304,4194304,0,0,0,15592,4194398,4194398,0,216341,0,0,0,33554432,0,0,0,0,639401975,0,2802641972,0,0,0,0,0,473431,0,0,217883,0,0,8388608,336,144,0,0,0,480,8388608,0,0,0,0,415646,0,0,0,10824,0,21630,0,6291456,6289600,96,1991,1878505,0,0,0,0,0,0,0,0,0,3145728,0,0,0,149043,4194304,4189866,144,4294,2097152,524288,1572864,0,0,0,0,0,0,524288,0,4128822,65534,4063245,0,0,8388608,0,41874937,0,1048576,10732,4194380,13293967,612010093,12074691237470968,12074712949814439,12074712950139236,12074691482363668
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/prev_analysis/1.csv
index 0b2c87c8c4..4e31a5ad32 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/prev_analysis/1.csv
@@ -1,2 +1,2 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 __amd_rocclr_fillBuffer.kd,1,324797.0,324797.0,324797.0,100.0
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/prev_analysis/1001.csv
index 2923ed58d3..25f1221e3b 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,18.0,Instr per wave
 SMEM,8.0,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/prev_analysis/101.csv
index dd4f4e2c45..16282eec04 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx908
 mi100
 48
 1228.8
-SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/prev_analysis/1202.csv
index 36a2c97827..1b5596b31e 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,2772.0957260131836,2772.0957260131836,2772.0957260131836,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/prev_analysis/1901.csv
index 1fbfb48c30..1644757669 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,8.0,smem_
 VALU,22.0,valu_
 MFMA,,mfma_
 VMEM,2.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,6.0,br_
 VGPR,8.0,vgpr_
 SGPR,32.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,524288.0,wavefronts_
 Workgroups,131072.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,12.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,8.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,0.0,hbm_rd_
 HBM Wr,8.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,25.0,vl1_coales_
 VL1 Stall,21.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,31.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/prev_analysis/2001.csv
index 90cd5504cd..5794a6cd05 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/prev_analysis/2001.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/prev_analysis/201.csv
index 4441890202..5fee13a41e 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,23.17392901554099,Pct,100,23.17392901554099
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,64.0,Threads,64,100.0
 IPC - Issue,0.9193548387096774,Instr/cycle,5,18.387096774193548
-LDS BW,0.0,Gb/sec,23070.72,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,23070.72,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99847369411813,Pct,100,99.99847369411813
 Instr Cache BW,1239.7072140444648,Gb/s,4614.144,26.867544967050545
 Scalar L1D Cache Hit Rate,99.99656325402565,Pct,100,99.99656325402565
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/prev_analysis/602.csv
index d47da1d486..d59bee7648 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,0.0,0,0,Simd
 Insufficient SIMD VGPRs,0.0,0,0,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/prev_analysis/701.csv
index ebf5f22ba4..1d3a71c87a 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,8.0,8,8,Registers
 SGPRs,32.0,32,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/sysinfo.csv
index 466a18d791..d92d06392f 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-D_str_inv4,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 11:04:19 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+D_str_inv4,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 11:04:19 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/timestamps.csv
index d5b76f0128..1644e76ff2 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,845736,845741,33554432,256,0,0,8,32,6464,0x0,0x7fa5f2c04180,12074712949765672,12074712949814439,12074712950139236,12074712950247648
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,845736,845741,32768,256,0,0,24,24,12480,0x0,0x7fa5f2c35100,12074712964863469,12074712964969515,12074712964975915,12074712964981519
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,845736,845741,4194304,256,0,0,24,24,12928,0x7fa722cfe900,0x7fa5f2c35140,12074712965035800,12074712965051114,12074712965185353,12074712965188564
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/SQ_IFETCH_LEVEL.csv
index 004c7b7659..b6263ce70d 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/SQ_IFETCH_LEVEL.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,127524,127524,33554432,256,0,0,4,32,4160,0x0,0x7fc796204280,381104,381104,524288,4718592,682194,76433352,15718532074887,15717765156713,15718679600910,15718679690210
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/SQ_INST_LEVEL_LDS.csv
index 3290f720e0..840bb9121c 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/SQ_INST_LEVEL_LDS.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,129376,129376,33554432,256,0,0,4,32,4160,0x0,0x7f28c3c04280,0,0,0,15733091654145,15732338002645,15733239862225,15733239973985
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/SQ_INST_LEVEL_SMEM.csv
index 671679b8bb..6cae91c526 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/SQ_INST_LEVEL_SMEM.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,127301,127301,33554432,256,0,0,4,32,4160,0x0,0x7f7b8fc04280,3670016,2914400,325749656,15717617267952,15711992155542,15717765156427,15717765249137
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/SQ_INST_LEVEL_VMEM.csv
index 260a897df6..f95fc7f760 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/SQ_INST_LEVEL_VMEM.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,129153,129153,33554432,256,0,0,4,32,4160,0x0,0x7f1dc0404280,524288,5498007,615706652,15732187800600,15731182419002,15732338002865,15732338116295
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/SQ_LEVEL_WAVES.csv
index c85e913434..b39aac87e7 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/SQ_LEVEL_WAVES.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,127747,127747,33554432,256,0,0,4,32,4160,0x0,0x7fbc58804280,379522,379522,8897,3036184,524288,238275346,2948757,0,969342960,15719440026097,15718679600826,15719589907556,15719590021486
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/pmc_dispatch_info.csv
index 8226fe9c0f..63bb17b9f9 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/pmc_dispatch_info.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/pmc_perf.csv
index 89a06b8d06..d8367f79ae 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/pmc_perf.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDI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],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBufferAligned.kd,0,0,0,128514,128514,33554432,256,0,0,4,32,4160,0x0,0x7f5dc3c04280,3098296,3011335,524288,39119198,245115092,392,224,0,387286,387286,39389459.0,38330348.0,3.0,4169262.0,31463015.0,31097115.0,38307499.0,37748068.0,3096585,3017739,387286,0,387286,0,12393152.0,9503429.0,0.0,0.0,0,0,616,0,4718592,4714676,112,3804,375141,0.0,0.0,0.0,524288.0,28475903.0,27753277.0,7668.0,524288.0,131072,524288,301,384112,2275,0,56.0,301.0,0.0,4194696.0,0,0,0,0,0,7340032,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,20092916.0,524288.0,0,383201,0,0,0,383201,0,0,0,383201,0,0,0,383201,0,0,0,383201,0,0,0,383201,0,0,0,383201,0,0,0,383201,0,0,0,383201,0,0,0,383201,0,0,0,383201,0,0,0,383201,0,0,0,383201,0,0,0,383201,0,0,0,383201,0,0,0,383201,0,0,0,383201,0,0,0,383201,0,0,0,383201,0,0,0,383201,0,0,0,383201,0,0,0,383201,0,0,0,383201,0,0,0,383201,0,0,0,383201,0,0,0,383201,0,0,0,383201,0,0,0,383201,0,0,0,383201,0,0,0,383201,0,0,0,383201,0,0,0,383201,0,0,0,0,0,0.0,21094978.0,32,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,0,0,56,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,112,0,0,0,35,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,5,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,1,0,0,0,524288.0,0.0,0,44935,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,333,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,44568,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,489,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,307410,129024,129024,0,498497,129024,129024,0,202,129024,129024,0,0,129024,129024,0,884,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,45327,129024,129024,0,861,129024,129024,0,0,129024,129024,0,0,129024,129024,0,187,129024,129024,524288.0,0.0,44220,0,0,50410619,45012,0,0,50440883,42861,0,0,49591702,47435,0,0,51817233,43970,0,0,50590330,44689,0,0,50799405,43489,0,0,50056825,47913,0,0,52688283,45188,0,0,50654050,45428,0,0,50547814,44778,0,0,50135221,47008,0,0,51972545,46435,0,0,51537673,45808,0,0,51197214,45886,0,0,51070365,47625,0,0,52734264,42982,0,0,49831641,45169,0,0,50355162,44148,0,0,49870504,46406,0,0,51553325,44445,0,0,50887002,45222,0,0,50981125,44419,0,0,50473008,48282,0,0,52683288,43826,0,0,50243422,45071,0,0,50466904,45016,0,0,50103290,47364,0,0,52091037,46737,0,0,51531727,46094,0,0,51397285,46306,0,0,51170304,48682,0,0,52769609,0.0,65536,65536,0,131072,65536,65648,112,131184,65536,65570,34,131106,65536,65536,0,131072,65646,65538,112,131184,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65568,32,131104,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65537,1,131073,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65568,32,131104,65536,65536,0,131072,65758,65538,224,131296,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65540,4,131076,65591,65593,112,131184,65536,65568,32,131104,65536,65536,0,131072,65591,65537,56,131128,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131184,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131296,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131128,0,131072,1037775,0,524288,3670016,3663342,224,6450,1048576,33554432.0,33554432.0,0.0,33554432.0,30390310.0,28734538.0,0.0,524288.0,221782,535861,8943,929,0,385231,4195056.0,0.0,2097594.0,2097462.0,1048576,1048576,0,524288,0,524288,7340032,0,0.0,0.0,104.0,8388608.0,29263471.0,2097152.0,0.0,198262,0,1198,381228,0,751.0,4194304.0,0.0,2064387.0,25690112,9437184,0,0,0,0,0,0,13277.0,8242561.0,0.0,8388608.0,2097152.0,4194304.0,9802802,0,0,8855,4128768.0,4128768.0,0.0,1490994.0,0,0,0,0,0,0,5767168,1048576,316116941.0,0.0,1473054684.0,0.0,47.0,0.0,0,0,374371,0.0,0.0,1490397.0,0.0,3670016,524288,0,0,0,2621440,524288,176878310,4194304.0,0.0,0.0,0.0,0.0,1210308.0,0,0,0.0,311.0,0.0,606.0,42334280,24117248,0,0,9437184,11010048,0,3145728,0.0,0.0,0.0,0.0,0.0,0.0,0,1572864,0.0,0.0,0.0,202478.0,524288,524288,0,3670016,7340032,603979776,4718592,0,0.0,0.0,0.0,0.0,0.0,0.0,524288,0,2064384.0,0.0,2031623.0,0.0,0,0,524288,0,0,0,0,33554432,0.0,4194304.0,0.0,18945243.0,0.0,0.0,142.0,4128768.0,979822.0,1701462477.0,15720835544123,15733876958945,15733877198786,15720989030945
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/prev_analysis/1.csv
index b87daa3671..f7da85a854 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/prev_analysis/1.csv
@@ -1,2 +1,2 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 __amd_rocclr_fillBufferAligned.kd,1,239841.0,239841.0,239841.0,100.0
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/prev_analysis/1001.csv
index e34ed0c6f6..0850fc4acd 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,18.0,Instr per wave
 VMEM,1.0,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,0.0,Instr per wave
 SALU,14.0,Instr per wave
 SMEM,7.0,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/prev_analysis/101.csv
index cc31cd17e0..c2a5224060 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx90a
 mi200
 56
 1638.4
-roofline|SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+roofline|SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/prev_analysis/1202.csv
index 12ca5d42b6..ae0301279c 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,1870.0797424316406,1870.0797424316406,1870.0797424316406,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/prev_analysis/1901.csv
index ebe49bd5e6..b796080233 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,7.0,smem_
 VALU,18.0,valu_
 MFMA,0.0,mfma_
 VMEM,1.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,5.0,br_
 VGPR,4.0,vgpr_
 SGPR,32.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,524288.0,wavefronts_
 Workgroups,131072.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,9.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,8.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,0.0,hbm_rd_
 HBM Wr,8.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,25.0,vl1_coales_
 VL1 Stall,11.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,25.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/prev_analysis/2001.csv
index 8226fe9c0f..63bb17b9f9 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/prev_analysis/2001.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/prev_analysis/201.csv
index d433a7caf0..255f8fb8f4 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,23.430269580143317,Pct,100,23.430269580143317
 MFMA Util,0.0,Pct,100,0.0
 VALU Active Threads/Wave,64.0,Threads,64,100.0
 IPC - Issue,1.0,Instr/cycle,5,20.0
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99762449552345,Pct,100,99.99762449552345
 Instr Cache BW,1259.1253705579948,Gb/s,6092.8,20.665791927488097
 Scalar L1D Cache Hit Rate,99.99388573864917,Pct,100,99.99388573864917
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/prev_analysis/602.csv
index bb58eeeda7..e3eafaac2d 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,9802802.0,9802802,9802802,Simd
 Insufficient SIMD VGPRs,0.0,0,0,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/prev_analysis/701.csv
index c47e77a25f..f8ed8cd0d3 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,4.0,4,4,Registers
 SGPRs,32.0,32,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/sysinfo.csv
index 8fbb3899f0..fd09a8dbe4 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-D_str_inv4,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:15:13 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,roofline|SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+D_str_inv4,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:15:13 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,roofline|SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/timestamps.csv
index ea06714b6d..560364a260 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_str_inv4/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,129459,129459,33554432,256,0,0,4,32,4160,0x0,0x7fec4ac04280,15733876934024,15733876958945,15733877198786,15733877280556
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,129459,129459,32768,256,0,0,12,24,13888,0x0,0x7fec4ac23f80,15733881995950,15733882011284,15733882024564,15733882042619
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,129459,129459,4194304,256,0,0,12,24,14336,0x7fec552ba380,0x7fec4ac23fc0,15733882047019,15733882103285,15733882196085,15733882198235
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/SQ_IFETCH_LEVEL.csv
index dd1eeb303c..6d8e6c2087 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/SQ_IFETCH_LEVEL.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,808596,808601,33554432,256,0,0,8,32,6464,0x0,0x7fd434804180,503009,503009,524288,6291456,793480,101575176,12074139675536887,12074139924250828,12074139924573706,12074139924662999
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/SQ_INST_LEVEL_LDS.csv
index 39efa34cfd..9c4146bafd 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/SQ_INST_LEVEL_LDS.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,810407,810412,33554432,256,0,0,8,32,6464,0x0,0x7f8014204180,0,0,0,12074161111412295,12074161348982066,12074161349304144,12074161349414047
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/SQ_INST_LEVEL_SMEM.csv
index c21ad52d80..0ffdb148c7 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/SQ_INST_LEVEL_SMEM.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,810028,810033,33554432,256,0,0,8,32,6464,0x0,0x7f860a004180,4194304,3070720,393228232,12074158665115166,12074158910537050,12074158910861048,12074158910970380
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/SQ_INST_LEVEL_VMEM.csv
index c6d810c10e..635df44ce8 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/SQ_INST_LEVEL_VMEM.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,810217,810222,33554432,256,0,0,8,32,6464,0x0,0x7f570ce04180,1048576,11304800,1445627280,12074159887998438,12074160134059328,12074160134385726,12074160134492208
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/SQ_LEVEL_WAVES.csv
index 776500f0d1..750c19af0d 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/SQ_LEVEL_WAVES.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,810598,810603,33554432,256,0,0,8,32,6464,0x0,0x7f93f6004180,505225,505225,17438,4041808,524288,368780213,3826817,0,1489936900,12074162335876264,12074162579636594,12074162579960752,12074162580071925
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/pmc_dispatch_info.csv
index 90cd5504cd..5794a6cd05 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/pmc_dispatch_info.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/pmc_perf.csv
index 33df7f19a7..5cf32adf51 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/pmc_perf.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBuffer.kd,0,0,0,809331,809336,33554432,256,0,0,8,32,6464,0x0,0x7f4b99404180,1048576,0,1048576,9437184,0,4194304,1048576,0,505257,505257,57932529,55396686,170,12986116,54605068,54507854,55366982,54186733,4042056,3846624,505257,0,505257,0,16168224,15306598,0,0,0,0,0,17791866,1048576,0,507633,0,0,0,507633,0,0,0,507633,0,0,0,507633,0,0,0,507633,0,0,0,507633,0,0,0,507633,0,0,0,507633,0,0,0,507633,0,0,0,507633,0,0,0,507633,0,0,0,507633,0,0,0,507633,0,0,0,507633,0,0,0,507633,0,0,0,507633,0,0,0,507633,0,0,0,507633,0,0,0,507633,0,0,0,507633,0,0,0,507633,0,0,0,507633,0,0,0,507633,0,0,0,507633,0,0,0,507633,0,0,0,507633,0,0,0,507633,0,0,0,507633,0,0,0,507633,0,0,0,507633,0,0,0,507633,0,0,0,507633,0,0,0,37644651,0,0,0,0,4,0,0,0,0,0,0,0,0,0,0,0,238,0,0,0,3,0,0,0,0,0,0,0,0,0,0,0,2616,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,48,0,0,0,2757,0,0,0,0,0,0,0,3,0,0,0,0,0,0,0,2277,0,0,0,2634,0,0,0,0,0,0,0,48,0,0,0,48,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,1,0,0,0,1048576,0,0,0,131076,131076,0,3126905,131075,131075,0,0,131072,131072,0,0,131072,131072,0,263,131076,131076,0,3214976,131076,131076,0,0,131072,131072,0,0,131072,131072,0,261,131076,131076,0,0,131076,131076,0,1473,131076,131076,0,0,131072,131072,0,0,131072,131072,0,11244,131076,131076,0,0,131072,131072,0,0,131072,131072,0,39848,131072,131072,0,781,131072,131072,0,0,131072,131072,0,0,131084,131084,0,565200,131076,131076,0,0,131072,131072,0,0,131076,131076,0,0,131080,131080,0,0,131080,131080,0,2997635,131076,131076,0,910,131072,131072,0,0,131072,131072,0,260,131072,131072,0,3274861,131076,131076,0,1674,131072,131072,0,21349,131080,131080,1048576,0,841,0,0,17051324,1237,0,0,17350970,1067,0,0,17635621,49676,0,0,30494410,775,0,0,17180660,781,0,0,17498172,1256,0,0,18182647,681,0,0,18403535,1011,0,0,17064887,1619,0,0,17617317,913,0,0,17069086,1574,0,0,16837220,1597,0,0,17146486,1071,0,0,17670047,1583,0,0,18169326,45841,0,0,30448699,820,0,0,16491482,993,0,0,17288163,1152,0,0,16974969,45565,0,0,30091120,965,0,0,17170784,857,0,0,17713271,843,0,0,17992751,819,0,0,18326583,1656,0,0,16819259,773,0,0,17006560,1622,0,0,17174383,1209,0,0,16728479,1007,0,0,17165396,862,0,0,17671410,1848,0,0,18190564,46208,0,0,30809531,1048576,131072,131075,3,262147,131260,131076,192,262336,131072,131072,0,262144,131072,133778,2706,264850,131119,131073,48,262192,131072,131072,0,262144,131072,131072,0,262144,131072,133595,2523,264667,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131091,19,262163,131072,131072,0,262144,131213,131075,144,262288,131072,131073,1,262145,131072,133588,2516,264660,131072,131072,0,262144,131072,131072,0,262144,131072,131121,49,262193,131072,131072,0,262144,131072,131120,48,262192,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131121,49,262193,131119,131074,49,262193,131072,133665,2593,264737,262144,0,262144,262336,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262288,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,0,0,3145728,524288,32505856,369448350,219715241,117227253,479157,0,0,0,1048576,52482958,52250391,1048576,1048576,131072,524288,731,500462,4066,0,96,10606,0,8388944,32505856,4019664,3819293,57137307,11534336,0,0,14155776,67108864,67108864,0,67108864,54415006,54091664,0,1048576,240485,764773,10928,2014,0,498398,8399596,0,4194727,4204869,13631488,0,3670016,1048576,1048576,0,4194304,9437184,0,0,360,33554432,54064856,4194304,0,0,2837,497740,0,11002,8388608,0,4194378,905969664,6291456,0,0,0,524288,524288,0,15351,16608463,0,16777216,4194304,4194304,0,0,0,17716,4194386,4194386,0,218359,0,0,0,33554432,0,0,0,0,634536739,0,2795095420,0,0,0,0,0,475949,0,0,210564,0,0,8388608,336,144,0,0,0,480,8388608,0,0,0,0,342542,0,0,0,10631,0,21244,0,6291456,6289544,96,1945,2003067,0,0,0,0,0,0,0,0,0,3145728,0,0,0,157584,4194304,4189875,144,4285,2097152,524288,1572864,0,0,0,0,0,0,524288,0,4128833,65536,4063248,0,0,8388608,0,42076747,0,1048576,10644,4194392,13001973,610694722,12074141754181951,12074163422846673,12074163423172110,12074142002486857
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/prev_analysis/1.csv
index b9c3bd2c7f..24a8331611 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/prev_analysis/1.csv
@@ -1,2 +1,2 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 __amd_rocclr_fillBuffer.kd,1,325437.0,325437.0,325437.0,100.0
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/prev_analysis/1001.csv
index 2923ed58d3..25f1221e3b 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,18.0,Instr per wave
 SMEM,8.0,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/prev_analysis/101.csv
index e7d621412c..8c7b8cbf6f 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx908
 mi100
 48
 1228.8
-SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/prev_analysis/1202.csv
index bc976a0e35..3c9ce231db 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,2818.667221069336,2818.667221069336,2818.667221069336,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/prev_analysis/1901.csv
index b67bbd6cf8..ccdeaa4c37 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,8.0,smem_
 VALU,22.0,valu_
 MFMA,,mfma_
 VMEM,2.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,6.0,br_
 VGPR,8.0,vgpr_
 SGPR,32.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,524288.0,wavefronts_
 Workgroups,131072.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,12.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,8.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,0.0,hbm_rd_
 HBM Wr,8.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,25.0,vl1_coales_
 VL1 Stall,22.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,30.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/prev_analysis/2001.csv
index 90cd5504cd..5794a6cd05 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/prev_analysis/2001.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/prev_analysis/201.csv
index 5326549cbe..713ccccec9 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,23.34748454746792,Pct,100,23.34748454746792
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,64.0,Threads,64,100.0
 IPC - Issue,0.9193548387096774,Instr/cycle,5,18.387096774193548
-LDS BW,0.0,Gb/sec,23070.72,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,23070.72,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99847368052862,Pct,100,99.99847368052862
 Instr Cache BW,1237.2692226145152,Gb/s,4614.144,26.81470761672187
 Scalar L1D Cache Hit Rate,99.99656326140764,Pct,100,99.99656326140764
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/prev_analysis/602.csv
index 3dab9673fb..613ca1cbc6 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,0.0,0,0,Simd
 Insufficient SIMD VGPRs,0.0,0,0,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/prev_analysis/701.csv
index ebf5f22ba4..1d3a71c87a 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,8.0,8,8,Registers
 SGPRs,32.0,32,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/sysinfo.csv
index 3ed357cef5..a86c2a4e5c 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-D_val_int,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 10:55:09 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+D_val_int,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 10:55:09 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/timestamps.csv
index 3bff69b79a..8212a56230 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,810647,810652,33554432,256,0,0,8,32,6464,0x0,0x7ff1ef204180,12074163422799658,12074163422846673,12074163423172110,12074163423264713
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,810647,810652,32768,256,0,0,24,24,12480,0x0,0x7ff1ef235100,12074163437610889,12074163437710941,12074163437717501,12074163437723238
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,810647,810652,4194304,256,0,0,24,24,12928,0x7ff31f3f0900,0x7ff1ef235140,12074163437764394,12074163437778781,12074163437909500,12074163437912670
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/SQ_IFETCH_LEVEL.csv
index 950caeae75..7dcb0a4c77 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/SQ_IFETCH_LEVEL.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,84811,84811,33554432,256,0,0,4,32,4160,0x0,0x7fd680e04280,380934,380934,524288,4718592,686671,76860020,15058026300547,15057271741949,15058174721005,15058174835735
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/SQ_INST_LEVEL_LDS.csv
index d7d3afecbb..8aa2791080 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/SQ_INST_LEVEL_LDS.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,86663,86663,33554432,256,0,0,4,32,4160,0x0,0x7f560a604280,0,0,0,15072481431450,15071726308033,15072624485746,15072624599676
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/SQ_INST_LEVEL_SMEM.csv
index 3ced4aea9f..762000bb10 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/SQ_INST_LEVEL_SMEM.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,84588,84588,33554432,256,0,0,4,32,4160,0x0,0x7f6a78804280,3670016,3083866,345356128,15057126889396,15051605998137,15057271741799,15057271854749
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/SQ_INST_LEVEL_VMEM.csv
index 742f9db8aa..a1cf48e0cd 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/SQ_INST_LEVEL_VMEM.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,86440,86440,33554432,256,0,0,4,32,4160,0x0,0x7fd7cc204280,524288,5476974,613456104,15071576239534,15070572285871,15071726307741,15071726420301
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/SQ_LEVEL_WAVES.csv
index 3b4daf1ac3..c5ca30a369 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/SQ_LEVEL_WAVES.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,85034,85034,33554432,256,0,0,4,32,4160,0x0,0x7fb803c04280,378622,378622,8820,3028984,524288,237421922,2939229,0,965969388,15058913982833,15058174721139,15059062458001,15059062570811
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/pmc_dispatch_info.csv
index 8226fe9c0f..63bb17b9f9 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/pmc_dispatch_info.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/pmc_perf.csv
index 802c8f73e7..24e0261f32 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/pmc_perf.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDI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],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBufferAligned.kd,0,0,0,85801,85801,33554432,256,0,0,4,32,4160,0x0,0x7f8e04604280,3078312,2990795,524288,38858325,243141653,392,224,0,384788,384788,39123050.0,38087397.0,14.0,4168437.0,31219628.0,30854438.0,38064277.0,37503678.0,3076601,2997195,384788,0,384788,0,12313216.0,9487893.0,0.0,0.0,0,0,616,0,4718592,4714371,112,4109,380522,0.0,0.0,0.0,524288.0,28854180.0,28152441.0,7842.0,524288.0,131072,524288,302,389461,2253,0,56.0,301.0,0.0,4194696.0,0,0,0,0,0,7340032,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,20002291.0,524288.0,0,383638,0,0,0,383638,0,0,0,383638,0,0,0,383638,0,0,0,383638,0,0,0,383638,0,0,0,383638,0,0,0,383638,0,0,0,383638,0,0,0,383638,0,0,0,383638,0,0,0,383638,0,0,0,383638,0,0,0,383638,0,0,0,383638,0,0,0,383638,0,0,0,383638,0,0,0,383638,0,0,0,383638,0,0,0,383638,0,0,0,383638,0,0,0,383638,0,0,0,383638,0,0,0,383638,0,0,0,383638,0,0,0,383638,0,0,0,383638,0,0,0,383638,0,0,0,383638,0,0,0,383638,0,0,0,383638,0,0,0,383638,0,0,0,0,0,0.0,21139868.0,0,0,0,0,0,0,0,0,0,0,0,0,33,0,0,0,2,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,56,0,0,0,33,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,35,0,0,0,4,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,113,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,0,0,1,0,0,0,524288.0,0.0,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,44012,129024,129024,0,273454,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,528919,129024,129024,0,0,129024,129024,0,0,129024,129024,0,43872,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,167,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,30433,129024,129024,0,874,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,44451,129024,129024,0,187,129024,129024,524288.0,0.0,43223,0,0,50328569,45097,0,0,50585896,45159,0,0,50379957,46088,0,0,51805023,44515,0,0,51013432,45745,0,0,51466493,45141,0,0,50886880,47716,0,0,52762193,45356,0,0,50976759,47132,0,0,51287264,46719,0,0,50917191,47335,0,0,52159969,45763,0,0,51587722,47294,0,0,51664127,45948,0,0,51206538,48098,0,0,52881525,44255,0,0,50514348,45416,0,0,50700789,45177,0,0,50407885,46762,0,0,51976285,43642,0,0,51171785,46371,0,0,51707252,44565,0,0,50576047,49069,0,0,52946078,45882,0,0,50932582,46000,0,0,50935115,45398,0,0,50488546,47479,0,0,52204632,45679,0,0,51469184,47362,0,0,51898889,45549,0,0,51164521,49537,0,0,53162709,0.0,65536,65568,32,131104,65536,65536,0,131072,65591,65537,56,131128,65536,65536,0,131072,65646,65538,112,131184,65536,65536,0,131072,65536,65592,56,131128,65536,65536,0,131072,65536,65536,0,131072,65536,65568,32,131104,65536,65536,0,131072,65536,65536,0,131072,65536,65649,113,131185,65536,65537,1,131073,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65537,1,131073,65536,65571,35,131107,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65758,65538,224,131296,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65568,32,131104,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65591,65537,56,131128,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131184,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131296,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131128,0,131072,1341826,0,524288,3670016,3663194,224,6598,1048576,33554432.0,33554432.0,0.0,33554432.0,30320685.0,28710826.0,0.0,524288.0,226408,536792,8648,938,0,386868,4195054.0,0.0,2097594.0,2097460.0,1048576,1048576,0,524288,0,524288,7340032,0,0.0,0.0,104.0,8388608.0,29519029.0,2097152.0,0.0,201541,0,1216,383206,0,751.0,4194304.0,0.0,2064387.0,25690112,9437184,0,0,0,0,0,0,13304.0,8242264.0,0.0,8388608.0,2097152.0,4194304.0,9995592,0,0,8960,4128768.0,4128768.0,0.0,1494941.0,0,0,0,0,0,0,5767168,1048576,315952101.0,0.0,1472082701.0,0.0,46.0,0.0,0,0,374988,0.0,0.0,1497807.0,0.0,3670016,524288,0,0,0,2621440,524288,177383041,4194304.0,0.0,0.0,0.0,0.0,1207712.0,0,0,0.0,310.0,0.0,604.0,42384928,24117248,0,0,9437184,11010048,0,3145728,0.0,0.0,0.0,0.0,0.0,0.0,0,1572864,0.0,0.0,0.0,203154.0,524288,524288,0,3670016,7340032,603979776,4718592,0,0.0,0.0,0.0,0.0,0.0,0.0,524288,0,2064384.0,0.0,2031624.0,0.0,0,0,524288,0,0,0,0,33554432,0.0,4194304.0,0.0,19158971.0,0.0,0.0,140.0,4128768.0,653550.0,1648200515.0,15060299748033,15073258626891,15073258868332,15060447850003
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/prev_analysis/1.csv
index ee486097a8..8c4357cb48 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/prev_analysis/1.csv
@@ -1,2 +1,2 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 __amd_rocclr_fillBufferAligned.kd,1,241441.0,241441.0,241441.0,100.0
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/prev_analysis/1001.csv
index e34ed0c6f6..0850fc4acd 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,18.0,Instr per wave
 VMEM,1.0,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,0.0,Instr per wave
 SALU,14.0,Instr per wave
 SMEM,7.0,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/prev_analysis/101.csv
index cb718fda62..ce009330a1 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx90a
 mi200
 56
 1638.4
-roofline|SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+roofline|SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/prev_analysis/1202.csv
index 3659e52d5a..492565ec17 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,1855.0235977172852,1855.0235977172852,1855.0235977172852,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/prev_analysis/1901.csv
index 8856a391c8..090c017197 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,7.0,smem_
 VALU,18.0,valu_
 MFMA,0.0,mfma_
 VMEM,1.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,5.0,br_
 VGPR,4.0,vgpr_
 SGPR,32.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,524288.0,wavefronts_
 Workgroups,131072.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,9.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,8.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,0.0,hbm_rd_
 HBM Wr,8.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,25.0,vl1_coales_
 VL1 Stall,11.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,25.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/prev_analysis/2001.csv
index 8226fe9c0f..63bb17b9f9 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/prev_analysis/2001.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/prev_analysis/201.csv
index 47657d1098..c85d0159b5 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,23.582376229548178,Pct,100,23.582376229548178
 MFMA Util,0.0,Pct,100,0.0
 VALU Active Threads/Wave,64.0,Threads,64,100.0
 IPC - Issue,1.0,Instr/cycle,5,20.0
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99762434184194,Pct,100,99.99762434184194
 Instr Cache BW,1250.781300607602,Gb/s,6092.8,20.528842249993467
 Scalar L1D Cache Hit Rate,99.9938854916365,Pct,100,99.9938854916365
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/prev_analysis/602.csv
index 56d549b404..8a2f1a0806 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,9995592.0,9995592,9995592,Simd
 Insufficient SIMD VGPRs,0.0,0,0,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/prev_analysis/701.csv
index c47e77a25f..f8ed8cd0d3 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,4.0,4,4,Registers
 SGPRs,32.0,32,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/sysinfo.csv
index f05508d7e0..6054e6d9dd 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-D_val_int,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:04:12 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,roofline|SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+D_val_int,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:04:12 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,roofline|SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/timestamps.csv
index dd82c08e4a..c4d583db08 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,86746,86746,33554432,256,0,0,4,32,4160,0x0,0x7f936c204280,15073258600671,15073258626891,15073258868332,15073258979812
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,86746,86746,32768,256,0,0,12,24,13888,0x0,0x7f936c223f80,15073263643990,15073263659546,15073263673146,15073263689999
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,86746,86746,4194304,256,0,0,12,24,14336,0x7f936f231380,0x7f936c223fc0,15073263695949,15073263741946,15073263834267,15073263836336
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/SQ_IFETCH_LEVEL.csv
index faf51ca963..40e92d9643 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/SQ_IFETCH_LEVEL.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,813616,813621,33554432,256,0,0,8,32,6464,0x0,0x7f8c23804180,504081,504081,524288,6291456,791096,101486400,12074219838366485,12074220083529526,12074220083853684,12074220083961926
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/SQ_INST_LEVEL_LDS.csv
index dff60b295a..f26eee26ab 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/SQ_INST_LEVEL_LDS.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,815412,815417,33554432,256,0,0,8,32,6464,0x0,0x7f8880404180,0,0,0,12074241352030822,12074241596258084,12074241596580322,12074241596690585
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/SQ_INST_LEVEL_SMEM.csv
index 2005c7ac74..92a97b3a3b 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/SQ_INST_LEVEL_SMEM.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,815034,815039,33554432,256,0,0,8,32,6464,0x0,0x7f9ede404180,4194304,3123364,399821408,12074238889117919,12074239132357451,12074239132681290,12074239132792812
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/SQ_INST_LEVEL_VMEM.csv
index e90e32b6d7..fa8a5c1e6b 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/SQ_INST_LEVEL_VMEM.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,815223,815228,33554432,256,0,0,8,32,6464,0x0,0x7fa55ea04180,1048576,11173943,1430218572,12074240117305828,12074240362833852,12074240363161050,12074240363274623
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/SQ_LEVEL_WAVES.csv
index d470ceafdd..253ecad722 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/SQ_LEVEL_WAVES.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,815603,815608,33554432,256,0,0,8,32,6464,0x0,0x7f3ede204180,499273,499273,17297,3994192,524288,370191090,3788897,0,1495542820,12074242575407481,12074242822350394,12074242822670872,12074242822780004
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/pmc_dispatch_info.csv
index 90cd5504cd..5794a6cd05 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/pmc_dispatch_info.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/pmc_perf.csv
index 8087ddbdeb..60d330a22b 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/pmc_perf.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBuffer.kd,0,0,0,814351,814356,33554432,256,0,0,8,32,6464,0x0,0x7ff12f804180,1048576,0,1048576,9437184,0,4194304,1048576,0,506601,506601,58222089,55776047,141,12748482,54859421,54752680,55726184,54542479,4052808,3865912,506601,0,506601,0,16211232,15343904,0,0,0,0,0,17116694,1048576,0,504561,0,0,0,504561,0,0,0,504561,0,0,0,504561,0,0,0,504561,0,0,0,504561,0,0,0,504561,0,0,0,504561,0,0,0,504561,0,0,0,504561,0,0,0,504561,0,0,0,504561,0,0,0,504561,0,0,0,504561,0,0,0,504561,0,0,0,504561,0,0,0,504561,0,0,0,504561,0,0,0,504561,0,0,0,504561,0,0,0,504561,0,0,0,504561,0,0,0,504561,0,0,0,504561,0,0,0,504561,0,0,0,504561,0,0,0,504561,0,0,0,504561,0,0,0,504561,0,0,0,504561,0,0,0,504561,0,0,0,504561,0,0,0,37292557,1,0,0,0,52,0,0,0,0,0,0,0,2692,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,16,0,0,0,0,0,0,0,2,0,0,0,0,0,0,0,1,0,0,0,96,0,0,0,0,0,0,0,2497,0,0,0,1,0,0,0,3,0,0,0,0,0,0,0,2714,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2514,0,0,0,1048576,0,0,14063,131072,131072,0,563493,131072,131072,0,771,131076,131076,0,3089588,131073,131073,0,0,131080,131080,0,0,131076,131076,0,0,131076,131076,0,3339098,131076,131076,0,0,131072,131072,0,0,131076,131076,0,1440,131072,131072,0,0,131076,131076,0,0,131072,131072,0,0,131072,131072,0,0,131072,131072,0,0,131072,131072,0,368,131072,131072,0,782,131072,131072,0,0,131076,131076,0,9300,131072,131072,0,0,131072,131072,0,0,131072,131072,0,0,131072,131072,0,0,131072,131072,0,0,131076,131076,0,0,131072,131072,0,261,131076,131076,0,3111381,131072,131072,0,0,131072,131072,0,0,131072,131072,0,267,131072,131072,0,3236887,131072,131072,1048576,0,702,0,0,17003315,1653,0,0,17067537,47123,0,0,30232582,1785,0,0,17486552,1585,0,0,17181873,1086,0,0,17246345,1378,0,0,17901511,1809,0,0,18943660,1732,0,0,17212053,758,0,0,17021453,869,0,0,16723890,746,0,0,17033168,1843,0,0,17340644,893,0,0,17207684,44508,0,0,30044883,1880,0,0,18925017,1037,0,0,16688324,741,0,0,16761742,49902,0,0,30261907,1978,0,0,17294286,928,0,0,17073206,908,0,0,17137659,741,0,0,17728997,969,0,0,18640074,1306,0,0,16727474,960,0,0,16684362,817,0,0,16799099,868,0,0,17150992,1410,0,0,17309747,1425,0,0,17291749,49912,0,0,30613916,808,0,0,18860320,1048576,131072,131073,1,262145,131260,131125,241,262385,131072,131072,0,262144,131072,133702,2630,264774,131072,131120,48,262192,131072,131072,0,262144,131072,131073,1,262145,131072,133820,2748,264892,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131119,131073,48,262192,131072,131073,1,262145,131213,131075,144,262288,131072,131072,0,262144,131072,131092,20,262164,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131119,131121,96,262240,131072,131072,0,262144,131072,133672,2600,264744,131072,131072,0,262144,131072,131072,0,262144,131072,131076,4,262148,131072,133693,2621,264765,262144,0,262144,262336,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262288,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,0,0,3145728,524288,32505856,371617586,219975093,119136637,484284,0,0,0,1048576,52783888,52558293,1048576,1048576,131072,524288,741,507572,4698,0,96,10678,0,8388944,32505856,4044624,3836547,57381560,11534336,0,0,14155776,67108864,67108864,0,67108864,54316824,53935959,0,1048576,245047,769335,12072,2382,0,500985,8399722,0,4194727,4204995,13631488,0,3670016,1048576,1048576,0,4194304,9437184,0,0,360,33554432,54098162,4194304,0,0,2827,498678,0,10951,8388608,0,4194370,905969664,6291456,0,0,0,524288,524288,0,15308,16608971,0,16777216,4194304,4194304,0,0,0,18358,4194348,4194348,0,222219,0,0,0,33554432,0,0,0,0,631333356,0,2769699277,0,0,0,0,0,480393,0,0,220213,0,0,8388608,336,144,0,0,0,480,8388608,0,0,0,0,266247,0,0,0,10779,0,21540,0,6291456,6289443,96,2244,1974907,0,0,0,0,0,0,0,0,0,3145728,0,0,0,151865,4194304,4189863,144,4297,2097152,524288,1572864,0,0,0,0,0,0,524288,0,4128857,65533,4063253,0,0,8388608,0,41994980,0,1048576,10374,4194380,12760305,609694263,12074221976126029,12074243664893082,12074243665216759,12074222222531546
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/prev_analysis/1.csv
index c360cb6854..e3494d049d 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/prev_analysis/1.csv
@@ -1,2 +1,2 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 __amd_rocclr_fillBuffer.kd,1,323677.0,323677.0,323677.0,100.0
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/prev_analysis/1001.csv
index 2923ed58d3..25f1221e3b 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,18.0,Instr per wave
 SMEM,8.0,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/prev_analysis/101.csv
index 3334076c32..c03f8079bd 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx908
 mi100
 48
 1228.8
-SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/prev_analysis/1202.csv
index d187257fd7..f81e291b78 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,2835.2171783447266,2835.2171783447266,2835.2171783447266,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/prev_analysis/1901.csv
index cf7b591abd..a9f5b4cc44 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,8.0,smem_
 VALU,22.0,valu_
 MFMA,,mfma_
 VMEM,2.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,6.0,br_
 VGPR,8.0,vgpr_
 SGPR,32.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,524288.0,wavefronts_
 Workgroups,131072.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,12.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,8.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,0.0,hbm_rd_
 HBM Wr,8.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,25.0,vl1_coales_
 VL1 Stall,22.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,31.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/prev_analysis/2001.csv
index 90cd5504cd..5794a6cd05 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/prev_analysis/2001.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/prev_analysis/201.csv
index b6564f7609..47af9139f9 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,23.285544244879105,Pct,100,23.285544244879105
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,64.0,Threads,64,100.0
 IPC - Issue,0.9193548387096774,Instr/cycle,5,18.387096774193548
-LDS BW,0.0,Gb/sec,23070.72,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,23070.72,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99847365601835,Pct,100,99.99847365601835
 Instr Cache BW,1243.9968981422837,Gb/s,4614.144,26.960513112340745
 Scalar L1D Cache Hit Rate,99.99656325156498,Pct,100,99.99656325156498
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/prev_analysis/602.csv
index 02ab2678ec..79eb6fd050 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,0.0,0,0,Simd
 Insufficient SIMD VGPRs,0.0,0,0,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/prev_analysis/701.csv
index ebf5f22ba4..1d3a71c87a 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,8.0,8,8,Registers
 SGPRs,32.0,32,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/sysinfo.csv
index 7131aff4e2..0e1429a270 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-D_val_int2,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 10:56:29 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+D_val_int2,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 10:56:29 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/timestamps.csv
index 5bdb14e157..d14ee7b1a9 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,815652,815657,33554432,256,0,0,8,32,6464,0x0,0x7fe94c604180,12074243664847671,12074243664893082,12074243665216759,12074243665326411
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,815652,815657,32768,256,0,0,24,24,12480,0x0,0x7fe94c635100,12074243680217791,12074243680327024,12074243680333584,12074243680339377
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,815652,815657,4194304,256,0,0,24,24,12928,0x7fea58305900,0x7fe94c635140,12074243680385021,12074243680398223,12074243680529902,12074243680533557
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/SQ_IFETCH_LEVEL.csv
index 869267ad05..ae5b805e9e 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/SQ_IFETCH_LEVEL.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,90913,90913,33554432,256,0,0,4,32,4160,0x0,0x7f3b43c04280,383034,383034,524288,4718592,686632,76862836,15153846440742,15153096050656,15153995602836,15153995693396
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/SQ_INST_LEVEL_LDS.csv
index a6a1c98c94..8004f4a81c 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/SQ_INST_LEVEL_LDS.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,92765,92765,33554432,256,0,0,4,32,4160,0x0,0x7f5537004280,0,0,0,15168213693776,15167460633231,15168358654476,15168358769216
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/SQ_INST_LEVEL_SMEM.csv
index fb129b4cdc..fd2bfb4d88 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/SQ_INST_LEVEL_SMEM.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,90690,90690,33554432,256,0,0,4,32,4160,0x0,0x7ff356204280,3670016,3078742,344577256,15152939270833,15147444181555,15153096050667,15153096134937
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/SQ_INST_LEVEL_VMEM.csv
index 50c5cd0f89..c7df43ce76 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/SQ_INST_LEVEL_VMEM.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,92542,92542,33554432,256,0,0,4,32,4160,0x0,0x7f42c3a04280,524288,5460928,611616244,15167313408702,15166323432920,15167460632899,15167460722639
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/SQ_LEVEL_WAVES.csv
index f4667eaa9b..b008a768aa 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/SQ_LEVEL_WAVES.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,91136,91136,33554432,256,0,0,4,32,4160,0x0,0x7fec0a004280,386176,386176,8785,3089416,524288,244042120,3003018,0,992484888,15154752568407,15153995602421,15154897447043,15154897559613
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/pmc_dispatch_info.csv
index 8226fe9c0f..63bb17b9f9 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/pmc_dispatch_info.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/pmc_perf.csv
index a3d1fdb0f8..aeba65f090 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/pmc_perf.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDI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],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBufferAligned.kd,0,0,0,91903,91903,33554432,256,0,0,4,32,4160,0x0,0x7f28c3c04280,3118248,3032444,524288,39399694,247900583,392,224,0,389780,389780,39664318.0,38212178.0,13.0,4206179.0,31369025.0,31010281.0,38195543.0,37637872.0,3116537,3038835,389780,0,389780,0,12472960.0,9450613.0,0.0,0.0,0,0,616,0,4718592,4714928,112,3552,376490,0.0,0.0,0.0,524288.0,28664146.0,27946083.0,7767.0,524288.0,131072,524288,302,385490,2320,0,56.0,302.0,0.0,4194696.0,0,0,0,0,0,7340032,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,20248354.0,524288.0,0,385767,0,0,0,385767,0,0,0,385767,0,0,0,385767,0,0,0,385767,0,0,0,385767,0,0,0,385767,0,0,0,385767,0,0,0,385767,0,0,0,385767,0,0,0,385767,0,0,0,385767,0,0,0,385767,0,0,0,385767,0,0,0,385767,0,0,0,385767,0,0,0,385767,0,0,0,385767,0,0,0,385767,0,0,0,385767,0,0,0,385767,0,0,0,385767,0,0,0,385767,0,0,0,385767,0,0,0,385767,0,0,0,385767,0,0,0,385767,0,0,0,385767,0,0,0,385767,0,0,0,385767,0,0,0,385767,0,0,0,385767,0,0,0,0,0,0.0,21243669.0,32,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,2,0,0,0,0,0,0,0,0,0,0,0,56,0,0,0,0,0,0,0,33,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,35,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,5,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,32,0,0,0,112,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,524288.0,0.0,0,44447,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,331,129024,129024,0,511,129024,129024,0,185204,129024,129024,0,0,129024,129024,0,0,129024,129024,0,43662,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,310936,129024,129024,0,0,129024,129024,0,1187,129024,129024,0,0,129024,129024,0,888,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,45161,129024,129024,0,0,129024,129024,0,171,129024,129024,0,0,129024,129024,0,186,129024,129024,524288.0,0.0,44713,0,0,50639762,45512,0,0,50757366,44556,0,0,50305326,47447,0,0,52095424,45182,0,0,51303062,45881,0,0,51308813,44316,0,0,50579217,47578,0,0,52780352,44505,0,0,50749064,45994,0,0,50906498,45365,0,0,50524051,48055,0,0,52189035,45499,0,0,51506091,47906,0,0,51901482,46021,0,0,51245390,49102,0,0,53288709,43482,0,0,50404874,46207,0,0,51018922,43514,0,0,49860026,47139,0,0,51957569,44979,0,0,51339757,45938,0,0,51241679,44666,0,0,50710369,47719,0,0,52595745,44789,0,0,50679038,45538,0,0,50938899,45222,0,0,50344183,47940,0,0,52263835,47015,0,0,51953543,47531,0,0,51880943,44770,0,0,50855868,48897,0,0,52946462,0.0,65536,65568,32,131104,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65646,65538,112,131184,65536,65536,0,131072,65536,65648,112,131184,65536,65536,0,131072,65536,65536,0,131072,65536,65568,32,131104,65536,65536,0,131072,65536,65592,56,131128,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65571,35,131107,65536,65537,1,131073,65536,65536,0,131072,65536,65536,0,131072,65758,65541,227,131299,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65568,32,131104,65536,65536,0,131072,65536,65536,0,131072,65591,65537,56,131128,65591,65537,56,131128,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131184,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131296,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131128,0,131072,1131611,0,524288,3670016,3663178,224,6614,1048576,33554432.0,33554432.0,0.0,33554432.0,29580998.0,27875655.0,0.0,524288.0,208317,538451,8536,940,0,378694,4195053.0,0.0,2097594.0,2097459.0,1048576,1048576,0,524288,0,524288,7340032,0,0.0,0.0,104.0,8388608.0,29617496.0,2097152.0,0.0,204429,0,1216,383132,0,750.0,4194304.0,0.0,2064387.0,25690112,9437184,0,0,0,0,0,0,13276.0,8242572.0,0.0,8388608.0,2097152.0,4194304.0,9896581,0,0,8932,4128768.0,4128768.0,0.0,1489101.0,0,0,0,0,0,0,5767168,1048576,316300229.0,0.0,1473030130.0,0.0,44.0,0.0,0,0,375067,0.0,0.0,1491433.0,0.0,3670016,524288,0,0,0,2621440,524288,177710806,4194304.0,0.0,0.0,0.0,0.0,1219992.0,0,0,0.0,312.0,0.0,608.0,42368212,24117248,0,0,9437184,11010048,0,3145728,0.0,0.0,0.0,0.0,0.0,0.0,0,1572864,0.0,0.0,0.0,198929.0,524288,524288,0,3670016,7340032,603979776,4718592,0,0.0,0.0,0.0,0.0,0.0,0.0,524288,0,2064384.0,0.0,2031624.0,0.0,0,0,524288,0,0,0,0,33554432,0.0,4194304.0,0.0,19088934.0,0.0,0.0,141.0,4128768.0,1007291.0,1668121998.0,15156145307114,15168985990090,15168986231051,15156293820877
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/prev_analysis/1.csv
index d8c0cec183..44bef41197 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/prev_analysis/1.csv
@@ -1,2 +1,2 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 __amd_rocclr_fillBufferAligned.kd,1,240961.0,240961.0,240961.0,100.0
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/prev_analysis/1001.csv
index e34ed0c6f6..0850fc4acd 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,18.0,Instr per wave
 VMEM,1.0,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,0.0,Instr per wave
 SALU,14.0,Instr per wave
 SMEM,7.0,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/prev_analysis/101.csv
index bc06f7f0d4..3341cb135c 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx90a
 mi200
 56
 1638.4
-roofline|SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+roofline|SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/prev_analysis/1202.csv
index b78c8ccde9..8d7c3558d0 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,1891.3313522338867,1891.3313522338867,1891.3313522338867,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/prev_analysis/1901.csv
index 4673e59347..c233e2ffa2 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,7.0,smem_
 VALU,18.0,valu_
 MFMA,0.0,mfma_
 VMEM,1.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,5.0,br_
 VGPR,4.0,vgpr_
 SGPR,32.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,524288.0,wavefronts_
 Workgroups,131072.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,9.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,8.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,0.0,hbm_rd_
 HBM Wr,8.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,25.0,vl1_coales_
 VL1 Stall,11.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,25.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/prev_analysis/2001.csv
index 8226fe9c0f..63bb17b9f9 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/prev_analysis/2001.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/prev_analysis/201.csv
index 8cdce4e1cd..b23b8aaf9b 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,23.280351440852236,Pct,100,23.280351440852236
 MFMA Util,0.0,Pct,100,0.0
 VALU Active Threads/Wave,64.0,Threads,64,100.0
 IPC - Issue,1.0,Instr/cycle,5,20.0
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99762462248465,Pct,100,99.99762462248465
 Instr Cache BW,1253.2728864837047,Gb/s,6092.8,20.56973618834862
 Scalar L1D Cache Hit Rate,99.99388546493122,Pct,100,99.99388546493122
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/prev_analysis/602.csv
index d864cd3c31..ea45e5dca4 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,9896581.0,9896581,9896581,Simd
 Insufficient SIMD VGPRs,0.0,0,0,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/prev_analysis/701.csv
index c47e77a25f..f8ed8cd0d3 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,4.0,4,4,Registers
 SGPRs,32.0,32,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/sysinfo.csv
index 5f4bed3baa..5868bfd063 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-D_val_int2,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:05:48 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,roofline|SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+D_val_int2,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:05:48 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,roofline|SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/timestamps.csv
index de55f4c791..643926022c 100644
--- a/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/D_val_int2/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,92848,92848,33554432,256,0,0,4,32,4160,0x0,0x7f8e1d204280,15168985964210,15168985990090,15168986231051,15168986352141
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,92848,92848,32768,256,0,0,12,24,13888,0x0,0x7f8e1d223f80,15168991007582,15168991022750,15168991036030,15168991053271
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,92848,92848,4194304,256,0,0,12,24,14336,0x7f8e20219380,0x7f8e1d223fc0,15168991057700,15168991106270,15168991198591,15168991200567
diff --git a/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/SQ_IFETCH_LEVEL.csv
index 8ab3680813..f63d93503f 100644
--- a/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/SQ_IFETCH_LEVEL.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,753474,753479,33554432,256,0,0,8,32,6464,0x0,0x7efb9f204180,505001,505001,524288,6291456,798970,102234720,12073249076478544,12073249322913758,12073249323238076,12073249323352138
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,753474,753479,32768,256,0,0,24,24,12480,0x0,0x7efb9f235100,28408,28408,512,8192,9212,1184280,12073249338249459,12073249338569276,12073249338575836,12073249338584161
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,753474,753479,4194304,256,0,0,24,24,12928,0x7efccf4e1900,0x7efb9f235140,215284,215284,65536,917504,140220,17924904,12073249338648751,12073249338877434,12073249339008634,12073249339012336
diff --git a/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/SQ_INST_LEVEL_LDS.csv
index b4f4b65416..1b53686527 100644
--- a/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/SQ_INST_LEVEL_LDS.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,755285,755290,33554432,256,0,0,8,32,6464,0x0,0x7f4409a04180,0,0,0,12073275525448091,12073275771371904,12073275771694462,12073275771804244
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,755285,755290,32768,256,0,0,24,24,12480,0x0,0x7f4409a35100,0,0,0,12073275786464083,12073275786775622,12073275786782662,12073275786791061
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,755285,755290,4194304,256,0,0,24,24,12928,0x7f4515574900,0x7f4409a35140,0,0,0,12073275786854108,12073275787071300,12073275787206180,12073275787210580
diff --git a/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/SQ_INST_LEVEL_SMEM.csv
index 7d47c7f5c2..312de25db2 100644
--- a/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/SQ_INST_LEVEL_SMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,754907,754912,33554432,256,0,0,8,32,6464,0x0,0x7fac21c04180,4194304,3069266,392921000,12073272986459573,12073273234249783,12073273234572661,12073273234687003
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,754907,754912,32768,256,0,0,24,24,12480,0x0,0x7fac21c35100,512,26698,3400104,12073273249150468,12073273249459097,12073273249466937,12073273249472336
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,754907,754912,4194304,256,0,0,24,24,12928,0x7fad2d8fa900,0x7fac21c35140,65536,183770,23525024,12073273249529852,12073273249799095,12073273249931735,12073273249936388
diff --git a/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/SQ_INST_LEVEL_VMEM.csv
index ecc594d24d..2771c698cb 100644
--- a/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/SQ_INST_LEVEL_VMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,755097,755102,33554432,256,0,0,8,32,6464,0x0,0x7f0708c04180,1048576,11229461,1436753852,12073274263481419,12073274504381763,12073274504703362,12073274504801504
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,755097,755102,32768,256,0,0,24,24,12480,0x0,0x7f0708c35100,4096,111655,14289648,12073274519488184,12073274519791569,12073274519797649,12073274519803319
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,755097,755102,4194304,256,0,0,24,24,12928,0x7f081480b900,0x7f0708c35140,524288,10912621,1396868500,12073274519868120,12073274520089008,12073274520225967,12073274520230152
diff --git a/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/SQ_LEVEL_WAVES.csv
index 6c913e1c6d..644f4a7a2d 100644
--- a/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/SQ_LEVEL_WAVES.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,755475,755480,33554432,256,0,0,8,32,6464,0x0,0x7ff9ce004180,505403,505403,16421,4043232,524288,375778688,3845014,0,1517893596,12073276799251457,12073277044879799,12073277045205717,12073277045322129
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,755475,755480,32768,256,0,0,24,24,12480,0x0,0x7ff9ce035100,27503,27503,20283,220032,512,1148263,78001,0,4607132,12073277060019208,12073277060348552,12073277060354952,12073277060363898
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,755475,755480,4194304,256,0,0,24,24,12928,0x7ffad9d4f900,0x7ff9ce035140,216404,216404,20803,1731240,65536,151708307,1571525,0,608646504,12073277060429520,12073277060674790,12073277060807109,12073277060810608
diff --git a/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/pmc_dispatch_info.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/pmc_perf.csv
index aee4714bb9..67344acd74 100644
--- a/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBuffer.kd,0,0,0,754208,754213,33554432,256,0,0,8,32,6464,0x0,0x7fac1ee04180,1048576,0,1048576,9437184,0,4194304,1048576,0,500538,500538,57415515,55137926,74,12919483,54450833,54376132,55106876,53932520,4004304,3812154,500538,0,500538,0,16017216,15168195,0,0,0,0,0,17084357,1048576,0,503590,0,0,0,503590,0,0,0,503590,0,0,0,503590,0,0,0,503590,0,0,0,503590,0,0,0,503590,0,0,0,503590,0,0,0,503590,0,0,0,503590,0,0,0,503590,0,0,0,503590,0,0,0,503590,0,0,0,503590,0,0,0,503590,0,0,0,503590,0,0,0,503590,0,0,0,503590,0,0,0,503590,0,0,0,503590,0,0,0,503590,0,0,0,503590,0,0,0,503590,0,0,0,503590,0,0,0,503590,0,0,0,503590,0,0,0,503590,0,0,0,503590,0,0,0,503590,0,0,0,503590,0,0,0,503590,0,0,0,503590,0,0,0,37296205,0,0,0,0,4,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,3,0,0,0,17,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2620,0,0,0,0,0,0,0,0,0,0,0,2,0,0,0,0,0,0,0,48,0,0,0,2539,0,0,0,0,0,0,0,0,0,0,0,48,0,0,0,1,0,0,0,0,0,0,0,2656,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,2619,0,0,0,1,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,1048576,0,0,0,131072,131072,0,30218,131072,131072,0,0,131076,131076,0,3123046,131072,131072,0,0,131072,131072,0,0,131072,131072,0,779,131072,131072,0,3296923,131072,131072,0,0,131076,131076,0,0,131080,131080,0,0,131072,131072,0,0,131072,131072,0,0,131080,131080,0,0,131072,131072,0,0,131080,131080,0,0,131072,131072,0,262,131072,131072,0,784,131072,131072,0,0,131076,131076,0,11071,131072,131072,0,1730,131072,131072,0,0,131072,131072,0,0,131076,131076,0,1491,131072,131072,0,0,131076,131076,0,0,131072,131072,0,0,131072,131072,0,3078448,131072,131072,0,262,131076,131076,0,578291,131076,131076,0,0,131076,131076,0,3242796,131080,131080,1048576,0,1657,0,0,17292670,883,0,0,17346440,1106,0,0,17210188,768,0,0,17189194,901,0,0,17476818,779,0,0,17291102,775,0,0,18085351,926,0,0,18647015,50971,0,0,30728852,1222,0,0,17387015,1008,0,0,17110985,1274,0,0,16840874,726,0,0,17242080,818,0,0,17429149,796,0,0,18099825,49307,0,0,31770898,705,0,0,16709546,835,0,0,17119824,855,0,0,17157969,44090,0,0,29468827,39162,0,0,29074737,1653,0,0,17434833,985,0,0,18065956,848,0,0,18419765,1203,0,0,16755354,993,0,0,17185603,854,0,0,17159106,1080,0,0,17060663,839,0,0,17360762,1157,0,0,17398923,890,0,0,17958709,940,0,0,18787676,1048576,131072,133826,2754,264898,131260,131076,192,262336,131072,131075,3,262147,131072,131072,0,262144,131072,133615,2543,264687,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131119,131073,48,262192,131119,131073,48,262192,131072,131073,1,262145,131072,131072,0,262144,131072,131090,18,262162,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131073,1,262145,131213,131123,192,262336,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,133715,2643,264787,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,133640,2568,264712,131072,131072,0,262144,131072,131072,0,262144,131072,131121,49,262193,262144,0,262144,262336,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262288,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,0,0,3145728,524288,32505856,368849060,217495277,118847927,476987,0,0,0,1048576,52446510,52240561,1048576,1048576,131072,524288,698,498383,4033,0,96,10599,0,8388944,32505856,4031816,3827413,57225717,11534336,0,0,14155776,67108864,67108864,0,67108864,54336713,53969013,0,1048576,245944,770232,11566,2452,0,499932,8399681,0,4194727,4204954,13631488,0,3670016,1048576,1048576,0,4194304,9437184,0,0,360,33554432,53716408,4194304,0,0,2417,496945,0,10782,8388608,0,4194370,905969664,6291456,0,0,0,524288,524288,0,15307,16608971,0,16777216,4194304,4194304,0,0,0,18005,4194376,4194376,0,224165,0,0,0,33554432,0,0,0,0,641489288,0,2810086152,0,0,0,0,0,475855,0,0,217815,0,0,8388608,336,144,0,0,0,480,8388608,0,0,0,0,317882,0,0,0,10705,0,21392,0,6291456,6289517,96,2044,1928688,0,0,0,0,0,0,0,0,0,3145728,0,0,0,156664,4194304,4189859,144,4301,2097152,524288,1572864,0,0,0,0,0,0,524288,0,4128817,65534,4063250,0,0,8388608,0,42442337,0,1048576,10673,4194361,13075430,608370265,12073251242118155,12073277939480571,12073277939805848,12073251490217286
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,754208,754213,32768,256,0,0,24,24,12480,0x0,0x7fac1ee35100,0,4096,4096,512,0,512,4096,0,28452,28452,1556207,599371,225,146795,87843,66051,591292,570773,227616,89567,28452,0,28452,0,910464,204002,0,0,0,0,0,61922,4096,0,28930,0,0,0,28930,0,0,0,28930,0,0,0,28930,0,0,0,28930,0,0,0,28930,0,0,0,28930,0,0,0,28930,0,0,0,28930,0,0,0,28930,0,0,0,28930,0,0,0,28930,0,0,0,28930,0,0,0,28930,0,0,0,28930,0,0,0,28930,0,0,0,28930,0,0,0,28930,0,0,0,28930,0,0,0,28930,0,0,0,28930,0,0,0,28930,0,0,0,28930,0,0,0,28930,0,0,0,28930,0,0,0,28930,0,0,0,28930,0,0,0,28930,0,0,0,28930,0,0,0,28930,0,0,0,28930,0,0,0,28930,0,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,376,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,261,0,0,0,256,0,0,0,304,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,258,0,0,0,256,0,0,0,4096,4096,0,115917,0,0,0,120965,0,0,0,72972,0,0,0,88249,0,0,0,82125,0,0,0,102139,0,0,0,74608,0,0,0,119944,0,0,0,102630,0,0,0,127539,0,0,0,89913,0,0,0,91334,0,0,0,113911,0,0,0,99133,0,0,0,91720,0,0,0,70176,0,0,0,124235,0,0,0,125384,0,0,0,74332,0,0,0,185651,0,0,0,86495,0,0,0,122560,0,0,0,91865,0,0,0,87171,0,0,0,107305,0,0,0,91362,0,0,0,70003,0,0,0,96155,0,0,0,78520,0,0,0,90131,0,0,0,84149,0,0,0,87589,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4096,0,304,304,304,0,256,256,256,0,257,257,257,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,47,257,304,304,0,256,256,256,0,257,257,257,0,256,256,256,0,376,376,376,0,256,256,256,188,260,448,448,0,256,256,256,0,257,257,257,0,256,256,256,188,260,448,448,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,257,257,257,0,256,256,256,47,257,304,304,0,305,305,305,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,304,0,0,256,0,0,0,0,512,512,35328,1181838,1132829,12657,12209,0,0,0,4096,75719,72532,4096,4096,128,512,607,27009,3982,0,48,219,0,8624,36352,220432,71852,1002979,26624,0,0,30208,65536,65536,65536,0,0,0,0,0,116,628,11542,2905,0,23475,8844,0,470,8374,1024,0,1024,4096,0,4096,512,512,0,0,360,16384,0,16384,0,0,2390,24827,0,8843,0,0,31,1933312,8192,0,0,0,512,512,0,120,15064,0,16384,16384,0,0,0,0,20826,0,0,0,0,0,0,0,32768,0,0,0,0,12319769,17649555,0,8192,0,0,0,0,695,0,0,0,0,0,1024,432,48,0,0,0,480,0,0,0,0,0,3176,0,0,0,8421,0,438,0,8192,6538,48,1606,1082,0,0,0,0,0,0,0,0,0,2560,0,0,0,49671,512,0,48,464,0,512,0,0,0,0,0,0,0,512,0,0,0,0,0,8192,0,0,446779,0,4096,8420,0,3384359,0,12073251505398644,12073277954543789,12073277954550669,12073251506358358
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,754208,754213,4194304,256,0,0,24,24,12928,0x7fad4ee67900,0x7fac1ee35140,0,524288,524288,65536,0,65536,524288,0,221202,221202,24684497,23422300,32121,8608587,23089826,23016598,23413900,21250286,1769616,1629647,221202,0,221202,0,7078464,6365902,0,0,0,0,0,19845565,524288,0,214231,0,0,0,214231,0,0,0,214231,0,0,0,214231,0,0,0,214231,0,0,0,214231,0,0,0,214231,0,0,0,214231,0,0,0,214231,0,0,0,214231,0,0,0,214231,0,0,0,214231,0,0,0,214231,0,0,0,214231,0,0,0,214231,0,0,0,214231,0,0,0,214231,0,0,0,214231,0,0,0,214231,0,0,0,214231,0,0,0,214231,0,0,0,214231,0,0,0,214231,0,0,0,214231,0,0,0,214231,0,0,0,214231,0,0,0,214231,0,0,0,214231,0,0,0,214231,0,0,0,214231,0,0,0,214231,0,0,0,214231,0,0,0,0,65536,0,225,0,65536,0,10792,0,65540,0,4936,0,65536,0,2317,0,65536,0,3091,0,65536,0,1871,0,65536,0,3971,0,65656,0,9959,0,65536,0,2726,0,65536,0,136,0,65536,0,12761,0,67195,0,50929,0,65536,0,8455,0,65536,0,8630,0,65537,0,161,0,65536,0,0,0,65584,0,6102,0,65536,0,6595,0,65536,0,3550,0,65536,0,1650,0,65536,0,2,0,65537,0,993,0,65536,0,6268,0,65536,0,13943,0,65537,0,11993,0,65536,0,8784,0,65536,0,844,0,68178,0,90546,0,65537,0,8685,0,65536,0,8492,0,65541,0,11312,0,65536,0,4083,0,524288,524288,0,23024391,0,0,0,22748314,0,0,0,25122341,0,0,0,51396609,0,0,0,26162659,0,0,0,26296268,0,0,0,25124663,0,0,0,26082468,0,0,0,24086669,0,0,0,24585213,0,0,0,22983263,0,0,0,25018623,0,0,0,26651672,0,0,0,25520952,0,0,0,24522212,0,0,0,25243694,0,0,0,25361061,0,0,0,24838335,0,0,0,26350109,0,0,0,29788738,0,0,0,22355504,0,0,0,23084849,0,0,0,25140203,0,0,0,24650236,0,0,0,25408289,0,0,0,24376974,0,0,0,27031344,0,0,0,26603409,0,0,0,23670122,0,0,0,24866948,0,0,0,22649299,0,0,0,44380029,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,524288,0,66865,66865,66865,0,65536,65536,65536,188,65541,65729,65729,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,47,65537,65584,65584,0,65536,65536,65536,0,65537,65537,65537,0,65536,65536,65536,0,65656,65656,65656,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65537,65537,65537,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,66061,66061,66061,0,65536,65536,65536,188,65540,65728,65728,0,65585,65585,65585,65536,0,0,65536,0,0,65728,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65728,0,0,65536,0,0,0,0,65536,65536,4128768,122661721,47898861,70503020,203886,0,0,0,524288,22129144,22115617,524288,524288,16384,65536,747,221399,3958,0,48,4003,0,2097536,4259840,1729576,1562748,23118568,3014656,0,0,3473408,8388608,8388608,8388608,0,0,0,0,0,190445,212199,11093,2468,0,212217,2100236,0,423,2099813,131072,0,131072,524288,0,524288,65536,65536,0,0,360,2097152,0,2097152,38284,0,2404,213650,0,2100410,0,0,31,222298112,917504,0,0,0,65536,65536,0,7549,2015897,0,2097152,2097152,0,599557,601297,0,21358,0,0,0,0,0,0,0,4194304,0,0,0,0,1104364706,1942934639,0,2097152,0,0,0,0,190460,0,0,0,0,0,131072,384,48,0,0,0,432,0,0,0,0,0,7863,0,0,0,2100302,0,6282,0,917504,914738,48,7476,210614,0,0,0,0,0,0,0,0,0,327680,0,0,477082,530147,65536,64048,48,1440,0,65536,0,0,0,0,0,0,0,65536,0,0,0,1966095,0,2097152,0,0,15238416,0,524288,2101061,0,1036928381,0,12073251506990833,12073277954616748,12073277954747147,12073251508270611
diff --git a/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/prev_analysis/1.csv
index cfb70f2c7c..1b414109b5 100644
--- a/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,6058514.0,6058514.0,6058514.0,9.175642272271793
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4527486.0,4527486.0,4527486.0,6.856894599685456
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 256u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,3052937.0,3052937.0,3052937.0,4.623684585326142
diff --git a/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/prev_analysis/1001.csv
index ca08330db0..0e3bf5267e 100644
--- a/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,46.862275449101794,Instr per wave
 SMEM,1.8083832335329342,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/prev_analysis/101.csv
index 0f1ac11782..2d43366c6e 100644
--- a/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx908
 mi100
 48
 1228.8
-SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/prev_analysis/1202.csv
index eb205153bf..9d488c9330 100644
--- a/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,33662.33208917858,2814.095001220703,547933.2963256836,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/prev_analysis/1901.csv
index b6ede4f357..d6ee1ee1d9 100644
--- a/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,2.0,smem_
 VALU,735.0,valu_
 MFMA,,mfma_
 VMEM,8.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,22.0,br_
 VGPR,24.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,67894.0,wavefronts_
 Workgroups,16973.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,163.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,0.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,44.0,hbm_rd_
 HBM Wr,0.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,70.0,vl1_coales_
 VL1 Stall,31.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,37.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/prev_analysis/2001.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/prev_analysis/201.csv
index b8b9992cca..b6f3f894c4 100644
--- a/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,59.83503670564975,Pct,100,59.83503670564975
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,63.96782368381927,Threads,64,99.94972450596761
 IPC - Issue,0.8437267435452248,Instr/cycle,5,16.874534870904498
-LDS BW,0.0,Gb/sec,23070.72,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,23070.72,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99340597424688,Pct,100,99.99340597424688
 Instr Cache BW,1406.0796376151418,Gb/s,4614.144,30.47325002460135
 Scalar L1D Cache Hit Rate,99.35620448525428,Pct,100,99.35620448525428
diff --git a/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/prev_analysis/602.csv
index 535804da70..ceacd88613 100644
--- a/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,68338.29341317365,0,767300,Simd
 Insufficient SIMD VGPRs,539206.1556886227,0,33616894,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/prev_analysis/701.csv
index d3f1bff5a3..1071413faa 100644
--- a/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,23.976047904191617,8,36,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/sysinfo.csv
index d1393e12db..3e60085f5a 100644
--- a/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-Double_N_flag,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 10:40:24 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+Double_N_flag,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 10:40:24 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/timestamps.csv
index 7f354d33dd..3f77d3b7b8 100644
--- a/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,755525,755530,33554432,256,0,0,8,32,6464,0x0,0x7f5a91804180,12073277939439483,12073277939480571,12073277939805848,12073277939922320
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,755525,755530,32768,256,0,0,24,24,12480,0x0,0x7f5a91835100,12073277954440757,12073277954543789,12073277954550669,12073277954557223
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,755525,755530,4194304,256,0,0,24,24,12928,0x7f5b9d52c900,0x7f5a91835140,12073277954599522,12073277954616748,12073277954747147,12073277954751133
diff --git a/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi200/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi200/SQ_IFETCH_LEVEL.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi200/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi200/SQ_IFETCH_LEVEL.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi200/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi200/SQ_INST_LEVEL_LDS.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi200/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi200/SQ_INST_LEVEL_LDS.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi200/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi200/SQ_INST_LEVEL_SMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi200/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi200/SQ_INST_LEVEL_SMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi200/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi200/SQ_INST_LEVEL_VMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi200/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi200/SQ_INST_LEVEL_VMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi200/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi200/SQ_LEVEL_WAVES.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi200/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi200/SQ_LEVEL_WAVES.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi200/pmc_perf.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi200/pmc_perf.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi200/timestamps.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/Double_N_flag/mi200/timestamps.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/HBM/mi100/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/HBM/mi100/SQ_IFETCH_LEVEL.csv
index 0dec63c5f0..af7b88f075 100644
--- a/projects/rocprofiler-compute/tests/workloads/HBM/mi100/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/HBM/mi100/SQ_IFETCH_LEVEL.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,873972,873977,33554432,256,0,0,8,32,6464,0x0,0x7f8ee3a04180,509817,509817,524288,6291456,792382,101515868,12075419862902974,12075420108485349,12075420108812067,12075420108922310
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,873972,873977,32768,256,0,0,24,24,12480,0x0,0x7f8ee3a35100,28725,28725,512,8192,8564,1106472,12075420123341778,12075420123657111,12075420123663351,12075420123671170
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,873972,873977,4194304,256,0,0,24,24,12928,0x7f9013d2a900,0x7f8ee3a35140,222139,222139,65536,917504,140727,17952788,12075420123735800,12075420123960790,12075420124096309,12075420124100558
diff --git a/projects/rocprofiler-compute/tests/workloads/HBM/mi100/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/HBM/mi100/SQ_INST_LEVEL_LDS.csv
index cde4ff759e..7489fd16e3 100644
--- a/projects/rocprofiler-compute/tests/workloads/HBM/mi100/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/HBM/mi100/SQ_INST_LEVEL_LDS.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,875773,875778,33554432,256,0,0,8,32,6464,0x0,0x7efd0fa04180,0,0,0,12075446198050940,12075446442424062,12075446442747100,12075446442857662
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,875773,875778,32768,256,0,0,24,24,12480,0x0,0x7efd0fa35100,0,0,0,12075446457398255,12075446457697741,12075446457704301,12075446457709524
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,875773,875778,4194304,256,0,0,24,24,12928,0x7efe3faf3900,0x7efd0fa35140,0,0,0,12075446457773643,12075446457993100,12075446458130539,12075446458134884
diff --git a/projects/rocprofiler-compute/tests/workloads/HBM/mi100/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/HBM/mi100/SQ_INST_LEVEL_SMEM.csv
index 5e91819f2a..b3723673b8 100644
--- a/projects/rocprofiler-compute/tests/workloads/HBM/mi100/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/HBM/mi100/SQ_INST_LEVEL_SMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,875394,875399,33554432,256,0,0,8,32,6464,0x0,0x7f9114204180,4194304,3178902,406901080,12075443676964683,12075443921800580,12075443922128098,12075443922232171
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,875394,875399,32768,256,0,0,24,24,12480,0x0,0x7f9114235100,512,22856,2927128,12075443936949303,12075443937266695,12075443937273575,12075443937283263
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,875394,875399,4194304,256,0,0,24,24,12928,0x7f921ff0c900,0x7f9114235140,65536,176256,22446856,12075443937346050,12075443937557573,12075443937689093,12075443937693215
diff --git a/projects/rocprofiler-compute/tests/workloads/HBM/mi100/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/HBM/mi100/SQ_INST_LEVEL_VMEM.csv
index 9624a44656..4c55da4ea9 100644
--- a/projects/rocprofiler-compute/tests/workloads/HBM/mi100/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/HBM/mi100/SQ_INST_LEVEL_VMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,875584,875589,33554432,256,0,0,8,32,6464,0x0,0x7f5b04404180,1048576,11071116,1417193120,12075444941615500,12075445186250006,12075445186573684,12075445186682496
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,875584,875589,32768,256,0,0,24,24,12480,0x0,0x7f5b04435100,4096,123364,15785988,12075445201347390,12075445201650930,12075445201656850,12075445201668637
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,875584,875589,4194304,256,0,0,24,24,12928,0x7f5c0ff99900,0x7f5b04435140,524288,12242043,1566904348,12075445201720614,12075445201935569,12075445202067728,12075445202071947
diff --git a/projects/rocprofiler-compute/tests/workloads/HBM/mi100/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/HBM/mi100/SQ_LEVEL_WAVES.csv
index cb487c777a..490fb6c8a5 100644
--- a/projects/rocprofiler-compute/tests/workloads/HBM/mi100/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/HBM/mi100/SQ_LEVEL_WAVES.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,875961,875968,33554432,256,0,0,8,32,6464,0x0,0x7f3be1604180,503051,503051,17342,4024416,524288,372614188,3821811,0,1505282744,12075447457147475,12075447697972945,12075447698296463,12075447698391406
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,875961,875968,32768,256,0,0,24,24,12480,0x0,0x7f3be1635100,28252,28252,21078,226024,512,1138227,76041,0,4567156,12075447712841591,12075447713206629,12075447713212869,12075447713218441
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,875961,875968,4194304,256,0,0,24,24,12928,0x7f3ced183900,0x7f3be1635140,215268,215268,20196,1722152,65536,145929920,1553929,0,585537796,12075447713295545,12075447713556867,12075447713688067,12075447713692583
diff --git a/projects/rocprofiler-compute/tests/workloads/HBM/mi100/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/HBM/mi100/pmc_dispatch_info.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/HBM/mi100/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/HBM/mi100/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/HBM/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/HBM/mi100/pmc_perf.csv
index 1eaa455319..52c44c6bbf 100644
--- a/projects/rocprofiler-compute/tests/workloads/HBM/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/HBM/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBuffer.kd,0,0,0,874707,874712,33554432,256,0,0,8,32,6464,0x0,0x7f202e804180,1048576,0,1048576,9437184,0,4194304,1048576,0,505678,505678,57906129,55767814,211,12067332,54756773,54649474,55728278,54545880,4045424,3844864,505678,0,505678,0,16181696,15324235,0,0,0,0,0,17528654,1048576,0,503673,0,0,0,503673,0,0,0,503673,0,0,0,503673,0,0,0,503673,0,0,0,503673,0,0,0,503673,0,0,0,503673,0,0,0,503673,0,0,0,503673,0,0,0,503673,0,0,0,503673,0,0,0,503673,0,0,0,503673,0,0,0,503673,0,0,0,503673,0,0,0,503673,0,0,0,503673,0,0,0,503673,0,0,0,503673,0,0,0,503673,0,0,0,503673,0,0,0,503673,0,0,0,503673,0,0,0,503673,0,0,0,503673,0,0,0,503673,0,0,0,503673,0,0,0,503673,0,0,0,503673,0,0,0,503673,0,0,0,503673,0,0,0,37487172,2605,0,0,0,52,0,0,0,48,0,0,0,0,0,0,0,2641,0,0,0,1,0,0,0,3,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,16,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,1,0,0,0,3,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2675,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,2570,0,0,0,0,0,0,0,0,0,0,0,49,0,0,0,1048576,0,0,261,131080,131080,0,20301,131072,131072,0,0,131072,131072,0,3231613,131072,131072,0,0,131072,131072,0,0,131076,131076,0,0,131080,131080,0,0,131076,131076,0,6765,131072,131072,0,0,131072,131072,0,1076,131072,131072,0,0,131072,131072,0,0,131072,131072,0,1742,131088,131088,0,0,131080,131080,0,2804829,131072,131072,0,0,131076,131076,0,782,131072,131072,0,0,131072,131072,0,3181581,131073,131073,0,0,131072,131072,0,0,131072,131072,0,0,131072,131072,0,0,131072,131072,0,262,131072,131072,0,0,131076,131076,0,0,131072,131072,0,1875,131076,131076,0,579787,131072,131072,0,0,131072,131072,0,0,131076,131076,0,3195793,131072,131072,1048576,0,47924,0,0,29520917,924,0,0,17181908,804,0,0,16550272,970,0,0,17465539,884,0,0,16934245,930,0,0,17316391,2113,0,0,17552303,844,0,0,18844844,1210,0,0,16891487,1211,0,0,17163131,947,0,0,16373470,852,0,0,17070059,47668,0,0,30247455,1261,0,0,17467688,930,0,0,17413284,919,0,0,18887992,48745,0,0,29650086,734,0,0,16643443,941,0,0,16405113,1079,0,0,17171522,1199,0,0,16980285,901,0,0,17335095,1109,0,0,17441342,883,0,0,18947868,1121,0,0,16594566,817,0,0,16700266,833,0,0,16294152,805,0,0,17114212,49057,0,0,30497283,1110,0,0,17273858,1696,0,0,17628078,1126,0,0,18936148,1048576,131072,133766,2694,264838,131260,131079,195,262339,131119,131073,48,262192,131072,131120,48,262192,131072,131120,48,262192,131072,131072,0,262144,131072,131073,1,262145,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,133601,2529,264673,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,133623,2551,264695,131260,131076,192,262336,131072,131073,1,262145,131072,131073,1,262145,131072,131072,0,262144,131072,131072,0,262144,131072,131143,71,262215,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,133855,2783,264927,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,262144,0,262144,262336,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262288,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,0,0,3145728,524288,32505856,372566667,220151710,119909101,478644,0,0,0,1048576,52845988,52654109,1048576,1048576,131072,524288,698,500771,4348,0,96,10620,0,8388944,32505856,4029128,3822589,57197514,11534336,0,0,14155776,67108864,67108864,0,67108864,54238174,53896492,0,1048576,251532,775820,12258,2396,0,499169,8399619,0,4194727,4204892,13631488,0,3670016,1048576,1048576,0,4194304,9437184,0,0,360,33554432,54190718,4194304,0,0,2835,497285,0,11006,8388608,0,4194382,905969664,6291456,0,0,0,524288,524288,0,15343,16608609,0,16777216,4194304,4194304,0,0,0,16952,4194364,4194364,0,220100,0,0,0,33554432,0,0,0,0,646417102,0,2823281594,0,0,0,0,0,477054,0,0,226394,0,0,8388608,336,144,0,0,0,480,8388608,0,0,0,0,362137,0,0,0,10753,0,21488,0,6291456,6289456,96,2089,1966224,0,0,0,0,0,0,0,0,0,3145728,0,0,0,150836,4194304,4189858,144,4302,2097152,524288,1572864,0,0,0,0,0,0,524288,0,4128837,65535,4063244,0,0,8388608,0,42169479,0,1048576,10682,4194360,13357267,610428878,12075421980047713,12075448588665738,12075448588990532,12075422224948160
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,874707,874712,32768,256,0,0,24,24,12480,0x0,0x7f202e835100,0,4096,4096,512,0,512,4096,0,28347,28347,1507907,627260,260,134064,99747,81059,619172,598637,226776,86345,28347,0,28347,0,907104,206375,0,0,0,0,0,57918,4096,0,28236,0,0,0,28236,0,0,0,28236,0,0,0,28236,0,0,0,28236,0,0,0,28236,0,0,0,28236,0,0,0,28236,0,0,0,28236,0,0,0,28236,0,0,0,28236,0,0,0,28236,0,0,0,28236,0,0,0,28236,0,0,0,28236,0,0,0,28236,0,0,0,28236,0,0,0,28236,0,0,0,28236,0,0,0,28236,0,0,0,28236,0,0,0,28236,0,0,0,28236,0,0,0,28236,0,0,0,28236,0,0,0,28236,0,0,0,28236,0,0,0,28236,0,0,0,28236,0,0,0,28236,0,0,0,28236,0,0,0,28236,0,0,0,0,256,0,0,0,304,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,376,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,257,0,0,0,305,0,0,0,4096,4096,0,93319,0,0,0,102315,0,0,0,79275,0,0,0,100619,0,0,0,86334,0,0,0,121828,0,0,0,86878,0,0,0,117902,0,0,0,167770,0,0,0,75290,0,0,0,80304,0,0,0,71395,0,0,0,85073,0,0,0,76774,0,0,0,67503,0,0,0,67185,0,0,0,101339,0,0,0,70461,0,0,0,64739,0,0,0,73820,0,0,0,132433,0,0,0,121365,0,0,0,89368,0,0,0,81295,0,0,0,129757,0,0,0,118112,0,0,0,92353,0,0,0,166992,0,0,0,92282,0,0,0,169757,0,0,0,91057,0,0,0,131451,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4096,0,256,256,256,0,257,257,257,0,256,256,256,0,304,304,304,0,256,256,256,0,256,256,256,0,257,257,257,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,188,260,448,448,0,256,256,256,0,256,256,256,47,257,304,304,188,261,449,449,0,257,257,257,0,256,256,256,0,256,256,256,0,424,424,424,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,47,257,304,304,0,256,256,256,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,304,0,0,256,0,0,0,0,512,512,35328,1153799,970795,146652,12213,0,0,0,4096,240619,238000,4096,4096,128,512,624,27591,4333,0,48,339,0,8624,36352,229880,75553,1062137,26624,0,0,30208,65536,65536,65536,0,0,0,0,0,115,627,12403,2402,0,24259,8892,0,470,8422,1024,0,1024,4096,0,4096,512,512,0,0,360,16384,0,16384,0,0,3393,25116,0,8892,0,0,31,1933312,8192,0,0,0,512,512,0,120,15064,0,16384,16384,0,0,0,0,19830,0,0,0,0,0,0,0,32768,0,0,0,0,12874048,17386824,0,8192,0,0,0,0,702,0,0,0,0,0,1024,432,48,0,0,0,480,0,0,0,0,0,2869,0,0,0,8422,0,440,0,8192,6569,48,1575,1058,0,0,0,0,0,0,0,0,0,2560,0,0,0,52354,512,0,48,464,0,512,0,0,0,0,0,0,0,512,0,0,0,0,0,8192,0,0,434745,0,4096,8421,0,3288888,0,12075422240108665,12075448603567040,12075448603573600,12075422241098755
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,874707,874712,4194304,256,0,0,24,24,12928,0x7f213a3e9900,0x7f202e835140,0,524288,524288,65536,0,65536,524288,0,226274,226274,25017707,23848162,28923,5423592,21864010,21644618,23833748,21675963,1810192,1651861,226274,0,226274,0,7240768,6520155,0,0,0,0,0,21096656,524288,0,222548,0,0,0,222548,0,0,0,222548,0,0,0,222548,0,0,0,222548,0,0,0,222548,0,0,0,222548,0,0,0,222548,0,0,0,222548,0,0,0,222548,0,0,0,222548,0,0,0,222548,0,0,0,222548,0,0,0,222548,0,0,0,222548,0,0,0,222548,0,0,0,222548,0,0,0,222548,0,0,0,222548,0,0,0,222548,0,0,0,222548,0,0,0,222548,0,0,0,222548,0,0,0,222548,0,0,0,222548,0,0,0,222548,0,0,0,222548,0,0,0,222548,0,0,0,222548,0,0,0,222548,0,0,0,222548,0,0,0,222548,0,0,0,0,67634,0,70590,0,65584,0,25457,0,65540,0,918,0,65536,0,6204,0,65536,0,21281,0,65537,0,18231,0,65536,0,22595,0,65536,0,11791,0,65536,0,6587,0,65536,0,15181,0,65536,0,28,0,65536,0,1909,0,65656,0,6521,0,65536,0,15320,0,65536,0,13424,0,65536,0,4305,0,65537,0,14017,0,65536,0,15567,0,65536,0,6402,0,65536,0,4281,0,65536,0,11475,0,65536,0,72094,0,65536,0,10115,0,65536,0,39507,0,65536,0,7556,0,65536,0,31654,0,65537,0,10120,0,65536,0,13716,0,65789,0,17623,0,65536,0,25301,0,65540,0,18023,0,65585,0,9730,0,524288,524288,0,31973999,0,0,0,33731624,0,0,0,31131127,0,0,0,28975334,0,0,0,36131647,0,0,0,31592743,0,0,0,35126988,0,0,0,35987845,0,0,0,38434389,0,0,0,33663391,0,0,0,36943588,0,0,0,37873243,0,0,0,32483172,0,0,0,33129615,0,0,0,32172950,0,0,0,43668213,0,0,0,33819161,0,0,0,30695295,0,0,0,34108752,0,0,0,47955169,0,0,0,29757660,0,0,0,35302713,0,0,0,34538225,0,0,0,32070057,0,0,0,37304481,0,0,0,38474312,0,0,0,41985908,0,0,0,38918704,0,0,0,35250004,0,0,0,40082298,0,0,0,39041315,0,0,0,38157553,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,524288,0,65536,65536,65536,0,65537,65537,65537,188,65540,65728,65728,0,65584,65584,65584,0,65536,65536,65536,0,65536,65536,65536,0,65537,65537,65537,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,66924,66924,66924,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,66383,66383,66383,47,65537,65584,65584,0,65537,65537,65537,0,65537,65537,65537,0,65536,65536,65536,0,65536,65536,65536,0,65704,65704,65704,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,188,65540,65728,65728,0,65536,65536,65536,65536,0,0,65536,0,0,65728,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65728,0,0,65536,0,0,0,0,65536,65536,4128768,142526067,53517077,84749150,196968,0,0,0,524288,21898352,21891524,524288,524288,16384,65536,771,214375,4140,0,48,2298,0,2097536,4259840,1715704,1545300,22845189,3014656,0,0,3473408,8388608,8388608,8388608,0,0,0,0,0,198864,222969,12465,2554,0,210189,2099417,0,423,2098994,131072,0,131072,524288,0,524288,65536,65536,0,0,360,2097152,0,2097152,36234,0,2780,217116,0,2101107,0,0,31,222298112,917504,0,0,0,65536,65536,0,7612,2014534,0,2097152,2097152,0,590458,592220,0,21339,0,0,0,0,0,0,0,4194304,0,0,0,0,960021495,1590583987,0,2097152,0,0,0,0,195758,0,0,0,0,0,131072,384,48,0,0,0,432,0,0,0,0,0,7101,0,0,0,2101919,0,9516,0,917504,914815,48,7384,229047,0,0,0,0,0,0,0,0,0,327680,0,0,288104,341897,65536,64048,48,1440,0,65536,0,0,0,0,0,0,0,65536,0,0,0,1966099,0,2097152,0,0,17731567,0,524288,2099453,0,1194043328,0,12075422241711374,12075448603638079,12075448603768636,12075422242966837
diff --git a/projects/rocprofiler-compute/tests/workloads/HBM/mi100/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/HBM/mi100/prev_analysis/1.csv
index 8a9cbdd727..22ba9ccbcf 100644
--- a/projects/rocprofiler-compute/tests/workloads/HBM/mi100/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/HBM/mi100/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,6056231.0,6056231.0,6056231.0,9.190448713978848
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4527133.0,4527133.0,4527133.0,6.870012662638067
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 256u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,3052595.0,3052595.0,3052595.0,4.632372475892723
diff --git a/projects/rocprofiler-compute/tests/workloads/HBM/mi100/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/HBM/mi100/prev_analysis/1001.csv
index ca08330db0..0e3bf5267e 100644
--- a/projects/rocprofiler-compute/tests/workloads/HBM/mi100/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/HBM/mi100/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,46.862275449101794,Instr per wave
 SMEM,1.8083832335329342,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/HBM/mi100/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/HBM/mi100/prev_analysis/101.csv
index 44db299a6e..37bf7d1546 100644
--- a/projects/rocprofiler-compute/tests/workloads/HBM/mi100/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/HBM/mi100/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx908
 mi100
 48
 1228.8
-SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/HBM/mi100/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/HBM/mi100/prev_analysis/1202.csv
index 912624d2f4..2f2f462d93 100644
--- a/projects/rocprofiler-compute/tests/workloads/HBM/mi100/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/HBM/mi100/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,33676.59823019062,2842.45809173584,547985.3085327148,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/HBM/mi100/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/HBM/mi100/prev_analysis/1901.csv
index 83a7f72b89..76aa3c3b51 100644
--- a/projects/rocprofiler-compute/tests/workloads/HBM/mi100/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/HBM/mi100/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,2.0,smem_
 VALU,735.0,valu_
 MFMA,,mfma_
 VMEM,8.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,22.0,br_
 VGPR,24.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,67894.0,wavefronts_
 Workgroups,16973.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,163.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,0.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,44.0,hbm_rd_
 HBM Wr,0.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,70.0,vl1_coales_
 VL1 Stall,29.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,34.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/HBM/mi100/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/HBM/mi100/prev_analysis/2001.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/HBM/mi100/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/HBM/mi100/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/HBM/mi100/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/HBM/mi100/prev_analysis/201.csv
index f9333e618e..9d6eacbfdc 100644
--- a/projects/rocprofiler-compute/tests/workloads/HBM/mi100/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/HBM/mi100/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,59.676879482999304,Pct,100,59.676879482999304
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,63.96798227036171,Threads,64,99.94997229744017
 IPC - Issue,0.8437278321487935,Instr/cycle,5,16.874556642975868
-LDS BW,0.0,Gb/sec,23070.72,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,23070.72,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.9934121023554,Pct,100,99.9934121023554
 Instr Cache BW,1411.7911427566892,Gb/s,4614.144,30.59703257541787
 Scalar L1D Cache Hit Rate,99.35620448524938,Pct,100,99.35620448524938
diff --git a/projects/rocprofiler-compute/tests/workloads/HBM/mi100/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/HBM/mi100/prev_analysis/602.csv
index 9a4786138f..477847997e 100644
--- a/projects/rocprofiler-compute/tests/workloads/HBM/mi100/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/HBM/mi100/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,46021.886227544914,0,590458,Simd
 Insufficient SIMD VGPRs,664869.0598802395,0,40730003,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/HBM/mi100/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/HBM/mi100/prev_analysis/701.csv
index d3f1bff5a3..1071413faa 100644
--- a/projects/rocprofiler-compute/tests/workloads/HBM/mi100/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/HBM/mi100/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,23.976047904191617,8,36,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/HBM/mi100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/HBM/mi100/sysinfo.csv
index dc32bd9a84..7ba35421fb 100644
--- a/projects/rocprofiler-compute/tests/workloads/HBM/mi100/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/HBM/mi100/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-HBM,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 11:16:34 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+HBM,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 11:16:34 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/HBM/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/HBM/mi100/timestamps.csv
index edff5e912b..4f1fb021d5 100644
--- a/projects/rocprofiler-compute/tests/workloads/HBM/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/HBM/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,876012,876017,33554432,256,0,0,8,32,6464,0x0,0x7ff524c04180,12075448588620347,12075448588665738,12075448588990532,12075448589097193
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,876012,876017,32768,256,0,0,24,24,12480,0x0,0x7ff524c35100,12075448603446801,12075448603567040,12075448603573600,12075448603579378
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,876012,876017,4194304,256,0,0,24,24,12928,0x7ff6307be900,0x7ff524c35140,12075448603623450,12075448603638079,12075448603768636,12075448603772236
diff --git a/projects/rocprofiler-compute/tests/workloads/HBM/mi200/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/HBM/mi200/SQ_IFETCH_LEVEL.csv
index 63a18b364d..cf8edecc04 100644
--- a/projects/rocprofiler-compute/tests/workloads/HBM/mi200/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/HBM/mi200/SQ_IFETCH_LEVEL.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,169067,169067,33554432,256,0,0,4,32,4160,0x0,0x7fc9f1804280,381054,381054,524288,4718592,685018,76662440,16686012409410,16685335266624,16686159441316,16686159553545
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,169067,169067,32768,256,0,0,12,24,13888,0x0,0x7fc9f1823f80,33513,33513,512,8192,6059,684380,16686164716134,16686159441316,16686164845446,16686164850159
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,169067,169067,4194304,256,0,0,12,24,14336,0x7fc9f4757380,0x7fc9f1823fc0,163951,163951,65536,917504,140001,15721348,16686164888588,16686164845446,16686165220003,16686165222817
diff --git a/projects/rocprofiler-compute/tests/workloads/HBM/mi200/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/HBM/mi200/SQ_INST_LEVEL_LDS.csv
index 9bf72ba2df..7fe0d192d7 100644
--- a/projects/rocprofiler-compute/tests/workloads/HBM/mi200/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/HBM/mi200/SQ_INST_LEVEL_LDS.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,170915,170915,33554432,256,0,0,4,32,4160,0x0,0x7f1581204280,0,0,0,16705461014066,16704748417215,16705608304127,16705608417536
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,170915,170915,32768,256,0,0,12,24,13888,0x0,0x7f1581223f80,0,0,0,16705613583716,16705608304127,16705613726176,16705613730821
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,170915,170915,4194304,256,0,0,12,24,14336,0x7f1584138380,0x7f1581223fc0,0,0,0,16705613765250,16705613726176,16705614091454,16705614093829
diff --git a/projects/rocprofiler-compute/tests/workloads/HBM/mi200/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/HBM/mi200/SQ_INST_LEVEL_SMEM.csv
index 637666b86b..be02a3287c 100644
--- a/projects/rocprofiler-compute/tests/workloads/HBM/mi200/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/HBM/mi200/SQ_INST_LEVEL_SMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,168845,168845,33554432,256,0,0,4,32,4160,0x0,0x7f758e804280,3670016,3090688,345969424,16685107292208,16679519771609,16685255521913,16685255636172
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,168845,168845,32768,256,0,0,12,24,13888,0x0,0x7f758e823f80,512,101656,11382912,16685260804240,16685255521913,16685260932125,16685260936516
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,168845,168845,4194304,256,0,0,12,24,14336,0x7f75917ec380,0x7f758e823fc0,65536,630202,70530368,16685260970545,16685260932125,16685261289563,16685261292034
diff --git a/projects/rocprofiler-compute/tests/workloads/HBM/mi200/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/HBM/mi200/SQ_INST_LEVEL_VMEM.csv
index d2124f3940..2ad96e6a83 100644
--- a/projects/rocprofiler-compute/tests/workloads/HBM/mi200/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/HBM/mi200/SQ_INST_LEVEL_VMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,170693,170693,33554432,256,0,0,4,32,4160,0x0,0x7fb8f4804280,524288,5478572,613543432,16704516970838,16702207675851,16704668110590,16704668215009
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,170693,170693,32768,256,0,0,12,24,13888,0x0,0x7fb8f4823f80,4096,51987,5829564,16704673421218,16704668110590,16704673546078,16704673550673
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,170693,170693,4194304,256,0,0,12,24,14336,0x7fb8f77b3380,0x7fb8f4823fc0,524288,10931927,1224463440,16704673584352,16704673546078,16704673911516,16704673913831
diff --git a/projects/rocprofiler-compute/tests/workloads/HBM/mi200/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/HBM/mi200/SQ_LEVEL_WAVES.csv
index 1e4c635eaa..364bafb7fb 100644
--- a/projects/rocprofiler-compute/tests/workloads/HBM/mi200/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/HBM/mi200/SQ_LEVEL_WAVES.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,169289,169289,33554432,256,0,0,4,32,4160,0x0,0x7f7d6aa04280,382373,382373,8918,3058992,524288,240391152,2971330,0,977786824,16686960387064,16686241961667,16687103578451,16687103695890
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,169289,169289,32768,256,0,0,12,24,13888,0x0,0x7f7d6aa23f80,33366,33366,29567,266936,512,1716066,160391,0,6877764,16687108874628,16687103578451,16687109011860,16687109016713
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,169289,169289,4194304,256,0,0,12,24,14336,0x7f7d6d9be380,0x7f7d6aa23fc0,164555,164555,13735,1316448,65536,78639125,1206963,0,316289224,16687109061442,16687109011860,16687109404658,16687109407430
diff --git a/projects/rocprofiler-compute/tests/workloads/HBM/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/HBM/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/HBM/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/HBM/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/HBM/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/HBM/mi200/pmc_perf.csv
index d3e93bd64c..240e0e9231 100644
--- a/projects/rocprofiler-compute/tests/workloads/HBM/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/HBM/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDI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],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBufferAligned.kd,0,0,0,170055,170055,33554432,256,0,0,4,32,4160,0x0,0x7f7283404280,3068336,2976868,524288,38673267,241600941,392,224,0,383541,383541,38940088.0,38006674.0,9.0,4142963.0,31149436.0,30783385.0,37985973.0,37426652.0,3066625,2983271,383541,0,383541,0,12273312.0,9448924.0,0.0,0.0,0,0,616,0,4718592,4714125,112,4355,376378,0.0,0.0,0.0,524288.0,28557660.0,27838563.0,7875.0,524288.0,131072,524288,302,385547,2276,0,56.0,300.0,0.0,4194696.0,0,0,0,0,0,7340032,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,20197307.0,524288.0,0,385740,0,0,0,385740,0,0,0,385740,0,0,0,385740,0,0,0,385740,0,0,0,385740,0,0,0,385740,0,0,0,385740,0,0,0,385740,0,0,0,385740,0,0,0,385740,0,0,0,385740,0,0,0,385740,0,0,0,385740,0,0,0,385740,0,0,0,385740,0,0,0,385740,0,0,0,385740,0,0,0,385740,0,0,0,385740,0,0,0,385740,0,0,0,385740,0,0,0,385740,0,0,0,385740,0,0,0,385740,0,0,0,385740,0,0,0,385740,0,0,0,385740,0,0,0,385740,0,0,0,385740,0,0,0,385740,0,0,0,385740,0,0,0,0,0,0.0,20763424.0,32,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,58,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,35,0,0,0,0,0,0,0,0,0,0,0,3,0,0,0,116,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,524288.0,0.0,0,552609,129024,129024,0,0,129024,129024,0,0,129024,129024,0,207,129024,129024,0,328,129024,129024,0,169,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,43575,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,28121,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,1955,129024,129024,0,0,129024,129024,0,0,129024,129024,0,166,129024,129024,0,0,129024,129024,0,45693,129024,129024,0,0,129024,129024,0,280530,129024,129024,0,0,129024,129024,0,185,129024,129024,524288.0,0.0,44593,0,0,50614095,44511,0,0,50418647,43849,0,0,50012581,46911,0,0,51996480,45266,0,0,51368435,44916,0,0,51149917,44843,0,0,50899651,48780,0,0,53088832,44722,0,0,50854147,46246,0,0,50951019,44069,0,0,50013540,47110,0,0,52164500,44496,0,0,51108994,47377,0,0,51797971,43698,0,0,50838236,48844,0,0,53140073,43410,0,0,50397603,46259,0,0,50904943,44482,0,0,50336056,46549,0,0,51851527,44692,0,0,51326429,45879,0,0,51320758,44264,0,0,50705979,48385,0,0,53176013,45333,0,0,50971604,45815,0,0,51118047,45701,0,0,50612930,47510,0,0,52178851,45380,0,0,51305319,46543,0,0,51531239,46094,0,0,51197438,48683,0,0,52983536,0.0,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65568,32,131104,65646,65538,112,131184,65536,65537,1,131073,65536,65536,0,131072,65536,65592,56,131128,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65568,32,131104,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65591,65537,56,131128,65536,65536,0,131072,65536,65537,1,131073,65536,65571,35,131107,65758,65538,224,131296,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65538,2,131074,65536,65648,112,131184,65536,65536,0,131072,65536,65568,32,131104,65591,65537,56,131128,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131184,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131296,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131128,0,131072,1089700,0,524288,3670016,3663273,224,6519,1048576,33554432.0,33554432.0,0.0,33554432.0,30169183.0,28508657.0,0.0,524288.0,217059,537553,8552,890,0,382629,4195055.0,0.0,2097594.0,2097461.0,1048576,1048576,0,524288,0,524288,7340032,0,0.0,0.0,104.0,8388608.0,29544977.0,2097152.0,0.0,203556,0,1221,383423,0,750.0,4194304.0,0.0,2064387.0,25690112,9437184,0,0,0,0,0,0,13289.0,8242429.0,0.0,8388608.0,2097152.0,4194304.0,9533840,0,0,8994,4128768.0,4128768.0,0.0,1474752.0,0,0,0,0,0,0,5767168,1048576,316317072.0,0.0,1474331106.0,0.0,49.0,0.0,0,0,373996,0.0,0.0,1494957.0,0.0,3670016,524288,0,0,0,2621440,524288,176854853,4194304.0,0.0,0.0,0.0,0.0,1223401.0,0,0,0.0,311.0,0.0,606.0,42985634,24117248,0,0,9437184,11010048,0,3145728,0.0,0.0,0.0,0.0,0.0,0.0,0,1572864,0.0,0.0,0.0,191617.0,524288,524288,0,3670016,7340032,603979776,4718592,0,0.0,0.0,0.0,0.0,0.0,0.0,524288,0,2064384.0,0.0,2031624.0,0.0,0,0,524288,0,0,0,0,33554432,0.0,4194304.0,0.0,19070154.0,0.0,0.0,145.0,4128768.0,651053.0,1661796359.0,16688397479429,16706281370699,16706281613098,16688546475481
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,170055,170055,32768,256,0,0,12,24,13888,0x0,0x7f7283423f80,271552,164727,512,1404244,1719890,504,56,0,33943,33943,2376020.0,172514.0,177.0,0.0,37546.0,34095.0,166220.0,147418.0,271544,171976,33943,0,33943,0,1086176.0,383913.0,0.0,0.0,0,0,560,0,8192,6151,56,1985,24019,0.0,0.0,0.0,4096.0,29170.0,27695.0,0.0,4096.0,128,512,302,34034,2280,0,0.0,60.0,0.0,4600.0,0,0,0,0,0,1024,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,11834.0,4096.0,0,33650,0,0,0,33650,0,0,0,33650,0,0,0,33650,0,0,0,33650,0,0,0,33650,0,0,0,33650,0,0,0,33650,0,0,0,33650,0,0,0,33650,0,0,0,33650,0,0,0,33650,0,0,0,33650,0,0,0,33650,0,0,0,33650,0,0,0,33650,0,0,0,33650,0,0,0,33650,0,0,0,33650,0,0,0,33650,0,0,0,33650,0,0,0,33650,0,0,0,33650,0,0,0,33650,0,0,0,33650,0,0,0,33650,0,0,0,33650,0,0,0,33650,0,0,0,33650,0,0,0,33650,0,0,0,33650,0,0,0,33650,0,0,0,0,0,0.0,0.0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,312,0,0,0,258,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,4096.0,4096.0,0,666964,0,0,0,79385,0,0,0,80682,0,0,0,88200,0,0,0,89265,0,0,0,79665,0,0,0,85695,0,0,0,97148,0,0,0,89087,0,0,0,86866,0,0,0,75460,0,0,0,135471,0,0,0,85712,0,0,0,90994,0,0,0,76472,0,0,0,81018,0,0,0,82713,0,0,0,86376,0,0,0,76395,0,0,0,89016,0,0,0,80440,0,0,0,87385,0,0,0,90875,0,0,0,95308,0,0,0,86510,0,0,0,77766,0,0,0,72516,0,0,0,82089,0,0,0,78935,0,0,0,80170,0,0,0,123354,0,0,0,94066,0,0,0.0,0.0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4096.0,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,222,131,353,353,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,222,130,352,352,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,129,129,129,0,129,129,129,0,128,128,128,55,129,184,184,0,128,128,128,0,128,128,128,0,128,128,128,0,129,129,129,0,184,184,184,0,128,128,128,0,128,128,128,0,128,128,128,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,352,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,352,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,184,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,672,0,0,512,0,56,456,0,65536.0,65536.0,65536.0,0.0,0.0,0.0,0.0,0.0,6,518,11357,1052,0,30937,4660.0,0.0,499.0,4161.0,512,0,0,0,4096,4096,512,0,0.0,0.0,104.0,16384.0,0.0,16384.0,4096.0,0,0,1444,31764,0,4661.0,0.0,0.0,31.0,35328,26112,0,0,0,0,0,0,104.0,15240.0,0.0,16384.0,16384.0,0.0,0,0,0,29546,0.0,0.0,0.0,0.0,0,0,0,0,0,0,10752,3584,4011276.0,5423177.0,0.0,8192.0,2.0,0.0,0,0,497,0.0,0.0,0.0,0.0,512,4096,0,0,0,512,512,1701319,0.0,0.0,0.0,0.0,0.0,1565.0,0,0,0.0,8261.0,0.0,120.0,13059,32256,0,0,26112,1024,0,1024,0.0,0.0,0.0,0.0,0.0,0.0,0,1024,0.0,0.0,0.0,50556.0,4096,0,4096,512,512,1671168,8192,0,0.0,0.0,0.0,0.0,0.0,0.0,512,0,0.0,0.0,0.0,0.0,0,0,512,0,0,0,0,32768,8192.0,0.0,0.0,123259.0,0.0,4096.0,8207.0,0.0,3365487.0,0.0,16688552701415,16706286446350,16706286459150,16688553183629
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,170055,170055,4194304,256,0,0,12,24,14336,0x7f7286370380,0x7f7283423fc0,1317272,1208422,65536,15631800,80527951,392,56,0,164658,164658,15940574.0,14529293.0,25012.0,750939.0,13859477.0,13647060.0,14522996.0,12387508.0,1317264,1215242,164658,0,164658,0,5269056.0,4734872.0,0.0,0.0,0,0,448,0,917504,913924,0,3580,152483,0.0,0.0,0.0,524288.0,13823855.0,13814164.0,2303.0,524288.0,16384,65536,302,162929,2292,0,0.0,178.0,0.0,1048968.0,0,0,0,0,0,131072,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,10954277.0,524288.0,0,163673,0,0,0,163673,0,0,0,163673,0,0,0,163673,0,0,0,163673,0,0,0,163673,0,0,0,163673,0,0,0,163673,0,0,0,163673,0,0,0,163673,0,0,0,163673,0,0,0,163673,0,0,0,163673,0,0,0,163673,0,0,0,163673,0,0,0,163673,0,0,0,163673,0,0,0,163673,0,0,0,163673,0,0,0,163673,0,0,0,163673,0,0,0,163673,0,0,0,163673,0,0,0,163673,0,0,0,163673,0,0,0,163673,0,0,0,163673,0,0,0,163673,0,0,0,163673,0,0,0,163673,0,0,0,163673,0,0,0,163673,0,0,0,0,0,0.0,0.0,65536,0,22109,0,65538,0,10950,0,65536,0,11133,0,65536,0,6233,0,65536,0,35159,0,65536,0,18420,0,65536,0,31433,0,65536,0,34802,0,65536,0,4896,0,65536,0,4387,0,65536,0,4255,0,65536,0,26264,0,65536,0,8123,0,65536,0,23405,0,65536,0,29678,0,65536,0,19437,0,65536,0,10477,0,65537,0,7827,0,65597,0,4851,0,65536,0,12109,0,65536,0,7577,0,65537,0,7873,0,65592,0,39035,0,65540,0,11249,0,65540,0,5385,0,65536,0,7643,0,65536,0,11242,0,65597,0,4775,0,65537,0,9237,0,65536,0,23834,0,65536,0,22694,0,65536,0,13145,0,524288.0,524288.0,0,42030502,0,0,0,42947380,0,0,0,41209603,0,0,0,49190428,0,0,0,45300923,0,0,0,44020849,0,0,0,45750380,0,0,0,51302752,0,0,0,45643152,0,0,0,43740158,0,0,0,44913733,0,0,0,43435804,0,0,0,42807117,0,0,0,43888696,0,0,0,45039301,0,0,0,44470169,0,0,0,50209554,0,0,0,48220165,0,0,0,42636357,0,0,0,47585692,0,0,0,49125385,0,0,0,43848172,0,0,0,46555941,0,0,0,46211378,0,0,0,44543367,0,0,0,48449981,0,0,0,42308047,0,0,0,45740665,0,0,0,45457549,0,0,0,42593263,0,0,0,48111934,0,0,0,50453364,0,0,0.0,0.0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,524288.0,0,32769,32769,32769,0,32768,32768,32768,0,32769,32769,32769,0,32768,32768,32768,0,32768,32768,32768,0,32769,32769,32769,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32769,32769,32769,0,32769,32769,32769,0,32827,32827,32827,0,32768,32768,32768,166,32770,32936,32936,222,32770,32992,32992,0,32768,32768,32768,0,32768,32768,32768,0,32769,32769,32769,0,32824,32824,32824,0,32768,32768,32768,0,32833,32833,32833,0,32768,32768,32768,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32936,0,0,32992,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,1799478,0,0,65536,63800,56,1680,0,8388608.0,8388608.0,8388608.0,0.0,0.0,0.0,0.0,0.0,187175,192478,14510,4530,0,164717,1049137.0,0.0,388.0,1048749.0,65536,0,0,0,524288,524288,131072,0,0.0,0.0,104.0,2097152.0,0.0,2097152.0,524288.0,42096,0,2445,161601,0,1049156.0,0.0,0.0,31.0,4063232,2883584,0,0,0,0,0,0,6579.0,2026612.0,0.0,2097152.0,2097152.0,0.0,1539763,0,0,14861,0.0,0.0,0.0,0.0,262144,0,0,0,0,0,1507328,458752,983103508.0,2165032108.0,0.0,2097152.0,82.0,0.0,0,0,148361,0.0,0.0,0.0,0.0,65536,524288,0,0,0,65536,65536,49008772,0.0,0.0,0.0,0.0,0.0,19076.0,0,0,0.0,2097341.0,0.0,364.0,24138177,3735552,0,0,2883584,196608,0,131072,0.0,0.0,0.0,0.0,0.0,0.0,0,131072,0.0,0.0,437002.0,1307933.0,524288,0,524288,65536,131072,184549376,917504,0,0.0,0.0,0.0,0.0,0.0,0.0,65536,0,0.0,0.0,983046.0,0.0,0,0,65536,0,0,0,0,4194304,2097152.0,0.0,0.0,12320042.0,0.0,524288.0,2097289.0,0.0,1481815762.0,0.0,16688554281132,16706286530989,16706286622989,16688555069816
diff --git a/projects/rocprofiler-compute/tests/workloads/HBM/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/HBM/mi200/prev_analysis/1.csv
index 6a06c5c78b..e227b6d7c7 100644
--- a/projects/rocprofiler-compute/tests/workloads/HBM/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/HBM/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,3357261.0,3357261.0,3357261.0,7.845784663999137
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,1724470.0,1724470.0,1724470.0,4.030017409884603
 "void benchmark_func<double, 256, 8u, 512u>(double, double*) [clone .kd]",1,1715511.0,1715511.0,1715511.0,4.009080585251436
diff --git a/projects/rocprofiler-compute/tests/workloads/HBM/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/HBM/mi200/prev_analysis/1001.csv
index f475f954a6..fb5988001a 100644
--- a/projects/rocprofiler-compute/tests/workloads/HBM/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/HBM/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,494.8622754491018,Instr per wave
 VMEM,7.958083832335329,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,0.0,Instr per wave
 SALU,24.520958083832337,Instr per wave
 SMEM,1.8023952095808384,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/HBM/mi200/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/HBM/mi200/prev_analysis/101.csv
index ccdc6e1d52..271b9bd932 100644
--- a/projects/rocprofiler-compute/tests/workloads/HBM/mi200/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/HBM/mi200/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx90a
 mi200
 56
 1638.4
-roofline|SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+roofline|SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/HBM/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/HBM/mi200/prev_analysis/1202.csv
index 3ef8873ce9..82a4a01308 100644
--- a/projects/rocprofiler-compute/tests/workloads/HBM/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/HBM/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,18505.33489830337,1843.268898010254,257704.96313476562,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/HBM/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/HBM/mi200/prev_analysis/1901.csv
index c162d1fd27..e28db4bd60 100644
--- a/projects/rocprofiler-compute/tests/workloads/HBM/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/HBM/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,2.0,smem_
 VALU,495.0,valu_
 MFMA,0.0,mfma_
 VMEM,8.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,10.0,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,67894.0,wavefronts_
 Workgroups,16973.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,128.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,0.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,44.0,hbm_rd_
 HBM Wr,0.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,70.0,vl1_coales_
 VL1 Stall,2.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,25.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/HBM/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/HBM/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/HBM/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/HBM/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/HBM/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/HBM/mi200/prev_analysis/201.csv
index 4ab444c408..ea2b5a9323 100644
--- a/projects/rocprofiler-compute/tests/workloads/HBM/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/HBM/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,58.30022836080683,Pct,100,58.30022836080683
 MFMA Util,0.0,Pct,100,0.0
 VALU Active Threads/Wave,64.0,Threads,64,100.0
 IPC - Issue,1.0,Instr/cycle,5,20.0
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99255541043459,Pct,100,99.99255541043459
 Instr Cache BW,1674.8886397454837,Gb/s,6092.8,27.48963760086469
 Scalar L1D Cache Hit Rate,99.34855886023404,Pct,100,99.34855886023404
diff --git a/projects/rocprofiler-compute/tests/workloads/HBM/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/HBM/mi200/prev_analysis/602.csv
index b660761141..098fcf31ef 100644
--- a/projects/rocprofiler-compute/tests/workloads/HBM/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/HBM/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,13027053.191616766,0,370999890,Simd
 Insufficient SIMD VGPRs,0.0,0,0,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/HBM/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/HBM/mi200/prev_analysis/701.csv
index 12250d77c0..db0925a109 100644
--- a/projects/rocprofiler-compute/tests/workloads/HBM/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/HBM/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/HBM/mi200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/HBM/mi200/sysinfo.csv
index a4a12b9a92..07332443ea 100644
--- a/projects/rocprofiler-compute/tests/workloads/HBM/mi200/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/HBM/mi200/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-HBM,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:31:25 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,roofline|SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+HBM,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:31:25 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,roofline|SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/HBM/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/HBM/mi200/timestamps.csv
index 8c600e832b..35fd2d9cfa 100644
--- a/projects/rocprofiler-compute/tests/workloads/HBM/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/HBM/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,170998,170998,33554432,256,0,0,4,32,4160,0x0,0x7ff430404280,16706281344389,16706281370699,16706281613098,16706281723087
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,170998,170998,32768,256,0,0,12,24,13888,0x0,0x7ff430423f80,16706286431293,16706286446350,16706286459150,16706286476871
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,170998,170998,4194304,256,0,0,12,24,14336,0x7ff43341d380,0x7ff430423fc0,16706286480211,16706286530989,16706286622989,16706286625156
diff --git a/projects/rocprofiler-compute/tests/workloads/K_int_inv1/mi100/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/K_int_inv1/mi100/SQ_IFETCH_LEVEL.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_int_inv1/mi100/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_int_inv1/mi100/SQ_IFETCH_LEVEL.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/K_int_inv1/mi100/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/K_int_inv1/mi100/SQ_INST_LEVEL_LDS.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_int_inv1/mi100/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_int_inv1/mi100/SQ_INST_LEVEL_LDS.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/K_int_inv1/mi100/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/K_int_inv1/mi100/SQ_INST_LEVEL_SMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_int_inv1/mi100/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_int_inv1/mi100/SQ_INST_LEVEL_SMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/K_int_inv1/mi100/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/K_int_inv1/mi100/SQ_INST_LEVEL_VMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_int_inv1/mi100/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_int_inv1/mi100/SQ_INST_LEVEL_VMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/K_int_inv1/mi100/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/K_int_inv1/mi100/SQ_LEVEL_WAVES.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_int_inv1/mi100/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_int_inv1/mi100/SQ_LEVEL_WAVES.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/K_int_inv1/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/K_int_inv1/mi100/pmc_perf.csv
index 7ce95d8af6..f105f6fca7 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_int_inv1/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_int_inv1/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,BeginNs,EndNs
+Dispatch_ID,Kernel_Name,Start_Timestamp,End_Timestamp
 ,,12073812903928197,12073812904253634
 ,,12073812919377104,12073812919384144
 ,,12073812919446544,12073812919580302
diff --git a/projects/rocprofiler-compute/tests/workloads/K_int_inv1/mi100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/K_int_inv1/mi100/sysinfo.csv
index 3d15fb1e83..ce0e4ea9ed 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_int_inv1/mi100/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_int_inv1/mi100/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-K_int_inv1,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 10:49:19 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+K_int_inv1,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 10:49:19 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/K_int_inv1/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/K_int_inv1/mi100/timestamps.csv
index 7cd55596f6..ce364d9dba 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_int_inv1/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_int_inv1/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,785581,785586,33554432,256,0,0,8,32,6464,0x0,0x7f9e50404180,12073812903887663,12073812903928197,12073812904253634,12073812904368346
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,785581,785586,32768,256,0,0,24,24,12480,0x0,0x7f9e50435100,12073812919274588,12073812919377104,12073812919384144,12073812919389572
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,785581,785586,4194304,256,0,0,24,24,12928,0x7f9f5c0e3900,0x7f9e50435140,12073812919433553,12073812919446544,12073812919580302,12073812919583672
diff --git a/projects/rocprofiler-compute/tests/workloads/K_int_inv1/mi200/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/K_int_inv1/mi200/SQ_IFETCH_LEVEL.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_int_inv1/mi200/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_int_inv1/mi200/SQ_IFETCH_LEVEL.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/K_int_inv1/mi200/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/K_int_inv1/mi200/SQ_INST_LEVEL_LDS.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_int_inv1/mi200/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_int_inv1/mi200/SQ_INST_LEVEL_LDS.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/K_int_inv1/mi200/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/K_int_inv1/mi200/SQ_INST_LEVEL_SMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_int_inv1/mi200/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_int_inv1/mi200/SQ_INST_LEVEL_SMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/K_int_inv1/mi200/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/K_int_inv1/mi200/SQ_INST_LEVEL_VMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_int_inv1/mi200/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_int_inv1/mi200/SQ_INST_LEVEL_VMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/K_int_inv1/mi200/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/K_int_inv1/mi200/SQ_LEVEL_WAVES.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_int_inv1/mi200/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_int_inv1/mi200/SQ_LEVEL_WAVES.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/K_int_inv1/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/K_int_inv1/mi200/pmc_perf.csv
index b648ae0624..6ac51fb7f6 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_int_inv1/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_int_inv1/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,BeginNs,EndNs
+Dispatch_ID,Kernel_Name,Start_Timestamp,End_Timestamp
 ,,14621776217873,14621776456753
 ,,14621781211476,14621781224916
 ,,14621781290356,14621781382836
diff --git a/projects/rocprofiler-compute/tests/workloads/K_int_inv1/mi200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/K_int_inv1/mi200/sysinfo.csv
index a146c51f23..d0e9791f7b 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_int_inv1/mi200/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_int_inv1/mi200/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-K_int_inv1,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 19:56:41 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,roofline|SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+K_int_inv1,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 19:56:41 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,roofline|SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/K_int_inv1/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/K_int_inv1/mi200/timestamps.csv
index 35c1b857da..57facd7ab9 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_int_inv1/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_int_inv1/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,56235,56235,33554432,256,0,0,4,32,4160,0x0,0x7f0cf9a04280,14621776193423,14621776217873,14621776456753,14621776568043
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,56235,56235,32768,256,0,0,12,24,13888,0x0,0x7f0cf9a23f80,14621781195879,14621781211476,14621781224916,14621781242028
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,56235,56235,4194304,256,0,0,12,24,14336,0x7f0cfca9a380,0x7f0cf9a23fc0,14621781247758,14621781290356,14621781382836,14621781384964
diff --git a/projects/rocprofiler-compute/tests/workloads/K_int_inv2/mi100/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/K_int_inv2/mi100/SQ_IFETCH_LEVEL.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_int_inv2/mi100/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_int_inv2/mi100/SQ_IFETCH_LEVEL.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/K_int_inv2/mi100/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/K_int_inv2/mi100/SQ_INST_LEVEL_LDS.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_int_inv2/mi100/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_int_inv2/mi100/SQ_INST_LEVEL_LDS.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/K_int_inv2/mi100/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/K_int_inv2/mi100/SQ_INST_LEVEL_SMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_int_inv2/mi100/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_int_inv2/mi100/SQ_INST_LEVEL_SMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/K_int_inv2/mi100/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/K_int_inv2/mi100/SQ_INST_LEVEL_VMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_int_inv2/mi100/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_int_inv2/mi100/SQ_INST_LEVEL_VMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/K_int_inv2/mi100/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/K_int_inv2/mi100/SQ_LEVEL_WAVES.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_int_inv2/mi100/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_int_inv2/mi100/SQ_LEVEL_WAVES.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/K_int_inv2/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/K_int_inv2/mi100/pmc_perf.csv
index aba4588104..70776bdc31 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_int_inv2/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_int_inv2/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,BeginNs,EndNs
+Dispatch_ID,Kernel_Name,Start_Timestamp,End_Timestamp
 ,,12073880436547597,12073880436871114
 ,,12073880451692626,12073880451699186
 ,,12073880451758225,12073880451892304
diff --git a/projects/rocprofiler-compute/tests/workloads/K_int_inv2/mi100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/K_int_inv2/mi100/sysinfo.csv
index 2d4e72fa10..7ef31bb7a1 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_int_inv2/mi100/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_int_inv2/mi100/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-K_int_inv2,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 10:50:26 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+K_int_inv2,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 10:50:26 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/K_int_inv2/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/K_int_inv2/mi100/timestamps.csv
index d6b12134b0..c848a38285 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_int_inv2/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_int_inv2/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,790597,790602,33554432,256,0,0,8,32,6464,0x0,0x7f60ee004180,12073880436501963,12073880436547597,12073880436871114,12073880436977586
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,790597,790602,32768,256,0,0,24,24,12480,0x0,0x7f60ee035100,12073880451590914,12073880451692626,12073880451699186,12073880451704575
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,790597,790602,4194304,256,0,0,24,24,12928,0x7f61f9bc9900,0x7f60ee035140,12073880451745270,12073880451758225,12073880451892304,12073880451895439
diff --git a/projects/rocprofiler-compute/tests/workloads/K_int_inv2/mi200/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/K_int_inv2/mi200/SQ_IFETCH_LEVEL.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_int_inv2/mi200/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_int_inv2/mi200/SQ_IFETCH_LEVEL.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/K_int_inv2/mi200/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/K_int_inv2/mi200/SQ_INST_LEVEL_LDS.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_int_inv2/mi200/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_int_inv2/mi200/SQ_INST_LEVEL_LDS.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/K_int_inv2/mi200/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/K_int_inv2/mi200/SQ_INST_LEVEL_SMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_int_inv2/mi200/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_int_inv2/mi200/SQ_INST_LEVEL_SMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/K_int_inv2/mi200/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/K_int_inv2/mi200/SQ_INST_LEVEL_VMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_int_inv2/mi200/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_int_inv2/mi200/SQ_INST_LEVEL_VMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/K_int_inv2/mi200/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/K_int_inv2/mi200/SQ_LEVEL_WAVES.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_int_inv2/mi200/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_int_inv2/mi200/SQ_LEVEL_WAVES.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/K_int_inv2/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/K_int_inv2/mi200/pmc_perf.csv
index cc6a21c19a..e788ad723c 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_int_inv2/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_int_inv2/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,BeginNs,EndNs
+Dispatch_ID,Kernel_Name,Start_Timestamp,End_Timestamp
 ,,14711872611205,14711872849605
 ,,14711877642252,14711877655692
 ,,14711877726572,14711877819372
diff --git a/projects/rocprofiler-compute/tests/workloads/K_int_inv2/mi200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/K_int_inv2/mi200/sysinfo.csv
index 48d85d3c60..a9eac5e7b5 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_int_inv2/mi200/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_int_inv2/mi200/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-K_int_inv2,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 19:58:11 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,roofline|SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+K_int_inv2,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 19:58:11 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,roofline|SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/K_int_inv2/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/K_int_inv2/mi200/timestamps.csv
index 0be3a28f80..d699181faf 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_int_inv2/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_int_inv2/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,62337,62337,33554432,256,0,0,4,32,4160,0x0,0x7f3277004280,14711872586034,14711872611205,14711872849605,14711872938945
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,62337,62337,32768,256,0,0,12,24,13888,0x0,0x7f3277023f80,14711877626503,14711877642252,14711877655692,14711877675622
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,62337,62337,4194304,256,0,0,12,24,14336,0x7f3279f96380,0x7f3277023fc0,14711877678932,14711877726572,14711877819372,14711877821588
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_inv1/mi100/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/K_str_inv1/mi100/SQ_IFETCH_LEVEL.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_inv1/mi100/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_inv1/mi100/SQ_IFETCH_LEVEL.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_inv1/mi100/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/K_str_inv1/mi100/SQ_INST_LEVEL_LDS.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_inv1/mi100/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_inv1/mi100/SQ_INST_LEVEL_LDS.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_inv1/mi100/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/K_str_inv1/mi100/SQ_INST_LEVEL_SMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_inv1/mi100/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_inv1/mi100/SQ_INST_LEVEL_SMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_inv1/mi100/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/K_str_inv1/mi100/SQ_INST_LEVEL_VMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_inv1/mi100/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_inv1/mi100/SQ_INST_LEVEL_VMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_inv1/mi100/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/K_str_inv1/mi100/SQ_LEVEL_WAVES.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_inv1/mi100/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_inv1/mi100/SQ_LEVEL_WAVES.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_inv1/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/K_str_inv1/mi100/pmc_perf.csv
index 9b64da2760..b42465323e 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_inv1/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_inv1/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,BeginNs,EndNs
+Dispatch_ID,Kernel_Name,Start_Timestamp,End_Timestamp
 ,,12073948226771836,12073948227096953
 ,,12073948241890986,12073948241898026
 ,,12073948241958506,12073948242089384
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_inv1/mi100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/K_str_inv1/mi100/sysinfo.csv
index 3b42fa4184..240a90f7c7 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_inv1/mi100/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_inv1/mi100/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-K_str_inv1,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 10:51:34 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+K_str_inv1,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 10:51:34 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_inv1/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/K_str_inv1/mi100/timestamps.csv
index 71a7065106..8bf177ceef 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_inv1/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_inv1/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,795609,795614,33554432,256,0,0,8,32,6464,0x0,0x7f5121e04180,12073948226724206,12073948226771836,12073948227096953,12073948227202545
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,795609,795614,32768,256,0,0,24,24,12480,0x0,0x7f5121e35100,12073948241789042,12073948241890986,12073948241898026,12073948241903815
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,795609,795614,4194304,256,0,0,24,24,12928,0x7f522da65900,0x7f5121e35140,12073948241945142,12073948241958506,12073948242089384,12073948242093578
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_inv1/mi200/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/K_str_inv1/mi200/SQ_IFETCH_LEVEL.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_inv1/mi200/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_inv1/mi200/SQ_IFETCH_LEVEL.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_inv1/mi200/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/K_str_inv1/mi200/SQ_INST_LEVEL_LDS.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_inv1/mi200/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_inv1/mi200/SQ_INST_LEVEL_LDS.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_inv1/mi200/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/K_str_inv1/mi200/SQ_INST_LEVEL_SMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_inv1/mi200/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_inv1/mi200/SQ_INST_LEVEL_SMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_inv1/mi200/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/K_str_inv1/mi200/SQ_INST_LEVEL_VMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_inv1/mi200/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_inv1/mi200/SQ_INST_LEVEL_VMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_inv1/mi200/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/K_str_inv1/mi200/SQ_LEVEL_WAVES.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_inv1/mi200/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_inv1/mi200/SQ_LEVEL_WAVES.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_inv1/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/K_str_inv1/mi200/pmc_perf.csv
index 7f886805d0..a197e22569 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_inv1/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_inv1/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,BeginNs,EndNs
+Dispatch_ID,Kernel_Name,Start_Timestamp,End_Timestamp
 ,,14801188147077,14801188386437
 ,,14801193191567,14801193205007
 ,,14801193270447,14801193362447
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_inv1/mi200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/K_str_inv1/mi200/sysinfo.csv
index bb520ea54b..af036de1d9 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_inv1/mi200/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_inv1/mi200/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-K_str_inv1,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 19:59:40 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,roofline|SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+K_str_inv1,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 19:59:40 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,roofline|SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_inv1/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/K_str_inv1/mi200/timestamps.csv
index 2054c3d39f..e7c4227cb4 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_inv1/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_inv1/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,68439,68439,33554432,256,0,0,4,32,4160,0x0,0x7fb15d804280,14801188122396,14801188147077,14801188386437,14801188495867
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,68439,68439,32768,256,0,0,12,24,13888,0x0,0x7fb15d823f80,14801193175938,14801193191567,14801193205007,14801193222127
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,68439,68439,4194304,256,0,0,12,24,14336,0x7fb160719380,0x7fb15d823fc0,14801193227877,14801193270447,14801193362447,14801193364414
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_inv2/mi100/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/K_str_inv2/mi100/SQ_IFETCH_LEVEL.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_inv2/mi100/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_inv2/mi100/SQ_IFETCH_LEVEL.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_inv2/mi100/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/K_str_inv2/mi100/SQ_INST_LEVEL_LDS.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_inv2/mi100/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_inv2/mi100/SQ_INST_LEVEL_LDS.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_inv2/mi100/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/K_str_inv2/mi100/SQ_INST_LEVEL_SMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_inv2/mi100/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_inv2/mi100/SQ_INST_LEVEL_SMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_inv2/mi100/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/K_str_inv2/mi100/SQ_INST_LEVEL_VMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_inv2/mi100/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_inv2/mi100/SQ_INST_LEVEL_VMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_inv2/mi100/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/K_str_inv2/mi100/SQ_LEVEL_WAVES.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_inv2/mi100/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_inv2/mi100/SQ_LEVEL_WAVES.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_inv2/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/K_str_inv2/mi100/pmc_perf.csv
index 22e64e0fc0..5da49c6fde 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_inv2/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_inv2/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,BeginNs,EndNs
+Dispatch_ID,Kernel_Name,Start_Timestamp,End_Timestamp
 ,,12074016993092405,12074016993414962
 ,,12074017008227112,12074017008233672
 ,,12074017008296551,12074017008433190
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_inv2/mi100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/K_str_inv2/mi100/sysinfo.csv
index 3d35ceee99..abe8adba06 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_inv2/mi100/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_inv2/mi100/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-K_str_inv2,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 10:52:43 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+K_str_inv2,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 10:52:43 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_inv2/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/K_str_inv2/mi100/timestamps.csv
index 16b15fd68f..07930db70b 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_inv2/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_inv2/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,800616,800621,33554432,256,0,0,8,32,6464,0x0,0x7f1fb8204180,12074016993044640,12074016993092405,12074016993414962,12074016993520945
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,800616,800621,32768,256,0,0,24,24,12480,0x0,0x7f1fb8235100,12074017008127085,12074017008227112,12074017008233672,12074017008239253
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,800616,800621,4194304,256,0,0,24,24,12928,0x7f20c3d9b900,0x7f1fb8235140,12074017008283044,12074017008296551,12074017008433190,12074017008436610
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_inv2/mi200/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/K_str_inv2/mi200/SQ_IFETCH_LEVEL.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_inv2/mi200/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_inv2/mi200/SQ_IFETCH_LEVEL.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_inv2/mi200/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/K_str_inv2/mi200/SQ_INST_LEVEL_LDS.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_inv2/mi200/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_inv2/mi200/SQ_INST_LEVEL_LDS.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_inv2/mi200/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/K_str_inv2/mi200/SQ_INST_LEVEL_SMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_inv2/mi200/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_inv2/mi200/SQ_INST_LEVEL_SMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_inv2/mi200/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/K_str_inv2/mi200/SQ_INST_LEVEL_VMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_inv2/mi200/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_inv2/mi200/SQ_INST_LEVEL_VMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_inv2/mi200/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/K_str_inv2/mi200/SQ_LEVEL_WAVES.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_inv2/mi200/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_inv2/mi200/SQ_LEVEL_WAVES.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_inv2/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/K_str_inv2/mi200/pmc_perf.csv
index beb4283bdd..09a13a2a42 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_inv2/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_inv2/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,BeginNs,EndNs
+Dispatch_ID,Kernel_Name,Start_Timestamp,End_Timestamp
 ,,14890891808310,14890892046870
 ,,14890896841118,14890896854238
 ,,14890896924798,14890897017118
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_inv2/mi200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/K_str_inv2/mi200/sysinfo.csv
index cf83862361..4b254d45d2 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_inv2/mi200/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_inv2/mi200/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-K_str_inv2,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:01:10 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,roofline|SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+K_str_inv2,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:01:10 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,roofline|SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_inv2/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/K_str_inv2/mi200/timestamps.csv
index 0a38702936..475dd1171a 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_inv2/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_inv2/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,74541,74541,33554432,256,0,0,4,32,4160,0x0,0x7f159c204280,14890891781810,14890891808310,14890892046870,14890892157240
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,74541,74541,32768,256,0,0,12,24,13888,0x0,0x7f159c223f80,14890896825434,14890896841118,14890896854238,14890896872383
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,74541,74541,4194304,256,0,0,12,24,14336,0x7f15baa51380,0x7f159c223fc0,14890896876933,14890896924798,14890897017118,14890897019270
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_inv3/mi100/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/K_str_inv3/mi100/SQ_IFETCH_LEVEL.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_inv3/mi100/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_inv3/mi100/SQ_IFETCH_LEVEL.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_inv3/mi100/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/K_str_inv3/mi100/SQ_INST_LEVEL_LDS.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_inv3/mi100/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_inv3/mi100/SQ_INST_LEVEL_LDS.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_inv3/mi100/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/K_str_inv3/mi100/SQ_INST_LEVEL_SMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_inv3/mi100/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_inv3/mi100/SQ_INST_LEVEL_SMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_inv3/mi100/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/K_str_inv3/mi100/SQ_INST_LEVEL_VMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_inv3/mi100/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_inv3/mi100/SQ_INST_LEVEL_VMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_inv3/mi100/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/K_str_inv3/mi100/SQ_LEVEL_WAVES.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_inv3/mi100/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_inv3/mi100/SQ_LEVEL_WAVES.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_inv3/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/K_str_inv3/mi100/pmc_perf.csv
index 7b6437356c..217addaaa1 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_inv3/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_inv3/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,BeginNs,EndNs
+Dispatch_ID,Kernel_Name,Start_Timestamp,End_Timestamp
 ,,12074086852546520,12074086852868916
 ,,12074086868085971,12074086868093171
 ,,12074086868158130,12074086868289009
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_inv3/mi100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/K_str_inv3/mi100/sysinfo.csv
index b51dd7087a..89a907de63 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_inv3/mi100/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_inv3/mi100/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-K_str_inv3,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 10:53:53 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+K_str_inv3,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 10:53:53 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_inv3/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/K_str_inv3/mi100/timestamps.csv
index ae2b7dee7a..d6b9f1367a 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_inv3/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_inv3/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,805626,805631,33554432,256,0,0,8,32,6464,0x0,0x7fb185e04180,12074086852499837,12074086852546520,12074086852868916,12074086852973757
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,805626,805631,32768,256,0,0,24,24,12480,0x0,0x7fb185e35100,12074086867987925,12074086868085971,12074086868093171,12074086868099052
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,805626,805631,4194304,256,0,0,24,24,12928,0x7fb291b5d900,0x7fb185e35140,12074086868143194,12074086868158130,12074086868289009,12074086868292682
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_inv3/mi200/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/K_str_inv3/mi200/SQ_IFETCH_LEVEL.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_inv3/mi200/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_inv3/mi200/SQ_IFETCH_LEVEL.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_inv3/mi200/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/K_str_inv3/mi200/SQ_INST_LEVEL_LDS.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_inv3/mi200/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_inv3/mi200/SQ_INST_LEVEL_LDS.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_inv3/mi200/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/K_str_inv3/mi200/SQ_INST_LEVEL_SMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_inv3/mi200/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_inv3/mi200/SQ_INST_LEVEL_SMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_inv3/mi200/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/K_str_inv3/mi200/SQ_INST_LEVEL_VMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_inv3/mi200/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_inv3/mi200/SQ_INST_LEVEL_VMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_inv3/mi200/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/K_str_inv3/mi200/SQ_LEVEL_WAVES.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_inv3/mi200/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_inv3/mi200/SQ_LEVEL_WAVES.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_inv3/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/K_str_inv3/mi200/pmc_perf.csv
index 2236d1be31..8f93af7107 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_inv3/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_inv3/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,BeginNs,EndNs
+Dispatch_ID,Kernel_Name,Start_Timestamp,End_Timestamp
 ,,14980298990601,14980299230601
 ,,14980304058133,14980304071573
 ,,14980304142934,14980304236214
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_inv3/mi200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/K_str_inv3/mi200/sysinfo.csv
index a0cb038bd3..cc4cc2aaff 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_inv3/mi200/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_inv3/mi200/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-K_str_inv3,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:02:39 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,roofline|SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+K_str_inv3,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:02:39 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,roofline|SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_inv3/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/K_str_inv3/mi200/timestamps.csv
index a8817466fd..c122704fee 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_inv3/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_inv3/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,80643,80643,33554432,256,0,0,4,32,4160,0x0,0x7ff682204280,14980298964549,14980298990601,14980299230601,14980299318021
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,80643,80643,32768,256,0,0,12,24,13888,0x0,0x7ff682223f80,14980304042106,14980304058133,14980304071573,14980304089435
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,80643,80643,4194304,256,0,0,12,24,14336,0x7ff685304380,0x7ff682223fc0,14980304094144,14980304142934,14980304236214,14980304238181
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi100/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi100/SQ_IFETCH_LEVEL.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi100/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi100/SQ_IFETCH_LEVEL.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi100/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi100/SQ_INST_LEVEL_LDS.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi100/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi100/SQ_INST_LEVEL_LDS.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi100/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi100/SQ_INST_LEVEL_SMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi100/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi100/SQ_INST_LEVEL_SMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi100/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi100/SQ_INST_LEVEL_VMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi100/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi100/SQ_INST_LEVEL_VMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi100/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi100/SQ_LEVEL_WAVES.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi100/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi100/SQ_LEVEL_WAVES.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi100/pmc_perf.csv
index 07ddbbf671..5aec7ba156 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,BeginNs,EndNs
+Dispatch_ID,Kernel_Name,Start_Timestamp,End_Timestamp
 ,,12073557258668628,12073557258992145
 ,,12073557273572174,12073557273578734
 ,,12073557273638893,12073557273772012
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi100/sysinfo.csv
index b1051ddc1c..29108eec27 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi100/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi100/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-K_str_valid_1,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 10:45:03 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+K_str_valid_1,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 10:45:03 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi100/timestamps.csv
index 536cd953cc..a89eb8dab3 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,770557,770562,33554432,256,0,0,8,32,6464,0x0,0x7f2efa604180,12073557258620671,12073557258668628,12073557258992145,12073557259092858
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,770557,770562,32768,256,0,0,24,24,12480,0x0,0x7f2efa635100,12073557273471860,12073557273572174,12073557273578734,12073557273584469
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,770557,770562,4194304,256,0,0,24,24,12928,0x7f30061b6900,0x7f2efa635140,12073557273625886,12073557273638893,12073557273772012,12073557273775264
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/SQ_IFETCH_LEVEL.csv
index 3ac261088e..cd26a85df3 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/SQ_IFETCH_LEVEL.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,41859,41859,33554432,256,0,0,4,32,4160,0x0,0x7fe0d0004280,380673,380673,524288,4718592,682181,76329868,14405520126644,14404780858501,14405667224915,14405667335964
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/SQ_INST_LEVEL_LDS.csv
index 971db238a3..7670dd417a 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/SQ_INST_LEVEL_LDS.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,43711,43711,33554432,256,0,0,4,32,4160,0x0,0x7f61dc204280,0,0,0,14419752469652,14419012796615,14419898550093,14419898640762
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/SQ_INST_LEVEL_SMEM.csv
index 387a78c8e1..ccd4010536 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/SQ_INST_LEVEL_SMEM.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,41636,41636,33554432,256,0,0,4,32,4160,0x0,0x7f7e61004280,3670016,3117498,348702672,14404632873185,14233495426789,14404780858547,14404780973016
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/SQ_INST_LEVEL_VMEM.csv
index 36b5220eb2..7ba3b96e23 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/SQ_INST_LEVEL_VMEM.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,43488,43488,33554432,256,0,0,4,32,4160,0x0,0x7f36f6c04280,524288,5312794,595017828,14418865425334,14417895695770,14419012796645,14419012909544
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/SQ_LEVEL_WAVES.csv
index 281e6c50ab..a786d6ffc4 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/SQ_LEVEL_WAVES.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,42082,42082,33554432,256,0,0,4,32,4160,0x0,0x7f3759e04280,382199,382199,8701,3057600,524288,240092938,2971463,0,976623656,14406407023127,14405667225040,14406554802589,14406554917128
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/pmc_dispatch_info.csv
index 8226fe9c0f..63bb17b9f9 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/pmc_dispatch_info.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/pmc_perf.csv
index 111003270d..8775a4b804 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/pmc_perf.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDI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],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBufferAligned.kd,0,0,0,42849,42849,33554432,256,0,0,4,32,4160,0x0,0x7fd8f6e04280,3080200,2988928,524288,38829583,242743275,392,224,0,385024,385024,39097427.0,38157261.0,0.0,4175482.0,31268672.0,30903499.0,38135939.0,37576376.0,3078489,2995325,385024,0,385024,0,12320768.0,9464941.0,0.0,0.0,0,0,616,0,4718592,4714712,112,3768,377498,0.0,0.0,0.0,524288.0,28724447.0,28006771.0,7824.0,524288.0,131072,524288,302,386591,2315,0,56.0,304.0,0.0,4194696.0,0,0,0,0,0,7340032,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,20117019.0,524288.0,0,383266,0,0,0,383266,0,0,0,383266,0,0,0,383266,0,0,0,383266,0,0,0,383266,0,0,0,383266,0,0,0,383266,0,0,0,383266,0,0,0,383266,0,0,0,383266,0,0,0,383266,0,0,0,383266,0,0,0,383266,0,0,0,383266,0,0,0,383266,0,0,0,383266,0,0,0,383266,0,0,0,383266,0,0,0,383266,0,0,0,383266,0,0,0,383266,0,0,0,383266,0,0,0,383266,0,0,0,383266,0,0,0,383266,0,0,0,383266,0,0,0,383266,0,0,0,383266,0,0,0,383266,0,0,0,383266,0,0,0,383266,0,0,0,0,0,0.0,21248722.0,112,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,2,0,0,0,0,0,0,0,35,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,88,0,0,0,32,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4,0,0,0,0,0,0,0,0,0,0,0,33,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,524288.0,0.0,0,44374,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,522,129024,129024,0,0,129024,129024,0,196004,129024,129024,0,0,129024,129024,0,0,129024,129024,0,44316,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,829,129024,129024,0,26845,129024,129024,0,0,129024,129024,0,278870,129024,129024,0,0,129024,129024,0,853,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,45417,129024,129024,0,438,129024,129024,0,0,129024,129024,0,0,129024,129024,0,185,129024,129024,524288.0,0.0,44446,0,0,50929410,45460,0,0,50908067,45817,0,0,50773632,49074,0,0,52885444,44734,0,0,51479285,47334,0,0,52193985,44911,0,0,51204267,48570,0,0,53288595,45754,0,0,51341866,45484,0,0,51132666,45275,0,0,50696372,48650,0,0,52750093,46956,0,0,52253119,47013,0,0,51938367,46806,0,0,51799141,47948,0,0,53262797,45369,0,0,51178166,46143,0,0,51319772,43407,0,0,50284453,47164,0,0,52287597,44174,0,0,51363259,45996,0,0,51702933,44560,0,0,51067322,49146,0,0,53476275,46342,0,0,51497761,46420,0,0,51399855,45865,0,0,51025771,47721,0,0,52525695,45500,0,0,51850296,47964,0,0,52246630,46961,0,0,51840223,49475,0,0,53530297,0.0,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65568,32,131104,65646,65539,113,131185,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65568,32,131104,65536,65536,0,131072,65536,65648,112,131184,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65537,1,131073,65536,65572,36,131108,65758,65538,224,131296,65536,65536,0,131072,65536,65536,0,131072,65591,65537,56,131128,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65569,33,131105,65591,65593,112,131184,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131184,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131296,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131128,0,131072,1089386,0,524288,3670016,3663237,224,6555,1048576,33554432.0,33554432.0,0.0,33554432.0,30259861.0,28605497.0,0.0,524288.0,219718,537229,8735,1125,0,384553,4195054.0,0.0,2097594.0,2097460.0,1048576,1048576,0,524288,0,524288,7340032,0,0.0,0.0,104.0,8388608.0,29778080.0,2097152.0,0.0,209255,0,1253,385026,0,754.0,4194304.0,0.0,2064387.0,25690112,9437184,0,0,0,0,0,0,13278.0,8242550.0,0.0,8388608.0,2097152.0,4194304.0,9999386,0,0,8918,4128768.0,4128768.0,0.0,1482823.0,0,0,0,0,0,0,5767168,1048576,315889990.0,0.0,1470359190.0,0.0,52.0,0.0,0,0,375309,0.0,0.0,1477107.0,0.0,3670016,524288,0,0,0,2621440,524288,177958802,4194304.0,0.0,0.0,0.0,0.0,1201898.0,0,0,0.0,312.0,0.0,608.0,42146473,24117248,0,0,9437184,11010048,0,3145728,0.0,0.0,0.0,0.0,0.0,0.0,0,1572864,0.0,0.0,0.0,192623.0,524288,524288,0,3670016,7340032,603979776,4718592,0,0.0,0.0,0.0,0.0,0.0,0.0,524288,0,2064384.0,0.0,2031624.0,0.0,0,0,524288,0,0,0,0,33554432,0.0,4194304.0,0.0,19136182.0,0.0,0.0,143.0,4128768.0,883461.0,1610991849.0,14407774170387,14420522207440,14420522448720,14407922784489
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/prev_analysis/1.csv
index 60cd9684b7..d4913ac06f 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/prev_analysis/1.csv
@@ -1,2 +1,2 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 __amd_rocclr_fillBufferAligned.kd,1,241280.0,241280.0,241280.0,100.0
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/prev_analysis/1001.csv
index e34ed0c6f6..0850fc4acd 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,18.0,Instr per wave
 VMEM,1.0,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,0.0,Instr per wave
 SALU,14.0,Instr per wave
 SMEM,7.0,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/prev_analysis/101.csv
index b6b938c266..aaf4299e59 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx90a
 mi200
 56
 1638.4
-roofline|SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+roofline|SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/prev_analysis/1202.csv
index ebd2a0008d..2756804183 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,1851.9842147827148,1851.9842147827148,1851.9842147827148,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/prev_analysis/1901.csv
index 96e1ca2d44..f2c208f5e1 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,7.0,smem_
 VALU,18.0,valu_
 MFMA,0.0,mfma_
 VMEM,1.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,5.0,br_
 VGPR,4.0,vgpr_
 SGPR,32.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,524288.0,wavefronts_
 Workgroups,131072.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,9.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,8.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,0.0,hbm_rd_
 HBM Wr,8.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,25.0,vl1_coales_
 VL1 Stall,11.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,25.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/prev_analysis/2001.csv
index 8226fe9c0f..63bb17b9f9 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/prev_analysis/2001.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/prev_analysis/201.csv
index cc19ea8f2c..b38eb8a3ce 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,23.567921440261866,Pct,100,23.567921440261866
 MFMA Util,0.0,Pct,100,0.0
 VALU Active Threads/Wave,64.0,Threads,64,100.0
 IPC - Issue,1.0,Instr/cycle,5,20.0
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99762451366159,Pct,100,99.99762451366159
 Instr Cache BW,1251.6159151193633,Gb/s,6092.8,20.542540623676526
 Scalar L1D Cache Hit Rate,99.99388556340575,Pct,100,99.99388556340575
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/prev_analysis/602.csv
index b69d9cb14b..8cdec4dee3 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,9999386.0,9999386,9999386,Simd
 Insufficient SIMD VGPRs,0.0,0,0,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/prev_analysis/701.csv
index c47e77a25f..f8ed8cd0d3 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,4.0,4,4,Registers
 SGPRs,32.0,32,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/sysinfo.csv
index bf1e749cb2..d1d682b5fd 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-K_str_valid_1,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 19:53:19 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,roofline|SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+K_str_valid_1,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 19:53:19 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,roofline|SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/timestamps.csv
index c317e65017..8c37f69611 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_1/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,43794,43794,33554432,256,0,0,4,32,4160,0x0,0x7f3320a04280,14420522182490,14420522207440,14420522448720,14420522556619
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,43794,43794,32768,256,0,0,12,24,13888,0x0,0x7f3320a23f80,14420527255202,14420527271272,14420527284392,14420527303331
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,43794,43794,4194304,256,0,0,12,24,14336,0x7f332391e380,0x7f3320a23fc0,14420527306921,14420527354952,14420527447432,14420527449366
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/SQ_IFETCH_LEVEL.csv
index 3ac8514f94..239de9439b 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/SQ_IFETCH_LEVEL.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,773513,773518,32768,256,0,0,24,24,12480,0x0,0x7f7749235100,27630,27630,512,8192,9241,1188528,12073606461789807,12073606707552916,12073606707559156,12073606707574148
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,773513,773518,4194304,256,0,0,24,24,12928,0x7f7854de7900,0x7f7749235140,217243,217243,65536,917504,147066,18811168,12073606707644800,12073606711021459,12073606711153778,12073606711157548
 3,"void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 0u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",0,0,6,773513,773518,4194304,256,0,0,36,24,13632,0x7f7854de7800,0x7f7749235180,390409,390409,65536,1245184,186718,24007636,12073606711229151,12073606711407217,12073606711656336,12073606711725463
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/SQ_INST_LEVEL_LDS.csv
index 72838e71f3..91bee0475e 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/SQ_INST_LEVEL_LDS.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,775323,775328,32768,256,0,0,24,24,12480,0x0,0x7f74ac635100,0,0,0,12073632858328367,12073633107538612,12073633107545012,12073633107560746
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,775323,775328,4194304,256,0,0,24,24,12928,0x7f75b830e900,0x7f74ac635140,0,0,0,12073633107631207,12073633111055357,12073633111192316,12073633111196482
 3,"void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 0u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",0,0,6,775323,775328,4194304,256,0,0,36,24,13632,0x7f75b830e800,0x7f74ac635180,0,0,0,12073633111264889,12073633111485435,12073633111739354,12073633111808840
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/SQ_INST_LEVEL_SMEM.csv
index 2efa357bfa..4162528cd6 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/SQ_INST_LEVEL_SMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,774943,774948,32768,256,0,0,24,24,12480,0x0,0x7ff7c0435100,512,24828,3181408,12073630322922362,12073630569272167,12073630569278567,12073630569295718
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,774943,774948,4194304,256,0,0,24,24,12928,0x7ff8cc146900,0x7ff7c0435140,65536,175568,22488608,12073630569351852,12073630572706750,12073630572845309,12073630572849302
 3,"void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 0u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",0,0,6,774943,774948,4194304,256,0,0,36,24,13632,0x7ff8cc146800,0x7ff7c0435180,65536,158198,20250872,12073630572917659,12073630573094908,12073630573347227,12073630573416636
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/SQ_INST_LEVEL_VMEM.csv
index 9ce517114c..5d6c8878c2 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/SQ_INST_LEVEL_VMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,775134,775139,32768,256,0,0,24,24,12480,0x0,0x7f9508235100,4096,102487,13112660,12073631591150656,12073631835948130,12073631835954210,12073631835974712
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,775134,775139,4194304,256,0,0,24,24,12928,0x7f9613571900,0x7f9508235140,524288,12212343,1563066804,12073631836032159,12073631839431837,12073631839565916,12073631839569132
 3,"void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 0u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",0,0,6,775134,775139,4194304,256,0,0,36,24,13632,0x7f9613571800,0x7f9508235180,524288,13767229,1762246408,12073631839627210,12073631839797276,12073631840047195,12073631840118663
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/SQ_LEVEL_WAVES.csv
index c725b6caec..a4a093e86f 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/SQ_LEVEL_WAVES.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,775513,775520,32768,256,0,0,24,24,12480,0x0,0x7f2b22835100,28648,28648,21090,229192,512,1130364,76722,0,4535476,12073634141284440,12073634385237417,12073634385243657,12073634385259098
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,775513,775520,4194304,256,0,0,24,24,12928,0x7f2c2e54d900,0x7f2b22835140,218484,218484,19998,1747880,65536,132599148,1575164,0,532212612,12073634385323217,12073634388707041,12073634388840000,12073634388843710
 3,"void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 0u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",0,0,6,775513,775520,4194304,256,0,0,36,24,13632,0x7f2c2e54d800,0x7f2b22835180,395077,395077,33725,3160624,65536,196412274,2983719,0,787466424,12073634388917887,12073634389118399,12073634389369118,12073634389420091
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/pmc_dispatch_info.csv
index 4544bf0858..8f3ca42ca4 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
 3,"void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 0u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/pmc_perf.csv
index 3b6e0cd1c3..e967e28a7c 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,774249,774254,32768,256,0,0,24,24,12480,0x0,0x7f2d6f035100,0,4096,4096,512,0,512,4096,0,28202,28202,1497585,576723,241,120147,94114,74649,568620,548015,225616,84286,28202,0,28202,0,902464,200819,0,0,0,0,0,99041,4096,0,28749,0,0,0,28749,0,0,0,28749,0,0,0,28749,0,0,0,28749,0,0,0,28749,0,0,0,28749,0,0,0,28749,0,0,0,28749,0,0,0,28749,0,0,0,28749,0,0,0,28749,0,0,0,28749,0,0,0,28749,0,0,0,28749,0,0,0,28749,0,0,0,28749,0,0,0,28749,0,0,0,28749,0,0,0,28749,0,0,0,28749,0,0,0,28749,0,0,0,28749,0,0,0,28749,0,0,0,28749,0,0,0,28749,0,0,0,28749,0,0,0,28749,0,0,0,28749,0,0,0,28749,0,0,0,28749,0,0,0,28749,0,0,0,0,256,0,0,0,304,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,261,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,376,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,4096,4096,0,94434,0,0,0,102776,0,0,0,91008,0,0,0,88253,0,0,0,88870,0,0,0,131354,0,0,0,86756,0,0,0,108041,0,0,0,85262,0,0,0,86987,0,0,0,72435,0,0,0,73137,0,0,0,98724,0,0,0,72813,0,0,0,84461,0,0,0,67537,0,0,0,122520,0,0,0,72757,0,0,0,92258,0,0,0,91677,0,0,0,133318,0,0,0,121641,0,0,0,77261,0,0,0,82662,0,0,0,105894,0,0,0,137650,0,0,0,96242,0,0,0,94856,0,0,0,200192,0,0,0,128042,0,0,0,120572,0,0,0,105218,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4096,0,256,256,256,0,257,257,257,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,188,260,448,448,47,257,304,304,0,256,256,256,0,256,256,256,188,261,449,449,0,304,304,304,0,256,256,256,0,256,256,256,0,425,425,425,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,47,258,305,305,0,257,257,257,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,304,0,0,256,0,0,0,0,512,512,35328,1104161,1045134,22675,12085,0,0,0,4096,50154,48010,4096,4096,128,512,624,27974,4265,0,48,219,0,8624,36352,231592,73773,1021101,26624,0,0,30208,65536,65536,65536,0,0,0,0,0,116,628,12574,1893,0,24468,8843,0,470,8373,1024,0,1024,4096,0,4096,512,512,0,0,360,16384,0,16384,0,0,2413,25171,0,8891,0,0,31,1933312,8192,0,0,0,512,512,0,120,15064,0,16384,16384,0,0,0,0,19971,0,0,0,0,0,0,0,32768,0,0,0,0,12113007,17184737,0,8192,0,0,0,0,695,0,0,0,0,0,1024,432,48,0,0,0,480,0,0,0,0,0,3197,0,0,0,8421,0,438,0,8192,6562,48,1582,1068,0,0,0,0,0,0,0,0,0,2560,0,0,0,49980,512,0,48,464,0,512,0,0,0,0,0,0,0,512,0,0,0,0,0,8192,0,0,440954,0,4096,8421,0,3203933,0,12073608589410601,12073635254661040,12073635254985997,12073608830934114
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,774249,774254,4194304,256,0,0,24,24,12928,0x7f2e9f13b900,0x7f2d6f035140,0,524288,524288,65536,0,65536,524288,0,219208,219208,23750057,22563889,31372,11707152,22166019,22101488,22554052,20382884,1753664,1567159,219208,0,219208,0,7014656,6179963,0,0,0,0,0,20053388,524288,0,220977,0,0,0,220977,0,0,0,220977,0,0,0,220977,0,0,0,220977,0,0,0,220977,0,0,0,220977,0,0,0,220977,0,0,0,220977,0,0,0,220977,0,0,0,220977,0,0,0,220977,0,0,0,220977,0,0,0,220977,0,0,0,220977,0,0,0,220977,0,0,0,220977,0,0,0,220977,0,0,0,220977,0,0,0,220977,0,0,0,220977,0,0,0,220977,0,0,0,220977,0,0,0,220977,0,0,0,220977,0,0,0,220977,0,0,0,220977,0,0,0,220977,0,0,0,220977,0,0,0,220977,0,0,0,220977,0,0,0,220977,0,0,0,0,65536,0,2308,0,65584,0,3036,0,65540,0,8906,0,65537,0,6017,0,65536,0,17193,0,65537,0,19124,0,65536,0,8736,0,65536,0,1828,0,65537,0,723,0,65536,0,7929,0,67472,0,75541,0,65537,0,7953,0,65536,0,785,0,65536,0,1536,0,65537,0,4011,0,65536,0,3595,0,65536,0,5574,0,65536,0,4340,0,65536,0,4874,0,65536,0,13576,0,65536,0,8025,0,65536,0,4415,0,67371,0,46979,0,65536,0,16928,0,65536,0,7525,0,65536,0,10664,0,65656,0,6443,0,65536,0,2544,0,65537,0,3346,0,65536,0,5632,0,65540,0,4860,0,65536,0,16748,0,524288,524288,0,57464562,0,0,0,29010686,0,0,0,31947022,0,0,0,30995575,0,0,0,30522183,0,0,0,29763437,0,0,0,28441166,0,0,0,31214868,0,0,0,26612933,0,0,0,26788784,0,0,0,29615917,0,0,0,29746032,0,0,0,32407468,0,0,0,30893962,0,0,0,29457222,0,0,0,31132806,0,0,0,30996796,0,0,0,30603018,0,0,0,30284089,0,0,0,30842447,0,0,0,30695479,0,0,0,32000489,0,0,0,30426337,0,0,0,28849502,0,0,0,39579204,0,0,0,29432469,0,0,0,32508392,0,0,0,30349150,0,0,0,31429438,0,0,0,31083671,0,0,0,28127142,0,0,0,30217379,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,524288,0,65536,65536,65536,0,65537,65537,65537,188,65540,65728,65728,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,67301,67301,67301,0,65536,65536,65536,0,65536,65536,65536,47,65537,65584,65584,0,66450,66450,66450,0,65536,65536,65536,0,65537,65537,65537,0,65584,65584,65584,0,65536,65536,65536,0,65536,65536,65536,0,65705,65705,65705,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,188,65541,65729,65729,0,65537,65537,65537,65536,0,0,65536,0,0,65728,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65728,0,0,65536,0,0,0,0,65536,65536,4128768,130557267,47527229,78770198,204648,0,0,0,524288,22505173,22496094,524288,524288,16384,65536,747,222377,4541,0,48,3866,0,2097536,4259840,1779168,1609256,23853588,3014656,0,0,3473408,8388608,8388608,8388608,0,0,0,0,0,163031,194539,12490,2152,0,218032,2101623,0,423,2101200,131072,0,131072,524288,0,524288,65536,65536,0,0,360,2097152,0,2097152,52960,0,2427,210208,0,2099507,0,0,31,222298112,917504,0,0,0,65536,65536,0,7586,2018790,0,2097152,2097152,0,756610,759201,0,21228,0,0,0,0,0,0,0,4194304,0,0,0,0,1081733435,1842519973,0,2097152,0,0,0,0,193139,0,0,0,0,0,131072,384,48,0,0,0,432,0,0,0,0,0,13674,0,0,0,2102504,0,10686,0,917504,914769,48,7397,185263,0,0,0,0,0,0,0,0,0,327680,0,0,277152,330861,65536,64048,48,1440,0,65536,0,0,0,0,0,0,0,65536,0,0,0,1966097,0,2097152,0,0,17289162,0,524288,2099680,0,1171144009,0,12073608831564866,12073635269823988,12073635269830388,12073608835895183
 3,"void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 0u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",0,0,6,774249,774254,4194304,256,0,0,36,24,13632,0x7f2e9f13b800,0x7f2d6f035180,0,524288,524288,917504,0,65536,524288,0,396997,396997,45718487,44302707,0,18576644,43306766,43155112,44283268,35884985,3175976,3031401,396997,0,396997,0,12703904,11978533,0,0,0,0,0,35757130,524288,0,399571,0,0,0,399571,0,0,0,399571,0,0,0,399571,0,0,0,399571,0,0,0,399571,0,0,0,399571,0,0,0,399571,0,0,0,399571,0,0,0,399571,0,0,0,399571,0,0,0,399571,0,0,0,399571,0,0,0,399571,0,0,0,399571,0,0,0,399571,0,0,0,399571,0,0,0,399571,0,0,0,399571,0,0,0,399571,0,0,0,399571,0,0,0,399571,0,0,0,399571,0,0,0,399571,0,0,0,399571,0,0,0,399571,0,0,0,399571,0,0,0,399571,0,0,0,399571,0,0,0,399571,0,0,0,399571,0,0,0,399571,0,0,0,0,131072,0,17544,0,131120,0,36682,0,131072,0,7711,0,131073,0,20601,0,131072,0,48454,0,131073,0,8688,0,131076,0,20850,0,131072,0,8850,0,131073,0,34686,0,131072,0,27923,0,132026,0,149057,0,131073,0,20433,0,132187,0,80438,0,131072,0,57290,0,131073,0,24248,0,131072,0,3170,0,131223,0,26215,0,131072,0,42054,0,131072,0,15195,0,131072,0,17287,0,131072,0,19827,0,131072,0,14383,0,131146,0,16041,0,131072,0,37666,0,131072,0,25736,0,131072,0,7959,0,131196,0,35044,0,131072,0,1315,0,131073,0,22946,0,131072,0,21479,0,131072,0,35381,0,131072,0,8528,0,524288,524288,0,79027332,0,0,0,71023391,0,0,0,71308653,0,0,0,78402767,0,0,0,91027890,0,0,0,83471376,0,0,0,73306952,0,0,0,76366973,0,0,0,79586728,0,0,0,88726123,0,0,0,72231979,0,0,0,69795464,0,0,0,81447639,0,0,0,84308673,0,0,0,77452946,0,0,0,77717945,0,0,0,83142921,0,0,0,68632381,0,0,0,70745490,0,0,0,77711485,0,0,0,94371314,0,0,0,82102539,0,0,0,77702154,0,0,0,75319763,0,0,0,103207455,0,0,0,86395231,0,0,0,77796072,0,0,0,69647452,0,0,0,72259185,0,0,0,75075474,0,0,0,86688583,0,0,0,80800372,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,132121,132121,132121,0,131073,131073,131073,0,131072,131072,131072,0,131072,131072,131072,0,131072,131072,131072,0,131072,131072,131072,188,131076,131264,131264,0,131072,131072,131072,0,131072,131072,131072,0,131072,131072,131072,0,131072,131072,131072,0,131072,131072,131072,0,131734,131734,131734,0,131072,131072,131072,0,131072,131072,131072,47,131073,131120,131120,0,131852,131852,131852,0,131072,131072,131072,0,131073,131073,131073,0,131120,131120,131120,0,131072,131072,131072,0,131072,131072,131072,94,131243,131337,131337,0,131072,131072,131072,0,131072,131072,131072,0,131072,131072,131072,188,131076,131264,131264,0,131072,131072,131072,0,131428,131428,131428,0,131072,131072,131072,0,131073,131073,131073,0,131073,131073,131073,131072,0,0,131072,0,0,131072,0,0,131072,0,0,131072,0,0,131072,0,0,131264,0,0,131072,0,0,131072,0,0,131072,0,0,131072,0,0,131072,0,0,131072,0,0,131072,0,0,131072,0,0,131072,0,0,131072,0,0,131072,0,0,131072,0,0,131072,0,0,131072,0,0,131072,0,0,131168,0,0,131072,0,0,131072,0,0,131072,0,0,131264,0,0,131072,0,0,131072,0,0,131072,0,0,131072,0,0,131072,0,0,0,0,131072,65536,6291456,224954296,57679475,160852293,378728,0,0,0,524288,44087322,44085943,0,524288,16384,65536,717,395997,4317,0,48,2113,0,4194784,6422528,3172584,3006782,44835542,4259840,0,0,4718592,33554432,33554432,33554432,0,0,0,0,0,461484,392890,12543,1993,0,392182,4196655,0,517,4196138,983040,0,196608,524288,0,524288,65536,917504,0,0,360,8388608,0,2097152,219436,0,2648,391749,0,4196967,0,0,31,301989888,1245184,0,0,0,65536,65536,0,14957,8227307,0,8388608,2097152,0,0,4784738,0,26794,0,0,0,0,0,0,0,4194304,0,0,0,0,1075984671,4021428805,0,4194304,0,0,0,0,358345,0,0,0,0,0,131072,480,48,0,0,0,528,0,0,0,0,0,1802,0,0,0,4196585,0,4540,0,1245184,1240624,48,7373,182236,0,0,0,0,0,0,0,0,0,327680,0,0,1047357,1100937,65536,64048,48,1440,0,65536,0,0,0,0,0,0,0,65536,0,0,0,4063245,0,4194304,0,0,31118740,0,0,4197913,0,2275359032,0,12073608836525695,12073635269892307,12073635270023986,12073608837873099
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/prev_analysis/1.csv
index c33ca8cb15..1cfa155fa2 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<double, 256, 8u, 512u>(double, double*) [clone .kd]",1,6055797.0,6055797.0,6055797.0,9.85911253160606
 "void benchmark_func<double, 256, 8u, 256u>(double, double*) [clone .kd]",1,3054538.0,3054538.0,3054538.0,4.972926581598906
 "void benchmark_func<__half2, 256, 8u, 512u>(__half2, __half2*) [clone .kd]",1,3040618.0,3040618.0,3040618.0,4.950264189441448
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/prev_analysis/1001.csv
index 1e8362a8e4..c706f4c2f5 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,47.036144578313255,Instr per wave
 SMEM,1.7710843373493976,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/prev_analysis/101.csv
index 258a097b41..594a990443 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx908
 mi100
 48
 1228.8
-SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/prev_analysis/1202.csv
index d137bb22f9..c664486233 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,33772.690496605566,7498.961181640625,547938.564453125,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/prev_analysis/1901.csv
index 4ebac09d5a..4e985aa356 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,2.0,smem_
 VALU,739.0,valu_
 MFMA,,mfma_
 VMEM,8.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,22.0,br_
 VGPR,24.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,65144.0,wavefronts_
 Workgroups,16286.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,164.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,0.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,45.0,hbm_rd_
 HBM Wr,0.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,70.0,vl1_coales_
 VL1 Stall,30.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,37.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/prev_analysis/2001.csv
index 4544bf0858..8f3ca42ca4 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
 3,"void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 0u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/prev_analysis/201.csv
index e2c0053336..8e8056bc2f 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,59.656313919435085,Pct,100,59.656313919435085
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,63.967364387615135,Threads,64,99.94900685564865
 IPC - Issue,0.8432688819739547,Instr/cycle,5,16.865377639479092
-LDS BW,0.0,Gb/sec,23070.72,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,23070.72,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99339955998376,Pct,100,99.99339955998376
 Instr Cache BW,1876.7046710049574,Gb/s,4614.144,40.672867405199256
 Scalar L1D Cache Hit Rate,99.35234690234445,Pct,100,99.35234690234445
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/prev_analysis/602.csv
index 47a8f10fc8..6bf0fac514 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,65472.79518072289,0,756610,Simd
 Insufficient SIMD VGPRs,638481.3554216868,0,41879521,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/prev_analysis/701.csv
index 878c96c694..aa09824713 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,24.072289156626507,12,36,Registers
 SGPRs,24.0,24,24,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/sysinfo.csv
index bf83ae11c3..85834f603c 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-K_str_valid_2,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 10:46:21 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+K_str_valid_2,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 10:46:21 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/timestamps.csv
index 32c38e17d3..13b4d6b155 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,775564,775569,33554432,256,0,0,8,32,6464,0x0,0x7fbd8c604180,12073635254615675,12073635254661040,12073635254985997,12073635255091460
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,775564,775569,32768,256,0,0,24,24,12480,0x0,0x7fbd8c635100,12073635269722329,12073635269823988,12073635269830388,12073635269836161
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,775564,775569,4194304,256,0,0,24,24,12928,0x7fbe9833b900,0x7fbd8c635140,12073635269878970,12073635269892307,12073635270023986,12073635270027376
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/SQ_IFETCH_LEVEL.csv
index 3ca7f85e73..3687ddd255 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/SQ_IFETCH_LEVEL.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,47961,47961,33554432,256,0,0,4,32,4160,0x0,0x7f3f26004280,380575,380575,524288,4718592,684146,76616992,14500852707317,14500149998705,14501002290552,14501002401812
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,47961,47961,32768,256,0,0,12,24,13888,0x0,0x7f3f26023f80,33397,33397,512,8192,6077,685940,14501007562688,14501002290552,14501007696472,14501007701194
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,47961,47961,4194304,256,0,0,12,24,14336,0x7f3f2910b380,0x7f3f26023fc0,164678,164678,65536,917504,140226,15737180,14501007739083,14501007696472,14501008073272,14501008075843
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/SQ_INST_LEVEL_LDS.csv
index d218817758..758781c803 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/SQ_INST_LEVEL_LDS.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,49813,49813,33554432,256,0,0,4,32,4160,0x0,0x7fa0e5604280,0,0,0,14520037503974,14519340354159,14520189852507,14520189969056
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,49813,49813,32768,256,0,0,12,24,13888,0x0,0x7fa0e5623f80,0,0,0,14520195149422,14520189852507,14520195276980,14520195281648
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,49813,49813,4194304,256,0,0,12,24,14336,0x7fa0e851b380,0x7fa0e5623fc0,0,0,0,14520195315287,14520195276980,14520195638100,14520195640638
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/SQ_INST_LEVEL_SMEM.csv
index be0816ccbb..3c542749f4 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/SQ_INST_LEVEL_SMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,47738,47738,33554432,256,0,0,4,32,4160,0x0,0x7fb3b1204280,3670016,3087276,345877256,14499919522662,14494397928095,14500069520014,14500069634253
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,47738,47738,32768,256,0,0,12,24,13888,0x0,0x7fb3b1223f80,512,95556,10718120,14500074764619,14500069520014,14500074895211,14500074900116
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,47738,47738,4194304,256,0,0,12,24,14336,0x7fb3b4129380,0x7fb3b1223fc0,65536,621032,69555184,14500074934675,14500074895211,14500075262571,14500075265205
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/SQ_INST_LEVEL_VMEM.csv
index 59596641c4..1f316d1006 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/SQ_INST_LEVEL_VMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,49590,49590,33554432,256,0,0,4,32,4160,0x0,0x7fb8cc204280,524288,5497657,615761124,14519108272125,14516848227188,14519259274315,14519259360224
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,49590,49590,32768,256,0,0,12,24,13888,0x0,0x7fb8cc223f80,4096,41503,4644980,14519264558770,14519259274315,14519264689989,14519264695006
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,49590,49590,4194304,256,0,0,12,24,14336,0x7fb8cf290380,0x7fb8cc223fc0,524288,10886486,1219253604,14519264728615,14519264689989,14519265060869,14519265063326
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/SQ_LEVEL_WAVES.csv
index 2a7ca1d9ef..a575061d4b 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/SQ_LEVEL_WAVES.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,48184,48184,33554432,256,0,0,4,32,4160,0x0,0x7f53b9a04280,375656,375656,9030,3005256,524288,233691898,2916453,0,950974040,14501787345173,14501085831162,14501930942868,14501931059117
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,48184,48184,32768,256,0,0,12,24,13888,0x0,0x7f53b9a23f80,33081,33081,29567,264656,512,1767172,159306,0,7082896,14501936246952,14501930942868,14501936379503,14501936384018
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,48184,48184,4194304,256,0,0,12,24,14336,0x7f53bc96a380,0x7f53b9a23fc0,163667,163667,13573,1309344,65536,80875724,1208698,0,325231544,14501936427317,14501936379503,14501936767822,14501936770417
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/pmc_perf.csv
index deb51a6789..df1012c5a6 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDI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],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBufferAligned.kd,0,0,0,48951,48951,33554432,256,0,0,4,32,4160,0x0,0x7f0a4d604280,3081968,2993634,524288,38880626,243029791,392,224,0,385245,385245,39159424.0,38196282.0,1.0,4186671.0,31306438.0,30940816.0,38170297.0,37609332.0,3080257,3000039,385245,0,385245,0,12327840.0,9477915.0,0.0,0.0,0,0,616,0,4718592,4714750,112,3730,375034,0.0,0.0,0.0,524288.0,28505695.0,27781268.0,7564.0,524288.0,131072,524288,301,384272,2322,0,56.0,303.0,0.0,4194696.0,0,0,0,0,0,7340032,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,20143985.0,524288.0,0,384082,0,0,0,384082,0,0,0,384082,0,0,0,384082,0,0,0,384082,0,0,0,384082,0,0,0,384082,0,0,0,384082,0,0,0,384082,0,0,0,384082,0,0,0,384082,0,0,0,384082,0,0,0,384082,0,0,0,384082,0,0,0,384082,0,0,0,384082,0,0,0,384082,0,0,0,384082,0,0,0,384082,0,0,0,384082,0,0,0,384082,0,0,0,384082,0,0,0,384082,0,0,0,384082,0,0,0,384082,0,0,0,384082,0,0,0,384082,0,0,0,384082,0,0,0,384082,0,0,0,384082,0,0,0,384082,0,0,0,384082,0,0,0,0,0,0.0,21128411.0,0,0,0,0,0,0,0,0,0,0,0,0,33,0,0,0,2,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,34,0,0,0,61,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,112,0,0,0,32,0,0,0,1,0,0,0,524288.0,0.0,0,0,129024,129024,0,198226,129024,129024,0,0,129024,129024,0,43904,129024,129024,0,333,129024,129024,0,539,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,44321,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,164,129024,129024,0,27632,129024,129024,0,886,129024,129024,0,185,129024,129024,0,0,129024,129024,0,0,129024,129024,0,282055,129024,129024,0,0,129024,129024,0,0,129024,129024,0,920,129024,129024,0,44789,129024,129024,0,186,129024,129024,524288.0,0.0,44562,0,0,50889537,45444,0,0,51033856,44235,0,0,50290420,46804,0,0,52065892,45540,0,0,51604271,45761,0,0,51494299,45017,0,0,51142377,47674,0,0,52895468,44627,0,0,51110073,47288,0,0,51511543,45285,0,0,50741693,47738,0,0,52473734,45177,0,0,51734041,46812,0,0,51827792,46242,0,0,51510117,48669,0,0,53295991,43796,0,0,50857284,46676,0,0,51333465,44666,0,0,50467668,48596,0,0,52650665,46440,0,0,52106193,46570,0,0,51809584,45628,0,0,51256446,47896,0,0,53057884,44598,0,0,50901568,46390,0,0,51252253,45801,0,0,50824847,48914,0,0,52785399,47304,0,0,52171113,48290,0,0,52407637,46256,0,0,51619016,50368,0,0,53707359,0.0,65536,65592,56,131128,65536,65537,1,131073,65536,65536,0,131072,65536,65536,0,131072,65646,65538,112,131184,65536,65536,0,131072,65536,65570,34,131106,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65591,65537,56,131128,65536,65568,32,131104,65536,65569,33,131105,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65758,65538,224,131296,65536,65536,0,131072,65536,65536,0,131072,65536,65568,32,131104,65536,65536,0,131072,65536,65536,0,131072,65536,65648,112,131184,65536,65536,0,131072,65536,65536,0,131072,65591,65537,56,131128,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131184,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131296,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131128,0,131072,1072379,0,524288,3670016,3663393,224,6399,1048576,33554432.0,33554432.0,0.0,33554432.0,30050449.0,28408014.0,0.0,524288.0,214956,536992,8883,889,0,382011,4195057.0,0.0,2097594.0,2097463.0,1048576,1048576,0,524288,0,524288,7340032,0,0.0,0.0,104.0,8388608.0,29519458.0,2097152.0,0.0,200310,0,1187,384289,0,750.0,4194304.0,0.0,2064387.0,25690112,9437184,0,0,0,0,0,0,13275.0,8242583.0,0.0,8388608.0,2097152.0,4194304.0,9992934,0,0,8862,4128768.0,4128768.0,0.0,1479909.0,0,0,0,0,0,0,5767168,1048576,315993999.0,0.0,1472761269.0,0.0,37.0,0.0,0,0,374639,0.0,0.0,1481296.0,0.0,3670016,524288,0,0,0,2621440,524288,178698399,4194304.0,0.0,0.0,0.0,0.0,1159221.0,0,0,0.0,311.0,0.0,606.0,42624948,24117248,0,0,9437184,11010048,0,3145728,0.0,0.0,0.0,0.0,0.0,0.0,0,1572864,0.0,0.0,0.0,196634.0,524288,524288,0,3670016,7340032,603979776,4718592,0,0.0,0.0,0.0,0.0,0.0,0.0,524288,0,2064384.0,0.0,2031625.0,0.0,0,0,524288,0,0,0,0,33554432,0.0,4194304.0,0.0,18906248.0,0.0,0.0,145.0,4128768.0,963632.0,1708283200.0,14503253560521,14520846104183,14520846343383,14503402226041
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,48951,48951,32768,256,0,0,12,24,13888,0x0,0x7f0a4d623f80,259960,156558,512,1352019,1701516,504,56,0,32494,32494,2266212.0,165391.0,143.0,0.0,36613.0,33418.0,159116.0,140376.0,259952,163500,32494,0,32494,0,1039808.0,366772.0,0.0,0.0,0,0,560,0,8192,6222,56,1914,24244,0.0,0.0,0.0,4096.0,29358.0,27949.0,0.0,4096.0,128,512,302,33809,2616,0,0.0,61.0,0.0,4600.0,0,0,0,0,0,1024,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,14705.0,4096.0,0,32581,0,0,0,32581,0,0,0,32581,0,0,0,32581,0,0,0,32581,0,0,0,32581,0,0,0,32581,0,0,0,32581,0,0,0,32581,0,0,0,32581,0,0,0,32581,0,0,0,32581,0,0,0,32581,0,0,0,32581,0,0,0,32581,0,0,0,32581,0,0,0,32581,0,0,0,32581,0,0,0,32581,0,0,0,32581,0,0,0,32581,0,0,0,32581,0,0,0,32581,0,0,0,32581,0,0,0,32581,0,0,0,32581,0,0,0,32581,0,0,0,32581,0,0,0,32581,0,0,0,32581,0,0,0,32581,0,0,0,32581,0,0,0,0,0,0.0,0.0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,258,0,0,0,257,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,312,0,0,0,256,0,0,0,256,0,0,0,4096.0,4096.0,0,77943,0,0,0,684795,0,0,0,79700,0,0,0,82886,0,0,0,81485,0,0,0,82669,0,0,0,76295,0,0,0,82822,0,0,0,79651,0,0,0,85367,0,0,0,79007,0,0,0,84387,0,0,0,96940,0,0,0,81858,0,0,0,79448,0,0,0,79172,0,0,0,77386,0,0,0,82387,0,0,0,79029,0,0,0,134202,0,0,0,83603,0,0,0,81441,0,0,0,81608,0,0,0,86460,0,0,0,77001,0,0,0,85976,0,0,0,72824,0,0,0,78282,0,0,0,112541,0,0,0,80946,0,0,0,80630,0,0,0,85133,0,0,0.0,0.0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4096.0,0,128,128,128,0,129,129,129,0,128,128,128,0,128,128,128,0,128,128,128,222,130,352,352,0,129,129,129,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,222,130,352,352,0,128,128,128,0,129,129,129,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,55,129,184,184,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,184,184,184,0,128,128,128,0,128,128,128,0,128,128,128,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,352,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,352,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,184,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,668,0,0,512,0,56,456,0,65536.0,65536.0,65536.0,0.0,0.0,0.0,0.0,0.0,6,518,11131,1017,0,30284,4660.0,0.0,499.0,4161.0,512,0,0,0,4096,4096,512,0,0.0,0.0,104.0,16384.0,0.0,16384.0,4096.0,0,0,1311,31892,0,4660.0,0.0,0.0,31.0,35328,26112,0,0,0,0,0,0,104.0,15240.0,0.0,16384.0,16384.0,0.0,0,0,0,29937,0.0,0.0,0.0,0.0,0,0,0,0,0,0,10752,3584,3428678.0,4835710.0,0.0,8192.0,2.0,0.0,0,0,497,0.0,0.0,0.0,0.0,512,4096,0,0,0,512,512,1630480,0.0,0.0,0.0,0.0,0.0,1514.0,0,0,0.0,8261.0,0.0,120.0,12401,32256,0,0,26112,1024,0,1024,0.0,0.0,0.0,0.0,0.0,0.0,0,1024,0.0,0.0,0.0,47154.0,4096,0,4096,512,512,1671168,8192,0,0.0,0.0,0.0,0.0,0.0,0.0,512,0,0.0,0.0,0.0,0.0,0,0,512,0,0,0,0,32768,8192.0,0.0,0.0,129739.0,0.0,4096.0,8206.0,0.0,3515168.0,0.0,14503408560943,14520851103379,14520851117299,14503409052019
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,48951,48951,4194304,256,0,0,12,24,14336,0x7f0a50689380,0x7f0a4d623fc0,1315128,1212529,65536,15693148,77734074,392,56,0,164390,164390,15993874.0,14515023.0,23878.0,710774.0,13342909.0,13011926.0,14508744.0,12373819.0,1315120,1219390,164390,0,164390,0,5260480.0,4730698.0,0.0,0.0,0,0,448,0,917504,913805,0,3699,153944,0.0,0.0,0.0,524288.0,12991967.0,12962559.0,2313.0,524288.0,16384,65536,302,164502,2589,0,0.0,180.0,0.0,1048968.0,0,0,0,0,0,131072,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,12139955.0,524288.0,0,164738,0,0,0,164738,0,0,0,164738,0,0,0,164738,0,0,0,164738,0,0,0,164738,0,0,0,164738,0,0,0,164738,0,0,0,164738,0,0,0,164738,0,0,0,164738,0,0,0,164738,0,0,0,164738,0,0,0,164738,0,0,0,164738,0,0,0,164738,0,0,0,164738,0,0,0,164738,0,0,0,164738,0,0,0,164738,0,0,0,164738,0,0,0,164738,0,0,0,164738,0,0,0,164738,0,0,0,164738,0,0,0,164738,0,0,0,164738,0,0,0,164738,0,0,0,164738,0,0,0,164738,0,0,0,164738,0,0,0,164738,0,0,0,0,0,0.0,0.0,65536,0,14246,0,65538,0,23234,0,65538,0,6783,0,65537,0,26999,0,65536,0,19123,0,65536,0,34098,0,65537,0,24949,0,65536,0,17562,0,65537,0,13352,0,65536,0,11887,0,65536,0,18001,0,65536,0,24824,0,65536,0,18226,0,65536,0,29676,0,65536,0,23980,0,65536,0,22755,0,65536,0,14736,0,65536,0,24579,0,65536,0,32486,0,65536,0,7869,0,65536,0,21799,0,65589,0,10868,0,65537,0,17019,0,65540,0,25386,0,65542,0,16377,0,65537,0,13522,0,65536,0,9698,0,65536,0,6894,0,65536,0,8746,0,65592,0,13332,0,65603,0,16708,0,65536,0,22939,0,524288.0,524288.0,0,42952772,0,0,0,43926381,0,0,0,42502047,0,0,0,41737443,0,0,0,45171617,0,0,0,47540490,0,0,0,47950818,0,0,0,47670371,0,0,0,44976684,0,0,0,43425176,0,0,0,41384825,0,0,0,43858306,0,0,0,44059448,0,0,0,46134614,0,0,0,44267462,0,0,0,44379750,0,0,0,46846387,0,0,0,46863018,0,0,0,41721911,0,0,0,44412456,0,0,0,45512239,0,0,0,46773755,0,0,0,47273034,0,0,0,41093321,0,0,0,41871413,0,0,0,45499555,0,0,0,40104910,0,0,0,47524703,0,0,0,43383868,0,0,0,43626885,0,0,0,44082080,0,0,0,47512016,0,0,0.0,0.0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,524288.0,0,32768,32768,32768,0,32769,32769,32769,0,32768,32768,32768,0,32769,32769,32769,0,32768,32768,32768,0,32768,32768,32768,0,32819,32819,32819,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32822,32822,32822,0,32769,32769,32769,0,32768,32768,32768,0,32769,32769,32769,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,166,32770,32936,32936,222,32770,32992,32992,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32824,32824,32824,0,32768,32768,32768,0,32768,32768,32768,0,32769,32769,32769,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32936,0,0,32992,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,867392,0,0,65536,63800,56,1680,0,8388608.0,8388608.0,8388608.0,0.0,0.0,0.0,0.0,0.0,124956,144681,10201,2444,0,162311,1049151.0,0.0,388.0,1048763.0,65536,0,0,0,524288,524288,131072,0,0.0,0.0,104.0,2097152.0,0.0,2097152.0,524288.0,41237,0,2783,161264,0,1049148.0,0.0,0.0,31.0,4063232,2883584,0,0,0,0,0,0,6585.0,2028759.0,0.0,2097152.0,2097152.0,0.0,1267991,0,0,13431,0.0,0.0,0.0,0.0,262144,0,0,0,0,0,1507328,458752,956861757.0,2221108896.0,0.0,2097152.0,52.0,0.0,0,0,147528,0.0,0.0,0.0,0.0,65536,524288,0,0,0,65536,65536,47936290,0.0,0.0,0.0,0.0,0.0,29430.0,0,0,0.0,2097345.0,0.0,372.0,30430014,3735552,0,0,2883584,196608,0,131072,0.0,0.0,0.0,0.0,0.0,0.0,0,131072,0.0,0.0,376645.0,1125607.0,524288,0,524288,65536,131072,184549376,917504,0,0.0,0.0,0.0,0.0,0.0,0.0,65536,0,0.0,0.0,983048.0,0.0,0,0,65536,0,0,0,0,4194304,2097152.0,0.0,0.0,12353247.0,0.0,524288.0,2097289.0,0.0,1414457310.0,0.0,14503410149759,14520851188339,14520851280659,14503410942686
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/prev_analysis/1.csv
index 09ae4ae22b..90fb6684c6 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,3356958.0,3356958.0,3356958.0,7.8358068642013405
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,1725599.0,1725599.0,1725599.0,4.0278908729447815
 "void benchmark_func<double, 256, 8u, 512u>(double, double*) [clone .kd]",1,1716159.0,1716159.0,1716159.0,4.005856037597404
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/prev_analysis/1001.csv
index f475f954a6..fb5988001a 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,494.8622754491018,Instr per wave
 VMEM,7.958083832335329,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,0.0,Instr per wave
 SALU,24.520958083832337,Instr per wave
 SMEM,1.8023952095808384,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/prev_analysis/101.csv
index d59a400a9d..1e2d630c4a 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx90a
 mi200
 56
 1638.4
-roofline|SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+roofline|SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/prev_analysis/1202.csv
index 10dd8dadd1..c57e0539c2 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,18371.238131723003,1854.1701583862305,258340.74670410156,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/prev_analysis/1901.csv
index 26f936701a..f6ea7f8976 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,2.0,smem_
 VALU,495.0,valu_
 MFMA,0.0,mfma_
 VMEM,8.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,10.0,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,67894.0,wavefronts_
 Workgroups,16973.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,128.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,0.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,44.0,hbm_rd_
 HBM Wr,0.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,70.0,vl1_coales_
 VL1 Stall,2.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,25.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/prev_analysis/201.csv
index d165d593e6..4c5a3bd064 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,58.40240772557741,Pct,100,58.40240772557741
 MFMA Util,0.0,Pct,100,0.0
 VALU Active Threads/Wave,64.0,Threads,64,100.0
 IPC - Issue,1.0,Instr/cycle,5,20.0
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.9926237339862,Pct,100,99.9926237339862
 Instr Cache BW,1671.6045757647576,Gb/s,6092.8,27.435736865886906
 Scalar L1D Cache Hit Rate,99.34855886143326,Pct,100,99.34855886143326
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/prev_analysis/602.csv
index 05a9fda9e7..4ac6a80127 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,12278962.898203593,0,374989194,Simd
 Insufficient SIMD VGPRs,0.0,0,0,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/prev_analysis/701.csv
index 12250d77c0..db0925a109 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/sysinfo.csv
index 720167c5ca..7f52f9b119 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-K_str_valid_2,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 19:55:00 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,roofline|SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+K_str_valid_2,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 19:55:00 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,roofline|SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/timestamps.csv
index 2382515787..38946a2ed7 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_2/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,49896,49896,33554432,256,0,0,4,32,4160,0x0,0x7f8c64c04280,14520846059113,14520846104183,14520846343383,14520846455732
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,49896,49896,32768,256,0,0,12,24,13888,0x0,0x7f8c64c23f80,14520851088263,14520851103379,14520851117299,14520851135452
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,49896,49896,4194304,256,0,0,12,24,14336,0x7f8c67bb1380,0x7f8c64c23fc0,14520851139562,14520851188339,14520851280659,14520851282948
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/SQ_IFETCH_LEVEL.csv
index ea340d2419..919cac4c3c 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/SQ_IFETCH_LEVEL.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,778531,778536,32768,256,0,0,24,24,12480,0x0,0x7fefdb235100,28035,28035,512,8192,9076,1163416,12073700196009055,12073700441515069,12073700441521629,12073700441537841
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,778531,778536,4194304,256,0,0,24,24,12928,0x7ff10b2ba900,0x7fefdb235140,215171,215171,65536,917504,148623,18989620,12073700441598714,12073700444996970,12073700445128010,12073700445132271
 3,"void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 0u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",0,0,6,778531,778536,4194304,256,0,0,36,24,13632,0x7ff10b2ba800,0x7fefdb235180,392817,392817,65536,1245184,184153,23500716,12073700445204075,12073700445386569,12073700445637607,12073700445706138
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/SQ_INST_LEVEL_LDS.csv
index f8b04e312b..c1a85234c4 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/SQ_INST_LEVEL_LDS.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,780333,780338,32768,256,0,0,24,24,12480,0x0,0x7f1b44a35100,0,0,0,12073726828846288,12073727075330881,12073727075337441,12073727075353603
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,780333,780338,4194304,256,0,0,24,24,12928,0x7f1c505ea900,0x7f1b44a35140,0,0,0,12073727075411440,12073727078794185,12073727078930985,12073727078935109
 3,"void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 0u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",0,0,6,780333,780338,4194304,256,0,0,36,24,13632,0x7f1c505ea800,0x7f1b44a35180,0,0,0,12073727079008936,12073727079185704,12073727079431623,12073727079498566
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/SQ_INST_LEVEL_SMEM.csv
index d548956d83..2f2d3cb346 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/SQ_INST_LEVEL_SMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,779952,779957,32768,256,0,0,24,24,12480,0x0,0x7f7d62435100,512,21056,2696456,12073724285633666,12073724535371558,12073724535378278,12073724535396390
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,779952,779957,4194304,256,0,0,24,24,12928,0x7f7e6e14a900,0x7f7d62435140,65536,168816,21707384,12073724535495424,12073724538844062,12073724538978461,12073724538981914
 3,"void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 0u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",0,0,6,779952,779957,4194304,256,0,0,36,24,13632,0x7f7e6e14a800,0x7f7d62435180,65536,174888,22361120,12073724539054298,12073724539230620,12073724539480699,12073724539548416
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/SQ_INST_LEVEL_VMEM.csv
index 695df00aaa..706d7dd67d 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/SQ_INST_LEVEL_VMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,780143,780148,32768,256,0,0,24,24,12480,0x0,0x7f8d1fa35100,4096,100782,12888576,12073725560982903,12073725805358650,12073725805364890,12073725805383082
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,780143,780148,4194304,256,0,0,24,24,12928,0x7f8e4fbc7900,0x7f8d1fa35140,524288,12057453,1543249680,12073725805443053,12073725808799553,12073725808931553,12073725808935924
 3,"void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 0u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",0,0,6,780143,780148,4194304,256,0,0,36,24,13632,0x7f8e4fbc7800,0x7f8d1fa35180,524288,12880032,1648649404,12073725809009260,12073725809183712,12073725809435711,12073725809503679
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/SQ_LEVEL_WAVES.csv
index f1ddcf0d40..6f6d0f79ca 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/SQ_LEVEL_WAVES.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,780524,780529,32768,256,0,0,24,24,12480,0x0,0x7f1e1f835100,29941,29941,21232,239536,512,1182525,79219,0,4744272,12073728099412336,12073728345247497,12073728345253897,12073728345267809
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,780524,780529,4194304,256,0,0,24,24,12928,0x7f1f4f795900,0x7f1e1f835140,228316,228316,20913,1826536,65536,142834314,1662821,0,573140496,12073728345335846,12073728348720482,12073728348860321,12073728348864193
 3,"void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 0u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",0,0,6,780524,780529,4194304,256,0,0,36,24,13632,0x7f1f4f795800,0x7f1e1f835180,399676,399676,28703,3197416,65536,232626831,3026015,0,932320684,12073728348938150,12073728349142080,12073728349395999,12073728349463787
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/pmc_dispatch_info.csv
index 4544bf0858..8f3ca42ca4 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
 3,"void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 0u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/pmc_perf.csv
index ade666a222..07cef43946 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,779266,779271,32768,256,0,0,24,24,12480,0x0,0x7f0c50a35100,0,4096,4096,512,0,512,4096,0,28433,28433,1566009,626904,249,136694,106361,89157,618756,598356,227464,88848,28433,0,28433,0,909856,204365,0,0,0,0,0,101910,4096,0,28146,0,0,0,28146,0,0,0,28146,0,0,0,28146,0,0,0,28146,0,0,0,28146,0,0,0,28146,0,0,0,28146,0,0,0,28146,0,0,0,28146,0,0,0,28146,0,0,0,28146,0,0,0,28146,0,0,0,28146,0,0,0,28146,0,0,0,28146,0,0,0,28146,0,0,0,28146,0,0,0,28146,0,0,0,28146,0,0,0,28146,0,0,0,28146,0,0,0,28146,0,0,0,28146,0,0,0,28146,0,0,0,28146,0,0,0,28146,0,0,0,28146,0,0,0,28146,0,0,0,28146,0,0,0,28146,0,0,0,28146,0,0,0,0,257,0,0,0,304,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,260,0,0,0,256,0,0,0,376,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,376,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,4096,4096,0,99113,0,0,0,90733,0,0,0,130568,0,0,0,104763,0,0,0,77699,0,0,0,78077,0,0,0,101467,0,0,0,129622,0,0,0,80905,0,0,0,79834,0,0,0,76922,0,0,0,79576,0,0,0,89978,0,0,0,83487,0,0,0,73120,0,0,0,94249,0,0,0,92985,0,0,0,118780,0,0,0,79333,0,0,0,93102,0,0,0,101537,0,0,0,127219,0,0,0,94491,0,0,0,87908,0,0,0,82039,0,0,0,81318,0,0,0,79849,0,0,0,72912,0,0,0,84389,0,0,0,78731,0,0,0,278162,0,0,0,79599,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4096,0,257,257,257,0,256,256,256,0,256,256,256,0,256,256,256,47,257,304,304,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,305,305,305,0,256,256,256,0,256,256,256,0,257,257,257,0,256,256,256,188,260,448,448,0,256,256,256,0,304,304,304,0,256,256,256,188,260,448,448,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,376,376,376,0,256,256,256,0,256,256,256,47,257,304,304,0,256,256,256,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,304,0,0,256,0,0,0,0,512,512,35328,1159386,1106288,16746,12088,0,0,0,4096,62845,60047,4096,4096,128,512,617,27487,4074,0,48,219,0,8624,36352,219256,71681,1003522,26624,0,0,30208,65536,65536,65536,0,0,0,0,0,115,627,11402,2411,0,23376,8844,0,470,8374,1024,0,1024,4096,0,4096,512,512,0,0,360,16384,0,16384,0,0,2875,24879,0,8892,0,0,31,1933312,8192,0,0,0,512,512,0,120,15064,0,16384,16384,0,0,0,0,20769,0,0,0,0,0,0,0,32768,0,0,0,0,12397226,16178639,0,8192,0,0,0,0,696,0,0,0,0,0,1024,432,48,0,0,0,480,0,0,0,0,0,3276,0,0,0,8373,0,342,0,8192,6547,48,1597,1082,0,0,0,0,0,0,0,0,0,2560,0,0,0,50673,512,0,48,464,0,512,0,0,0,0,0,0,0,512,0,0,0,0,0,8192,0,0,471125,0,4096,8373,0,3199649,0,12073702329966474,12073729212993521,12073729213317198,12073702577269809
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,779266,779271,4194304,256,0,0,24,24,12928,0x7f0d5c6bf900,0x7f0c50a35140,0,524288,524288,65536,0,65536,524288,0,222738,222738,24761293,23545035,31928,8439056,23102672,23027645,23535700,21369830,1781904,1634587,222738,0,222738,0,7127616,6402710,0,0,0,0,0,19850005,524288,0,214548,0,0,0,214548,0,0,0,214548,0,0,0,214548,0,0,0,214548,0,0,0,214548,0,0,0,214548,0,0,0,214548,0,0,0,214548,0,0,0,214548,0,0,0,214548,0,0,0,214548,0,0,0,214548,0,0,0,214548,0,0,0,214548,0,0,0,214548,0,0,0,214548,0,0,0,214548,0,0,0,214548,0,0,0,214548,0,0,0,214548,0,0,0,214548,0,0,0,214548,0,0,0,214548,0,0,0,214548,0,0,0,214548,0,0,0,214548,0,0,0,214548,0,0,0,214548,0,0,0,214548,0,0,0,214548,0,0,0,214548,0,0,0,0,65537,0,17821,0,65584,0,1195,0,65540,0,21768,0,65536,0,17569,0,65536,0,19735,0,65536,0,12181,0,65536,0,15524,0,65536,0,5459,0,66383,0,56678,0,65536,0,13382,0,65536,0,14083,0,65536,0,7598,0,65537,0,14085,0,65536,0,18034,0,65536,0,12277,0,67169,0,71166,0,65536,0,19122,0,65537,0,36192,0,65536,0,21112,0,65536,0,14593,0,65656,0,31868,0,65536,0,39038,0,65536,0,34048,0,65536,0,11826,0,65656,0,24808,0,65537,0,27751,0,65536,0,20459,0,65536,0,11183,0,65536,0,5731,0,65536,0,18914,0,65540,0,3972,0,65536,0,19641,0,524288,524288,0,29453127,0,0,0,28909912,0,0,0,29271412,0,0,0,30761049,0,0,0,28258878,0,0,0,33065253,0,0,0,48054546,0,0,0,28804953,0,0,0,27819938,0,0,0,27188070,0,0,0,26412817,0,0,0,30585781,0,0,0,26401013,0,0,0,27807068,0,0,0,27923660,0,0,0,29007477,0,0,0,26332711,0,0,0,29534584,0,0,0,28291749,0,0,0,32153671,0,0,0,27822033,0,0,0,31332720,0,0,0,30423704,0,0,0,26372895,0,0,0,31412256,0,0,0,31075826,0,0,0,47134244,0,0,0,32677629,0,0,0,27083822,0,0,0,33780754,0,0,0,30509542,0,0,0,35741405,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,524288,0,65537,65537,65537,0,65536,65536,65536,188,65540,65728,65728,0,65536,65536,65536,47,65537,65584,65584,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65585,65585,65585,0,65536,65536,65536,0,67066,67066,67066,0,65537,65537,65537,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65584,65584,65584,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,67918,67918,67918,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65657,65657,65657,0,65536,65536,65536,0,65536,65536,65536,188,65540,65728,65728,0,65536,65536,65536,65536,0,0,65536,0,0,65728,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65728,0,0,65536,0,0,0,0,65536,65536,4128768,154765976,51185006,99321130,200179,0,0,0,524288,22633375,22630827,524288,524288,16384,65536,757,216660,3929,0,48,2987,0,2097536,4259840,1763280,1602081,23701126,3014656,0,0,3473408,8388608,8388608,8388608,0,0,0,0,0,160471,193648,11266,2451,0,216486,2101238,0,423,2100815,131072,0,131072,524288,0,524288,65536,65536,0,0,360,2097152,0,2097152,30266,0,2875,220685,0,2102055,0,0,31,222298112,917504,0,0,0,65536,65536,0,7602,2016105,0,2097152,2097152,0,527919,529407,0,20392,0,0,0,0,0,0,0,4194304,0,0,0,0,929571541,1532522567,0,2097152,0,0,0,0,196931,0,0,0,0,0,131072,384,48,0,0,0,432,0,0,0,0,0,5310,0,0,0,2101916,0,9510,0,917504,914717,48,7532,208906,0,0,0,0,0,0,0,0,0,327680,0,0,464810,517695,65536,64048,48,1440,0,65536,0,0,0,0,0,0,0,65536,0,0,0,1966099,0,2097152,0,0,15023828,0,524288,2101572,0,862888219,0,12073702577891915,12073729227849151,12073729227855871,12073702582235747
 3,"void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 0u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",0,0,6,779266,779271,4194304,256,0,0,36,24,13632,0x7f0d5c6bf800,0x7f0c50a35180,0,524288,524288,917504,0,65536,524288,0,390274,390274,44863337,43617588,0,20555745,43330338,43287735,43606672,35212777,3122192,2974895,390274,0,390274,0,12488768,11760105,0,0,0,0,0,34709206,524288,0,395727,0,0,0,395727,0,0,0,395727,0,0,0,395727,0,0,0,395727,0,0,0,395727,0,0,0,395727,0,0,0,395727,0,0,0,395727,0,0,0,395727,0,0,0,395727,0,0,0,395727,0,0,0,395727,0,0,0,395727,0,0,0,395727,0,0,0,395727,0,0,0,395727,0,0,0,395727,0,0,0,395727,0,0,0,395727,0,0,0,395727,0,0,0,395727,0,0,0,395727,0,0,0,395727,0,0,0,395727,0,0,0,395727,0,0,0,395727,0,0,0,395727,0,0,0,395727,0,0,0,395727,0,0,0,395727,0,0,0,395727,0,0,0,0,131073,0,16339,0,131120,0,20839,0,131072,0,21114,0,131237,0,30714,0,131072,0,40992,0,131072,0,9259,0,131076,0,1072,0,131072,0,14816,0,131604,0,58185,0,131072,0,32061,0,131072,0,6986,0,131072,0,29628,0,131073,0,10126,0,131072,0,9301,0,131072,0,30032,0,132233,0,118524,0,131072,0,51718,0,131073,0,8403,0,131072,0,12528,0,132001,0,98176,0,131192,0,17149,0,131072,0,18550,0,131074,0,2484,0,131072,0,26062,0,131192,0,13219,0,131073,0,19536,0,131076,0,64660,0,131072,0,14066,0,131072,0,24045,0,131072,0,37905,0,131072,0,9437,0,131072,0,20744,0,524288,524288,0,67512729,0,0,0,72561970,0,0,0,81769039,0,0,0,81929623,0,0,0,62684041,0,0,0,71955785,0,0,0,90774052,0,0,0,79076497,0,0,0,76950054,0,0,0,78030775,0,0,0,95370013,0,0,0,76524014,0,0,0,75973487,0,0,0,76337660,0,0,0,77958100,0,0,0,77531064,0,0,0,77062539,0,0,0,75274066,0,0,0,77819404,0,0,0,79592719,0,0,0,74853835,0,0,0,75559524,0,0,0,82810373,0,0,0,74488992,0,0,0,75129762,0,0,0,66480981,0,0,0,76678271,0,0,0,71959882,0,0,0,72589966,0,0,0,74237428,0,0,0,87375538,0,0,0,84628882,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,131073,131073,131073,0,131072,131072,131072,0,131072,131072,131072,0,131072,131072,131072,47,131073,131120,131120,0,131072,131072,131072,188,131076,131264,131264,0,131072,131072,131072,0,131072,131072,131072,0,131121,131121,131121,0,131072,131072,131072,0,131699,131699,131699,0,131073,131073,131073,0,131260,131260,131260,0,131072,131072,131072,0,131072,131072,131072,0,131120,131120,131120,0,132009,132009,132009,0,131072,131072,131072,0,131072,131072,131072,0,131072,131072,131072,0,131072,131072,131072,94,131074,131168,131168,0,131927,131927,131927,0,131072,131072,131072,0,131072,131072,131072,188,131076,131264,131264,0,131192,131192,131192,0,131072,131072,131072,0,131072,131072,131072,0,131072,131072,131072,0,131072,131072,131072,131072,0,0,131072,0,0,131072,0,0,131072,0,0,131072,0,0,131072,0,0,131264,0,0,131072,0,0,131072,0,0,131072,0,0,131072,0,0,131072,0,0,131072,0,0,131072,0,0,131072,0,0,131072,0,0,131072,0,0,131072,0,0,131072,0,0,131072,0,0,131072,0,0,131072,0,0,131168,0,0,131072,0,0,131072,0,0,131072,0,0,131264,0,0,131072,0,0,131072,0,0,131072,0,0,131072,0,0,131072,0,0,0,0,131072,65536,6291456,257569619,55991208,195155883,377390,0,0,0,524288,44013267,44011740,0,524288,16384,65536,731,394198,4102,0,48,3145,0,4194784,6422528,3094928,2929881,43721245,4259840,0,0,4718592,33554432,33554432,33554432,0,0,0,0,0,458306,369295,11129,2558,0,382912,4196733,0,517,4196216,983040,0,196608,524288,0,524288,65536,917504,0,0,360,8388608,0,2097152,147135,0,2923,395480,0,4197490,0,0,31,301989888,1245184,0,0,0,65536,65536,0,14469,8233747,0,8388608,2097152,0,0,5102263,0,27132,0,0,0,0,0,0,0,4194304,0,0,0,0,1059020355,3832320624,0,4194304,0,0,0,0,370516,0,0,0,0,0,131072,480,48,0,0,0,528,0,0,0,0,0,1698,0,0,0,4197164,0,5698,0,1245184,1240598,48,7365,201667,0,0,0,0,0,0,0,0,0,327680,0,0,898876,952713,65536,64048,48,1440,0,65536,0,0,0,0,0,0,0,65536,0,0,0,4063255,0,4194304,0,0,32540791,0,0,4197063,0,2038178632,0,12073702582858985,12073729227917790,12073729228048669,12073702584276620
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/prev_analysis/1.csv
index 8b8a66d4ad..6cf3c90065 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<double, 256, 8u, 512u>(double, double*) [clone .kd]",1,6060277.0,6060277.0,6060277.0,9.847195731335022
 "void benchmark_func<double, 256, 8u, 256u>(double, double*) [clone .kd]",1,3055658.0,3055658.0,3055658.0,4.9650638764564246
 "void benchmark_func<__half2, 256, 8u, 512u>(__half2, __half2*) [clone .kd]",1,3047658.0,3047658.0,3047658.0,4.952064872310133
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/prev_analysis/1001.csv
index 1e8362a8e4..c706f4c2f5 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,47.036144578313255,Instr per wave
 SMEM,1.7710843373493976,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/prev_analysis/101.csv
index 24b48c1822..cb07f19bd4 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx908
 mi100
 48
 1228.8
-SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/prev_analysis/1202.csv
index 3e0c88bc19..e3cdeb93d0 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,34039.38846450254,8700.946716308594,547928.248840332,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/prev_analysis/1901.csv
index 9069313100..7211db6356 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,2.0,smem_
 VALU,739.0,valu_
 MFMA,,mfma_
 VMEM,8.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,22.0,br_
 VGPR,24.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,65144.0,wavefronts_
 Workgroups,16286.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,164.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,0.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,45.0,hbm_rd_
 HBM Wr,0.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,70.0,vl1_coales_
 VL1 Stall,31.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,37.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/prev_analysis/2001.csv
index 4544bf0858..8f3ca42ca4 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
 3,"void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 0u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/prev_analysis/201.csv
index 909a98c3c8..22ef6f34f1 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,59.88205636978777,Pct,100,59.88205636978777
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,63.96967548771782,Threads,64,99.9526179495591
 IPC - Issue,0.8432892442629379,Instr/cycle,5,16.86578488525876
-LDS BW,0.0,Gb/sec,23070.72,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,23070.72,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99341044850715,Pct,100,99.99341044850715
 Instr Cache BW,1869.5438313853824,Gb/s,4614.144,40.51767416416528
 Scalar L1D Cache Hit Rate,99.35234690234445,Pct,100,99.35234690234445
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/prev_analysis/602.csv
index 077458a148..b449c1d385 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,55846.48795180723,0,656869,Simd
 Insufficient SIMD VGPRs,623601.4337349398,0,35142593,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/prev_analysis/701.csv
index 878c96c694..aa09824713 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,24.072289156626507,12,36,Registers
 SGPRs,24.0,24,24,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/sysinfo.csv
index ef4061a786..7c328ed8a4 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-K_str_valid_3,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 10:47:55 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+K_str_valid_3,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 10:47:55 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/timestamps.csv
index bcaf6b85d2..41e2f2301d 100644
--- a/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/K_str_valid_3/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,780573,780578,33554432,256,0,0,8,32,6464,0x0,0x7f3ed1804180,12073729212947921,12073729212993521,12073729213317198,12073729213421341
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,780573,780578,32768,256,0,0,24,24,12480,0x0,0x7f3ed1835100,12073729227745721,12073729227849151,12073729227855871,12073729227861747
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,780573,780578,4194304,256,0,0,24,24,12928,0x7f3fdd432900,0x7f3ed1835140,12073729227905658,12073729227917790,12073729228048669,12073729228052201
diff --git a/projects/rocprofiler-compute/tests/workloads/L2/mi100/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/L2/mi100/SQ_IFETCH_LEVEL.csv
index 22145d12ac..abfb2abc8c 100644
--- a/projects/rocprofiler-compute/tests/workloads/L2/mi100/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/L2/mi100/SQ_IFETCH_LEVEL.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,878965,878970,33554432,256,0,0,8,32,6464,0x0,0x7f2dc4404180,503729,503729,524288,6291456,790670,101359200,12075512902723943,12075513148727144,12075513149050342,12075513149160654
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,878965,878970,32768,256,0,0,24,24,12480,0x0,0x7f2dc4435100,27887,27887,512,8192,9675,1239748,12075513163481509,12075513163795496,12075513163801896,12075513163809909
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,878965,878970,4194304,256,0,0,24,24,12928,0x7f2ed00c2900,0x7f2dc4435140,225939,225939,65536,917504,134015,17160796,12075513163869921,12075513164104454,12075513164242693,12075513164246831
diff --git a/projects/rocprofiler-compute/tests/workloads/L2/mi100/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/L2/mi100/SQ_INST_LEVEL_LDS.csv
index 49f8fedcf2..703b66acaf 100644
--- a/projects/rocprofiler-compute/tests/workloads/L2/mi100/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/L2/mi100/SQ_INST_LEVEL_LDS.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,880769,880774,33554432,256,0,0,8,32,6464,0x0,0x7f7857204180,0,0,0,12075539223562575,12075539467660681,12075539467987880,12075539468097332
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,880769,880774,32768,256,0,0,24,24,12480,0x0,0x7f7857235100,0,0,0,12075539482817159,12075539483127613,12075539483134333,12075539483143365
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,880769,880774,4194304,256,0,0,24,24,12928,0x7f79873eb900,0x7f7857235140,0,0,0,12075539483206322,12075539483420572,12075539483552891,12075539483556633
diff --git a/projects/rocprofiler-compute/tests/workloads/L2/mi100/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/L2/mi100/SQ_INST_LEVEL_SMEM.csv
index 60b24202b6..23e306ef81 100644
--- a/projects/rocprofiler-compute/tests/workloads/L2/mi100/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/L2/mi100/SQ_INST_LEVEL_SMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,880391,880396,33554432,256,0,0,8,32,6464,0x0,0x7f2c10c04180,4194304,3146026,402749560,12075536711335293,12075536954971850,12075536955296328,12075536955407670
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,880391,880396,32768,256,0,0,24,24,12480,0x0,0x7f2c10c35100,512,21876,2775000,12075536969889464,12075536970192928,12075536970199328,12075536970212084
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,880391,880396,4194304,256,0,0,24,24,12928,0x7f2d1c80b900,0x7f2c10c35140,65536,170518,21917192,12075536970267747,12075536970478846,12075536970609886,12075536970614381
diff --git a/projects/rocprofiler-compute/tests/workloads/L2/mi100/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/L2/mi100/SQ_INST_LEVEL_VMEM.csv
index 65fca0eec6..2271659699 100644
--- a/projects/rocprofiler-compute/tests/workloads/L2/mi100/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/L2/mi100/SQ_INST_LEVEL_VMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,880581,880586,33554432,256,0,0,8,32,6464,0x0,0x7fe7ed804180,1048576,11078382,1417971496,12075537965584008,12075538208404486,12075538208731365,12075538208839027
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,880581,880586,32768,256,0,0,24,24,12480,0x0,0x7fe7ed835100,4096,117181,14993908,12075538223157086,12075538223463229,12075538223469789,12075538223481179
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,880581,880586,4194304,256,0,0,24,24,12928,0x7fe8f94cc900,0x7fe7ed835140,524288,10299796,1318424996,12075538223533306,12075538223749628,12075538223889627,12075538223893285
diff --git a/projects/rocprofiler-compute/tests/workloads/L2/mi100/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/L2/mi100/SQ_LEVEL_WAVES.csv
index 6b608198cc..ed82e5628d 100644
--- a/projects/rocprofiler-compute/tests/workloads/L2/mi100/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/L2/mi100/SQ_LEVEL_WAVES.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,880957,880964,33554432,256,0,0,8,32,6464,0x0,0x7fbbc9804180,511270,511270,18203,4090168,524288,371009394,3889064,0,1498830132,12075540475152851,12075540722085912,12075540722414550,12075540722536682
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,880957,880964,32768,256,0,0,24,24,12480,0x0,0x7fbbc9835100,28664,28664,21288,229320,512,1163551,79211,0,4668272,12075540737022053,12075540737345759,12075540737352479,12075540737361113
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,880957,880964,4194304,256,0,0,24,24,12928,0x7fbcd54c2900,0x7fbbc9835140,219356,219356,25236,1754856,65536,152021207,1580132,0,609892964,12075540737433828,12075540737667677,12075540737800796,12075540737804818
diff --git a/projects/rocprofiler-compute/tests/workloads/L2/mi100/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/L2/mi100/pmc_dispatch_info.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/L2/mi100/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/L2/mi100/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/L2/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/L2/mi100/pmc_perf.csv
index b193b9992c..95ff90844f 100644
--- a/projects/rocprofiler-compute/tests/workloads/L2/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/L2/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBuffer.kd,0,0,0,879699,879704,33554432,256,0,0,8,32,6464,0x0,0x7ff166a04180,1048576,0,1048576,9437184,0,4194304,1048576,0,507958,507958,58251189,55621489,143,12745093,54721775,54625127,55574938,54398793,4063664,3867868,507958,0,507958,0,16254656,15366904,0,0,0,0,0,16961580,1048576,0,503458,0,0,0,503458,0,0,0,503458,0,0,0,503458,0,0,0,503458,0,0,0,503458,0,0,0,503458,0,0,0,503458,0,0,0,503458,0,0,0,503458,0,0,0,503458,0,0,0,503458,0,0,0,503458,0,0,0,503458,0,0,0,503458,0,0,0,503458,0,0,0,503458,0,0,0,503458,0,0,0,503458,0,0,0,503458,0,0,0,503458,0,0,0,503458,0,0,0,503458,0,0,0,503458,0,0,0,503458,0,0,0,503458,0,0,0,503458,0,0,0,503458,0,0,0,503458,0,0,0,503458,0,0,0,503458,0,0,0,503458,0,0,0,37276925,48,0,0,0,52,0,0,0,0,0,0,0,2730,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,20,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,48,0,0,0,0,0,0,0,2500,0,0,0,0,0,0,0,3,0,0,0,0,0,0,0,2671,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,5,0,0,0,0,0,0,0,0,0,0,0,2588,0,0,0,1048576,0,0,0,131077,131077,0,1456,131072,131072,0,264,131072,131072,0,3136678,131072,131072,0,0,131072,131072,0,0,131072,131072,0,0,131076,131076,0,3003407,131072,131072,0,0,131072,131072,0,0,131072,131072,0,0,131072,131072,0,0,131080,131080,0,0,131076,131076,0,0,131076,131076,0,1487,131076,131076,0,5710,131076,131076,0,0,131076,131076,0,782,131080,131080,0,1771,131072,131072,0,2798926,131072,131072,0,0,131072,131072,0,0,131072,131072,0,14117,131076,131076,0,0,131080,131080,0,1070,131080,131080,0,0,131072,131072,0,259,131072,131072,0,559810,131072,131072,0,0,131072,131072,0,21598,131076,131076,0,0,131076,131076,0,3138368,131072,131072,1048576,0,1072,0,0,16781008,1533,0,0,17063446,1392,0,0,17208415,45821,0,0,29577172,810,0,0,17160252,736,0,0,17305992,1208,0,0,17959098,1586,0,0,18357131,45394,0,0,29465127,1793,0,0,17165398,949,0,0,16899847,665,0,0,16614200,809,0,0,17021728,893,0,0,17364795,967,0,0,18129135,49780,0,0,31620443,1757,0,0,16791513,910,0,0,16715479,1013,0,0,17046159,48557,0,0,30028007,1873,0,0,17304963,1650,0,0,17378563,1584,0,0,17979046,1314,0,0,18686462,874,0,0,16705713,1160,0,0,16926837,843,0,0,16997739,869,0,0,16597278,754,0,0,17077841,1804,0,0,17375117,808,0,0,17915939,1747,0,0,18480255,1048576,131072,133659,2587,264731,131307,131125,288,262432,131072,131072,0,262144,131072,131120,48,262192,131072,133852,2780,264924,131072,131072,0,262144,131072,131075,3,262147,131072,131120,48,262192,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131213,131075,144,262288,131072,131072,0,262144,131119,131073,48,262192,131072,133658,2586,264730,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,133718,2646,264790,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131090,18,262162,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,262144,0,262144,262336,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262288,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,0,0,3145728,524288,32505856,372307531,218034072,121767603,482230,0,0,0,1048576,52315991,52080096,1048576,1048576,131072,524288,739,504678,4278,0,96,10594,0,8388944,32505856,3989024,3776975,56536840,11534336,0,0,14155776,67108864,67108864,0,67108864,53814400,53489783,0,1048576,233249,757537,11764,2399,0,494322,8399407,0,4194727,4204680,13631488,0,3670016,1048576,1048576,0,4194304,9437184,0,0,360,33554432,53995815,4194304,0,0,2804,501596,0,11037,8388608,0,4194379,905969664,6291456,0,0,0,524288,524288,0,15324,16608827,0,16777216,4194304,4194304,0,0,0,16870,4194364,4194364,0,217747,0,0,0,33554432,0,0,0,0,630749172,0,2766769209,0,0,0,0,0,474800,0,0,218484,0,0,8388608,336,144,0,0,0,480,8388608,0,0,0,0,411502,0,0,0,10339,0,20660,0,6291456,6289441,96,2113,2577282,0,0,0,0,0,0,0,0,0,3145728,0,0,0,152746,4194304,4189842,144,4318,2097152,524288,1572864,0,0,0,0,0,0,524288,0,4128825,65535,4063247,0,0,8388608,0,42447525,0,1048576,10369,4194340,12528698,611313458,12075515002634914,12075541612965894,12075541613290531,12075515249946291
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,879699,879704,32768,256,0,0,24,24,12480,0x0,0x7ff166a35100,0,4096,4096,512,0,512,4096,0,29395,29395,1557407,627085,224,150909,92662,69059,619020,598606,235160,89653,29395,0,29395,0,940640,205150,0,0,0,0,0,72479,4096,0,27786,0,0,0,27786,0,0,0,27786,0,0,0,27786,0,0,0,27786,0,0,0,27786,0,0,0,27786,0,0,0,27786,0,0,0,27786,0,0,0,27786,0,0,0,27786,0,0,0,27786,0,0,0,27786,0,0,0,27786,0,0,0,27786,0,0,0,27786,0,0,0,27786,0,0,0,27786,0,0,0,27786,0,0,0,27786,0,0,0,27786,0,0,0,27786,0,0,0,27786,0,0,0,27786,0,0,0,27786,0,0,0,27786,0,0,0,27786,0,0,0,27786,0,0,0,27786,0,0,0,27786,0,0,0,27786,0,0,0,27786,0,0,0,0,256,0,0,0,304,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,378,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,304,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,4096,4096,0,106119,0,0,0,150649,0,0,0,82839,0,0,0,121154,0,0,0,91809,0,0,0,143207,0,0,0,91260,0,0,0,101278,0,0,0,79855,0,0,0,82151,0,0,0,72146,0,0,0,123399,0,0,0,109641,0,0,0,118281,0,0,0,74695,0,0,0,184299,0,0,0,185261,0,0,0,85664,0,0,0,79688,0,0,0,85014,0,0,0,103587,0,0,0,157447,0,0,0,144650,0,0,0,144866,0,0,0,122672,0,0,0,83071,0,0,0,81452,0,0,0,112125,0,0,0,90170,0,0,0,104563,0,0,0,92232,0,0,0,110561,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4096,0,256,256,256,47,305,352,352,0,256,256,256,0,256,256,256,0,257,257,257,0,256,256,256,0,257,257,257,0,304,304,304,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,188,260,448,448,0,256,256,256,0,256,256,256,0,256,256,256,188,260,448,448,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,378,378,378,0,256,256,256,47,257,304,304,0,256,256,256,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,304,0,0,256,0,0,0,0,512,512,35328,1153433,1101552,15529,11564,0,0,0,4096,69616,66564,4096,4096,128,512,648,28264,4369,0,48,220,0,8624,36352,220264,73017,1014846,26624,0,0,30208,65536,65536,65536,0,0,0,0,0,115,627,11666,2387,0,23204,8892,0,470,8422,1024,0,1024,4096,0,4096,512,512,0,0,360,16384,0,16384,0,0,3160,25212,0,8892,0,0,31,1933312,8192,0,0,0,512,512,0,120,15064,0,16384,16384,0,0,0,0,20024,0,0,0,0,0,0,0,32768,0,0,0,0,12704231,17138372,0,8192,0,0,0,0,696,0,0,0,0,0,1024,432,48,0,0,0,480,0,0,0,0,0,3164,0,0,0,8373,0,342,0,8192,6559,48,1585,1082,0,0,0,0,0,0,0,0,0,2560,0,0,0,49984,512,0,48,464,0,512,0,0,0,0,0,0,0,512,0,0,0,0,0,8192,0,0,421085,0,4096,8421,0,3133425,0,12075515264711081,12075541628465232,12075541628472112,12075515265706210
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,879699,879704,4194304,256,0,0,24,24,12928,0x7ff296976900,0x7ff166a35140,0,524288,524288,65536,0,65536,524288,0,222458,222458,24614987,23394846,31190,7398768,22871748,22785840,23385488,21221384,1779664,1625005,222458,0,222458,0,7118656,6372852,0,0,0,0,0,19817635,524288,0,211062,0,0,0,211062,0,0,0,211062,0,0,0,211062,0,0,0,211062,0,0,0,211062,0,0,0,211062,0,0,0,211062,0,0,0,211062,0,0,0,211062,0,0,0,211062,0,0,0,211062,0,0,0,211062,0,0,0,211062,0,0,0,211062,0,0,0,211062,0,0,0,211062,0,0,0,211062,0,0,0,211062,0,0,0,211062,0,0,0,211062,0,0,0,211062,0,0,0,211062,0,0,0,211062,0,0,0,211062,0,0,0,211062,0,0,0,211062,0,0,0,211062,0,0,0,211062,0,0,0,211062,0,0,0,211062,0,0,0,211062,0,0,0,0,65536,0,12567,0,65584,0,9185,0,65540,0,3055,0,65536,0,7190,0,65537,0,21105,0,65536,0,25631,0,65536,0,8829,0,65536,0,3869,0,65658,0,22484,0,65536,0,12688,0,65536,0,10624,0,65536,0,13727,0,65536,0,8376,0,65584,0,25535,0,65536,0,7437,0,66209,0,59804,0,65536,0,14790,0,65536,0,9965,0,65536,0,6598,0,67478,0,56531,0,65536,0,4457,0,65536,0,14087,0,65536,0,1105,0,65536,0,3586,0,65536,0,12986,0,65536,0,30354,0,65537,0,4362,0,65536,0,11772,0,65536,0,17814,0,65536,0,50189,0,65540,0,32086,0,65536,0,12451,0,524288,524288,0,21982358,0,0,0,22849491,0,0,0,22096553,0,0,0,42990795,0,0,0,24702409,0,0,0,22024933,0,0,0,25308042,0,0,0,24938531,0,0,0,22485518,0,0,0,22587688,0,0,0,23051435,0,0,0,23284372,0,0,0,23698004,0,0,0,23747464,0,0,0,25445512,0,0,0,24438316,0,0,0,22814517,0,0,0,23017138,0,0,0,20487178,0,0,0,48410756,0,0,0,23060737,0,0,0,24310768,0,0,0,23336375,0,0,0,22852880,0,0,0,24456449,0,0,0,24358678,0,0,0,22579536,0,0,0,23060593,0,0,0,24313781,0,0,0,23550189,0,0,0,23906127,0,0,0,23733497,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,524288,0,66498,66498,66498,47,65585,65632,65632,188,65540,65728,65728,0,65536,65536,65536,0,65537,65537,65537,0,65536,65536,65536,0,65537,65537,65537,0,65584,65584,65584,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65833,65833,65833,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65658,65658,65658,0,65536,65536,65536,188,65540,65728,65728,0,65536,65536,65536,65536,0,0,65536,0,0,65728,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65728,0,0,65536,0,0,0,0,65536,65536,4128768,130979109,45356323,81362946,208745,0,0,0,524288,22919786,22910078,524288,524288,16384,65536,701,228858,4282,0,48,4688,0,2097536,4259840,1720928,1553491,22965342,3014656,0,0,3473408,8388608,8388608,8388608,0,0,0,0,0,186999,212015,11848,2559,0,211000,2099680,0,423,2099257,131072,0,131072,524288,0,524288,65536,65536,0,0,360,2097152,0,2097152,32973,0,2823,220727,0,2101274,0,0,31,222298112,917504,0,0,0,65536,65536,0,7566,2019784,0,2097152,2097152,0,930174,933510,0,21248,0,0,0,0,0,0,0,4194304,0,0,0,0,1031896996,1687565251,0,2097152,0,0,0,0,194241,0,0,0,0,0,131072,384,48,0,0,0,432,0,0,0,0,0,9655,0,0,0,2101199,0,8076,0,917504,914605,48,7653,183403,0,0,0,0,0,0,0,0,0,327680,0,0,606507,659797,65536,64048,48,1440,0,65536,0,0,0,0,0,0,0,65536,0,0,0,1966092,0,2097152,0,0,15287655,0,524288,2101271,0,942174874,0,12075515266337163,12075541628536752,12075541628671150,12075515267593818
diff --git a/projects/rocprofiler-compute/tests/workloads/L2/mi100/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/L2/mi100/prev_analysis/1.csv
index 70434364c4..29dcf3ce09 100644
--- a/projects/rocprofiler-compute/tests/workloads/L2/mi100/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/L2/mi100/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,6054191.0,6054191.0,6054191.0,9.190496154853548
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4526683.0,4526683.0,4526683.0,6.871679916563736
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 256u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,3050055.0,3050055.0,3050055.0,4.630101486654755
diff --git a/projects/rocprofiler-compute/tests/workloads/L2/mi100/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/L2/mi100/prev_analysis/1001.csv
index ca08330db0..0e3bf5267e 100644
--- a/projects/rocprofiler-compute/tests/workloads/L2/mi100/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/L2/mi100/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,46.862275449101794,Instr per wave
 SMEM,1.8083832335329342,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/L2/mi100/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/L2/mi100/prev_analysis/101.csv
index 019645cdf0..c80065914e 100644
--- a/projects/rocprofiler-compute/tests/workloads/L2/mi100/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/L2/mi100/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx908
 mi100
 48
 1228.8
-SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/L2/mi100/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/L2/mi100/prev_analysis/1202.csv
index 70d42485d1..ca39aace4f 100644
--- a/projects/rocprofiler-compute/tests/workloads/L2/mi100/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/L2/mi100/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,33802.98853905044,2840.48104095459,547996.350402832,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/L2/mi100/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/L2/mi100/prev_analysis/1901.csv
index 3c5fd28c9b..65df9e05ee 100644
--- a/projects/rocprofiler-compute/tests/workloads/L2/mi100/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/L2/mi100/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,2.0,smem_
 VALU,735.0,valu_
 MFMA,,mfma_
 VMEM,8.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,22.0,br_
 VGPR,24.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,67894.0,wavefronts_
 Workgroups,16973.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,163.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,0.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,44.0,hbm_rd_
 HBM Wr,0.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,70.0,vl1_coales_
 VL1 Stall,31.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,37.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/L2/mi100/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/L2/mi100/prev_analysis/2001.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/L2/mi100/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/L2/mi100/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/L2/mi100/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/L2/mi100/prev_analysis/201.csv
index f4a611a70b..b3aafc06be 100644
--- a/projects/rocprofiler-compute/tests/workloads/L2/mi100/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/L2/mi100/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,59.72477580210259,Pct,100,59.72477580210259
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,63.9694788137774,Threads,64,99.95231064652718
 IPC - Issue,0.84374103503627,Instr/cycle,5,16.8748207007254
-LDS BW,0.0,Gb/sec,23070.72,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,23070.72,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99342783786308,Pct,100,99.99342783786308
 Instr Cache BW,1412.9778922668122,Gb/s,4614.144,30.622752394958027
 Scalar L1D Cache Hit Rate,99.35620448517078,Pct,100,99.35620448517078
diff --git a/projects/rocprofiler-compute/tests/workloads/L2/mi100/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/L2/mi100/prev_analysis/602.csv
index ff48f257c9..b15988526f 100644
--- a/projects/rocprofiler-compute/tests/workloads/L2/mi100/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/L2/mi100/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,67112.53892215568,0,935164,Simd
 Insufficient SIMD VGPRs,577840.125748503,0,36598405,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/L2/mi100/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/L2/mi100/prev_analysis/701.csv
index d3f1bff5a3..1071413faa 100644
--- a/projects/rocprofiler-compute/tests/workloads/L2/mi100/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/L2/mi100/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,23.976047904191617,8,36,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/L2/mi100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/L2/mi100/sysinfo.csv
index 610ef9bd10..383131c818 100644
--- a/projects/rocprofiler-compute/tests/workloads/L2/mi100/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/L2/mi100/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-L2,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 11:18:07 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+L2,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 11:18:07 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/L2/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/L2/mi100/timestamps.csv
index c908b809b6..0032bc2104 100644
--- a/projects/rocprofiler-compute/tests/workloads/L2/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/L2/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,881008,881013,33554432,256,0,0,8,32,6464,0x0,0x7f1646a04180,12075541612917956,12075541612965894,12075541613290531,12075541613400493
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,881008,881013,32768,256,0,0,24,24,12480,0x0,0x7f1646a35100,12075541628364443,12075541628465232,12075541628472112,12075541628477513
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,881008,881013,4194304,256,0,0,24,24,12928,0x7f17769fb900,0x7f1646a35140,12075541628523428,12075541628536752,12075541628671150,12075541628674439
diff --git a/projects/rocprofiler-compute/tests/workloads/L2/mi200/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/L2/mi200/SQ_IFETCH_LEVEL.csv
index 0bf522d379..342204f977 100644
--- a/projects/rocprofiler-compute/tests/workloads/L2/mi200/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/L2/mi200/SQ_IFETCH_LEVEL.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,175157,175157,33554432,256,0,0,4,32,4160,0x0,0x7fc664e04280,380929,380929,524288,4718592,683147,76438696,16791755331355,16791047155631,16791901760418,16791901870857
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,175157,175157,32768,256,0,0,12,24,13888,0x0,0x7fc664e23f80,33336,33336,512,8192,5565,633828,16791907048544,16791901760418,16791907182478,16791907187250
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,175157,175157,4194304,256,0,0,12,24,14336,0x7fc667eb5380,0x7fc664e23fc0,164297,164297,65536,917504,142023,15909444,16791907224319,16791907182478,16791907560396,16791907563038
diff --git a/projects/rocprofiler-compute/tests/workloads/L2/mi200/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/L2/mi200/SQ_INST_LEVEL_LDS.csv
index 20a7c5a833..2621139a40 100644
--- a/projects/rocprofiler-compute/tests/workloads/L2/mi200/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/L2/mi200/SQ_INST_LEVEL_LDS.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,177005,177005,33554432,256,0,0,4,32,4160,0x0,0x7ff270c04280,0,0,0,16811153277662,16810443849877,16811301498942,16811301584321
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,177005,177005,32768,256,0,0,12,24,13888,0x0,0x7ff270c23f80,0,0,0,16811306763779,16811301498942,16811306891077,16811306895955
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,177005,177005,4194304,256,0,0,12,24,14336,0x7ff273ce5380,0x7ff270c23fc0,0,0,0,16811306930984,16811306891077,16811307257476,16811307260064
diff --git a/projects/rocprofiler-compute/tests/workloads/L2/mi200/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/L2/mi200/SQ_INST_LEVEL_SMEM.csv
index cb8aca0cd7..7ce0a27b76 100644
--- a/projects/rocprofiler-compute/tests/workloads/L2/mi200/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/L2/mi200/SQ_INST_LEVEL_SMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,174935,174935,33554432,256,0,0,4,32,4160,0x0,0x7f090be04280,3670016,3123906,349239680,16790822424947,16785324886982,16790967861419,16790967975528
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,174935,174935,32768,256,0,0,12,24,13888,0x0,0x7f090be23f80,512,98092,10976944,16790973109527,16790967861419,16790973234676,16790973239113
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,174935,174935,4194304,256,0,0,12,24,14336,0x7f091a6f6380,0x7f090be23fc0,65536,651948,72985536,16790973273982,16790973234676,16790973592274,16790973594531
diff --git a/projects/rocprofiler-compute/tests/workloads/L2/mi200/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/L2/mi200/SQ_INST_LEVEL_VMEM.csv
index 7dc34f0935..9947e42aa6 100644
--- a/projects/rocprofiler-compute/tests/workloads/L2/mi200/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/L2/mi200/SQ_INST_LEVEL_VMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,176783,176783,33554432,256,0,0,4,32,4160,0x0,0x7fcb9c804280,524288,5478000,613454648,16810213261190,16807892511106,16810364459955,16810364571254
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,176783,176783,32768,256,0,0,12,24,13888,0x0,0x7fcb9c823f80,4096,35204,3946644,16810369719563,16810364459955,16810369846011,16810369850749
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,176783,176783,4194304,256,0,0,12,24,14336,0x7fcb9f733380,0x7fcb9c823fc0,524288,10762506,1205314288,16810369884598,16810369846011,16810370212570,16810370214988
diff --git a/projects/rocprofiler-compute/tests/workloads/L2/mi200/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/L2/mi200/SQ_LEVEL_WAVES.csv
index 64eb793114..caf2d4c281 100644
--- a/projects/rocprofiler-compute/tests/workloads/L2/mi200/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/L2/mi200/SQ_LEVEL_WAVES.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,175379,175379,33554432,256,0,0,4,32,4160,0x0,0x7fce3f804280,380644,380644,8666,3045160,524288,238245177,2959012,0,969233460,16792691334909,16791983173970,16792834490537,16792834600426
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,175379,175379,32768,256,0,0,12,24,13888,0x0,0x7fce3f823f80,33369,33369,29853,266960,512,1661479,164195,0,6659136,16792839726115,16792834490537,16792839860756,16792839865120
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,175379,175379,4194304,256,0,0,12,24,14336,0x7fcf4a0c6380,0x7fce3f823fc0,168953,168953,15194,1351632,65536,94817324,1245795,0,381000384,16792839908649,16792839860756,16792840256915,16792840259288
diff --git a/projects/rocprofiler-compute/tests/workloads/L2/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/L2/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/L2/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/L2/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/L2/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/L2/mi200/pmc_perf.csv
index bf2bf0661b..55225491f3 100644
--- a/projects/rocprofiler-compute/tests/workloads/L2/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/L2/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDI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],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBufferAligned.kd,0,0,0,176145,176145,33554432,256,0,0,4,32,4160,0x0,0x7f8ea2004280,3078560,2988849,524288,38833408,243020419,392,224,0,384819,384819,39097895.0,38049577.0,8.0,4152095.0,31184183.0,30822792.0,38028366.0,37470147.0,3076849,2995249,384819,0,384819,0,12314208.0,9481949.0,0.0,0.0,0,0,616,0,4718592,4714949,112,3531,377162,0.0,0.0,0.0,524288.0,28619027.0,27899431.0,7668.0,524288.0,131072,524288,301,386309,2298,0,56.0,305.0,0.0,4194696.0,0,0,0,0,0,7340032,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,20084778.0,524288.0,0,383820,0,0,0,383820,0,0,0,383820,0,0,0,383820,0,0,0,383820,0,0,0,383820,0,0,0,383820,0,0,0,383820,0,0,0,383820,0,0,0,383820,0,0,0,383820,0,0,0,383820,0,0,0,383820,0,0,0,383820,0,0,0,383820,0,0,0,383820,0,0,0,383820,0,0,0,383820,0,0,0,383820,0,0,0,383820,0,0,0,383820,0,0,0,383820,0,0,0,383820,0,0,0,383820,0,0,0,383820,0,0,0,383820,0,0,0,383820,0,0,0,383820,0,0,0,383820,0,0,0,383820,0,0,0,383820,0,0,0,383820,0,0,0,0,0,0.0,21244574.0,32,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,32,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,36,0,0,0,0,0,0,0,0,0,0,0,57,0,0,0,8,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,113,0,0,0,524288.0,0.0,0,45111,129024,129024,0,0,129024,129024,0,0,129024,129024,0,1049,129024,129024,0,331,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,502737,129024,129024,0,43062,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,27018,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,1040,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,46481,129024,129024,0,0,129024,129024,0,171,129024,129024,0,282567,129024,129024,0,187,129024,129024,524288.0,0.0,43943,0,0,50606220,45106,0,0,50727342,44563,0,0,50293656,46642,0,0,51695991,45011,0,0,51340525,45905,0,0,51359978,44642,0,0,50856587,47916,0,0,52869545,45082,0,0,50763019,46779,0,0,51231803,44658,0,0,50271844,47601,0,0,52333777,46040,0,0,51462443,47328,0,0,51682419,46038,0,0,51353943,47894,0,0,52988467,45219,0,0,50805846,46284,0,0,50934138,44315,0,0,50271421,47074,0,0,51969644,45893,0,0,51669803,46693,0,0,51661427,44010,0,0,50543086,48789,0,0,53202595,45686,0,0,51017277,45944,0,0,50906286,45089,0,0,50396823,48381,0,0,52460417,45197,0,0,51525100,46903,0,0,51720949,44983,0,0,51032374,47504,0,0,52948331,0.0,65536,65568,32,131104,65536,65536,0,131072,65536,65536,0,131072,65536,65537,1,131073,65646,65538,112,131184,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65568,32,131104,65536,65536,0,131072,65536,65536,0,131072,65591,65537,56,131128,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65571,35,131107,65536,65648,112,131184,65536,65536,0,131072,65536,65536,0,131072,65758,65539,225,131297,65536,65536,0,131072,65536,65536,0,131072,65536,65537,1,131073,65536,65536,0,131072,65536,65624,88,131160,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65591,65537,56,131128,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131184,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131296,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131128,0,131072,1047643,0,524288,3670016,3663327,224,6465,1048576,33554432.0,33554432.0,0.0,33554432.0,30075834.0,28429747.0,0.0,524288.0,216205,536767,8631,923,0,383016,4195055.0,0.0,2097594.0,2097461.0,1048576,1048576,0,524288,0,524288,7340032,0,0.0,0.0,104.0,8388608.0,29463147.0,2097152.0,0.0,200978,0,1220,383304,0,750.0,4194304.0,0.0,2064387.0,25690112,9437184,0,0,0,0,0,0,13272.0,8242616.0,0.0,8388608.0,2097152.0,4194304.0,10198978,0,0,8771,4128768.0,4128768.0,0.0,1540826.0,0,0,0,0,0,0,5767168,1048576,321674272.0,0.0,1492698306.0,0.0,17.0,0.0,0,0,384084,0.0,0.0,1552673.0,0.0,3670016,524288,0,0,0,2621440,524288,179166775,4194304.0,0.0,0.0,0.0,0.0,1154078.0,0,0,0.0,312.0,0.0,608.0,43920481,24117248,0,0,9437184,11010048,0,3145728,0.0,0.0,0.0,0.0,0.0,0.0,0,1572864,0.0,0.0,0.0,191176.0,524288,524288,0,3670016,7340032,603979776,4718592,0,0.0,0.0,0.0,0.0,0.0,0.0,524288,0,2064384.0,0.0,2031623.0,0.0,0,0,524288,0,0,0,0,33554432,0.0,4194304.0,0.0,18995009.0,0.0,0.0,143.0,4128768.0,656479.0,1698825285.0,16794117409219,16811968824945,16811969064464,16794261049807
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,176145,176145,32768,256,0,0,12,24,13888,0x0,0x7f8ea2023f80,266664,163597,512,1442521,1784914,504,56,0,33332,33332,2358395.0,151387.0,167.0,0.0,36812.0,33703.0,145060.0,126278.0,266656,170590,33332,0,33332,0,1066624.0,374035.0,0.0,0.0,0,0,560,0,8192,6174,56,1962,23451,0.0,0.0,0.0,4096.0,37719.0,36315.0,0.0,4096.0,128,512,302,33084,2606,0,0.0,60.0,0.0,4600.0,0,0,0,0,0,1024,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,16860.0,4096.0,0,32756,0,0,0,32756,0,0,0,32756,0,0,0,32756,0,0,0,32756,0,0,0,32756,0,0,0,32756,0,0,0,32756,0,0,0,32756,0,0,0,32756,0,0,0,32756,0,0,0,32756,0,0,0,32756,0,0,0,32756,0,0,0,32756,0,0,0,32756,0,0,0,32756,0,0,0,32756,0,0,0,32756,0,0,0,32756,0,0,0,32756,0,0,0,32756,0,0,0,32756,0,0,0,32756,0,0,0,32756,0,0,0,32756,0,0,0,32756,0,0,0,32756,0,0,0,32756,0,0,0,32756,0,0,0,32756,0,0,0,32756,0,0,0,0,0,0.0,0.0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,258,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,257,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,312,0,0,0,4096.0,4096.0,0,123511,0,0,0,79597,0,0,0,89837,0,0,0,81351,0,0,0,86667,0,0,0,81372,0,0,0,80114,0,0,0,84260,0,0,0,647310,0,0,0,75101,0,0,0,77714,0,0,0,85331,0,0,0,78574,0,0,0,90048,0,0,0,96876,0,0,0,84565,0,0,0,78875,0,0,0,80552,0,0,0,84640,0,0,0,119474,0,0,0,79550,0,0,0,104765,0,0,0,76788,0,0,0,99184,0,0,0,80788,0,0,0,76636,0,0,0,76944,0,0,0,79281,0,0,0,74709,0,0,0,79304,0,0,0,79427,0,0,0,87878,0,0,0.0,0.0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4096.0,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,222,130,352,352,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,222,130,352,352,0,128,128,128,0,128,128,128,0,128,128,128,0,129,129,129,0,184,184,184,0,128,128,128,0,128,128,128,0,129,129,129,55,129,184,184,0,128,128,128,0,129,129,129,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,352,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,352,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,184,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,662,0,0,512,0,56,456,0,65536.0,65536.0,65536.0,0.0,0.0,0.0,0.0,0.0,6,518,11428,1145,0,31108,4659.0,0.0,499.0,4160.0,512,0,0,0,4096,4096,512,0,0.0,0.0,104.0,16384.0,0.0,16384.0,4096.0,0,0,1341,31864,0,4660.0,0.0,0.0,31.0,35328,26112,0,0,0,0,0,0,104.0,15240.0,0.0,16384.0,16384.0,0.0,0,0,0,29343,0.0,0.0,0.0,0.0,0,0,0,0,0,0,10752,3584,4184291.0,5475169.0,0.0,8192.0,2.0,0.0,0,0,496,0.0,0.0,0.0,0.0,512,4096,0,0,0,512,512,1741594,0.0,0.0,0.0,0.0,0.0,1379.0,0,0,0.0,8261.0,0.0,120.0,15439,32256,0,0,26112,1024,0,1024,0.0,0.0,0.0,0.0,0.0,0.0,0,1024,0.0,0.0,0.0,32751.0,4096,0,4096,512,512,1671168,8192,0,0.0,0.0,0.0,0.0,0.0,0.0,512,0,0.0,0.0,0.0,0.0,0,0,512,0,0,0,0,32768,8192.0,0.0,0.0,123189.0,0.0,4096.0,8204.0,0.0,3285155.0,0.0,16794267230693,16811973896601,16811973909720,16794267713938
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,176145,176145,4194304,256,0,0,12,24,14336,0x7f8ea4f62380,0x7f8ea2023fc0,1318120,1208067,65536,15637970,70179938,392,56,0,164764,164764,15939600.0,14501333.0,24537.0,429395.0,12248897.0,11724840.0,14494708.0,12356939.0,1318112,1215344,164764,0,164764,0,5272448.0,4742868.0,0.0,0.0,0,0,448,0,917504,913917,0,3587,155042,0.0,0.0,0.0,524288.0,12415001.0,12373238.0,2144.0,524288.0,16384,65536,302,166124,2634,0,0.0,182.0,0.0,1048968.0,0,0,0,0,0,131072,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,9626247.0,524288.0,0,172413,0,0,0,172413,0,0,0,172413,0,0,0,172413,0,0,0,172413,0,0,0,172413,0,0,0,172413,0,0,0,172413,0,0,0,172413,0,0,0,172413,0,0,0,172413,0,0,0,172413,0,0,0,172413,0,0,0,172413,0,0,0,172413,0,0,0,172413,0,0,0,172413,0,0,0,172413,0,0,0,172413,0,0,0,172413,0,0,0,172413,0,0,0,172413,0,0,0,172413,0,0,0,172413,0,0,0,172413,0,0,0,172413,0,0,0,172413,0,0,0,172413,0,0,0,172413,0,0,0,172413,0,0,0,172413,0,0,0,172413,0,0,0,0,0,0.0,0.0,65536,0,18711,0,65538,0,16333,0,65536,0,13234,0,65536,0,17690,0,65536,0,18386,0,65536,0,11789,0,65536,0,16920,0,65540,0,15891,0,65536,0,19574,0,65536,0,17515,0,65536,0,17152,0,65536,0,24632,0,65536,0,25391,0,65536,0,8702,0,65536,0,17615,0,65536,0,21552,0,65536,0,23325,0,65536,0,21681,0,65597,0,9998,0,65536,0,17167,0,65539,0,26160,0,65539,0,24517,0,65538,0,8033,0,65539,0,21459,0,65540,0,23354,0,65537,0,13229,0,65536,0,13886,0,65599,0,16601,0,65536,0,27632,0,65538,0,12023,0,65536,0,19830,0,65649,0,17024,0,524288.0,524288.0,0,42006295,0,0,0,38590400,0,0,0,39592202,0,0,0,46261555,0,0,0,42880191,0,0,0,48073503,0,0,0,44117444,0,0,0,47937731,0,0,0,41674651,0,0,0,41392154,0,0,0,44782663,0,0,0,39075812,0,0,0,43182593,0,0,0,38975329,0,0,0,41306029,0,0,0,49029743,0,0,0,46912553,0,0,0,45861380,0,0,0,38390450,0,0,0,41684644,0,0,0,47058217,0,0,0,39324016,0,0,0,45113423,0,0,0,39036690,0,0,0,35367743,0,0,0,45775302,0,0,0,36402577,0,0,0,43745714,0,0,0,42123142,0,0,0,38780054,0,0,0,39797830,0,0,0,46750778,0,0,0.0,0.0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,524288.0,0,32768,32768,32768,0,32770,32770,32770,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32826,32826,32826,0,32824,32824,32824,0,32768,32768,32768,0,32768,32768,32768,0,32769,32769,32769,166,32770,32936,32936,222,32770,32992,32992,0,32769,32769,32769,0,32768,32768,32768,0,32830,32830,32830,0,32768,32768,32768,0,32769,32769,32769,0,32768,32768,32768,0,32768,32768,32768,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32936,0,0,32992,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,903126,0,0,65536,63800,56,1680,0,8388608.0,8388608.0,8388608.0,0.0,0.0,0.0,0.0,0.0,125524,147966,9629,2193,0,161468,1049152.0,0.0,388.0,1048764.0,65536,0,0,0,524288,524288,131072,0,0.0,0.0,104.0,2097152.0,0.0,2097152.0,524288.0,42142,0,2372,161975,0,1049155.0,0.0,0.0,31.0,4063232,2883584,0,0,0,0,0,0,6593.0,2027826.0,0.0,2097152.0,2097152.0,0.0,1378685,0,0,14190,0.0,0.0,0.0,0.0,262144,0,0,0,0,0,1507328,458752,959599092.0,2304591299.0,0.0,2097152.0,71.0,0.0,0,0,146825,0.0,0.0,0.0,0.0,65536,524288,0,0,0,65536,65536,48761833,0.0,0.0,0.0,0.0,0.0,20966.0,0,0,0.0,2097347.0,0.0,376.0,19511924,3735552,0,0,2883584,196608,0,131072,0.0,0.0,0.0,0.0,0.0,0.0,0,131072,0.0,0.0,585180.0,1758167.0,524288,0,524288,65536,131072,184549376,917504,0,0.0,0.0,0.0,0.0,0.0,0.0,65536,0,0.0,0.0,983047.0,0.0,0,0,65536,0,0,0,0,4194304,2097152.0,0.0,0.0,12330781.0,0.0,524288.0,2097289.0,0.0,1480425963.0,0.0,16794268811433,16811973977400,16811974069880,16794269562990
diff --git a/projects/rocprofiler-compute/tests/workloads/L2/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/L2/mi200/prev_analysis/1.csv
index ff90bc1254..4753f9661f 100644
--- a/projects/rocprofiler-compute/tests/workloads/L2/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/L2/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,3357424.0,3357424.0,3357424.0,7.846862058227441
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,1725112.0,1725112.0,1725112.0,4.031875598373294
 "void benchmark_func<double, 256, 8u, 512u>(double, double*) [clone .kd]",1,1714712.0,1714712.0,1714712.0,4.007569056987528
diff --git a/projects/rocprofiler-compute/tests/workloads/L2/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/L2/mi200/prev_analysis/1001.csv
index f475f954a6..fb5988001a 100644
--- a/projects/rocprofiler-compute/tests/workloads/L2/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/L2/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,494.8622754491018,Instr per wave
 VMEM,7.958083832335329,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,0.0,Instr per wave
 SALU,24.520958083832337,Instr per wave
 SMEM,1.8023952095808384,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/L2/mi200/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/L2/mi200/prev_analysis/101.csv
index a39202d26c..9011f18558 100644
--- a/projects/rocprofiler-compute/tests/workloads/L2/mi200/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/L2/mi200/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx90a
 mi200
 56
 1638.4
-roofline|SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+roofline|SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/L2/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/L2/mi200/prev_analysis/1202.csv
index b28bf460c3..047c2e41aa 100644
--- a/projects/rocprofiler-compute/tests/workloads/L2/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/L2/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,18181.03086747952,1854.0986557006836,258197.27294921875,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/L2/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/L2/mi200/prev_analysis/1901.csv
index 954833afb2..3e930b6d76 100644
--- a/projects/rocprofiler-compute/tests/workloads/L2/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/L2/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,2.0,smem_
 VALU,495.0,valu_
 MFMA,0.0,mfma_
 VMEM,8.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,10.0,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,67894.0,wavefronts_
 Workgroups,16973.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,128.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,0.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,44.0,hbm_rd_
 HBM Wr,0.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,70.0,vl1_coales_
 VL1 Stall,2.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,26.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/L2/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/L2/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/L2/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/L2/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/L2/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/L2/mi200/prev_analysis/201.csv
index eaa2a9e4f3..f4c091fa7c 100644
--- a/projects/rocprofiler-compute/tests/workloads/L2/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/L2/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,58.302235295342015,Pct,100,58.302235295342015
 MFMA Util,0.0,Pct,100,0.0
 VALU Active Threads/Wave,64.0,Threads,64,100.0
 IPC - Issue,1.0,Instr/cycle,5,20.0
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99255834735887,Pct,100,99.99255834735887
 Instr Cache BW,1675.4235970503782,Gb/s,6092.8,27.49841775621025
 Scalar L1D Cache Hit Rate,99.3485588607737,Pct,100,99.3485588607737
diff --git a/projects/rocprofiler-compute/tests/workloads/L2/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/L2/mi200/prev_analysis/602.csv
index 115e18fb04..98d1df2460 100644
--- a/projects/rocprofiler-compute/tests/workloads/L2/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/L2/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,12681603.532934131,0,383527713,Simd
 Insufficient SIMD VGPRs,0.0,0,0,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/L2/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/L2/mi200/prev_analysis/701.csv
index 12250d77c0..db0925a109 100644
--- a/projects/rocprofiler-compute/tests/workloads/L2/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/L2/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/L2/mi200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/L2/mi200/sysinfo.csv
index d01d301617..deca95e079 100644
--- a/projects/rocprofiler-compute/tests/workloads/L2/mi200/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/L2/mi200/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-L2,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:33:11 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,roofline|SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+L2,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:33:11 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,roofline|SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/L2/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/L2/mi200/timestamps.csv
index 364a3528e7..339bf46934 100644
--- a/projects/rocprofiler-compute/tests/workloads/L2/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/L2/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,177088,177088,33554432,256,0,0,4,32,4160,0x0,0x7f0d5c804280,16811968799934,16811968824945,16811969064464,16811969154652
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,177088,177088,32768,256,0,0,12,24,13888,0x0,0x7f0d5c823f80,16811973880645,16811973896601,16811973909720,16811973927494
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,177088,177088,4194304,256,0,0,12,24,14336,0x7f0d5f807380,0x7f0d5c823fc0,16811973932533,16811973977400,16811974069880,16811974072089
diff --git a/projects/rocprofiler-compute/tests/workloads/LDS/mi100/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/LDS/mi100/SQ_IFETCH_LEVEL.csv
index 1b998d7826..b4d35b0bdb 100644
--- a/projects/rocprofiler-compute/tests/workloads/LDS/mi100/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/LDS/mi100/SQ_IFETCH_LEVEL.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,884232,884237,33554432,256,0,0,8,32,6464,0x0,0x7f8d4aa04180,503521,503521,524288,6291456,791867,101527648,12075619663348244,12075619911524059,12075619911847417,12075619911960749
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,884232,884237,32768,256,0,0,24,24,12480,0x0,0x7f8d4aa35100,28048,28048,512,8192,8896,1125388,12075619926497405,12075619926825017,12075619926831737,12075619926840142
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,884232,884237,4194304,256,0,0,24,24,12928,0x7f8e566fa900,0x7f8d4aa35140,220203,220203,65536,917504,140683,17968308,12075619926896707,12075619927139096,12075619927273495,12075619927276994
diff --git a/projects/rocprofiler-compute/tests/workloads/LDS/mi100/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/LDS/mi100/SQ_INST_LEVEL_LDS.csv
index e1f13ac4b6..c4439cfdd1 100644
--- a/projects/rocprofiler-compute/tests/workloads/LDS/mi100/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/LDS/mi100/SQ_INST_LEVEL_LDS.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,886028,886033,33554432,256,0,0,8,32,6464,0x0,0x7fcf4e404180,0,0,0,12075646180516257,12075646424410985,12075646424734184,12075646424847586
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,886028,886033,32768,256,0,0,24,24,12480,0x0,0x7fcf4e435100,0,0,0,12075646439713714,12075646440027638,12075646440034358,12075646440043206
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,886028,886033,4194304,256,0,0,24,24,12928,0x7fd05a091900,0x7fcf4e435140,0,0,0,12075646440101765,12075646440321077,12075646440454677,12075646440458067
diff --git a/projects/rocprofiler-compute/tests/workloads/LDS/mi100/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/LDS/mi100/SQ_INST_LEVEL_SMEM.csv
index 76b923d5dd..28fb1d30d7 100644
--- a/projects/rocprofiler-compute/tests/workloads/LDS/mi100/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/LDS/mi100/SQ_INST_LEVEL_SMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,885650,885655,33554432,256,0,0,8,32,6464,0x0,0x7f3db2804180,4194304,3150786,403220608,12075643646573035,12075643891053217,12075643891374335,12075643891492447
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,885650,885655,32768,256,0,0,24,24,12480,0x0,0x7f3db2835100,512,21880,2779208,12075643906340522,12075643906646578,12075643906653138,12075643906665255
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,885650,885655,4194304,256,0,0,24,24,12928,0x7f3ebe4d9900,0x7f3db2835140,65536,196232,25070520,12075643906724375,12075643906937777,12075643907077616,12075643907082491
diff --git a/projects/rocprofiler-compute/tests/workloads/LDS/mi100/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/LDS/mi100/SQ_INST_LEVEL_VMEM.csv
index 12287faee6..2023b104ea 100644
--- a/projects/rocprofiler-compute/tests/workloads/LDS/mi100/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/LDS/mi100/SQ_INST_LEVEL_VMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,885840,885845,33554432,256,0,0,8,32,6464,0x0,0x7fef7d404180,1048576,11091777,1419101252,12075644913284723,12075645156991230,12075645157319388,12075645157431910
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,885840,885845,32768,256,0,0,24,24,12480,0x0,0x7fef7d435100,4096,104499,13386952,12075645172226194,12075645172532828,12075645172539068,12075645172547591
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,885840,885845,4194304,256,0,0,24,24,12928,0x7ff088fa9900,0x7fef7d435140,524288,12304897,1575006532,12075645172600981,12075645172823226,12075645172955386,12075645172958906
diff --git a/projects/rocprofiler-compute/tests/workloads/LDS/mi100/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/LDS/mi100/SQ_LEVEL_WAVES.csv
index f05aa7ca2d..1971246f8d 100644
--- a/projects/rocprofiler-compute/tests/workloads/LDS/mi100/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/LDS/mi100/SQ_LEVEL_WAVES.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,886218,886223,33554432,256,0,0,8,32,6464,0x0,0x7f36e2c04180,507439,507439,16865,4059520,524288,379327981,3860712,0,1532115384,12075647438667565,12075647681960945,12075647682287663,12075647682401904
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,886218,886223,32768,256,0,0,24,24,12480,0x0,0x7f36e2c35100,27723,27723,20592,221792,512,1180779,78189,0,4737472,12075647697074733,12075647697402191,12075647697408751,12075647697416829
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,886218,886223,4194304,256,0,0,24,24,12928,0x7f3812b80900,0x7f36e2c35140,216269,216269,20777,1730160,65536,147203015,1567867,0,590624508,12075647697486298,12075647697729230,12075647697861229,12075647697864231
diff --git a/projects/rocprofiler-compute/tests/workloads/LDS/mi100/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/LDS/mi100/pmc_dispatch_info.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/LDS/mi100/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/LDS/mi100/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/LDS/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/LDS/mi100/pmc_perf.csv
index 87205ca466..99a1a93bd1 100644
--- a/projects/rocprofiler-compute/tests/workloads/LDS/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/LDS/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBuffer.kd,0,0,0,884968,884973,33554432,256,0,0,8,32,6464,0x0,0x7f7ed4a04180,1048576,0,1048576,9437184,0,4194304,1048576,0,508138,508138,58406634,55809253,114,13188081,54966367,54864686,55765841,54591975,4065104,3878230,508138,0,508138,0,16260416,15381103,0,0,0,0,0,17518742,1048576,0,499735,0,0,0,499735,0,0,0,499735,0,0,0,499735,0,0,0,499735,0,0,0,499735,0,0,0,499735,0,0,0,499735,0,0,0,499735,0,0,0,499735,0,0,0,499735,0,0,0,499735,0,0,0,499735,0,0,0,499735,0,0,0,499735,0,0,0,499735,0,0,0,499735,0,0,0,499735,0,0,0,499735,0,0,0,499735,0,0,0,499735,0,0,0,499735,0,0,0,499735,0,0,0,499735,0,0,0,499735,0,0,0,499735,0,0,0,499735,0,0,0,499735,0,0,0,499735,0,0,0,499735,0,0,0,499735,0,0,0,499735,0,0,0,36903989,1,0,0,0,52,0,0,0,0,0,0,0,2711,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2591,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,48,0,0,0,0,0,0,0,21,0,0,0,1,0,0,0,3,0,0,0,0,0,0,0,2560,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,49,0,0,0,4,0,0,0,2635,0,0,0,1048576,0,0,0,131076,131076,0,22113,131072,131072,0,0,131072,131072,0,9037,131072,131072,0,0,131076,131076,0,0,131072,131072,0,0,131072,131072,0,3091585,131080,131080,0,0,131080,131080,0,549307,131072,131072,0,788,131072,131072,0,2896500,131080,131080,0,0,131072,131072,0,0,131076,131076,0,0,131072,131072,0,0,131072,131072,0,0,131080,131080,0,781,131072,131072,0,0,131072,131072,0,0,131076,131076,0,1952,131076,131076,0,1453,131088,131088,0,0,131072,131072,0,0,131088,131088,0,262,131072,131072,0,319,131076,131076,0,0,131072,131072,0,3289860,131077,131077,0,0,131076,131076,0,0,131080,131080,0,0,131072,131072,0,2962131,131072,131072,1048576,0,721,0,0,17139630,920,0,0,17015128,768,0,0,17148039,46054,0,0,29584588,672,0,0,17620750,1086,0,0,17265239,894,0,0,18241730,48557,0,0,31401559,1774,0,0,17418785,1543,0,0,17348745,1477,0,0,17073303,941,0,0,16698791,1798,0,0,17671984,1826,0,0,17361075,1249,0,0,18136504,1069,0,0,18357138,884,0,0,16836254,816,0,0,16933676,814,0,0,16974669,945,0,0,16558597,1279,0,0,17679573,843,0,0,17325537,960,0,0,18101953,806,0,0,18372706,1544,0,0,16894644,1106,0,0,16896003,1087,0,0,16988766,49067,0,0,29526495,1101,0,0,17381244,2077,0,0,17372100,945,0,0,18076009,49943,0,0,31482690,1048576,131072,131072,0,262144,131307,131077,240,262384,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131119,131073,48,262192,131072,131072,0,262144,131072,131072,0,262144,131072,131073,1,262145,131072,131072,0,262144,131072,133596,2524,264668,131072,131072,0,262144,131072,133677,2605,264749,131072,131072,0,262144,131072,131072,0,262144,131072,131124,52,262196,131213,133779,2848,264992,131072,131072,0,262144,131072,131072,0,262144,131072,131073,1,262145,131072,131072,0,262144,131072,131072,0,262144,131072,133766,2694,264838,131072,131073,1,262145,131072,131072,0,262144,131072,131072,0,262144,131072,131097,25,262169,131072,131072,0,262144,131072,131072,0,262144,131072,131120,48,262192,131072,131072,0,262144,262144,0,262144,262336,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262288,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,0,0,3145728,524288,32505856,374296341,219031185,122759300,481077,0,0,0,1048576,52775897,52568328,1048576,1048576,131072,524288,698,502737,4127,0,96,10681,0,8388944,32505856,4023552,3816822,57070370,11534336,0,0,14155776,67108864,67108864,0,67108864,54243963,53915720,0,1048576,241422,765710,11918,2392,0,498658,8399731,0,4194727,4205004,13631488,0,3670016,1048576,1048576,0,4194304,9437184,0,0,360,33554432,54066312,4194304,0,0,2765,503983,0,11151,8388608,0,4194380,905969664,6291456,0,0,0,524288,524288,0,15339,16608600,0,16777216,4194304,4194304,0,0,0,16329,4194356,4194356,0,222487,0,0,0,33554432,0,0,0,0,642626030,0,2816062716,0,0,0,0,0,474403,0,0,221057,0,0,8388608,336,144,0,0,0,480,8388608,0,0,0,0,306305,0,0,0,10655,0,21292,0,6291456,6289167,96,2783,1857540,0,0,0,0,0,0,0,0,0,3145728,0,0,0,146878,4194304,4189867,144,4293,2097152,524288,1572864,0,0,0,0,0,0,524288,0,4128836,65532,4063247,0,0,8388608,0,41694360,0,1048576,10503,4194356,13175756,613441606,12075621837404111,12075648571717424,12075648572040141,12075622082218437
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,884968,884973,32768,256,0,0,24,24,12480,0x0,0x7f7ed4a35100,0,4096,4096,512,0,512,4096,0,27828,27828,1586387,672168,235,145415,95693,77759,664072,643584,222624,91579,27828,0,27828,0,890496,210592,0,0,0,0,0,47777,4096,0,28049,0,0,0,28049,0,0,0,28049,0,0,0,28049,0,0,0,28049,0,0,0,28049,0,0,0,28049,0,0,0,28049,0,0,0,28049,0,0,0,28049,0,0,0,28049,0,0,0,28049,0,0,0,28049,0,0,0,28049,0,0,0,28049,0,0,0,28049,0,0,0,28049,0,0,0,28049,0,0,0,28049,0,0,0,28049,0,0,0,28049,0,0,0,28049,0,0,0,28049,0,0,0,28049,0,0,0,28049,0,0,0,28049,0,0,0,28049,0,0,0,28049,0,0,0,28049,0,0,0,28049,0,0,0,28049,0,0,0,28049,0,0,0,0,257,0,0,0,304,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,260,0,0,0,376,0,0,0,257,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,305,0,0,0,257,0,0,0,256,0,0,0,4096,4096,0,165052,0,0,0,122446,0,0,0,114521,0,0,0,173857,0,0,0,80448,0,0,0,128056,0,0,0,101689,0,0,0,87681,0,0,0,86382,0,0,0,86830,0,0,0,67464,0,0,0,107644,0,0,0,82345,0,0,0,84528,0,0,0,69263,0,0,0,68752,0,0,0,132589,0,0,0,112977,0,0,0,64480,0,0,0,102189,0,0,0,100124,0,0,0,130365,0,0,0,86181,0,0,0,237052,0,0,0,103481,0,0,0,82269,0,0,0,93037,0,0,0,82236,0,0,0,122135,0,0,0,82804,0,0,0,105992,0,0,0,141473,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4096,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,47,257,304,304,0,256,256,256,0,256,256,256,0,257,257,257,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,188,260,448,448,0,256,256,256,0,305,305,305,0,256,256,256,188,260,448,448,0,256,256,256,0,257,257,257,0,256,256,256,0,256,256,256,0,256,256,256,0,257,257,257,0,256,256,256,0,256,256,256,0,376,376,376,0,256,256,256,0,256,256,256,47,257,304,304,0,256,256,256,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,304,0,0,256,0,0,0,0,512,512,35328,1144414,1092528,15534,11570,0,0,0,4096,65154,62117,4096,4096,128,512,607,26652,4166,0,48,220,0,8624,36352,226088,76117,1064963,26624,0,0,30208,65536,65536,65536,0,0,0,0,0,115,627,11878,2390,0,23976,8892,0,470,8422,1024,0,1024,4096,0,4096,512,512,0,0,360,16384,0,16384,0,0,2739,24277,0,8892,0,0,31,1933312,8192,0,0,0,512,512,0,120,15064,0,16384,16384,0,0,0,0,20683,0,0,0,0,0,0,0,32768,0,0,0,0,12196352,17018248,0,8192,0,0,0,0,694,0,0,0,0,0,1024,432,48,0,0,0,480,0,0,0,0,0,2336,0,0,0,8373,0,342,0,8192,6585,48,1559,1092,0,0,0,0,0,0,0,0,0,2560,0,0,0,48646,512,0,48,464,0,512,0,0,0,0,0,0,0,512,0,0,0,0,0,8192,0,0,420801,0,4096,8421,0,3127993,0,12075622097306758,12075648586789750,12075648586796630,12075622098296097
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,884968,884973,4194304,256,0,0,24,24,12928,0x7f7fe069c900,0x7f7ed4a35140,0,524288,524288,65536,0,65536,524288,0,214031,214031,23857277,22612297,32649,12191606,22291615,22247441,22602656,20433172,1712248,1573723,214031,0,214031,0,6848992,6148634,0,0,0,0,0,19428928,524288,0,216153,0,0,0,216153,0,0,0,216153,0,0,0,216153,0,0,0,216153,0,0,0,216153,0,0,0,216153,0,0,0,216153,0,0,0,216153,0,0,0,216153,0,0,0,216153,0,0,0,216153,0,0,0,216153,0,0,0,216153,0,0,0,216153,0,0,0,216153,0,0,0,216153,0,0,0,216153,0,0,0,216153,0,0,0,216153,0,0,0,216153,0,0,0,216153,0,0,0,216153,0,0,0,216153,0,0,0,216153,0,0,0,216153,0,0,0,216153,0,0,0,216153,0,0,0,216153,0,0,0,216153,0,0,0,216153,0,0,0,216153,0,0,0,0,65537,0,0,0,65584,0,2935,0,65540,0,3331,0,68046,0,57473,0,65536,0,1494,0,65536,0,0,0,65536,0,12006,0,65537,0,0,0,65536,0,4221,0,65536,0,2612,0,65536,0,515,0,65536,0,1124,0,65536,0,0,0,65536,0,799,0,65536,0,1743,0,65656,0,2835,0,65537,0,0,0,65536,0,0,0,65536,0,20,0,67894,0,70633,0,65536,0,0,0,65536,0,239,0,65536,0,179,0,65536,0,4662,0,65536,0,3455,0,65536,0,2360,0,65536,0,2559,0,65536,0,5586,0,65536,0,3929,0,65585,0,0,0,65540,0,134,0,65536,0,6760,0,524288,524288,0,23121008,0,0,0,22761744,0,0,0,24188897,0,0,0,23519213,0,0,0,22430877,0,0,0,23506363,0,0,0,23120813,0,0,0,44666220,0,0,0,22619426,0,0,0,23297314,0,0,0,23150952,0,0,0,23105075,0,0,0,23340141,0,0,0,23749521,0,0,0,23556524,0,0,0,22828747,0,0,0,22746252,0,0,0,22033479,0,0,0,21688216,0,0,0,23906151,0,0,0,22430009,0,0,0,24470431,0,0,0,22237248,0,0,0,22367791,0,0,0,21786232,0,0,0,22729711,0,0,0,23005928,0,0,0,23669043,0,0,0,23711922,0,0,0,23616949,0,0,0,21495544,0,0,0,47803145,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,524288,0,65536,65536,65536,0,65536,65536,65536,188,65540,65728,65728,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,47,65537,65584,65584,0,65536,65536,65536,0,65536,65536,65536,0,65537,65537,65537,0,65536,65536,65536,0,66104,66104,66104,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65585,65585,65585,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65537,65537,65537,0,65536,65536,65536,0,65536,65536,65536,0,68154,68154,68154,0,65537,65537,65537,0,65536,65536,65536,0,65536,65536,65536,0,65657,65657,65657,0,65536,65536,65536,0,65536,65536,65536,188,65540,65728,65728,0,65536,65536,65536,65536,0,0,65536,0,0,65728,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65728,0,0,65536,0,0,0,0,65536,65536,4128768,135793943,49339998,82194105,203370,0,0,0,524288,22411112,22401658,524288,524288,16384,65536,771,220310,4069,0,48,3638,0,2097536,4259840,1733816,1553368,23015778,3014656,0,0,3473408,8388608,8388608,8388608,0,0,0,0,0,178268,207441,12301,2432,0,212536,2100013,0,423,2099590,131072,0,131072,524288,0,524288,65536,65536,0,0,360,2097152,0,2097152,33096,0,2826,218919,0,2101185,0,0,31,222298112,917504,0,0,0,65536,65536,0,7598,2018221,0,2097152,2097152,0,628322,630417,0,21892,0,0,0,0,0,0,0,4194304,0,0,0,0,1026817345,1759665495,0,2097152,0,0,0,0,191989,0,0,0,0,0,131072,384,48,0,0,0,432,0,0,0,0,0,4789,0,0,0,2099033,0,3744,0,917504,914729,48,7365,181969,0,0,0,0,0,0,0,0,0,327680,0,0,484912,538343,65536,64048,48,1440,0,65536,0,0,0,0,0,0,0,65536,0,0,0,1966091,0,2097152,0,0,13828717,0,524288,2102621,0,759261765,0,12075622098930396,12075648586856789,12075648586989268,12075622100174047
diff --git a/projects/rocprofiler-compute/tests/workloads/LDS/mi100/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/LDS/mi100/prev_analysis/1.csv
index de2e6bb444..8373617eb0 100644
--- a/projects/rocprofiler-compute/tests/workloads/LDS/mi100/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/LDS/mi100/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,6052907.0,6052907.0,6052907.0,9.178367736339249
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4526200.0,4526200.0,4526200.0,6.863334931169221
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 256u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,3050373.0,3050373.0,3050373.0,4.625454368785173
diff --git a/projects/rocprofiler-compute/tests/workloads/LDS/mi100/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/LDS/mi100/prev_analysis/1001.csv
index ca08330db0..0e3bf5267e 100644
--- a/projects/rocprofiler-compute/tests/workloads/LDS/mi100/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/LDS/mi100/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,46.862275449101794,Instr per wave
 SMEM,1.8083832335329342,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/LDS/mi100/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/LDS/mi100/prev_analysis/101.csv
index 39a52c5b89..9a0ff8db4b 100644
--- a/projects/rocprofiler-compute/tests/workloads/LDS/mi100/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/LDS/mi100/prev_analysis/101.csv
@@ -1,5 +1,5 @@
 Info
-LDS
+LDS_Per_Workgroup
 vesuvius
 AMD EPYC 7542 32-Core Processor
 ""
@@ -23,4 +23,4 @@ gfx908
 mi100
 48
 1228.8
-SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/LDS/mi100/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/LDS/mi100/prev_analysis/1202.csv
index 6010fdfebb..6b9f436a2f 100644
--- a/projects/rocprofiler-compute/tests/workloads/LDS/mi100/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/LDS/mi100/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,33695.0935133974,2855.654457092285,547909.6384887695,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/LDS/mi100/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/LDS/mi100/prev_analysis/1901.csv
index a626c00812..86c651b5a5 100644
--- a/projects/rocprofiler-compute/tests/workloads/LDS/mi100/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/LDS/mi100/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,2.0,smem_
 VALU,735.0,valu_
 MFMA,,mfma_
 VMEM,8.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,22.0,br_
 VGPR,24.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,67894.0,wavefronts_
 Workgroups,16973.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,163.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,0.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,44.0,hbm_rd_
 HBM Wr,0.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,70.0,vl1_coales_
 VL1 Stall,30.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,36.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/LDS/mi100/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/LDS/mi100/prev_analysis/2001.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/LDS/mi100/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/LDS/mi100/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/LDS/mi100/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/LDS/mi100/prev_analysis/201.csv
index b08e08cef9..84659e4095 100644
--- a/projects/rocprofiler-compute/tests/workloads/LDS/mi100/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/LDS/mi100/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,59.587355669324566,Pct,100,59.587355669324566
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,63.96669242997463,Threads,64,99.94795692183536
 IPC - Issue,0.8437169643268545,Instr/cycle,5,16.87433928653709
-LDS BW,0.0,Gb/sec,23070.72,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,23070.72,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99346464516054,Pct,100,99.99346464516054
 Instr Cache BW,1409.5594562466663,Gb/s,4614.144,30.54866636686385
 Scalar L1D Cache Hit Rate,99.35620448529356,Pct,100,99.35620448529356
diff --git a/projects/rocprofiler-compute/tests/workloads/LDS/mi100/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/LDS/mi100/prev_analysis/602.csv
index 9d50869bb8..44bb231163 100644
--- a/projects/rocprofiler-compute/tests/workloads/LDS/mi100/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/LDS/mi100/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,59410.790419161676,0,735877,Simd
 Insufficient SIMD VGPRs,529013.6167664671,0,29952813,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/LDS/mi100/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/LDS/mi100/prev_analysis/701.csv
index d3f1bff5a3..1071413faa 100644
--- a/projects/rocprofiler-compute/tests/workloads/LDS/mi100/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/LDS/mi100/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,23.976047904191617,8,36,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/LDS/mi100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/LDS/mi100/sysinfo.csv
index 41aca5325b..53856aa000 100644
--- a/projects/rocprofiler-compute/tests/workloads/LDS/mi100/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/LDS/mi100/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-LDS,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 11:19:54 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+LDS_Per_Workgroup,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 11:19:54 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/LDS/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/LDS/mi100/timestamps.csv
index d660eb45d8..9b5f36f04a 100644
--- a/projects/rocprofiler-compute/tests/workloads/LDS/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/LDS/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,886268,886273,33554432,256,0,0,8,32,6464,0x0,0x7f4abcc04180,12075648571674268,12075648571717424,12075648572040141,12075648572150313
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,886268,886273,32768,256,0,0,24,24,12480,0x0,0x7f4abcc35100,12075648586690004,12075648586789750,12075648586796630,12075648586801992
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,886268,886273,4194304,256,0,0,24,24,12928,0x7f4bc8806900,0x7f4abcc35140,12075648586843760,12075648586856789,12075648586989268,12075648586992366
diff --git a/projects/rocprofiler-compute/tests/workloads/LDS/mi200/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/LDS/mi200/SQ_IFETCH_LEVEL.csv
index ad0c1ad371..1a184cb2d0 100644
--- a/projects/rocprofiler-compute/tests/workloads/LDS/mi200/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/LDS/mi200/SQ_IFETCH_LEVEL.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,181588,181588,33554432,256,0,0,4,32,4160,0x0,0x7f5c3c204280,383779,383779,524288,4718592,680791,76298180,16905275892927,16904563758520,16905422801787,16905422915136
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,181588,181588,32768,256,0,0,12,24,13888,0x0,0x7f5c3c223f80,33925,33925,512,8192,7641,860824,16905428065962,16905422801787,16905428197614,16905428202268
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,181588,181588,4194304,256,0,0,12,24,14336,0x7f5c3f277380,0x7f5c3c223fc0,167038,167038,65536,917504,139481,15714820,16905428239037,16905428197614,16905428581773,16905428584227
diff --git a/projects/rocprofiler-compute/tests/workloads/LDS/mi200/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/LDS/mi200/SQ_INST_LEVEL_LDS.csv
index d6db046714..b07d8c3e34 100644
--- a/projects/rocprofiler-compute/tests/workloads/LDS/mi200/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/LDS/mi200/SQ_INST_LEVEL_LDS.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,183436,183436,33554432,256,0,0,4,32,4160,0x0,0x7f3f03604280,0,0,0,16924668595638,16923966494861,16924819033898,16924819145857
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,183436,183436,32768,256,0,0,12,24,13888,0x0,0x7f3f03623f80,0,0,0,16924824276904,16924819033898,16924824410041,16924824414810
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,183436,183436,4194304,256,0,0,12,24,14336,0x7f3f0a76b380,0x7f3f03623fc0,0,0,0,16924824449859,16924824410041,16924824779800,16924824782369
diff --git a/projects/rocprofiler-compute/tests/workloads/LDS/mi200/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/LDS/mi200/SQ_INST_LEVEL_SMEM.csv
index a8e5a055a0..da841fff16 100644
--- a/projects/rocprofiler-compute/tests/workloads/LDS/mi200/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/LDS/mi200/SQ_INST_LEVEL_SMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,181366,181366,33554432,256,0,0,4,32,4160,0x0,0x7f33a6c04280,3670016,3019484,338020728,16904335818371,16891058910669,16904484999882,16904485116821
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,181366,181366,32768,256,0,0,12,24,13888,0x0,0x7f33a6c23f80,512,101100,11349552,16904490248777,16904484999882,16904490374105,16904490378944
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,181366,181366,4194304,256,0,0,12,24,14336,0x7f33a9bc8380,0x7f33a6c23fc0,65536,666782,74629024,16904490412293,16904490374105,16904490739224,16904490741593
diff --git a/projects/rocprofiler-compute/tests/workloads/LDS/mi200/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/LDS/mi200/SQ_INST_LEVEL_VMEM.csv
index 3b6a947c59..97c47da6fd 100644
--- a/projects/rocprofiler-compute/tests/workloads/LDS/mi200/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/LDS/mi200/SQ_INST_LEVEL_VMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,183214,183214,33554432,256,0,0,4,32,4160,0x0,0x7f2f90604280,524288,5470219,612567120,16923739028927,16921436568901,16923886206421,16923886320630
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,183214,183214,32768,256,0,0,12,24,13888,0x0,0x7f2f90623f80,4096,35703,3996116,16923891496516,16923886206421,16923891629922,16923891634782
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,183214,183214,4194304,256,0,0,12,24,14336,0x7f2f936bd380,0x7f2f90623fc0,524288,10698602,1198180000,16923891669571,16923891629922,16923892002401,16923892005181
diff --git a/projects/rocprofiler-compute/tests/workloads/LDS/mi200/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/LDS/mi200/SQ_LEVEL_WAVES.csv
index 07bb4e8d4e..015f72cd56 100644
--- a/projects/rocprofiler-compute/tests/workloads/LDS/mi200/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/LDS/mi200/SQ_LEVEL_WAVES.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,181810,181810,33554432,256,0,0,4,32,4160,0x0,0x7f42bde04280,383039,383039,8904,3064320,524288,241651199,2976525,0,982860712,16906212789798,16905505040720,16906357262874,16906357372203
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,181810,181810,32768,256,0,0,12,24,13888,0x0,0x7f42bde23f80,34254,34254,30694,274040,512,1869563,175258,0,7492256,16906362486000,16906357262874,16906362619499,16906362623886
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,181810,181810,4194304,256,0,0,12,24,14336,0x7f42c0e26380,0x7f42bde23fc0,167429,167429,14593,1339440,65536,93543115,1236719,0,375895260,16906362668124,16906362619499,16906363010538,16906363013154
diff --git a/projects/rocprofiler-compute/tests/workloads/LDS/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/LDS/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/LDS/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/LDS/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/LDS/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/LDS/mi200/pmc_perf.csv
index ece5ba82ea..e3d1dad9d1 100644
--- a/projects/rocprofiler-compute/tests/workloads/LDS/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/LDS/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDI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],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBufferAligned.kd,0,0,0,182576,182576,33554432,256,0,0,4,32,4160,0x0,0x7fb700604280,3110304,3023771,524288,39283824,247867088,392,224,0,388787,388787,39550880.0,38529073.0,3.0,4270412.0,31717733.0,31368348.0,38506576.0,37945450.0,3108593,3030173,388787,0,388787,0,12441184.0,9540336.0,0.0,0.0,0,0,616,0,4718592,4714945,112,3535,381975,0.0,0.0,0.0,524288.0,29166046.0,28495753.0,7587.0,524288.0,131072,524288,302,390932,2251,0,56.0,303.0,0.0,4194696.0,0,0,0,0,0,7340032,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,20235407.0,524288.0,0,386739,0,0,0,386739,0,0,0,386739,0,0,0,386739,0,0,0,386739,0,0,0,386739,0,0,0,386739,0,0,0,386739,0,0,0,386739,0,0,0,386739,0,0,0,386739,0,0,0,386739,0,0,0,386739,0,0,0,386739,0,0,0,386739,0,0,0,386739,0,0,0,386739,0,0,0,386739,0,0,0,386739,0,0,0,386739,0,0,0,386739,0,0,0,386739,0,0,0,386739,0,0,0,386739,0,0,0,386739,0,0,0,386739,0,0,0,386739,0,0,0,386739,0,0,0,386739,0,0,0,386739,0,0,0,386739,0,0,0,386739,0,0,0,0,0,0.0,21592527.0,32,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,3,0,0,0,57,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,0,0,112,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,34,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,5,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,524288.0,0.0,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,44963,129024,129024,0,322,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,436576,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,43638,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,164,129024,129024,0,23008,129024,129024,0,863,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,177,129024,129024,0,0,129024,129024,0,0,129024,129024,0,45391,129024,129024,0,265090,129024,129024,524288.0,0.0,45868,0,0,52149072,47807,0,0,52459589,46413,0,0,51894770,49280,0,0,53823948,46029,0,0,52549984,47941,0,0,53025740,46772,0,0,52548728,49542,0,0,54280489,45873,0,0,52313370,48401,0,0,52793823,46820,0,0,51816820,48900,0,0,53649447,47910,0,0,53259992,48606,0,0,52980836,47723,0,0,52750066,50130,0,0,54437700,46311,0,0,52274127,47363,0,0,52305811,45886,0,0,51513987,49303,0,0,53539108,46858,0,0,53009938,47141,0,0,52678019,46328,0,0,52239612,49841,0,0,54360432,47411,0,0,52542468,48414,0,0,52840038,47570,0,0,52160679,50011,0,0,53967759,47753,0,0,53155464,49096,0,0,53345652,47514,0,0,52701575,50401,0,0,54425792,0.0,65536,65568,32,131104,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65646,65538,112,131184,65536,65537,1,131073,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65568,32,131104,65536,65592,56,131128,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65591,65683,202,131274,65536,65536,0,131072,65536,65536,0,131072,65536,65537,1,131073,65758,65538,224,131296,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65568,32,131104,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65591,65539,58,131130,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131184,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131296,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131128,0,131072,1104531,0,524288,3670016,3663184,224,6608,1048576,33554432.0,33554432.0,0.0,33554432.0,30691498.0,29137286.0,0.0,524288.0,226542,538145,8504,921,0,387765,4195055.0,0.0,2097594.0,2097461.0,1048576,1048576,0,524288,0,524288,7340032,0,0.0,0.0,104.0,8388608.0,30271791.0,2097152.0,0.0,219755,0,1247,390765,0,750.0,4194304.0,0.0,2064387.0,25690112,9437184,0,0,0,0,0,0,13312.0,8242176.0,0.0,8388608.0,2097152.0,4194304.0,10554029,0,0,8862,4128768.0,4128768.0,0.0,1547953.0,0,0,0,0,0,0,5767168,1048576,319547637.0,0.0,1487039074.0,0.0,20.0,0.0,0,0,376239,0.0,0.0,1525026.0,0.0,3670016,524288,0,0,0,2621440,524288,177524647,4194304.0,0.0,0.0,0.0,0.0,1205183.0,0,0,0.0,309.0,0.0,602.0,43301066,24117248,0,0,9437184,11010048,0,3145728,0.0,0.0,0.0,0.0,0.0,0.0,0,1572864,0.0,0.0,0.0,196472.0,524288,524288,0,3670016,7340032,603979776,4718592,0,0.0,0.0,0.0,0.0,0.0,0.0,524288,0,2064384.0,0.0,2031623.0,0.0,0,0,524288,0,0,0,0,33554432,0.0,4194304.0,0.0,19020340.0,0.0,0.0,142.0,4128768.0,644478.0,1700855586.0,16907642305589,16925492349123,16925492592483,16907788632393
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,182576,182576,32768,256,0,0,12,24,13888,0x0,0x7fb700623f80,255520,156570,512,1338111,1654462,504,56,0,31939,31939,2268847.0,154141.0,185.0,0.0,37606.0,34558.0,147864.0,129081.0,255512,163708,31939,0,31939,0,1022048.0,364944.0,0.0,0.0,0,0,560,0,8192,6270,56,1866,24019,0.0,0.0,0.0,4096.0,29614.0,28247.0,0.0,4096.0,128,512,302,33135,2323,0,0.0,60.0,0.0,4600.0,0,0,0,0,0,1024,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,16553.0,4096.0,0,33690,0,0,0,33690,0,0,0,33690,0,0,0,33690,0,0,0,33690,0,0,0,33690,0,0,0,33690,0,0,0,33690,0,0,0,33690,0,0,0,33690,0,0,0,33690,0,0,0,33690,0,0,0,33690,0,0,0,33690,0,0,0,33690,0,0,0,33690,0,0,0,33690,0,0,0,33690,0,0,0,33690,0,0,0,33690,0,0,0,33690,0,0,0,33690,0,0,0,33690,0,0,0,33690,0,0,0,33690,0,0,0,33690,0,0,0,33690,0,0,0,33690,0,0,0,33690,0,0,0,33690,0,0,0,33690,0,0,0,33690,0,0,0,0,0,0.0,0.0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,261,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,312,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,4096.0,4096.0,0,84099,0,0,0,86653,0,0,0,94534,0,0,0,124697,0,0,0,82522,0,0,0,76524,0,0,0,78102,0,0,0,85346,0,0,0,653999,0,0,0,97247,0,0,0,90793,0,0,0,99356,0,0,0,94235,0,0,0,82169,0,0,0,85528,0,0,0,82026,0,0,0,78026,0,0,0,99619,0,0,0,96370,0,0,0,116037,0,0,0,91826,0,0,0,100106,0,0,0,111955,0,0,0,88222,0,0,0,81044,0,0,0,100900,0,0,0,76127,0,0,0,92264,0,0,0,105132,0,0,0,98994,0,0,0,95491,0,0,0,87677,0,0,0.0,0.0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4096.0,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,222,130,352,352,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,222,130,352,352,0,128,128,128,0,128,128,128,0,128,128,128,0,186,186,186,0,128,128,128,0,128,128,128,0,129,129,129,0,128,128,128,55,129,184,184,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,129,129,129,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,352,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,352,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,184,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,680,0,0,512,0,56,456,0,65536.0,65536.0,65536.0,0.0,0.0,0.0,0.0,0.0,6,518,11326,996,0,30393,4660.0,0.0,499.0,4161.0,512,0,0,0,4096,4096,512,0,0.0,0.0,104.0,16384.0,0.0,16384.0,4096.0,0,0,1321,32251,0,4660.0,0.0,0.0,31.0,35328,26112,0,0,0,0,0,0,104.0,15240.0,0.0,16384.0,16384.0,0.0,0,0,0,29515,0.0,0.0,0.0,0.0,0,0,0,0,0,0,10752,3584,4759543.0,5571557.0,0.0,8192.0,4.0,0.0,0,0,499,0.0,0.0,0.0,0.0,512,4096,0,0,0,512,512,1645401,0.0,0.0,0.0,0.0,0.0,1386.0,0,0,0.0,8262.0,0.0,122.0,13446,32256,0,0,26112,1024,0,1024,0.0,0.0,0.0,0.0,0.0,0.0,0,1024,0.0,0.0,0.0,31658.0,4096,0,4096,512,512,1671168,8192,0,0.0,0.0,0.0,0.0,0.0,0.0,512,0,0.0,0.0,0.0,0.0,0,0,512,0,0,0,0,32768,8192.0,0.0,0.0,134846.0,0.0,4096.0,8205.0,0.0,3271363.0,0.0,16907794827638,16925497381908,16925497395028,16907795302683
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,182576,182576,4194304,256,0,0,12,24,14336,0x7fb70ee12380,0x7fb700623fc0,1317584,1213647,65536,15697741,78963609,392,56,0,164697,164697,16011783.0,14600411.0,22709.0,1177201.0,13345443.0,13059598.0,14594050.0,12462807.0,1317576,1220884,164697,0,164697,0,5270304.0,4742474.0,0.0,0.0,0,0,448,0,917504,913920,0,3584,158749,0.0,0.0,0.0,524288.0,14325222.0,14316408.0,2072.0,524288.0,16384,65536,302,169150,2644,0,0.0,166.0,0.0,1048968.0,0,0,0,0,0,131072,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,10990227.0,524288.0,0,173095,0,0,0,173095,0,0,0,173095,0,0,0,173095,0,0,0,173095,0,0,0,173095,0,0,0,173095,0,0,0,173095,0,0,0,173095,0,0,0,173095,0,0,0,173095,0,0,0,173095,0,0,0,173095,0,0,0,173095,0,0,0,173095,0,0,0,173095,0,0,0,173095,0,0,0,173095,0,0,0,173095,0,0,0,173095,0,0,0,173095,0,0,0,173095,0,0,0,173095,0,0,0,173095,0,0,0,173095,0,0,0,173095,0,0,0,173095,0,0,0,173095,0,0,0,173095,0,0,0,173095,0,0,0,173095,0,0,0,173095,0,0,0,0,0,0.0,0.0,65536,0,25719,0,65536,0,15111,0,65536,0,29240,0,65537,0,8390,0,65536,0,7226,0,65537,0,31214,0,65537,0,36103,0,65536,0,33736,0,65536,0,6996,0,65538,0,10302,0,65592,0,5187,0,65537,0,18747,0,65536,0,6357,0,65536,0,21011,0,65536,0,35643,0,65536,0,13325,0,65537,0,15970,0,65536,0,28640,0,65595,0,5082,0,65536,0,34054,0,65536,0,24987,0,65536,0,20789,0,65537,0,27273,0,65539,0,7810,0,65540,0,9937,0,65536,0,12140,0,65536,0,13400,0,65602,0,4714,0,65536,0,8743,0,65536,0,17881,0,65536,0,6102,0,65536,0,10527,0,524288.0,524288.0,0,40937422,0,0,0,40716429,0,0,0,40515032,0,0,0,49486919,0,0,0,46691572,0,0,0,46389435,0,0,0,42955999,0,0,0,48259846,0,0,0,42681520,0,0,0,40848143,0,0,0,39954180,0,0,0,44404488,0,0,0,47182688,0,0,0,43882820,0,0,0,42218804,0,0,0,41900811,0,0,0,41596698,0,0,0,48115213,0,0,0,42014388,0,0,0,47210439,0,0,0,42973620,0,0,0,41073860,0,0,0,48890203,0,0,0,41658539,0,0,0,40960305,0,0,0,48271347,0,0,0,39978610,0,0,0,41049086,0,0,0,46426095,0,0,0,44550632,0,0,0,44996932,0,0,0,46031463,0,0,0.0,0.0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,524288.0,0,32768,32768,32768,0,32768,32768,32768,0,32769,32769,32769,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32769,32769,32769,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32881,32881,32881,0,32768,32768,32768,0,32768,32768,32768,0,32769,32769,32769,0,32768,32768,32768,166,32770,32936,32936,222,32770,32992,32992,0,32768,32768,32768,0,32768,32768,32768,0,32831,32831,32831,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32769,32769,32769,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32936,0,0,32992,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,877783,0,0,65536,63800,56,1680,0,8388608.0,8388608.0,8388608.0,0.0,0.0,0.0,0.0,0.0,126485,148305,9870,2516,0,162406,1049153.0,0.0,388.0,1048765.0,65536,0,0,0,524288,524288,131072,0,0.0,0.0,104.0,2097152.0,0.0,2097152.0,524288.0,47464,0,2367,161351,0,1049144.0,0.0,0.0,31.0,4063232,2883584,0,0,0,0,0,0,6622.0,2026954.0,0.0,2097152.0,2097152.0,0.0,1330051,0,0,13508,0.0,0.0,0.0,0.0,262144,0,0,0,0,0,1507328,458752,1010286398.0,2225494112.0,0.0,2097152.0,53.0,0.0,0,0,147957,0.0,0.0,0.0,0.0,65536,524288,0,0,0,65536,65536,48437237,0.0,0.0,0.0,0.0,0.0,25340.0,0,0,0.0,2097346.0,0.0,374.0,22002561,3735552,0,0,2883584,196608,0,131072,0.0,0.0,0.0,0.0,0.0,0.0,0,131072,0.0,0.0,453204.0,1359700.0,524288,0,524288,65536,131072,184549376,917504,0,0.0,0.0,0.0,0.0,0.0,0.0,65536,0,0.0,0.0,983046.0,0.0,0,0,65536,0,0,0,0,4194304,2097152.0,0.0,0.0,12400037.0,0.0,524288.0,2097289.0,0.0,1451128647.0,0.0,16907796398260,16925497462068,16925497554548,16907797134798
diff --git a/projects/rocprofiler-compute/tests/workloads/LDS/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/LDS/mi200/prev_analysis/1.csv
index e5bf0ae06c..2bae583393 100644
--- a/projects/rocprofiler-compute/tests/workloads/LDS/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/LDS/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,3358711.0,3358711.0,3358711.0,7.846568285268675
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,1724475.0,1724475.0,1724475.0,4.028691615247248
 "void benchmark_func<double, 256, 8u, 512u>(double, double*) [clone .kd]",1,1715675.0,1715675.0,1715675.0,4.0081331924146895
diff --git a/projects/rocprofiler-compute/tests/workloads/LDS/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/LDS/mi200/prev_analysis/1001.csv
index f475f954a6..fb5988001a 100644
--- a/projects/rocprofiler-compute/tests/workloads/LDS/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/LDS/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,494.8622754491018,Instr per wave
 VMEM,7.958083832335329,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,0.0,Instr per wave
 SALU,24.520958083832337,Instr per wave
 SMEM,1.8023952095808384,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/LDS/mi200/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/LDS/mi200/prev_analysis/101.csv
index 9916b07a5c..16f4cd7c28 100644
--- a/projects/rocprofiler-compute/tests/workloads/LDS/mi200/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/LDS/mi200/prev_analysis/101.csv
@@ -1,5 +1,5 @@
 Info
-LDS
+LDS_Per_Workgroup
 06fa5f860366
 AMD EPYC 7282 16-Core Processor
 Ubuntu 20.04.5 LTS
@@ -23,4 +23,4 @@ gfx90a
 mi200
 56
 1638.4
-roofline|SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+roofline|SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/LDS/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/LDS/mi200/prev_analysis/1202.csv
index c9faeeb65c..13a6483e1c 100644
--- a/projects/rocprofiler-compute/tests/workloads/LDS/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/LDS/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,18422.732679903864,1891.0758056640625,258297.59991455078,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/LDS/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/LDS/mi200/prev_analysis/1901.csv
index e2c1e8398a..d666b61db7 100644
--- a/projects/rocprofiler-compute/tests/workloads/LDS/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/LDS/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,2.0,smem_
 VALU,495.0,valu_
 MFMA,0.0,mfma_
 VMEM,8.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,10.0,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,67894.0,wavefronts_
 Workgroups,16973.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,128.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,0.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,44.0,hbm_rd_
 HBM Wr,0.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,70.0,vl1_coales_
 VL1 Stall,2.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,26.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/LDS/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/LDS/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/LDS/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/LDS/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/LDS/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/LDS/mi200/prev_analysis/201.csv
index 034702503f..bb00f67d20 100644
--- a/projects/rocprofiler-compute/tests/workloads/LDS/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/LDS/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,58.400637555578996,Pct,100,58.400637555578996
 MFMA Util,0.0,Pct,100,0.0
 VALU Active Threads/Wave,64.0,Threads,64,100.0
 IPC - Issue,1.0,Instr/cycle,5,20.0
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99267875444308,Pct,100,99.99267875444308
 Instr Cache BW,1674.4206186917627,Gb/s,6092.8,27.481956057834868
 Scalar L1D Cache Hit Rate,99.34855885934454,Pct,100,99.34855885934454
diff --git a/projects/rocprofiler-compute/tests/workloads/LDS/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/LDS/mi200/prev_analysis/602.csv
index c9b04fb7ec..9cacd3ce2f 100644
--- a/projects/rocprofiler-compute/tests/workloads/LDS/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/LDS/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,12585834.670658683,0,374412893,Simd
 Insufficient SIMD VGPRs,0.0,0,0,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/LDS/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/LDS/mi200/prev_analysis/701.csv
index 12250d77c0..db0925a109 100644
--- a/projects/rocprofiler-compute/tests/workloads/LDS/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/LDS/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/LDS/mi200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/LDS/mi200/sysinfo.csv
index b01469e412..e8f028a6d4 100644
--- a/projects/rocprofiler-compute/tests/workloads/LDS/mi200/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/LDS/mi200/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-LDS,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:35:04 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,roofline|SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+LDS_Per_Workgroup,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:35:04 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,roofline|SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/LDS/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/LDS/mi200/timestamps.csv
index e99796e2c9..0e5670d9fe 100644
--- a/projects/rocprofiler-compute/tests/workloads/LDS/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/LDS/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,183519,183519,33554432,256,0,0,4,32,4160,0x0,0x7f4af2404280,16925492322133,16925492349123,16925492592483,16925492682502
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,183519,183519,32768,256,0,0,12,24,13888,0x0,0x7f4af2423f80,16925497366713,16925497381908,16925497395028,16925497413372
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,183519,183519,4194304,256,0,0,12,24,14336,0x7f4af5424380,0x7f4af2423fc0,16925497417351,16925497462068,16925497554548,16925497556747
diff --git a/projects/rocprofiler-compute/tests/workloads/SPI/mi100/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/SPI/mi100/pmc_dispatch_info.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/SPI/mi100/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SPI/mi100/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/SPI/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/SPI/mi100/pmc_perf.csv
index 161dfbdf3b..523bedab54 100644
--- a/projects/rocprofiler-compute/tests/workloads/SPI/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SPI/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,GRBM_COUNT,GRBM_GUI_ACTIVE,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,GRBM_SPI_BUSY,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,GRBM_COUNT,GRBM_GUI_ACTIVE,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,GRBM_SPI_BUSY,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBuffer.kd,0,0,0,866123,866128,33554432,256,0,0,8,32,6464,0x0,0x7f8756c04180,4039312,3829273,524288,504913,504913,4039304,3841146,480691,131072,524288,243029,767317,0,0,0,0,0,0,0,0,0,3145728,524288,0,12075222642432714,12075231812466956,12075231812792233,12075222885713539
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,866123,866128,32768,256,0,0,24,24,12480,0x0,0x7f8756c35100,223584,76405,512,27947,27947,223576,88027,12078,128,512,116,628,0,0,0,0,0,0,0,0,0,2560,512,0,12075222900007172,12075231827875508,12075231827882068,12075222900344198
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,866123,866128,4194304,256,0,0,24,24,12928,0x7f8886c24900,0x7f8756c35140,1737952,1566380,65536,217243,217243,1737944,1578107,198642,16384,65536,231405,241240,27397,0,772162,774953,0,0,0,0,0,327680,65536,0,12075222900410802,12075231827930868,12075231828062387,12075222900772574
diff --git a/projects/rocprofiler-compute/tests/workloads/SPI/mi100/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/SPI/mi100/prev_analysis/1.csv
index a5f98619c4..096ed766b9 100644
--- a/projects/rocprofiler-compute/tests/workloads/SPI/mi100/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SPI/mi100/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,6054197.0,6054197.0,6054197.0,9.181487611317175
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4527648.0,4527648.0,4527648.0,6.866400948037368
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 256u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,3050539.0,3050539.0,3050539.0,4.626292477159215
diff --git a/projects/rocprofiler-compute/tests/workloads/SPI/mi100/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/SPI/mi100/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/SPI/mi100/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SPI/mi100/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/SPI/mi100/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/SPI/mi100/prev_analysis/1202.csv
index d92c0479fa..2d4898d1f7 100644
--- a/projects/rocprofiler-compute/tests/workloads/SPI/mi100/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SPI/mi100/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,,,,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/SPI/mi100/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/SPI/mi100/prev_analysis/1901.csv
index f1556d6a26..f626057062 100644
--- a/projects/rocprofiler-compute/tests/workloads/SPI/mi100/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SPI/mi100/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,24.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,67894.0,wavefronts_
 Workgroups,16973.0,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,,il1_fetch_
 IL1 Hit,,il1_hit_
 IL1_L2 Rd,,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/SPI/mi100/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/SPI/mi100/prev_analysis/2001.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/SPI/mi100/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SPI/mi100/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/SPI/mi100/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/SPI/mi100/prev_analysis/201.csv
index 52e9f5bf0c..91625c4b2e 100644
--- a/projects/rocprofiler-compute/tests/workloads/SPI/mi100/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SPI/mi100/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,,Gb/sec,23070.72,
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,,Gb/sec,23070.72,
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,,Pct,100,
 Instr Cache BW,,Gb/s,4614.144,
 Scalar L1D Cache Hit Rate,,Pct,100,
diff --git a/projects/rocprofiler-compute/tests/workloads/SPI/mi100/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/SPI/mi100/prev_analysis/602.csv
index ff27321c2c..840f0272b0 100644
--- a/projects/rocprofiler-compute/tests/workloads/SPI/mi100/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SPI/mi100/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,59217.11976047904,0,772162,Simd
 Insufficient SIMD VGPRs,610425.4730538923,0,36746998,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/SPI/mi100/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/SPI/mi100/prev_analysis/701.csv
index 251e393e89..b26c791122 100644
--- a/projects/rocprofiler-compute/tests/workloads/SPI/mi100/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SPI/mi100/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,23.976047904191617,8,36,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/SPI/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/SPI/mi100/timestamps.csv
index 96bddc46cb..e6f600be6c 100644
--- a/projects/rocprofiler-compute/tests/workloads/SPI/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SPI/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,866419,866424,33554432,256,0,0,8,32,6464,0x0,0x7f0bbe804180,12075231812421071,12075231812466956,12075231812792233,12075231812896955
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,866419,866424,32768,256,0,0,24,24,12480,0x0,0x7f0bbe835100,12075231827776346,12075231827875508,12075231827882068,12075231827887974
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,866419,866424,4194304,256,0,0,24,24,12928,0x7f0cee94d900,0x7f0bbe835140,12075231827918631,12075231827930868,12075231828062387,12075231828065914
diff --git a/projects/rocprofiler-compute/tests/workloads/SPI/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/SPI/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/SPI/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SPI/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/SPI/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/SPI/mi200/pmc_perf.csv
index 3a56e709a8..88d911c762 100644
--- a/projects/rocprofiler-compute/tests/workloads/SPI/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SPI/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,GRBM_COUNT,GRBM_GUI_ACTIVE,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,GRBM_SPI_BUSY,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,GRBM_COUNT,GRBM_GUI_ACTIVE,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,GRBM_SPI_BUSY,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBufferAligned.kd,0,0,0,157596,157596,33554432,256,0,0,4,32,4160,0x0,0x7f3dcc204280,3029720,2939484,524288,378714,378714,3028009,2945891,370029,131072,524288,208770,534570,194898,0,9353793,0,0,0,0,0,0,1572864,524288,0,16379423217189,16385586870073,16385587107675,16379569394275
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,157596,157596,32768,256,0,0,12,24,13888,0x0,0x7f3dcc223f80,201600,101231,512,25199,25199,201592,109278,14871,128,512,6,518,0,0,0,0,0,0,0,0,0,1024,512,0,16379574609650,16385591946586,16385591956026,16379574748737
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,157596,157596,4194304,256,0,0,12,24,14336,0x7f3dea9f1380,0x7f3dcc223fc0,1315896,1206067,65536,164486,164486,1315888,1214126,153755,16384,65536,221429,216568,70636,0,1718682,0,0,0,0,0,0,131072,65536,0,16379574791106,16385592030587,16385592123387,16379575140868
diff --git a/projects/rocprofiler-compute/tests/workloads/SPI/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/SPI/mi200/prev_analysis/1.csv
index 1a96c79c1a..0d9a8d4330 100644
--- a/projects/rocprofiler-compute/tests/workloads/SPI/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SPI/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,3354742.0,3354742.0,3354742.0,7.874929090844986
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,1722252.0,1722252.0,1722252.0,4.042818308104158
 "void benchmark_func<double, 256, 8u, 512u>(double, double*) [clone .kd]",1,1713132.0,1713132.0,1713132.0,4.021409999116908
diff --git a/projects/rocprofiler-compute/tests/workloads/SPI/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/SPI/mi200/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/SPI/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SPI/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/SPI/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/SPI/mi200/prev_analysis/1202.csv
index d92c0479fa..2d4898d1f7 100644
--- a/projects/rocprofiler-compute/tests/workloads/SPI/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SPI/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,,,,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/SPI/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/SPI/mi200/prev_analysis/1901.csv
index 2fbb314bca..6afc7632e9 100644
--- a/projects/rocprofiler-compute/tests/workloads/SPI/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SPI/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,67894.0,wavefronts_
 Workgroups,16973.0,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,,il1_fetch_
 IL1 Hit,,il1_hit_
 IL1_L2 Rd,,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/SPI/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/SPI/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/SPI/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SPI/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/SPI/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/SPI/mi200/prev_analysis/201.csv
index b4d9ea9d64..2086c73dba 100644
--- a/projects/rocprofiler-compute/tests/workloads/SPI/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SPI/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,,Gb/sec,22630.4,
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,,Gb/sec,22630.4,
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,,Pct,100,
 Instr Cache BW,,Gb/s,6092.8,
 Scalar L1D Cache Hit Rate,,Pct,100,
diff --git a/projects/rocprofiler-compute/tests/workloads/SPI/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/SPI/mi200/prev_analysis/602.csv
index 475ebe00c6..a3f78d6539 100644
--- a/projects/rocprofiler-compute/tests/workloads/SPI/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SPI/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,15544952.269461079,0,408383757,Simd
 Insufficient SIMD VGPRs,0.0,0,0,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/SPI/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/SPI/mi200/prev_analysis/701.csv
index 6c1da816d8..e5a0856200 100644
--- a/projects/rocprofiler-compute/tests/workloads/SPI/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SPI/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/SPI/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/SPI/mi200/timestamps.csv
index 92e60215e0..24d9f0563e 100644
--- a/projects/rocprofiler-compute/tests/workloads/SPI/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SPI/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,157887,157887,33554432,256,0,0,4,32,4160,0x0,0x7fc364c04280,16385586841853,16385586870073,16385587107675,16385587214525
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,157887,157887,32768,256,0,0,12,24,13888,0x0,0x7fc364c23f80,16385591930561,16385591946586,16385591956026,16385591977510
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,157887,157887,4194304,256,0,0,12,24,14336,0x7fc367c0c380,0x7fc364c23fc0,16385591979080,16385592030587,16385592123387,16385592125537
diff --git a/projects/rocprofiler-compute/tests/workloads/SQ/mi100/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/SQ/mi100/SQ_IFETCH_LEVEL.csv
index 191c1a87bd..e283a0f97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/SQ/mi100/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SQ/mi100/SQ_IFETCH_LEVEL.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,851446,851451,33554432,256,0,0,8,32,6464,0x0,0x7f57d7204180,502017,502017,524288,6291456,791691,101396696,12074888626877398,12074888876000832,12074888876323390,12074888876416213
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,851446,851451,32768,256,0,0,24,24,12480,0x0,0x7f57d7235100,27806,27806,512,8192,9394,1198836,12074888891216898,12074888891548393,12074888891555113,12074888891564213
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,851446,851451,4194304,256,0,0,24,24,12928,0x7f5907505900,0x7f57d7235140,216862,216862,65536,917504,139878,17901600,12074888891674198,12074888891859432,12074888891991591,12074888891995104
diff --git a/projects/rocprofiler-compute/tests/workloads/SQ/mi100/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/SQ/mi100/SQ_INST_LEVEL_LDS.csv
index 19d4dfcfa6..5cc3ee7695 100644
--- a/projects/rocprofiler-compute/tests/workloads/SQ/mi100/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SQ/mi100/SQ_INST_LEVEL_LDS.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,852721,852726,33554432,256,0,0,8,32,6464,0x0,0x7f6e8fa04180,0,0,0,12074902136846207,12074902384490777,12074902384815895,12074902384929407
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,852721,852726,32768,256,0,0,24,24,12480,0x0,0x7f6e8fa35100,0,0,0,12074902399651707,12074902399953892,12074902399960772,12074902399971361
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,852721,852726,4194304,256,0,0,24,24,12928,0x7f6fbfb0d900,0x7f6e8fa35140,0,0,0,12074902400033135,12074902400249250,12074902400384129,12074902400387534
diff --git a/projects/rocprofiler-compute/tests/workloads/SQ/mi100/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/SQ/mi100/SQ_INST_LEVEL_SMEM.csv
index 0a3387869e..5ebf71638a 100644
--- a/projects/rocprofiler-compute/tests/workloads/SQ/mi100/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SQ/mi100/SQ_INST_LEVEL_SMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,852343,852348,33554432,256,0,0,8,32,6464,0x0,0x7f1281c04180,4194304,3113414,398152752,12074899625250804,12074899870091626,12074899870413864,12074899870526486
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,852343,852348,32768,256,0,0,24,24,12480,0x0,0x7f1281c35100,512,24164,3091584,12074899885466780,12074899885762069,12074899885768149,12074899885772278
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,852343,852348,4194304,256,0,0,24,24,12928,0x7f138d92a900,0x7f1281c35140,65536,186070,23892320,12074899885835055,12074899886060468,12074899886199187,12074899886202548
diff --git a/projects/rocprofiler-compute/tests/workloads/SQ/mi100/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/SQ/mi100/SQ_INST_LEVEL_VMEM.csv
index 4dc5088059..b32ae18701 100644
--- a/projects/rocprofiler-compute/tests/workloads/SQ/mi100/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SQ/mi100/SQ_INST_LEVEL_VMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,852531,852536,33554432,256,0,0,8,32,6464,0x0,0x7fb7aea04180,1048576,11152581,1428431508,12074900885374645,12074901130497971,12074901130818609,12074901130931851
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,852531,852536,32768,256,0,0,24,24,12480,0x0,0x7fb7aea35100,4096,101519,12998948,12074901145721305,12074901146039652,12074901146045892,12074901146055175
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,852531,852536,4194304,256,0,0,24,24,12928,0x7fb8ba5d7900,0x7fb7aea35140,524288,11529184,1475572344,12074901146108474,12074901146331810,12074901146466850,12074901146470246
diff --git a/projects/rocprofiler-compute/tests/workloads/SQ/mi100/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/SQ/mi100/SQ_LEVEL_WAVES.csv
index 949df13068..be958f25fc 100644
--- a/projects/rocprofiler-compute/tests/workloads/SQ/mi100/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SQ/mi100/SQ_LEVEL_WAVES.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,852909,852914,33554432,256,0,0,8,32,6464,0x0,0x7fae92804180,503727,503727,16747,4029824,524288,367002422,3824302,0,1482807932,12074903397207541,12074903646084267,12074903646407785,12074903646560960
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,852909,852914,32768,256,0,0,24,24,12480,0x0,0x7fae92835100,27441,27441,20306,219536,512,1140556,76455,0,4576460,12074903661224461,12074903661584067,12074903661590467,12074903661596843
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,852909,852914,4194304,256,0,0,24,24,12928,0x7fafc2802900,0x7fae92835140,219572,219572,20780,1756584,65536,129130219,1589265,0,518339256,12074903661670540,12074903661999745,12074903662134144,12074903662139852
diff --git a/projects/rocprofiler-compute/tests/workloads/SQ/mi100/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/SQ/mi100/pmc_dispatch_info.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/SQ/mi100/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SQ/mi100/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/SQ/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/SQ/mi100/pmc_perf.csv
index 8031d3ba4f..7d42134e47 100644
--- a/projects/rocprofiler-compute/tests/workloads/SQ/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SQ/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBuffer.kd,0,0,0,851908,851913,33554432,256,0,0,8,32,6464,0x0,0x7f16e3a04180,1048576,0,1048576,9437184,0,4194304,1048576,0,506765,506765,0,0,3145728,524288,32505856,374667926,219574763,122587307,32505856,4005136,3805741,56961485,11534336,0,0,14155776,13631488,0,3670016,1048576,1048576,0,4194304,9437184,905969664,6291456,0,0,0,524288,524288,0,0,0,0,33554432,0,0,0,0,0,8388608,336,144,0,0,0,480,0,6291456,6289457,96,2186,1819322,0,0,4194304,4189863,144,4297,2097152,524288,1572864,12074890142342317,12074904556684405,12074904557010162,12074890391224712
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,851908,851913,32768,256,0,0,24,24,12480,0x0,0x7f16e3a35100,0,4096,4096,512,0,512,4096,0,27610,27610,0,0,512,512,35328,1108710,1055334,17024,36352,225392,77450,1080338,26624,0,0,30208,1024,0,1024,4096,0,4096,512,512,1933312,8192,0,0,0,512,512,0,0,0,0,32768,0,0,0,0,0,1024,432,48,0,0,0,480,0,8192,6578,48,1566,1058,0,0,512,0,48,464,0,512,0,12074890405606408,12074904572874025,12074904572881385,12074890405950457
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,851908,851913,4194304,256,0,0,24,24,12928,0x7f1813b26900,0x7f16e3a35140,0,524288,524288,65536,0,65536,524288,0,214967,214967,0,0,65536,65536,4128768,152547403,55797172,92490391,4259840,1831576,1658706,24593622,3014656,0,0,3473408,131072,0,131072,524288,0,524288,65536,65536,222298112,917504,0,0,0,65536,65536,0,0,0,0,4194304,0,0,0,0,0,131072,384,48,0,0,0,432,0,917504,914912,48,7430,204790,0,0,65536,64048,48,1440,0,65536,0,12074890406038090,12074904572956424,12074904573090983,12074890406424128
diff --git a/projects/rocprofiler-compute/tests/workloads/SQ/mi100/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/SQ/mi100/prev_analysis/1.csv
index a45d11b38d..47f8ebca59 100644
--- a/projects/rocprofiler-compute/tests/workloads/SQ/mi100/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SQ/mi100/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,6056915.0,6056915.0,6056915.0,9.15285531234674
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4527006.0,4527006.0,4527006.0,6.840946408547185
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 256u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,3051657.0,3051657.0,3051657.0,4.611485382230083
diff --git a/projects/rocprofiler-compute/tests/workloads/SQ/mi100/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/SQ/mi100/prev_analysis/1001.csv
index ca08330db0..0e3bf5267e 100644
--- a/projects/rocprofiler-compute/tests/workloads/SQ/mi100/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SQ/mi100/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,46.862275449101794,Instr per wave
 SMEM,1.8083832335329342,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/SQ/mi100/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/SQ/mi100/prev_analysis/1202.csv
index 9b5f5a8c7e..43a30c4b8f 100644
--- a/projects/rocprofiler-compute/tests/workloads/SQ/mi100/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SQ/mi100/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,33707.31541680433,2858.4894256591797,547965.4020385742,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/SQ/mi100/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/SQ/mi100/prev_analysis/1901.csv
index c1fa269939..73b1ab2c4a 100644
--- a/projects/rocprofiler-compute/tests/workloads/SQ/mi100/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SQ/mi100/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,2.0,smem_
 VALU,735.0,valu_
 MFMA,,mfma_
 VMEM,8.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,22.0,br_
 VGPR,24.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,163.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,33.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/SQ/mi100/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/SQ/mi100/prev_analysis/2001.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/SQ/mi100/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SQ/mi100/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/SQ/mi100/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/SQ/mi100/prev_analysis/201.csv
index d66053317f..b8a69e61aa 100644
--- a/projects/rocprofiler-compute/tests/workloads/SQ/mi100/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SQ/mi100/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,59.72765004181832,Pct,100,59.72765004181832
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,63.968123840938844,Threads,64,99.95019350146694
 IPC - Issue,0.8437291186566603,Instr/cycle,5,16.874582373133208
-LDS BW,0.0,Gb/sec,23070.72,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,23070.72,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99345948949716,Pct,100,99.99345948949716
 Instr Cache BW,1402.9024000933537,Gb/s,4614.144,30.40439136908934
 Scalar L1D Cache Hit Rate,99.35620448527392,Pct,100,99.35620448527392
diff --git a/projects/rocprofiler-compute/tests/workloads/SQ/mi100/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/SQ/mi100/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/SQ/mi100/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SQ/mi100/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/SQ/mi100/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/SQ/mi100/prev_analysis/701.csv
index e64851d52b..cdde4fb05f 100644
--- a/projects/rocprofiler-compute/tests/workloads/SQ/mi100/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SQ/mi100/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,23.976047904191617,8,36,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/SQ/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/SQ/mi100/timestamps.csv
index 4d7afe380e..66a1380128 100644
--- a/projects/rocprofiler-compute/tests/workloads/SQ/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SQ/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,852960,852965,33554432,256,0,0,8,32,6464,0x0,0x7ff680a04180,12074904556644669,12074904556684405,12074904557010162,12074904557120564
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,852960,852965,32768,256,0,0,24,24,12480,0x0,0x7ff680a35100,12074904572766009,12074904572874025,12074904572881385,12074904572887104
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,852960,852965,4194304,256,0,0,24,24,12928,0x7ff78c695900,0x7ff680a35140,12074904572942988,12074904572956424,12074904573090983,12074904573094329
diff --git a/projects/rocprofiler-compute/tests/workloads/SQ/mi200/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/SQ/mi200/SQ_IFETCH_LEVEL.csv
index f987e8a238..419b8863dc 100644
--- a/projects/rocprofiler-compute/tests/workloads/SQ/mi200/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SQ/mi200/SQ_IFETCH_LEVEL.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,137044,137044,33554432,256,0,0,4,32,4160,0x0,0x7fb803a04280,384485,384485,524288,4718592,685685,76747320,15893779864514,15893103396404,15893926395314,15893926508014
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,137044,137044,32768,256,0,0,12,24,13888,0x0,0x7fb803a23f80,33460,33460,512,8192,5981,659896,15893931668709,15893926395314,15893931801246,15893931805906
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,137044,137044,4194304,256,0,0,12,24,14336,0x7fb822385380,0x7fb803a23fc0,164874,164874,65536,917504,141375,15902036,15893931844195,15893931801246,15893932177247,15893932179668
diff --git a/projects/rocprofiler-compute/tests/workloads/SQ/mi200/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/SQ/mi200/SQ_INST_LEVEL_LDS.csv
index 8eef6948d2..72919cbcc3 100644
--- a/projects/rocprofiler-compute/tests/workloads/SQ/mi200/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SQ/mi200/SQ_INST_LEVEL_LDS.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,138652,138652,33554432,256,0,0,4,32,4160,0x0,0x7f5f48204280,0,0,0,15906151326125,15905443557786,15906300453989,15906300545499
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,138652,138652,32768,256,0,0,12,24,13888,0x0,0x7f5f48223f80,0,0,0,15906305702753,15906300453989,15906305829843,15906305834530
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,138652,138652,4194304,256,0,0,12,24,14336,0x7f5f56a38380,0x7f5f48223fc0,0,0,0,15906305869720,15906305829843,15906306214644,15906306217152
diff --git a/projects/rocprofiler-compute/tests/workloads/SQ/mi200/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/SQ/mi200/SQ_INST_LEVEL_SMEM.csv
index 235e313559..042b58893a 100644
--- a/projects/rocprofiler-compute/tests/workloads/SQ/mi200/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SQ/mi200/SQ_INST_LEVEL_SMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,136822,136822,33554432,256,0,0,4,32,4160,0x0,0x7ff914a04280,3670016,2916842,326647824,15892871944314,15808676099944,15893020002100,15893020095280
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,136822,136822,32768,256,0,0,12,24,13888,0x0,0x7ff914a23f80,512,99786,11189496,15893025292904,15893020002100,15893025424675,15893025429601
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,136822,136822,4194304,256,0,0,12,24,14336,0x7ff917ab0380,0x7ff914a23fc0,65536,627382,70264104,15893025464240,15893025424675,15893025793636,15893025796253
diff --git a/projects/rocprofiler-compute/tests/workloads/SQ/mi200/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/SQ/mi200/SQ_INST_LEVEL_VMEM.csv
index 4c69a64331..5786e30a53 100644
--- a/projects/rocprofiler-compute/tests/workloads/SQ/mi200/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SQ/mi200/SQ_INST_LEVEL_VMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,138430,138430,33554432,256,0,0,4,32,4160,0x0,0x7f80e4204280,524288,5415305,606439548,15905219297983,15904274091722,15905364242620,15905364355920
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,138430,138430,32768,256,0,0,12,24,13888,0x0,0x7f80e4223f80,4096,33999,3812512,15905369523304,15905364242620,15905369646311,15905369651142
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,138430,138430,4194304,256,0,0,12,24,14336,0x7f8102aa6380,0x7f80e4223fc0,524288,10729326,1201590968,15905369686011,15905369646311,15905370017192,15905370019713
diff --git a/projects/rocprofiler-compute/tests/workloads/SQ/mi200/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/SQ/mi200/SQ_LEVEL_WAVES.csv
index 8daa099d86..eaf4943720 100644
--- a/projects/rocprofiler-compute/tests/workloads/SQ/mi200/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SQ/mi200/SQ_LEVEL_WAVES.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,137266,137266,33554432,256,0,0,4,32,4160,0x0,0x7feb78404280,388592,388592,8652,3108744,524288,245654179,3022814,0,998905728,15894714993359,15894007718666,15894865243286,15894865331336
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,137266,137266,32768,256,0,0,12,24,13888,0x0,0x7feb78423f80,33345,33345,29846,266768,512,1688520,169915,0,6767260,15894870480071,15894865243286,15894870613861,15894870618498
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,137266,137266,4194304,256,0,0,12,24,14336,0x7feb7b479380,0x7feb78423fc0,164243,164243,13776,1313952,65536,75793880,1207030,0,304907864,15894870663287,15894870613861,15894870999942,15894871001980
diff --git a/projects/rocprofiler-compute/tests/workloads/SQ/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/SQ/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/SQ/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SQ/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/SQ/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/SQ/mi200/pmc_perf.csv
index 9bc7da96c0..7ccf91f80b 100644
--- a/projects/rocprofiler-compute/tests/workloads/SQ/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SQ/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS,SQ_INSTS_VALU,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS,SQ_INSTS_VALU,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBufferAligned.kd,0,0,0,137896,137896,33554432,256,0,0,4,32,4160,0x0,0x7f6ef5c04280,0,524288,0,524288,7340032,0,25690112,9437184,386272,386272,0,0,0,0,0,0,0,0,0,0,0,616,0,4718592,4714901,112,3510,1131343,0,524288,3670016,3663234,224,6558,1048576,1048576,1048576,0,0,0,0,5767168,1048576,3670016,524288,0,0,0,2621440,524288,246413115,178736228,43559639,24117248,3073544,2986786,38806136,0,0,9437184,11010048,0,3145728,524288,524288,0,3670016,7340032,603979776,4718592,0,0,0,524288,524288,0,0,0,0,33554432,0,0,0,0,0,7340032,0,0,0,0,0,0,0,0,0,0,0,0,0,392,224,15896002897487,15906971870954,15906972109355,15896147670838
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,137896,137896,32768,256,0,0,12,24,13888,0x0,0x7f6ef5c23f80,0,0,4096,4096,512,0,35328,26112,33732,33732,0,0,0,0,0,0,0,0,0,0,0,560,0,8192,6202,56,2001,670,0,0,512,0,56,456,0,512,0,0,0,0,0,10752,3584,512,4096,0,0,0,512,512,1667298,1615115,19927,32256,260520,154115,1394994,0,0,26112,1024,0,1024,4096,0,4096,512,512,1671168,8192,0,0,0,512,512,0,0,0,0,32768,0,0,0,0,0,1024,0,0,0,0,0,0,0,0,0,0,0,0,0,504,56,15896152854722,15906976935930,15906976949530,15896152998919
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,137896,137896,4194304,256,0,0,12,24,14336,0x7f6ef8b5e380,0x7f6ef5c23fc0,0,0,524288,524288,131072,0,4063232,2883584,164664,164664,0,0,0,0,0,0,262144,0,0,0,0,448,0,917504,912756,0,3554,907658,0,0,65536,63800,56,1680,0,65536,0,0,0,0,0,1507328,458752,65536,524288,0,0,0,65536,65536,76929059,47981683,25211824,3735552,1311456,1210376,15640237,0,0,2883584,196608,0,131072,524288,0,524288,65536,131072,184549376,917504,0,0,0,65536,65536,0,0,0,0,4194304,0,0,0,0,0,131072,0,0,0,0,0,0,0,0,0,0,0,0,0,392,56,15896153048378,15906977018810,15906977110971,15896153397420
diff --git a/projects/rocprofiler-compute/tests/workloads/SQ/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/SQ/mi200/prev_analysis/1.csv
index f2944e04e4..efb1d1a92f 100644
--- a/projects/rocprofiler-compute/tests/workloads/SQ/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SQ/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,3356651.0,3356651.0,3356651.0,7.842821735506013
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,1724326.0,1724326.0,1724326.0,4.028891127465483
 "void benchmark_func<double, 256, 8u, 512u>(double, double*) [clone .kd]",1,1714886.0,1714886.0,1714886.0,4.006834548695996
diff --git a/projects/rocprofiler-compute/tests/workloads/SQ/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/SQ/mi200/prev_analysis/1001.csv
index f475f954a6..fb5988001a 100644
--- a/projects/rocprofiler-compute/tests/workloads/SQ/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SQ/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,494.8622754491018,Instr per wave
 VMEM,7.958083832335329,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,0.0,Instr per wave
 SALU,24.520958083832337,Instr per wave
 SMEM,1.8023952095808384,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/SQ/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/SQ/mi200/prev_analysis/1202.csv
index 845bc84bce..6ec8ffd63d 100644
--- a/projects/rocprofiler-compute/tests/workloads/SQ/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SQ/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,18223.096808838985,1879.9828720092773,258137.4652709961,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/SQ/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/SQ/mi200/prev_analysis/1901.csv
index c5d7de8a2d..437efcaba0 100644
--- a/projects/rocprofiler-compute/tests/workloads/SQ/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SQ/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,2.0,smem_
 VALU,495.0,valu_
 MFMA,0.0,mfma_
 VMEM,8.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,10.0,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,128.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,26.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/SQ/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/SQ/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/SQ/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SQ/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/SQ/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/SQ/mi200/prev_analysis/201.csv
index f839151300..351e3a0f5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/SQ/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SQ/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,58.22763983715233,Pct,100,58.22763983715233
 MFMA Util,0.0,Pct,100,0.0
 VALU Active Threads/Wave,64.0,Threads,64,100.0
 IPC - Issue,1.0,Instr/cycle,5,20.0
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99259395413537,Pct,100,99.99259395413537
 Instr Cache BW,1674.120336500895,Gb/s,6092.8,27.477027581750512
 Scalar L1D Cache Hit Rate,99.34855885984425,Pct,100,99.34855885984425
diff --git a/projects/rocprofiler-compute/tests/workloads/SQ/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/SQ/mi200/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/SQ/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SQ/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/SQ/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/SQ/mi200/prev_analysis/701.csv
index 138a2b5ecf..519511494f 100644
--- a/projects/rocprofiler-compute/tests/workloads/SQ/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SQ/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/SQ/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/SQ/mi200/timestamps.csv
index 1f41ba2981..edf8ad8a45 100644
--- a/projects/rocprofiler-compute/tests/workloads/SQ/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SQ/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,138735,138735,33554432,256,0,0,4,32,4160,0x0,0x7f5708c04280,15906971845734,15906971870954,15906972109355,15906972221885
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,138735,138735,32768,256,0,0,12,24,13888,0x0,0x7f5708c23f80,15906976919790,15906976935930,15906976949530,15906976966389
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,138735,138735,4194304,256,0,0,12,24,14336,0x7f5713361380,0x7f5708c23fc0,15906976972839,15906977018810,15906977110971,15906977113236
diff --git a/projects/rocprofiler-compute/tests/workloads/SQC/mi100/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/SQC/mi100/pmc_dispatch_info.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/SQC/mi100/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SQC/mi100/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/SQC/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/SQC/mi100/pmc_perf.csv
index dc0a13207a..3f48d97c06 100644
--- a/projects/rocprofiler-compute/tests/workloads/SQC/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SQC/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBuffer.kd,0,0,0,855764,855769,33554432,256,0,0,8,32,6464,0x0,0x7fb575604180,4036048,3830361,57276432,524288,368613040,336,144,0,504505,504505,0,0,480,0,6291456,6289559,96,2065,2135034,0,0,4194304,4189868,144,4292,2097152,524288,1572864,12074964410272267,12074968630893202,12074968631219119,12074964656414640
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,855764,855769,32768,256,0,0,24,24,12480,0x0,0x7fb575635100,222552,77206,1085921,512,1157151,432,48,0,27818,27818,0,0,480,0,8192,6581,48,1563,1092,0,0,512,0,48,464,0,512,0,12074964670870775,12074968646292397,12074968646299117,12074964671216828
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,855764,855769,4194304,256,0,0,24,24,12928,0x7fb681303900,0x7fb575635140,1758432,1592376,23570750,65536,137358092,384,48,0,219803,219803,0,0,432,0,917504,914195,71,5918,183298,0,0,65536,64048,48,1440,0,65536,0,12074964671293881,12074968646365997,12074968646499116,12074964671663969
diff --git a/projects/rocprofiler-compute/tests/workloads/SQC/mi100/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/SQC/mi100/prev_analysis/1.csv
index 7b42027ffa..16c56a7505 100644
--- a/projects/rocprofiler-compute/tests/workloads/SQC/mi100/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SQC/mi100/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,6054520.0,6054520.0,6054520.0,9.18188638863126
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4526210.0,4526210.0,4526210.0,6.8641520700380365
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 256u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,3051020.0,3051020.0,3051020.0,4.626976045903184
diff --git a/projects/rocprofiler-compute/tests/workloads/SQC/mi100/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/SQC/mi100/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/SQC/mi100/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SQC/mi100/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/SQC/mi100/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/SQC/mi100/prev_analysis/1202.csv
index 6019ed7d7c..3772447924 100644
--- a/projects/rocprofiler-compute/tests/workloads/SQC/mi100/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SQC/mi100/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,33356.74017005052,2812.2943115234375,547945.6834716797,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/SQC/mi100/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/SQC/mi100/prev_analysis/1901.csv
index 2e92141385..73e7a47e83 100644
--- a/projects/rocprofiler-compute/tests/workloads/SQC/mi100/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SQC/mi100/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,24.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,163.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/SQC/mi100/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/SQC/mi100/prev_analysis/2001.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/SQC/mi100/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SQC/mi100/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/SQC/mi100/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/SQC/mi100/prev_analysis/201.csv
index 83fb7bc91a..17cb6b9441 100644
--- a/projects/rocprofiler-compute/tests/workloads/SQC/mi100/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SQC/mi100/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,,Gb/sec,23070.72,
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,,Gb/sec,23070.72,
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99340225613768,Pct,100,99.99340225613768
 Instr Cache BW,1411.1691618570987,Gb/s,4614.144,30.583552699202684
 Scalar L1D Cache Hit Rate,99.35620448529848,Pct,100,99.35620448529848
diff --git a/projects/rocprofiler-compute/tests/workloads/SQC/mi100/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/SQC/mi100/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/SQC/mi100/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SQC/mi100/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/SQC/mi100/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/SQC/mi100/prev_analysis/701.csv
index 8fb0971b0c..b6e142aea6 100644
--- a/projects/rocprofiler-compute/tests/workloads/SQC/mi100/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SQC/mi100/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,23.976047904191617,8,36,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/SQC/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/SQC/mi100/timestamps.csv
index edd2230928..dc6b7d70c4 100644
--- a/projects/rocprofiler-compute/tests/workloads/SQC/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SQC/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,855909,855914,33554432,256,0,0,8,32,6464,0x0,0x7f96d3204180,12074968630846690,12074968630893202,12074968631219119,12074968631310091
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,855909,855914,32768,256,0,0,24,24,12480,0x0,0x7f96d3235100,12074968646192088,12074968646292397,12074968646299117,12074968646304877
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,855909,855914,4194304,256,0,0,24,24,12928,0x7f980336b900,0x7f96d3235140,12074968646353167,12074968646365997,12074968646499116,12074968646502645
diff --git a/projects/rocprofiler-compute/tests/workloads/SQC/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/SQC/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/SQC/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SQC/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/SQC/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/SQC/mi200/pmc_perf.csv
index 0f4f42be17..f384ff2be7 100644
--- a/projects/rocprofiler-compute/tests/workloads/SQC/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SQC/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBufferAligned.kd,0,0,0,142876,142876,33554432,256,0,0,4,32,4160,0x0,0x7f9c48e04280,3083768,2993273,38889450,524288,244059548,392,224,0,385470,385470,0,0,616,0,4718592,4714796,112,3684,1043234,0,524288,3670016,3663326,224,6466,1048576,1048576,1048576,15992426510816,15995326289103,15995326528944,15992575262378
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,142876,142876,32768,256,0,0,12,24,13888,0x0,0x7f9c48e23f80,261016,158043,1348509,512,1598971,504,56,0,32626,32626,0,0,560,0,8192,6249,56,1887,652,0,0,512,0,56,456,0,512,0,15992580439443,15995331324002,15995331337762,15992580578030
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,142876,142876,4194304,256,0,0,12,24,14336,0x7f9c4bd80380,0x7f9c48e23fc0,1318936,1211916,15668226,65536,81562850,392,56,0,164866,164866,0,0,448,0,917504,913474,0,4030,890705,0,0,65536,63800,56,1680,0,65536,0,15992580627039,15995331407843,15995331500803,15992580974291
diff --git a/projects/rocprofiler-compute/tests/workloads/SQC/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/SQC/mi200/prev_analysis/1.csv
index 6a75de14a8..2ab3fb8a50 100644
--- a/projects/rocprofiler-compute/tests/workloads/SQC/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SQC/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,3358094.0,3358094.0,3358094.0,7.8413507966862595
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,1726407.0,1726407.0,1726407.0,4.031263837419303
 "void benchmark_func<double, 256, 8u, 512u>(double, double*) [clone .kd]",1,1716007.0,1716007.0,1716007.0,4.006979213973522
diff --git a/projects/rocprofiler-compute/tests/workloads/SQC/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/SQC/mi200/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/SQC/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SQC/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/SQC/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/SQC/mi200/prev_analysis/1202.csv
index 646912340c..d721a34d23 100644
--- a/projects/rocprofiler-compute/tests/workloads/SQC/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SQC/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,18329.806727426494,1862.0265808105469,257834.38427734375,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/SQC/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/SQC/mi200/prev_analysis/1901.csv
index cc484de095..7e2dcffeb3 100644
--- a/projects/rocprofiler-compute/tests/workloads/SQC/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SQC/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,128.0,il1_fetch_
 IL1 Hit,99.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/SQC/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/SQC/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/SQC/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SQC/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/SQC/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/SQC/mi200/prev_analysis/201.csv
index 1542d0c354..fd37939350 100644
--- a/projects/rocprofiler-compute/tests/workloads/SQC/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SQC/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,,Gb/sec,22630.4,
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,,Gb/sec,22630.4,
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99255517664069,Pct,100,99.99255517664069
 Instr Cache BW,1672.0066536496913,Gb/s,6092.8,27.442336095878602
 Scalar L1D Cache Hit Rate,99.34855886076369,Pct,100,99.34855886076369
diff --git a/projects/rocprofiler-compute/tests/workloads/SQC/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/SQC/mi200/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/SQC/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SQC/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/SQC/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/SQC/mi200/prev_analysis/701.csv
index d28098ed25..9d9e3a3dab 100644
--- a/projects/rocprofiler-compute/tests/workloads/SQC/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SQC/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/SQC/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/SQC/mi200/timestamps.csv
index 81a3bb8711..125d04340b 100644
--- a/projects/rocprofiler-compute/tests/workloads/SQC/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/SQC/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,143037,143037,33554432,256,0,0,4,32,4160,0x0,0x7fd1f5204280,15995326264762,15995326289103,15995326528944,15995326640693
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,143037,143037,32768,256,0,0,12,24,13888,0x0,0x7fd1f5223f80,15995331308630,15995331324002,15995331337762,15995331355039
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,143037,143037,4194304,256,0,0,12,24,14336,0x7fd1f8121380,0x7fd1f5223fc0,15995331360479,15995331407843,15995331500803,15995331502795
diff --git a/projects/rocprofiler-compute/tests/workloads/TA/mi100/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/TA/mi100/pmc_dispatch_info.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/TA/mi100/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TA/mi100/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/TA/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/TA/mi100/pmc_perf.csv
index 4ae6e4b2de..2054c53813 100644
--- a/projects/rocprofiler-compute/tests/workloads/TA/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TA/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,GRBM_COUNT,GRBM_GUI_ACTIVE,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,GRBM_COUNT,GRBM_GUI_ACTIVE,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBuffer.kd,0,0,0,857583,857588,33554432,256,0,0,8,32,6464,0x0,0x7fbf7a204180,4016848,3808248,56922495,524288,372711809,502105,502105,54315858,54220114,0,0,17584769,1048576,0,37475666,1048576,0,1048576,0,1048576,52267001,52021897,53959648,53632699,54157650,4194304,4194304,4194304,0,0,0,365635,0,0,0,0,0,1048576,12075005624787169,12075022762977568,12075022763304925,12075005872218276
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,857583,857588,32768,256,0,0,24,24,12480,0x0,0x7fbf7a235100,224120,77149,1079368,512,1150204,28014,28014,131904,113142,0,0,60588,4096,0,0,4096,4096,0,0,4096,68890,65845,0,0,0,16384,16384,0,0,0,0,2296,0,0,0,0,0,4096,12075005887090134,12075022779046022,12075022779052582,12075005887527727
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,857583,857588,4194304,256,0,0,24,24,12928,0x7fc085d83900,0x7fbf7a235140,1746856,1582962,23486854,65536,136653633,218356,218356,22023321,21895572,0,0,21003847,524288,0,0,524288,524288,0,0,524288,22455427,22452384,0,0,0,2097152,2097152,0,0,0,0,16385,0,0,0,0,0,524288,12075005887702171,12075022779130981,12075022779261700,12075005888204024
diff --git a/projects/rocprofiler-compute/tests/workloads/TA/mi100/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/TA/mi100/prev_analysis/1.csv
index e8ef0b6ec7..2ae591c034 100644
--- a/projects/rocprofiler-compute/tests/workloads/TA/mi100/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TA/mi100/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,6051953.0,6051953.0,6051953.0,9.170412884681694
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4525085.0,4525085.0,4525085.0,6.856777934045399
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 256u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,3047976.0,3047976.0,3047976.0,4.618541879390102
diff --git a/projects/rocprofiler-compute/tests/workloads/TA/mi100/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/TA/mi100/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/TA/mi100/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TA/mi100/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/TA/mi100/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/TA/mi100/prev_analysis/1202.csv
index 614ce9007d..a3b1b481ef 100644
--- a/projects/rocprofiler-compute/tests/workloads/TA/mi100/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TA/mi100/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,33586.87437288204,2843.5654373168945,547900.4818725586,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/TA/mi100/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/TA/mi100/prev_analysis/1901.csv
index f64846925a..627696d1ef 100644
--- a/projects/rocprofiler-compute/tests/workloads/TA/mi100/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TA/mi100/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,24.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,,il1_fetch_
 IL1 Hit,,il1_hit_
 IL1_L2 Rd,,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/TA/mi100/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/TA/mi100/prev_analysis/2001.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/TA/mi100/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TA/mi100/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/TA/mi100/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/TA/mi100/prev_analysis/201.csv
index 07a3c668c7..179480bed5 100644
--- a/projects/rocprofiler-compute/tests/workloads/TA/mi100/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TA/mi100/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,,Gb/sec,23070.72,
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,,Gb/sec,23070.72,
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,,Pct,100,
 Instr Cache BW,,Gb/s,4614.144,
 Scalar L1D Cache Hit Rate,,Pct,100,
diff --git a/projects/rocprofiler-compute/tests/workloads/TA/mi100/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/TA/mi100/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/TA/mi100/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TA/mi100/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/TA/mi100/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/TA/mi100/prev_analysis/701.csv
index 8fb0971b0c..b6e142aea6 100644
--- a/projects/rocprofiler-compute/tests/workloads/TA/mi100/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TA/mi100/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,23.976047904191617,8,36,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/TA/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/TA/mi100/timestamps.csv
index fd29689095..359cdd533f 100644
--- a/projects/rocprofiler-compute/tests/workloads/TA/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TA/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,858094,858099,33554432,256,0,0,8,32,6464,0x0,0x7f2c50c04180,12075022762935705,12075022762977568,12075022763304925,12075022763431626
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,858094,858099,32768,256,0,0,24,24,12480,0x0,0x7f2c50c35100,12075022778935889,12075022779046022,12075022779052582,12075022779058687
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,858094,858099,4194304,256,0,0,24,24,12928,0x7f2d5c76e900,0x7f2c50c35140,12075022779116895,12075022779130981,12075022779261700,12075022779265211
diff --git a/projects/rocprofiler-compute/tests/workloads/TA/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/TA/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/TA/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TA/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/TA/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/TA/mi200/pmc_perf.csv
index eae08464b7..6ef72004c2 100644
--- a/projects/rocprofiler-compute/tests/workloads/TA/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TA/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,GRBM_COUNT,GRBM_GUI_ACTIVE,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,GRBM_COUNT,GRBM_GUI_ACTIVE,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBufferAligned.kd,0,0,0,145593,145593,33554432,256,0,0,4,32,4160,0x0,0x7fc075e04280,3086600,2999136,38943805,524288,242505422,385824,385824,31218489.0,30844323.0,28229379.0,27478990.0,0.0,0.0,19970745.0,524288.0,0.0,20911587.0,524288.0,0.0,524288.0,0.0,0.0,29781861.0,28088624.0,29252073.0,2097152.0,2097152.0,4194304.0,77.0,0.0,0.0,1245507.0,0.0,0.0,0.0,0.0,0.0,0.0,16062052903004,16074044451735,16074044692537,16062204068440
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,145593,145593,32768,256,0,0,12,24,13888,0x0,0x7fc075e23f80,273568,158617,1465257,512,1782234,34195,34195,35277.0,30729.0,37671.0,36325.0,0.0,0.0,16621.0,4096.0,0.0,0.0,4096.0,4096.0,0.0,0.0,4096.0,0.0,0.0,0.0,16384.0,16384.0,0.0,0.0,0.0,0.0,1341.0,0.0,0.0,0.0,0.0,0.0,4096.0,16062209486770,16074049489845,16074049503445,16062209674865
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,145593,145593,4194304,256,0,0,12,24,14336,0x7fc078d53380,0x7fc075e23fc0,1410112,1280712,16509767,65536,80439646,176263,176263,11638605.0,11329706.0,12043703.0,12011243.0,0.0,0.0,9081557.0,524288.0,0.0,0.0,524288.0,524288.0,0.0,0.0,524288.0,0.0,0.0,0.0,2097152.0,2097152.0,0.0,160.0,0.0,0.0,43360.0,0.0,0.0,0.0,0.0,0.0,524288.0,16062209964069,16074049569366,16074049661366,16062210260012
diff --git a/projects/rocprofiler-compute/tests/workloads/TA/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/TA/mi200/prev_analysis/1.csv
index 5733f86cd5..cf269ac5e7 100644
--- a/projects/rocprofiler-compute/tests/workloads/TA/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TA/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,3357141.0,3357141.0,3357141.0,7.837409965493733
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,1724971.0,1724971.0,1724971.0,4.027029220872072
 "void benchmark_func<double, 256, 8u, 512u>(double, double*) [clone .kd]",1,1715371.0,1715371.0,1715371.0,4.0046175510408855
diff --git a/projects/rocprofiler-compute/tests/workloads/TA/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/TA/mi200/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/TA/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TA/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/TA/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/TA/mi200/prev_analysis/1202.csv
index dc18d0b076..a8829aed29 100644
--- a/projects/rocprofiler-compute/tests/workloads/TA/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TA/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,18130.19254462876,1850.1695404052734,257775.34197998047,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/TA/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/TA/mi200/prev_analysis/1901.csv
index 7496dfafd2..7c7f7ca887 100644
--- a/projects/rocprofiler-compute/tests/workloads/TA/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TA/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,,il1_fetch_
 IL1 Hit,,il1_hit_
 IL1_L2 Rd,,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/TA/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/TA/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/TA/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TA/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/TA/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/TA/mi200/prev_analysis/201.csv
index a68da7a926..055e24ffb6 100644
--- a/projects/rocprofiler-compute/tests/workloads/TA/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TA/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,,Gb/sec,22630.4,
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,,Gb/sec,22630.4,
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,,Pct,100,
 Instr Cache BW,,Gb/s,6092.8,
 Scalar L1D Cache Hit Rate,,Pct,100,
diff --git a/projects/rocprofiler-compute/tests/workloads/TA/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/TA/mi200/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/TA/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TA/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/TA/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/TA/mi200/prev_analysis/701.csv
index d28098ed25..9d9e3a3dab 100644
--- a/projects/rocprofiler-compute/tests/workloads/TA/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TA/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/TA/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/TA/mi200/timestamps.csv
index 17c2a94fdd..ac3db92eef 100644
--- a/projects/rocprofiler-compute/tests/workloads/TA/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TA/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,146066,146066,33554432,256,0,0,4,32,4160,0x0,0x7f1450604280,16074044426366,16074044451735,16074044692537,16074044806897
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,146066,146066,32768,256,0,0,12,24,13888,0x0,0x7f1450623f80,16074049474714,16074049489845,16074049503445,16074049520623
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,146066,146066,4194304,256,0,0,12,24,14336,0x7f1453686380,0x7f1450623fc0,16074049526892,16074049569366,16074049661366,16074049663339
diff --git a/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi100/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi100/pmc_dispatch_info.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi100/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi100/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi100/pmc_perf.csv
index 90ed33d78c..3903ca750d 100644
--- a/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,GRBM_COUNT,GRBM_GUI_ACTIVE,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,CPC_ME1_DC0_SPI_BUSY,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,GRBM_COUNT,GRBM_GUI_ACTIVE,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,CPC_ME1_DC0_SPI_BUSY,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBuffer.kd,0,0,0,871499,871504,33554432,256,0,0,8,32,6464,0x0,0x7f4be5a04180,4059152,3844127,524288,57377893,367960703,507393,507393,54491517,54385312,507393,0,0,0,17573208,1048576,0,37445754,1048576,0,1048576,0,1048576,52652181,52428399,724,502077,54350164,54039227,11893,2015,54077405,4194304,2904,498642,4194304,4194304,0,16455,0,0,477793,0,329999,0,0,0,0,0,1048576,12075355475932331,12075372569005997,12075372569330474,12075355721433734
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,871499,871504,32768,256,0,0,24,24,12480,0x0,0x7f4be5a35100,225320,77757,512,1082107,1153771,28164,28164,88545,63266,28164,0,0,0,104775,4096,0,0,4096,4096,0,0,4096,69572,66590,606,26910,0,0,11530,2023,0,16384,2798,24972,16384,0,0,19972,0,0,696,0,3198,0,0,0,0,0,4096,12075355735989601,12075372584412327,12075372584418887,12075355736459775
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,871499,871504,4194304,256,0,0,24,24,12928,0x7f4cf1757900,0x7f4be5a35140,1721336,1554366,65536,23051560,137677073,215166,215166,21611925,21435597,215166,0,0,0,19421739,524288,0,0,524288,524288,0,0,524288,22593525,22582088,747,224718,0,0,11116,2060,0,2097152,2915,210511,2097152,0,0,21453,0,0,194283,0,4852,0,0,0,0,0,524288,12075355736631033,12075372584470887,12075372584608486,12075355737130741
diff --git a/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi100/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi100/prev_analysis/1.csv
index f5616de6b6..d54a1dd6fc 100644
--- a/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi100/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi100/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,6057389.0,6057389.0,6057389.0,9.157323354905657
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4526043.0,4526043.0,4526043.0,6.842294471959331
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 256u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,3053575.0,3053575.0,3053575.0,4.616275042506935
diff --git a/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi100/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi100/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi100/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi100/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi100/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi100/prev_analysis/1202.csv
index 9d94c4c19c..ed265ec446 100644
--- a/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi100/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi100/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,33614.53280434066,2807.3173751831055,547947.6419677734,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi100/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi100/prev_analysis/1901.csv
index c4ae26ace1..198a134472 100644
--- a/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi100/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi100/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,24.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,,il1_fetch_
 IL1 Hit,,il1_hit_
 IL1_L2 Rd,,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi100/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi100/prev_analysis/2001.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi100/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi100/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi100/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi100/prev_analysis/201.csv
index 70e9b2404f..3899a6ac1e 100644
--- a/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi100/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi100/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,,Gb/sec,23070.72,
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,,Gb/sec,23070.72,
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,,Pct,100,
 Instr Cache BW,,Gb/s,4614.144,
 Scalar L1D Cache Hit Rate,,Pct,100,
diff --git a/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi100/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi100/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi100/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi100/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi100/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi100/prev_analysis/701.csv
index 8fb0971b0c..b6e142aea6 100644
--- a/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi100/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi100/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,23.976047904191617,8,36,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi100/timestamps.csv
index 8042c588f5..ec810780ef 100644
--- a/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,872025,872030,33554432,256,0,0,8,32,6464,0x0,0x7faa2e404180,12075372568959986,12075372569005997,12075372569330474,12075372569438535
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,872025,872030,32768,256,0,0,24,24,12480,0x0,0x7faa2e435100,12075372584310659,12075372584412327,12075372584418887,12075372584424721
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,872025,872030,4194304,256,0,0,24,24,12928,0x7fab39fb2900,0x7faa2e435140,12075372584458875,12075372584470887,12075372584608486,12075372584611979
diff --git a/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi200/pmc_perf.csv
index 6a52df804e..62c4a32d68 100644
--- a/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,GRBM_COUNT,GRBM_GUI_ACTIVE,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,CPC_ME1_DC0_SPI_BUSY,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,GRBM_COUNT,GRBM_GUI_ACTIVE,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,CPC_ME1_DC0_SPI_BUSY,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBufferAligned.kd,0,0,0,165605,165605,33554432,256,0,0,4,32,4160,0x0,0x7fc640604280,3058048,2972073,524288,38600369,239545380,382255,382255,30887826.0,30512995.0,382255,0,28043621.0,27295529.0,302,379838,0.0,0.0,19868578.0,524288.0,0.0,20898975.0,524288.0,0.0,524288.0,0.0,0.0,29753468.0,28054132.0,8360,900,29389392.0,2097152.0,1234,382437,2097152.0,4194304.0,0,8953,64.0,0.0,370417,0.0,1287339.0,0.0,0.0,0.0,0.0,0.0,0.0,16597143607745,16609156749657,16609156989655,16597287175645
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,165605,165605,32768,256,0,0,12,24,13888,0x0,0x7fc640623f80,265200,158951,512,1384849,1677609,33149,33149,36320.0,33364.0,33149,0,31904.0,30544.0,302,33529,0.0,0.0,24422.0,4096.0,0.0,0.0,4096.0,4096.0,0.0,0.0,4096.0,0.0,0.0,11312,1026,0.0,16384.0,1353,32187,16384.0,0.0,0,29773,2.0,0.0,497,0.0,1393.0,0.0,0.0,0.0,0.0,0.0,4096.0,16597292632314,16609161812981,16609161826261,16597292827068
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,165605,165605,4194304,256,0,0,12,24,14336,0x7fc65ed2e380,0x7fc640623fc0,1386256,1259569,65536,16297251,81916630,173281,173281,11933110.0,11603768.0,173281,0,11686577.0,11647908.0,351,178495,0.0,0.0,11705475.0,524288.0,0.0,0.0,524288.0,524288.0,0.0,0.0,524288.0,0.0,0.0,19095,4135,0.0,2097152.0,4644,168667,2097152.0,0.0,0,20836,209.0,0.0,154668,0.0,21793.0,0.0,0.0,0.0,0.0,0.0,524288.0,16597293117657,16609161893620,16609161985780,16597293401058
diff --git a/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi200/prev_analysis/1.csv
index dcd1856427..234043b1a4 100644
--- a/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,3357736.0,3357736.0,3357736.0,7.835448981441057
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,1724628.0,1724628.0,1724628.0,4.024507795122883
 "void benchmark_func<double, 256, 8u, 512u>(double, double*) [clone .kd]",1,1716788.0,1716788.0,1716788.0,4.0062127534595415
diff --git a/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi200/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi200/prev_analysis/1202.csv
index 0dd98b5e4d..90eafdc664 100644
--- a/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,18225.31987008649,1827.5862121582031,257818.0599975586,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi200/prev_analysis/1901.csv
index 175504a3c4..2854b46b80 100644
--- a/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,,il1_fetch_
 IL1 Hit,,il1_hit_
 IL1_L2 Rd,,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi200/prev_analysis/201.csv
index a68da7a926..055e24ffb6 100644
--- a/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,,Gb/sec,22630.4,
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,,Gb/sec,22630.4,
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,,Pct,100,
 Instr Cache BW,,Gb/s,6092.8,
 Scalar L1D Cache Hit Rate,,Pct,100,
diff --git a/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi200/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi200/prev_analysis/701.csv
index d28098ed25..9d9e3a3dab 100644
--- a/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi200/timestamps.csv
index ee03171b98..939e5a61da 100644
--- a/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TA_CPC/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,166078,166078,33554432,256,0,0,4,32,4160,0x0,0x7f7fe5804280,16609156724687,16609156749657,16609156989655,16609157080154
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,166078,166078,32768,256,0,0,12,24,13888,0x0,0x7f7fe5823f80,16609161797070,16609161812981,16609161826261,16609161844229
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,166078,166078,4194304,256,0,0,12,24,14336,0x7f7fe88fd380,0x7f7fe5823fc0,16609161849149,16609161893620,16609161985780,16609161988234
diff --git a/projects/rocprofiler-compute/tests/workloads/TCC/mi100/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/TCC/mi100/pmc_dispatch_info.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/TCC/mi100/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TCC/mi100/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/TCC/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/TCC/mi100/pmc_perf.csv
index 6171b64b26..f2ea1d20dc 100644
--- a/projects/rocprofiler-compute/tests/workloads/TCC/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TCC/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,GRBM_COUNT,GRBM_GUI_ACTIVE,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TCC_EA_ATOMIC_LEVEL_sum,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,GRBM_COUNT,GRBM_GUI_ACTIVE,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TCC_EA_ATOMIC_LEVEL_sum,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBuffer.kd,0,0,0,863873,863878,33554432,256,0,0,8,32,6464,0x0,0x7f6c94804180,4043984,3841536,524288,505497,505497,16175904,15326395,0,0,0,96,10687,0,8388944,8399871,0,4194727,4205144,11097,8388608,0,4194394,4194364,4194364,0,223527,0,0,215899,0,0,10563,0,21108,0,0,0,151892,4128825,65535,4063244,0,10517,4194368,13171725,611665146,12075166098232254,12075177938979153,12075177939304590,12075166346728601
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,863873,863878,32768,256,0,0,24,24,12480,0x0,0x7f6c94835100,218536,76907,512,27316,27316,874112,194008,0,0,0,48,220,0,8624,8893,0,470,8423,8891,0,0,31,0,0,0,0,0,0,0,0,0,8422,0,440,0,0,0,49837,0,0,0,0,8372,0,3391711,0,12075166361193422,12075177954367351,12075177954373911,12075166361704922
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,863873,863878,4194304,256,0,0,24,24,12928,0x7f6da043e900,0x7f6c94835140,1818352,1657128,65536,227293,227293,7273376,6556470,0,0,0,48,3128,0,2097536,2101971,0,423,2101548,2102687,0,0,31,0,0,0,0,0,0,0,0,0,2101790,0,9258,0,0,351401,404242,0,0,1966096,0,2099593,0,1102585342,0,12075166361821559,12075177954432950,12075177954570549,12075166362465015
diff --git a/projects/rocprofiler-compute/tests/workloads/TCC/mi100/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/TCC/mi100/prev_analysis/1.csv
index bb04a349dd..e601d0de50 100644
--- a/projects/rocprofiler-compute/tests/workloads/TCC/mi100/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TCC/mi100/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,6055165.0,6055165.0,6055165.0,9.17360050008471
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4528134.0,4528134.0,4528134.0,6.860142098002381
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 256u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,3052302.0,3052302.0,3052302.0,4.624250396745516
diff --git a/projects/rocprofiler-compute/tests/workloads/TCC/mi100/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/TCC/mi100/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/TCC/mi100/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TCC/mi100/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/TCC/mi100/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/TCC/mi100/prev_analysis/1202.csv
index d92c0479fa..2d4898d1f7 100644
--- a/projects/rocprofiler-compute/tests/workloads/TCC/mi100/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TCC/mi100/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,,,,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/TCC/mi100/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/TCC/mi100/prev_analysis/1901.csv
index 3c05bc5ae6..84e45db8f7 100644
--- a/projects/rocprofiler-compute/tests/workloads/TCC/mi100/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TCC/mi100/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,24.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,,il1_fetch_
 IL1 Hit,,il1_hit_
 IL1_L2 Rd,,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,0.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,44.0,hbm_rd_
 HBM Wr,0.0,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/TCC/mi100/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/TCC/mi100/prev_analysis/2001.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/TCC/mi100/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TCC/mi100/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/TCC/mi100/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/TCC/mi100/prev_analysis/201.csv
index e04e5a0bf0..d7832f936c 100644
--- a/projects/rocprofiler-compute/tests/workloads/TCC/mi100/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TCC/mi100/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,,Gb/sec,23070.72,
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,,Gb/sec,23070.72,
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,,Pct,100,
 Instr Cache BW,,Gb/s,4614.144,
 Scalar L1D Cache Hit Rate,,Pct,100,
diff --git a/projects/rocprofiler-compute/tests/workloads/TCC/mi100/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/TCC/mi100/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/TCC/mi100/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TCC/mi100/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/TCC/mi100/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/TCC/mi100/prev_analysis/701.csv
index 8fb0971b0c..b6e142aea6 100644
--- a/projects/rocprofiler-compute/tests/workloads/TCC/mi100/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TCC/mi100/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,23.976047904191617,8,36,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/TCC/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/TCC/mi100/timestamps.csv
index f6b0ece59a..62ba5fd1cc 100644
--- a/projects/rocprofiler-compute/tests/workloads/TCC/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TCC/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,864231,864236,33554432,256,0,0,8,32,6464,0x0,0x7fbc82404180,12075177938939454,12075177938979153,12075177939304590,12075177939417693
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,864231,864236,32768,256,0,0,24,24,12480,0x0,0x7fbc82435100,12075177954267699,12075177954367351,12075177954373911,12075177954379056
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,864231,864236,4194304,256,0,0,24,24,12928,0x7fbd8df8b900,0x7fbc82435140,12075177954420163,12075177954432950,12075177954570549,12075177954573548
diff --git a/projects/rocprofiler-compute/tests/workloads/TCC/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/TCC/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/TCC/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TCC/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/TCC/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/TCC/mi200/pmc_perf.csv
index 849b2da762..77e8f08939 100644
--- a/projects/rocprofiler-compute/tests/workloads/TCC/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TCC/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,GRBM_COUNT,GRBM_GUI_ACTIVE,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,TCC_EA_ATOMIC_LEVEL_sum,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,GRBM_COUNT,GRBM_GUI_ACTIVE,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,TCC_EA_ATOMIC_LEVEL_sum,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBufferAligned.kd,0,0,0,154513,154513,33554432,256,0,0,4,32,4160,0x0,0x7fbb0a204280,3076816,2991462,524288,384601,384601,12307232.0,9403842.0,0.0,0.0,56.0,303.0,0.0,4194696.0,0.0,4195052.0,0.0,2097594.0,2097458.0,750.0,4194304.0,0.0,2064387.0,4128768.0,4128768.0,0.0,1472185.0,0.0,0.0,1492792.0,0.0,0.0,311.0,0.0,606.0,0.0,0.0,0.0,200953.0,2064384.0,0.0,2031623.0,0.0,141.0,4128768.0,989215.0,1616374412.0,16299483631972,16307555332228,16307555571270,16299629181928
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,154513,154513,32768,256,0,0,12,24,13888,0x0,0x7fbb0a223f80,268296,168350,512,33536,33536,1073152.0,397446.0,0.0,0.0,0.0,60.0,0.0,4600.0,0.0,4659.0,0.0,499.0,4160.0,4660.0,0.0,0.0,31.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,8260.0,0.0,118.0,0.0,0.0,0.0,52775.0,0.0,0.0,0.0,0.0,8205.0,0.0,3274341.0,0.0,16299634449212,16307560365218,16307560378338,16299634704877
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,154513,154513,4194304,256,0,0,12,24,14336,0x7fbb0cfbe380,0x7fbb0a223fc0,1322240,1212884,65536,165279,165279,5288928.0,4735777.0,0.0,0.0,0.0,186.0,0.0,1048968.0,0.0,1049151.0,0.0,388.0,1048763.0,1049143.0,0.0,0.0,31.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,2097344.0,0.0,370.0,0.0,0.0,499659.0,1573706.0,0.0,0.0,983046.0,0.0,2097289.0,0.0,1443042619.0,0.0,16299634791785,16307560446819,16307560538979,16299635362512
diff --git a/projects/rocprofiler-compute/tests/workloads/TCC/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/TCC/mi200/prev_analysis/1.csv
index ee5da9ff50..888f20aa28 100644
--- a/projects/rocprofiler-compute/tests/workloads/TCC/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TCC/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,3358900.0,3358900.0,3358900.0,7.84242453986607
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,1726090.0,1726090.0,1726090.0,4.03010824198917
 "void benchmark_func<double, 256, 8u, 512u>(double, double*) [clone .kd]",1,1716011.0,1716011.0,1716011.0,4.006575598285187
diff --git a/projects/rocprofiler-compute/tests/workloads/TCC/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/TCC/mi200/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/TCC/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TCC/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/TCC/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/TCC/mi200/prev_analysis/1202.csv
index d92c0479fa..2d4898d1f7 100644
--- a/projects/rocprofiler-compute/tests/workloads/TCC/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TCC/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,,,,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/TCC/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/TCC/mi200/prev_analysis/1901.csv
index 3c812f7ee9..1e5bb4744d 100644
--- a/projects/rocprofiler-compute/tests/workloads/TCC/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TCC/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,,il1_fetch_
 IL1 Hit,,il1_hit_
 IL1_L2 Rd,,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,0.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,44.0,hbm_rd_
 HBM Wr,0.0,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/TCC/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/TCC/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/TCC/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TCC/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/TCC/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/TCC/mi200/prev_analysis/201.csv
index 49709e0741..f6565c9ae1 100644
--- a/projects/rocprofiler-compute/tests/workloads/TCC/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TCC/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,,Gb/sec,22630.4,
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,,Gb/sec,22630.4,
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,,Pct,100,
 Instr Cache BW,,Gb/s,6092.8,
 Scalar L1D Cache Hit Rate,,Pct,100,
diff --git a/projects/rocprofiler-compute/tests/workloads/TCC/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/TCC/mi200/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/TCC/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TCC/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/TCC/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/TCC/mi200/prev_analysis/701.csv
index d28098ed25..9d9e3a3dab 100644
--- a/projects/rocprofiler-compute/tests/workloads/TCC/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TCC/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/TCC/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/TCC/mi200/timestamps.csv
index 3838347049..345175f5ba 100644
--- a/projects/rocprofiler-compute/tests/workloads/TCC/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TCC/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,154856,154856,33554432,256,0,0,4,32,4160,0x0,0x7f3b44204280,16307555306468,16307555332228,16307555571270,16307555684360
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,154856,154856,32768,256,0,0,12,24,13888,0x0,0x7f3b44223f80,16307560349507,16307560365218,16307560378338,16307560395576
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,154856,154856,4194304,256,0,0,12,24,14336,0x7f3b62b2a380,0x7f3b44223fc0,16307560400826,16307560446819,16307560538979,16307560541203
diff --git a/projects/rocprofiler-compute/tests/workloads/TCP/mi100/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/TCP/mi100/pmc_dispatch_info.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/TCP/mi100/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TCP/mi100/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/TCP/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/TCP/mi100/pmc_perf.csv
index 4ddae0d580..878e3c8377 100644
--- a/projects/rocprofiler-compute/tests/workloads/TCP/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TCP/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBuffer.kd,0,0,0,861653,861658,33554432,256,0,0,8,32,6464,0x0,0x7fa2ed804180,4017616,3811368,57010570,524288,365706290,502201,502201,57581369,55291458,172,12242759,0,0,0,1048576,67108864,67108864,0,67108864,0,0,360,33554432,15326,16608774,0,16777216,641000253,0,2809786101,0,8388608,0,0,0,0,0,0,0,0,0,0,0,0,8388608,0,42066228,12075111806057902,12075122867722970,12075122868048567,12075112052782898
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,861653,861658,32768,256,0,0,24,24,12480,0x0,0x7fa2ed835100,226960,75885,1058218,512,1129881,28369,28369,1525247,590890,223,123973,0,0,0,4096,65536,65536,65536,0,0,0,360,16384,120,15064,0,16384,13651060,18072802,0,8192,0,0,0,0,0,0,0,0,0,0,0,0,8192,0,0,433075,12075112067269329,12075122883005681,12075122883012241,12075112067789165
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,861653,861658,4194304,256,0,0,24,24,12928,0x7fa3f9496900,0x7fa2ed835140,1851568,1678532,24917394,65536,123263676,231445,231445,25593587,24315118,28167,4305461,0,0,0,524288,8388608,8388608,8388608,0,0,0,360,2097152,7590,2017879,0,2097152,1001448598,1625054991,0,2097152,0,0,0,0,0,0,0,0,0,0,0,0,2097152,0,0,16241328,12075112068132513,12075122883073521,12075122883205199,12075112068769106
diff --git a/projects/rocprofiler-compute/tests/workloads/TCP/mi100/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/TCP/mi100/prev_analysis/1.csv
index e02ef1247d..fe1eab4f0d 100644
--- a/projects/rocprofiler-compute/tests/workloads/TCP/mi100/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TCP/mi100/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,6055155.0,6055155.0,6055155.0,9.183478194506762
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4526687.0,4526687.0,4526687.0,6.86534553745647
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 256u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,3053577.0,3053577.0,3053577.0,4.631170927044374
diff --git a/projects/rocprofiler-compute/tests/workloads/TCP/mi100/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/TCP/mi100/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/TCP/mi100/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TCP/mi100/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/TCP/mi100/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/TCP/mi100/prev_analysis/1202.csv
index c341670a25..633cca670a 100644
--- a/projects/rocprofiler-compute/tests/workloads/TCP/mi100/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TCP/mi100/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,33617.4255854441,2790.1175689697266,547908.5648803711,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/TCP/mi100/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/TCP/mi100/prev_analysis/1901.csv
index 157af0f6bc..935dd7e76c 100644
--- a/projects/rocprofiler-compute/tests/workloads/TCP/mi100/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TCP/mi100/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,24.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,,il1_fetch_
 IL1 Hit,,il1_hit_
 IL1_L2 Rd,,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,29.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/TCP/mi100/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/TCP/mi100/prev_analysis/2001.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/TCP/mi100/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TCP/mi100/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/TCP/mi100/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/TCP/mi100/prev_analysis/201.csv
index 0d8987d5e9..c61d8a2635 100644
--- a/projects/rocprofiler-compute/tests/workloads/TCP/mi100/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TCP/mi100/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,,Gb/sec,23070.72,
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,,Gb/sec,23070.72,
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,,Pct,100,
 Instr Cache BW,,Gb/s,4614.144,
 Scalar L1D Cache Hit Rate,,Pct,100,
diff --git a/projects/rocprofiler-compute/tests/workloads/TCP/mi100/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/TCP/mi100/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/TCP/mi100/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TCP/mi100/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/TCP/mi100/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/TCP/mi100/prev_analysis/701.csv
index 8fb0971b0c..b6e142aea6 100644
--- a/projects/rocprofiler-compute/tests/workloads/TCP/mi100/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TCP/mi100/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,23.976047904191617,8,36,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/TCP/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/TCP/mi100/timestamps.csv
index 33ccfbc7ac..16a2024b2f 100644
--- a/projects/rocprofiler-compute/tests/workloads/TCP/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TCP/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,861981,861986,33554432,256,0,0,8,32,6464,0x0,0x7fbb92a04180,12075122867675859,12075122867722970,12075122868048567,12075122868154970
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,861981,861986,32768,256,0,0,24,24,12480,0x0,0x7fbb92a35100,12075122882900422,12075122883005681,12075122883012241,12075122883018001
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,861981,861986,4194304,256,0,0,24,24,12928,0x7fbcc2b2b900,0x7fbb92a35140,12075122883060480,12075122883073521,12075122883205199,12075122883208515
diff --git a/projects/rocprofiler-compute/tests/workloads/TCP/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/TCP/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/TCP/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TCP/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/TCP/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/TCP/mi200/pmc_perf.csv
index 7330f3cccc..c2f825fdbc 100644
--- a/projects/rocprofiler-compute/tests/workloads/TCP/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TCP/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBufferAligned.kd,0,0,0,151449,151449,33554432,256,0,0,4,32,4160,0x0,0x7f022a604280,3076512,2989574,38842013,524288,242121889,384563,384563,39106410.0,38083768.0,3.0,4067115.0,0.0,0.0,0.0,524288.0,33554432.0,33554432.0,0.0,33554432.0,0.0,0.0,104.0,8388608.0,13284.0,8242484.0,0.0,8388608.0,313264439.0,0.0,1463068751.0,0.0,4194304.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,4194304.0,0.0,19128712.0,16219564975519,16227562900659,16227563139060,16219710251567
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,151449,151449,32768,256,0,0,12,24,13888,0x0,0x7f022a623f80,265008,169056,1410267,512,1756157,33125,33125,2433904.0,174869.0,208.0,0.0,0.0,0.0,0.0,4096.0,65536.0,65536.0,65536.0,0.0,0.0,0.0,104.0,16384.0,104.0,15240.0,0.0,16384.0,3868580.0,5430964.0,0.0,8192.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,8192.0,0.0,0.0,124860.0,16219715974101,16227567936047,16227567949487,16219716213625
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,151449,151449,4194304,256,0,0,12,24,14336,0x7f022d5aa380,0x7f022a623fc0,1390672,1257890,16244343,65536,95138833,173833,173833,16588733.0,13862093.0,23826.0,680816.0,0.0,0.0,0.0,524288.0,8388608.0,8388608.0,8388608.0,0.0,0.0,0.0,208.0,2097152.0,6560.0,2028965.0,0.0,2097152.0,894852738.0,2174316602.0,0.0,2097152.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,2097152.0,0.0,0.0,11602704.0,16219716751753,16227568019567,16227568112208,16219717067306
diff --git a/projects/rocprofiler-compute/tests/workloads/TCP/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/TCP/mi200/prev_analysis/1.csv
index 4bd781ecfc..b32d73b05e 100644
--- a/projects/rocprofiler-compute/tests/workloads/TCP/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TCP/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,3357619.0,3357619.0,3357619.0,7.844741995405001
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,1724810.0,1724810.0,1724810.0,4.029846579106951
 "void benchmark_func<double, 256, 8u, 512u>(double, double*) [clone .kd]",1,1716969.0,1716969.0,1716969.0,4.011526864456191
diff --git a/projects/rocprofiler-compute/tests/workloads/TCP/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/TCP/mi200/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/TCP/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TCP/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/TCP/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/TCP/mi200/prev_analysis/1202.csv
index 14a20dd1c0..0f1711827d 100644
--- a/projects/rocprofiler-compute/tests/workloads/TCP/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TCP/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,18369.813897641117,1847.2434158325195,257897.74127197266,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/TCP/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/TCP/mi200/prev_analysis/1901.csv
index ce4a02d9b4..cb4ade25e6 100644
--- a/projects/rocprofiler-compute/tests/workloads/TCP/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TCP/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,,il1_fetch_
 IL1 Hit,,il1_hit_
 IL1_L2 Rd,,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,2.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/TCP/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/TCP/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/TCP/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TCP/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/TCP/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/TCP/mi200/prev_analysis/201.csv
index e907d6f186..117842f0d6 100644
--- a/projects/rocprofiler-compute/tests/workloads/TCP/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TCP/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,,Gb/sec,22630.4,
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,,Gb/sec,22630.4,
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,,Pct,100,
 Instr Cache BW,,Gb/s,6092.8,
 Scalar L1D Cache Hit Rate,,Pct,100,
diff --git a/projects/rocprofiler-compute/tests/workloads/TCP/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/TCP/mi200/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/TCP/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TCP/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/TCP/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/TCP/mi200/prev_analysis/701.csv
index d28098ed25..9d9e3a3dab 100644
--- a/projects/rocprofiler-compute/tests/workloads/TCP/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TCP/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/TCP/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/TCP/mi200/timestamps.csv
index 9c75060304..4138962e63 100644
--- a/projects/rocprofiler-compute/tests/workloads/TCP/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TCP/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,151766,151766,33554432,256,0,0,4,32,4160,0x0,0x7fde9d204280,16227562875467,16227562900659,16227563139060,16227563229520
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,151766,151766,32768,256,0,0,12,24,13888,0x0,0x7fde9d223f80,16227567920646,16227567936047,16227567949487,16227567968405
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,151766,151766,4194304,256,0,0,12,24,14336,0x7fdea01c0380,0x7fde9d223fc0,16227567970275,16227568019567,16227568112208,16227568114092
diff --git a/projects/rocprofiler-compute/tests/workloads/TD/mi100/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/TD/mi100/pmc_dispatch_info.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/TD/mi100/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TD/mi100/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/TD/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/TD/mi100/pmc_perf.csv
index a4f0c0f60e..e2cdc2ca94 100644
--- a/projects/rocprofiler-compute/tests/workloads/TD/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TD/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,GRBM_COUNT,GRBM_GUI_ACTIVE,TD_TD_BUSY_sum,TD_TC_STALL_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,GRBM_COUNT,GRBM_GUI_ACTIVE,TD_TD_BUSY_sum,TD_TC_STALL_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBuffer.kd,0,0,0,860130,860135,33554432,256,0,0,8,32,6464,0x0,0x7f875ea04180,4026768,3823281,57089627,524288,372083385,503345,503345,55261707,54086759,1048576,1048576,0,1048576,12075073030672697,12075076321956559,12075076322280876,12075073277403934
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,860130,860135,32768,256,0,0,24,24,12480,0x0,0x7f875ea35100,223144,80823,1099072,512,1174935,27892,27892,638660,618215,4096,4096,0,0,12075073291830284,12075076336906869,12075076336914069,12075073292285439
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,860130,860135,4194304,256,0,0,24,24,12928,0x7f888eafa900,0x7f875ea35140,1754480,1587646,23501113,65536,129814297,219309,219309,22913864,20742872,524288,524288,0,0,12075073292452770,12075076336979349,12075076337114228,12075073292947069
diff --git a/projects/rocprofiler-compute/tests/workloads/TD/mi100/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/TD/mi100/prev_analysis/1.csv
index 011a7e8d4d..df362d7281 100644
--- a/projects/rocprofiler-compute/tests/workloads/TD/mi100/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TD/mi100/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,6054837.0,6054837.0,6054837.0,9.19028788551146
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4525248.0,4525248.0,4525248.0,6.868612957431383
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 256u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,3050218.0,3050218.0,3050218.0,4.629749988904573
diff --git a/projects/rocprofiler-compute/tests/workloads/TD/mi100/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/TD/mi100/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/TD/mi100/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TD/mi100/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/TD/mi100/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/TD/mi100/prev_analysis/1202.csv
index 66aea44574..49325c598d 100644
--- a/projects/rocprofiler-compute/tests/workloads/TD/mi100/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TD/mi100/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,33804.82737763913,2838.7709426879883,547990.7490844727,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/TD/mi100/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/TD/mi100/prev_analysis/1901.csv
index 35f43f6080..cc846c20c9 100644
--- a/projects/rocprofiler-compute/tests/workloads/TD/mi100/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TD/mi100/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,24.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,,il1_fetch_
 IL1 Hit,,il1_hit_
 IL1_L2 Rd,,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/TD/mi100/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/TD/mi100/prev_analysis/2001.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/TD/mi100/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TD/mi100/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/TD/mi100/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/TD/mi100/prev_analysis/201.csv
index 1fea9afbb7..00efc0d277 100644
--- a/projects/rocprofiler-compute/tests/workloads/TD/mi100/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TD/mi100/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,,Gb/sec,23070.72,
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,,Gb/sec,23070.72,
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,,Pct,100,
 Instr Cache BW,,Gb/s,4614.144,
 Scalar L1D Cache Hit Rate,,Pct,100,
diff --git a/projects/rocprofiler-compute/tests/workloads/TD/mi100/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/TD/mi100/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/TD/mi100/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TD/mi100/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/TD/mi100/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/TD/mi100/prev_analysis/701.csv
index 8fb0971b0c..b6e142aea6 100644
--- a/projects/rocprofiler-compute/tests/workloads/TD/mi100/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TD/mi100/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,23.976047904191617,8,36,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/TD/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/TD/mi100/timestamps.csv
index af43675cae..cb04ee9fdf 100644
--- a/projects/rocprofiler-compute/tests/workloads/TD/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TD/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,860241,860246,33554432,256,0,0,8,32,6464,0x0,0x7f22fa804180,12075076321911995,12075076321956559,12075076322280876,12075076322370868
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,860241,860246,32768,256,0,0,24,24,12480,0x0,0x7f22fa835100,12075076336802477,12075076336906869,12075076336914069,12075076336919785
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,860241,860246,4194304,256,0,0,24,24,12928,0x7f242a8aa900,0x7f22fa835140,12075076336963797,12075076336979349,12075076337114228,12075076337117783
diff --git a/projects/rocprofiler-compute/tests/workloads/TD/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/TD/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/TD/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TD/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/TD/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/TD/mi200/pmc_perf.csv
index 1a59a7c956..3180140b04 100644
--- a/projects/rocprofiler-compute/tests/workloads/TD/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TD/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,GRBM_COUNT,GRBM_GUI_ACTIVE,TD_TD_BUSY_sum,TD_TC_STALL_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,TD_COALESCABLE_WAVEFRONT_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,GRBM_COUNT,GRBM_GUI_ACTIVE,TD_TD_BUSY_sum,TD_TC_STALL_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,TD_COALESCABLE_WAVEFRONT_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBufferAligned.kd,0,0,0,148935,148935,33554432,256,0,0,4,32,4160,0x0,0x7fe74a404280,3060592,2972533,38620036,524288,240875275,382573,382573,37840900.0,37281003.0,7661.0,524288.0,0.0,524288.0,0.0,16149794842349,16152833487509,16152833727350,16149943687783
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,148935,148935,32768,256,0,0,12,24,13888,0x0,0x7fe74a423f80,263752,161641,1390824,512,1728708,32968,32968,178468.0,159696.0,0.0,4096.0,0.0,0.0,4096.0,16149949158912,16152838526258,16152838539378,16149949350468
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,148935,148935,4194304,256,0,0,12,24,14336,0x7fe74d4cf380,0x7fe74a423fc0,1567456,1438041,18621854,65536,104017641,195931,195931,13732372.0,11593614.0,2600.0,524288.0,0.0,0.0,524288.0,16149949640741,16152838607859,16152838700339,16149949912285
diff --git a/projects/rocprofiler-compute/tests/workloads/TD/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/TD/mi200/prev_analysis/1.csv
index f3df32bee8..044cdca844 100644
--- a/projects/rocprofiler-compute/tests/workloads/TD/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TD/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,3356981.0,3356981.0,3356981.0,7.842544274999051
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,1724010.0,1724010.0,1724010.0,4.027614322375109
 "void benchmark_func<double, 256, 8u, 512u>(double, double*) [clone .kd]",1,1715530.0,1715530.0,1715530.0,4.007803434124031
diff --git a/projects/rocprofiler-compute/tests/workloads/TD/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/TD/mi200/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/TD/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TD/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/TD/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/TD/mi200/prev_analysis/1202.csv
index e170183314..3c497545b8 100644
--- a/projects/rocprofiler-compute/tests/workloads/TD/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TD/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,18482.287568920387,1837.7325057983398,258479.85809326172,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/TD/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/TD/mi200/prev_analysis/1901.csv
index 330df996aa..653f145df7 100644
--- a/projects/rocprofiler-compute/tests/workloads/TD/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TD/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,,il1_fetch_
 IL1 Hit,,il1_hit_
 IL1_L2 Rd,,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/TD/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/TD/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/TD/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TD/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/TD/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/TD/mi200/prev_analysis/201.csv
index a68da7a926..055e24ffb6 100644
--- a/projects/rocprofiler-compute/tests/workloads/TD/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TD/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,,Gb/sec,22630.4,
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,,Gb/sec,22630.4,
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,,Pct,100,
 Instr Cache BW,,Gb/s,6092.8,
 Scalar L1D Cache Hit Rate,,Pct,100,
diff --git a/projects/rocprofiler-compute/tests/workloads/TD/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/TD/mi200/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/TD/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TD/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/TD/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/TD/mi200/prev_analysis/701.csv
index d28098ed25..9d9e3a3dab 100644
--- a/projects/rocprofiler-compute/tests/workloads/TD/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TD/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/TD/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/TD/mi200/timestamps.csv
index 93e2d1cabc..d91029404a 100644
--- a/projects/rocprofiler-compute/tests/workloads/TD/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/TD/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,149096,149096,33554432,256,0,0,4,32,4160,0x0,0x7fd2ec604280,16152833461627,16152833487509,16152833727350,16152833816800
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,149096,149096,32768,256,0,0,12,24,13888,0x0,0x7fd2ec623f80,16152838510616,16152838526258,16152838539378,16152838557375
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,149096,149096,4194304,256,0,0,12,24,14336,0x7fd2ef6ec380,0x7fd2ec623fc0,16152838562854,16152838607859,16152838700339,16152838702261
diff --git a/projects/rocprofiler-compute/tests/workloads/dev0/mi100/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/dev0/mi100/SQ_IFETCH_LEVEL.csv
index ee2315619d..bc1c55fae5 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev0/mi100/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev0/mi100/SQ_IFETCH_LEVEL.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,919533,919538,33554432,256,0,0,8,32,6464,0x0,0x7f539a404180,510905,510905,524288,6291456,791255,101484656,12076299622617100,12076299868527949,12076299868855467,12076299868966179
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,919533,919538,32768,256,0,0,24,24,12480,0x0,0x7f539a435100,29103,29103,512,8192,11024,1421636,12076299883226411,12076299883536030,12076299883542910,12076299883550754
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,919533,919538,4194304,256,0,0,24,24,12928,0x7f54a6102900,0x7f539a435140,214348,214348,65536,917504,141051,18053272,12076299883612759,12076299883846109,12076299883977148,12076299883980823
diff --git a/projects/rocprofiler-compute/tests/workloads/dev0/mi100/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/dev0/mi100/SQ_INST_LEVEL_LDS.csv
index 73100e4b80..4995ba2618 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev0/mi100/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev0/mi100/SQ_INST_LEVEL_LDS.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,921341,921346,33554432,256,0,0,8,32,6464,0x0,0x7f75c7a04180,0,0,0,12076325872059438,12076326117604157,12076326117928636,12076326118038409
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,921341,921346,32768,256,0,0,24,24,12480,0x0,0x7f75c7a35100,0,0,0,12076326132896351,12076326133202573,12076326133209293,12076326133221776
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,921341,921346,4194304,256,0,0,24,24,12928,0x7f76f7c91900,0x7f75c7a35140,0,0,0,12076326133274564,12076326133491052,12076326133626091,12076326133629754
diff --git a/projects/rocprofiler-compute/tests/workloads/dev0/mi100/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/dev0/mi100/SQ_INST_LEVEL_SMEM.csv
index fe95fe1533..62fcbe6918 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev0/mi100/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev0/mi100/SQ_INST_LEVEL_SMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,920962,920967,33554432,256,0,0,8,32,6464,0x0,0x7f7263004180,4194304,3135444,401545944,12076323351077524,12076323592299708,12076323592623867,12076323592733000
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,920962,920967,32768,256,0,0,24,24,12480,0x0,0x7f7263035100,512,24896,3171600,12076323607390380,12076323607684997,12076323607691557,12076323607697111
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,920962,920967,4194304,256,0,0,24,24,12928,0x7f7393007900,0x7f7263035140,65536,199274,25512368,12076323607762212,12076323607972035,12076323608104675,12076323608108936
diff --git a/projects/rocprofiler-compute/tests/workloads/dev0/mi100/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/dev0/mi100/SQ_INST_LEVEL_VMEM.csv
index 34e5e2af81..e97f5ef15f 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev0/mi100/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev0/mi100/SQ_INST_LEVEL_VMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,921153,921158,33554432,256,0,0,8,32,6464,0x0,0x7fbf7ac04180,1048576,11001658,1408052856,12076324607361092,12076324851578856,12076324851903654,12076324852039846
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,921153,921158,32768,256,0,0,24,24,12480,0x0,0x7fbf7ac35100,4096,113289,14479660,12076324866554932,12076324866851777,12076324866858017,12076324866863235
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,921153,921158,4194304,256,0,0,24,24,12928,0x7fc0aab91900,0x7fbf7ac35140,524288,12401318,1587311276,12076324866927514,12076324867148415,12076324867279615,12076324867283767
diff --git a/projects/rocprofiler-compute/tests/workloads/dev0/mi100/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/dev0/mi100/SQ_LEVEL_WAVES.csv
index 08882d8a0b..817c200126 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev0/mi100/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev0/mi100/SQ_LEVEL_WAVES.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,921529,921534,33554432,256,0,0,8,32,6464,0x0,0x7f6f26204180,502695,502695,17046,4021568,524288,372600279,3816924,0,1505167052,12076327135265660,12076327381325743,12076327381649102,12076327381757735
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,921529,921534,32768,256,0,0,24,24,12480,0x0,0x7f6f26235100,27819,27819,20311,222560,512,1122712,74488,0,4504968,12076327396356075,12076327396679513,12076327396685593,12076327396695125
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,921529,921534,4194304,256,0,0,24,24,12928,0x7f7031f1d900,0x7f6f26235140,219204,219204,20615,1753640,65536,131444628,1582707,0,527592892,12076327396760457,12076327397000951,12076327397134071,12076327397138189
diff --git a/projects/rocprofiler-compute/tests/workloads/dev0/mi100/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/dev0/mi100/pmc_dispatch_info.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev0/mi100/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev0/mi100/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/dev0/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/dev0/mi100/pmc_perf.csv
index c77faf9379..8e4c4812c7 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev0/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev0/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBuffer.kd,0,0,0,920267,920272,33554432,256,0,0,8,32,6464,0x0,0x7fab06204180,1048576,0,1048576,9437184,0,4194304,1048576,0,504086,504086,57841875,55545051,101,12842339,54600119,54479341,55506879,54325282,4032688,3840582,504086,0,504086,0,16130752,15292780,0,0,0,0,0,17364464,1048576,0,504436,0,0,0,504436,0,0,0,504436,0,0,0,504436,0,0,0,504436,0,0,0,504436,0,0,0,504436,0,0,0,504436,0,0,0,504436,0,0,0,504436,0,0,0,504436,0,0,0,504436,0,0,0,504436,0,0,0,504436,0,0,0,504436,0,0,0,504436,0,0,0,504436,0,0,0,504436,0,0,0,504436,0,0,0,504436,0,0,0,504436,0,0,0,504436,0,0,0,504436,0,0,0,504436,0,0,0,504436,0,0,0,504436,0,0,0,504436,0,0,0,504436,0,0,0,504436,0,0,0,504436,0,0,0,504436,0,0,0,504436,0,0,0,37416639,48,0,0,0,7,0,0,0,0,0,0,0,2626,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,16,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,48,0,0,0,0,0,0,0,2749,0,0,0,1,0,0,0,3,0,0,0,1,0,0,0,2717,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,2521,0,0,0,1048576,0,0,0,131072,131072,0,1473,131072,131072,0,0,131072,131072,0,0,131072,131072,0,0,131072,131072,0,0,131072,131072,0,267,131076,131076,0,0,131072,131072,0,0,131072,131072,0,510337,131072,131072,0,9569,131072,131072,0,0,131076,131076,0,2960652,131081,131081,0,1851,131076,131076,0,1102,131080,131080,0,21623,131072,131072,0,3137909,131072,131072,0,784,131072,131072,0,0,131080,131080,0,0,131072,131072,0,0,131076,131076,0,0,131072,131072,0,2866651,131076,131076,0,0,131076,131076,0,0,131080,131080,0,0,131072,131072,0,1457,131076,131076,0,0,131072,131072,0,3079721,131072,131072,0,0,131076,131076,0,0,131072,131072,0,0,131072,131072,1048576,0,744,0,0,17166601,793,0,0,17334803,878,0,0,17585011,743,0,0,17119289,822,0,0,17405285,1138,0,0,17288100,807,0,0,18394900,50524,0,0,31546623,757,0,0,17257814,1624,0,0,17330628,775,0,0,17238993,47461,0,0,29636612,767,0,0,17411517,1535,0,0,17346510,1236,0,0,18453856,1438,0,0,18610451,849,0,0,16959535,993,0,0,16670830,1146,0,0,17333955,1484,0,0,16972090,1085,0,0,17430813,1275,0,0,17368545,1322,0,0,18348597,1413,0,0,18513190,791,0,0,16747391,1029,0,0,16863961,1252,0,0,17345123,47163,0,0,30190206,1058,0,0,17389331,829,0,0,17357142,1335,0,0,18555221,47812,0,0,30960009,1048576,131072,131120,48,262192,131260,131076,192,262336,131072,131074,2,262146,131072,131092,20,262164,131072,131120,48,262192,131072,131072,0,262144,131072,131072,0,262144,131072,133714,2642,264786,131072,131072,0,262144,131072,131072,0,262144,131072,131073,1,262145,131072,133526,2454,264598,131072,131073,1,262145,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131073,1,262145,131213,131075,144,262288,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131119,131073,48,262192,131119,131073,48,262192,131072,131072,0,262144,131072,131121,49,262193,131072,131072,0,262144,131072,133718,2646,264790,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,133593,2521,264665,262144,0,262144,262336,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262288,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,0,0,3145728,524288,32505856,367747059,219374587,115866616,483385,0,0,0,1048576,52602364,52346062,1048576,1048576,131072,524288,705,505701,4425,0,96,10724,0,8388944,32505856,4037048,3835935,57310757,11534336,0,0,14155776,67108864,67108864,0,67108864,54387981,54014630,0,1048576,243485,767773,11897,2012,0,498015,8399777,0,4194727,4205050,13631488,0,3670016,1048576,1048576,0,4194304,9437184,0,0,360,33554432,54380247,4194304,0,0,2916,502471,0,11204,8388608,0,4194378,905969664,6291456,0,0,0,524288,524288,0,15325,16608747,0,16777216,4194304,4194304,0,0,0,17732,4194408,4194408,0,216998,0,0,0,33554432,0,0,0,0,635687727,0,2787031935,0,0,0,0,0,477673,0,0,212282,0,0,8388608,336,144,0,0,0,480,8388608,0,0,0,0,324761,0,0,0,10719,0,21420,0,6291456,6289506,96,2061,1930014,0,0,0,0,0,0,0,0,0,3145728,0,0,0,162090,4194304,4189866,144,4294,2097152,524288,1572864,0,0,0,0,0,0,524288,0,4128846,65534,4063249,0,0,8388608,0,42496440,0,1048576,10393,4194393,12442674,608197244,12076301756038962,12076328266837802,12076328267160519,12076302003284266
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,920267,920272,32768,256,0,0,24,24,12480,0x0,0x7fab06235100,0,4096,4096,512,0,512,4096,0,29293,29293,1488707,608227,242,130194,92018,66804,600172,579538,234344,85073,29293,0,29293,0,937376,206624,0,0,0,0,0,59459,4096,0,29798,0,0,0,29798,0,0,0,29798,0,0,0,29798,0,0,0,29798,0,0,0,29798,0,0,0,29798,0,0,0,29798,0,0,0,29798,0,0,0,29798,0,0,0,29798,0,0,0,29798,0,0,0,29798,0,0,0,29798,0,0,0,29798,0,0,0,29798,0,0,0,29798,0,0,0,29798,0,0,0,29798,0,0,0,29798,0,0,0,29798,0,0,0,29798,0,0,0,29798,0,0,0,29798,0,0,0,29798,0,0,0,29798,0,0,0,29798,0,0,0,29798,0,0,0,29798,0,0,0,29798,0,0,0,29798,0,0,0,29798,0,0,0,0,304,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,377,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,304,0,0,0,260,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,261,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,258,0,0,0,256,0,0,0,4096,4096,0,83375,0,0,0,81959,0,0,0,85882,0,0,0,83256,0,0,0,81576,0,0,0,125640,0,0,0,98045,0,0,0,88067,0,0,0,80503,0,0,0,83351,0,0,0,175877,0,0,0,72400,0,0,0,80056,0,0,0,84370,0,0,0,65934,0,0,0,93249,0,0,0,92025,0,0,0,81708,0,0,0,72868,0,0,0,85760,0,0,0,82397,0,0,0,79640,0,0,0,100917,0,0,0,86993,0,0,0,206250,0,0,0,210656,0,0,0,94596,0,0,0,118463,0,0,0,243668,0,0,0,207178,0,0,0,110578,0,0,0,186203,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4096,0,304,304,304,0,256,256,256,0,256,256,256,0,376,376,376,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,257,257,257,0,256,256,256,0,257,257,257,0,256,256,256,188,260,448,448,0,256,256,256,0,257,257,257,0,256,256,256,188,260,448,448,0,256,256,256,0,256,256,256,0,256,256,256,47,257,304,304,0,256,256,256,0,256,256,256,0,305,305,305,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,47,257,304,304,0,256,256,256,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,304,0,0,256,0,0,0,0,512,512,35328,1111517,1058342,16823,11697,0,0,0,4096,64016,60932,4096,4096,128,512,615,27655,4398,0,48,220,0,8624,36352,223752,78244,1079730,26624,0,0,30208,65536,65536,65536,0,0,0,0,0,113,625,11969,1943,0,23615,8891,0,470,8421,1024,0,1024,4096,0,4096,512,512,0,0,360,16384,0,16384,0,0,2897,26458,0,8844,0,0,31,1933312,8192,0,0,0,512,512,0,120,15064,0,16384,16384,0,0,0,0,20528,0,0,0,0,0,0,0,32768,0,0,0,0,11953036,17161711,0,8192,0,0,0,0,695,0,0,0,0,0,1024,432,48,0,0,0,480,0,0,0,0,0,2272,0,0,0,8421,0,438,0,8192,6582,48,1562,1054,0,0,0,0,0,0,0,0,0,2560,0,0,0,49531,512,0,48,464,0,512,0,0,0,0,0,0,0,512,0,0,0,0,0,8192,0,0,440301,0,4096,8373,0,3443573,0,12076302018296035,12076328282246095,12076328282252495,12076302019298037
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,920267,920272,4194304,256,0,0,24,24,12928,0x7fac11e69900,0x7fab06235140,0,524288,524288,65536,0,65536,524288,0,223905,223905,24901953,23653587,29067,7302852,23349113,23295764,23644532,21487887,1791240,1643623,223905,0,223905,0,7164960,6434223,0,0,0,0,0,20832121,524288,0,224910,0,0,0,224910,0,0,0,224910,0,0,0,224910,0,0,0,224910,0,0,0,224910,0,0,0,224910,0,0,0,224910,0,0,0,224910,0,0,0,224910,0,0,0,224910,0,0,0,224910,0,0,0,224910,0,0,0,224910,0,0,0,224910,0,0,0,224910,0,0,0,224910,0,0,0,224910,0,0,0,224910,0,0,0,224910,0,0,0,224910,0,0,0,224910,0,0,0,224910,0,0,0,224910,0,0,0,224910,0,0,0,224910,0,0,0,224910,0,0,0,224910,0,0,0,224910,0,0,0,224910,0,0,0,224910,0,0,0,224910,0,0,0,0,65584,0,3980,0,65536,0,16317,0,65540,0,15297,0,65536,0,8909,0,65536,0,8303,0,65536,0,8886,0,65536,0,515,0,65536,0,1012,0,65657,0,34343,0,65536,0,2353,0,65536,0,6419,0,65536,0,17895,0,65536,0,7727,0,65584,0,9855,0,65536,0,24429,0,66270,0,37218,0,65537,0,4077,0,65536,0,7570,0,65537,0,9539,0,67975,0,61391,0,65536,0,15403,0,65536,0,7285,0,65536,0,8902,0,65536,0,5248,0,65536,0,2066,0,65536,0,10082,0,65536,0,1017,0,65537,0,18194,0,65536,0,5760,0,65536,0,21412,0,65541,0,15593,0,65536,0,41083,0,524288,524288,0,30575203,0,0,0,29841366,0,0,0,30490331,0,0,0,35164476,0,0,0,31986886,0,0,0,35525305,0,0,0,34506416,0,0,0,33567601,0,0,0,29114151,0,0,0,28100002,0,0,0,33737648,0,0,0,31368243,0,0,0,31984966,0,0,0,31891072,0,0,0,33275205,0,0,0,27971128,0,0,0,50509102,0,0,0,32107338,0,0,0,33494516,0,0,0,33826601,0,0,0,37758137,0,0,0,33480656,0,0,0,44452926,0,0,0,32088174,0,0,0,29703856,0,0,0,31837287,0,0,0,32229510,0,0,0,29259919,0,0,0,25740323,0,0,0,27482841,0,0,0,33229239,0,0,0,32019754,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,524288,0,65584,65584,65584,0,65536,65536,65536,188,65540,65728,65728,0,65656,65656,65656,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,67775,67775,67775,0,65536,65536,65536,0,65536,65536,65536,0,65537,65537,65537,0,65536,65536,65536,0,65537,65537,65537,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65537,65537,65537,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,47,65537,65584,65584,0,65536,65536,65536,0,65536,65536,65536,0,65585,65585,65585,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,188,65540,65728,65728,0,68065,68065,68065,65536,0,0,65536,0,0,65728,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65728,0,0,65536,0,0,0,0,65536,65536,4128768,146371252,53165279,88946133,198258,0,0,0,524288,22087696,22081885,524288,524288,16384,65536,754,215618,4305,0,48,2480,0,2097536,4259840,1704592,1535334,22763379,3014656,0,0,3473408,8388608,8388608,8388608,0,0,0,0,0,188295,214792,12114,2265,0,208811,2099229,0,423,2098806,131072,0,131072,524288,0,524288,65536,65536,0,0,360,2097152,0,2097152,44649,0,2812,212171,0,2099944,0,0,31,222298112,917504,0,0,0,65536,65536,0,7603,2019845,0,2097152,2097152,0,731049,733486,0,21225,0,0,0,0,0,0,0,4194304,0,0,0,0,1104351900,1925966895,0,2097152,0,0,0,0,189853,0,0,0,0,0,131072,384,48,0,0,0,432,0,0,0,0,0,4691,0,0,0,2098999,0,3676,0,917504,914537,48,7607,184555,0,0,0,0,0,0,0,0,0,327680,0,0,371043,424454,65536,64048,48,1440,0,65536,0,0,0,0,0,0,0,65536,0,0,0,1966091,0,2097152,0,0,17973668,0,524288,2099110,0,1336424342,0,12076302019894165,12076328282317774,12076328282452973,12076302021141603
diff --git a/projects/rocprofiler-compute/tests/workloads/dev0/mi100/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/dev0/mi100/prev_analysis/1.csv
index 8d357b71a6..a9866004e2 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev0/mi100/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev0/mi100/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,6055312.0,6055312.0,6055312.0,9.17581889130573
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4527004.0,4527004.0,4527004.0,6.859922135179261
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 256u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,3055336.0,3055336.0,3055336.0,4.629853884999894
diff --git a/projects/rocprofiler-compute/tests/workloads/dev0/mi100/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/dev0/mi100/prev_analysis/1001.csv
index ca08330db0..0e3bf5267e 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev0/mi100/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev0/mi100/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,46.862275449101794,Instr per wave
 SMEM,1.8083832335329342,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/dev0/mi100/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/dev0/mi100/prev_analysis/101.csv
index 8b1497e1b2..74353c755c 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev0/mi100/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev0/mi100/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx908
 mi100
 48
 1228.8
-SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/dev0/mi100/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/dev0/mi100/prev_analysis/1202.csv
index 069576cfdd..d68bce0b6a 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev0/mi100/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev0/mi100/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,33761.37244470105,2805.687400817871,547941.7736816406,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/dev0/mi100/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/dev0/mi100/prev_analysis/1901.csv
index f3915a812b..6fc025d8a5 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev0/mi100/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev0/mi100/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,2.0,smem_
 VALU,735.0,valu_
 MFMA,,mfma_
 VMEM,8.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,22.0,br_
 VGPR,24.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,67894.0,wavefronts_
 Workgroups,16973.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,163.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,0.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,44.0,hbm_rd_
 HBM Wr,0.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,70.0,vl1_coales_
 VL1 Stall,30.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,34.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/dev0/mi100/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/dev0/mi100/prev_analysis/2001.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev0/mi100/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev0/mi100/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/dev0/mi100/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/dev0/mi100/prev_analysis/201.csv
index a0a5a2b2c0..a9528fc553 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev0/mi100/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev0/mi100/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,59.49293302260621,Pct,100,59.49293302260621
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,63.96757475781579,Threads,64,99.94933555908717
 IPC - Issue,0.8437242643821745,Instr/cycle,5,16.874485287643488
-LDS BW,0.0,Gb/sec,23070.72,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,23070.72,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99340470515173,Pct,100,99.99340470515173
 Instr Cache BW,1409.2232915418736,Gb/s,4614.144,30.54138083991036
 Scalar L1D Cache Hit Rate,99.35620448528866,Pct,100,99.35620448528866
diff --git a/projects/rocprofiler-compute/tests/workloads/dev0/mi100/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/dev0/mi100/prev_analysis/602.csv
index 8b7bed7603..8395eb271e 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev0/mi100/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev0/mi100/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,57830.431137724554,0,731049,Simd
 Insufficient SIMD VGPRs,568474.6706586826,0,41500307,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/dev0/mi100/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/dev0/mi100/prev_analysis/701.csv
index d3f1bff5a3..1071413faa 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev0/mi100/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev0/mi100/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,23.976047904191617,8,36,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/dev0/mi100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/dev0/mi100/sysinfo.csv
index 9abd8d3f35..889fae8e7b 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev0/mi100/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev0/mi100/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-dev0,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 11:31:14 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+dev0,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 11:31:14 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/dev0/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/dev0/mi100/timestamps.csv
index 75354a09ff..c0dc6af174 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev0/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev0/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,921580,921585,33554432,256,0,0,8,32,6464,0x0,0x7fc0c2804180,12076328266793044,12076328266837802,12076328267160519,12076328267269900
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,921580,921585,32768,256,0,0,24,24,12480,0x0,0x7fc0c2835100,12076328282132912,12076328282246095,12076328282252495,12076328282258235
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,921580,921585,4194304,256,0,0,24,24,12928,0x7fc1ce3b2900,0x7fc0c2835140,12076328282304692,12076328282317774,12076328282452973,12076328282456624
diff --git a/projects/rocprofiler-compute/tests/workloads/dev0/mi200/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/dev0/mi200/SQ_IFETCH_LEVEL.csv
index 56c96f21c9..bef3a5276c 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev0/mi200/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev0/mi200/SQ_IFETCH_LEVEL.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,223297,223297,33554432,256,0,0,4,32,4160,0x0,0x7fc57a604280,379284,379284,524288,4718592,681163,76310828,17598097140845,17597387743185,17598246526395,17598246639545
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,223297,223297,32768,256,0,0,12,24,13888,0x0,0x7fc57a623f80,33251,33251,512,8192,6010,679448,17598251787224,17598246526395,17598251919198,17598251924230
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,223297,223297,4194304,256,0,0,12,24,14336,0x7fc57d663380,0x7fc57a623fc0,163594,163594,65536,917504,141997,15950860,17598251961259,17598251919198,17598252301279,17598252303751
diff --git a/projects/rocprofiler-compute/tests/workloads/dev0/mi200/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/dev0/mi200/SQ_INST_LEVEL_LDS.csv
index 5fe25a79dc..5b9052110b 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev0/mi200/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev0/mi200/SQ_INST_LEVEL_LDS.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,225145,225145,33554432,256,0,0,4,32,4160,0x0,0x7f6011204280,0,0,0,17617373642292,17616657358066,17617521510730,17617521624110
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,225145,225145,32768,256,0,0,12,24,13888,0x0,0x7f6011223f80,0,0,0,17617526822058,17617521510730,17617526949772,17617526954185
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,225145,225145,4194304,256,0,0,12,24,14336,0x7f601422d380,0x7f6011223fc0,0,0,0,17617526989654,17617526949772,17617527316172,17617527318486
diff --git a/projects/rocprofiler-compute/tests/workloads/dev0/mi200/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/dev0/mi200/SQ_INST_LEVEL_SMEM.csv
index 833430f997..09a3813b19 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev0/mi200/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev0/mi200/SQ_INST_LEVEL_SMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,223075,223075,33554432,256,0,0,4,32,4160,0x0,0x7f931ec04280,3670016,2924224,327281248,17597154367976,17588719430319,17597306738811,17597306856651
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,223075,223075,32768,256,0,0,12,24,13888,0x0,0x7f931ec23f80,512,96990,10865032,17597311964571,17597306738811,17597312097854,17597312102767
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,223075,223075,4194304,256,0,0,12,24,14336,0x7f9321c13380,0x7f931ec23fc0,65536,635542,71138720,17597312138116,17597312097854,17597312468574,17597312471268
diff --git a/projects/rocprofiler-compute/tests/workloads/dev0/mi200/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/dev0/mi200/SQ_INST_LEVEL_VMEM.csv
index ebf510ba36..54d20d3a84 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev0/mi200/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev0/mi200/SQ_INST_LEVEL_VMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,224923,224923,33554432,256,0,0,4,32,4160,0x0,0x7f6676804280,524288,5433099,608528124,17616429017287,17614162329648,17616578244180,17616578354430
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,224923,224923,32768,256,0,0,12,24,13888,0x0,0x7f6676823f80,4096,42285,4736872,17616583510399,17616578244180,17616583637143,17616583641776
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,224923,224923,4194304,256,0,0,12,24,14336,0x7f66798a9380,0x7f6676823fc0,524288,10680424,1196193368,17616583675735,17616583637143,17616584007223,17616584009546
diff --git a/projects/rocprofiler-compute/tests/workloads/dev0/mi200/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/dev0/mi200/SQ_LEVEL_WAVES.csv
index 80cfe08593..4056687612 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev0/mi200/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev0/mi200/SQ_LEVEL_WAVES.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,223519,223519,33554432,256,0,0,4,32,4160,0x0,0x7f1ce5804280,387094,387094,8680,3096760,524288,245771477,3011216,0,999328548,17599035568236,17598328816642,17599185813205,17599185923274
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,223519,223519,32768,256,0,0,12,24,13888,0x0,0x7f1ce5823f80,33003,33003,29549,264032,512,1739044,167125,0,6969744,17599191082624,17599185813205,17599191227446,17599191232450
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,223519,223519,4194304,256,0,0,12,24,14336,0x7f1ce8890380,0x7f1ce5823fc0,164050,164050,13444,1312408,65536,80869811,1211279,0,325210296,17599191275709,17599191227446,17599191628886,17599191631540
diff --git a/projects/rocprofiler-compute/tests/workloads/dev0/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/dev0/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev0/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev0/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/dev0/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/dev0/mi200/pmc_perf.csv
index a762e981f8..d5a5df6b16 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev0/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev0/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDI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],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBufferAligned.kd,0,0,0,224285,224285,33554432,256,0,0,4,32,4160,0x0,0x7fec46c04280,3094336,3007243,524288,39071475,245948025,392,224,0,386791,386791,39336445.0,38412045.0,1.0,4271139.0,31599588.0,31245663.0,38391465.0,37832571.0,3092625,3013651,386791,0,386791,0,12377312.0,9517046.0,0.0,0.0,0,0,616,0,4718592,4714998,112,3482,377494,0.0,0.0,0.0,524288.0,28934829.0,28267128.0,7801.0,524288.0,131072,524288,302,386637,2303,0,56.0,302.0,0.0,4194696.0,0,0,0,0,0,7340032,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,20604239.0,524288.0,0,385932,0,0,0,385932,0,0,0,385932,0,0,0,385932,0,0,0,385932,0,0,0,385932,0,0,0,385932,0,0,0,385932,0,0,0,385932,0,0,0,385932,0,0,0,385932,0,0,0,385932,0,0,0,385932,0,0,0,385932,0,0,0,385932,0,0,0,385932,0,0,0,385932,0,0,0,385932,0,0,0,385932,0,0,0,385932,0,0,0,385932,0,0,0,385932,0,0,0,385932,0,0,0,385932,0,0,0,385932,0,0,0,385932,0,0,0,385932,0,0,0,385932,0,0,0,385932,0,0,0,385932,0,0,0,385932,0,0,0,385932,0,0,0,0,0,0.0,21893186.0,32,0,0,0,0,0,0,0,112,0,0,0,2,0,0,0,2,0,0,0,2,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,33,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,34,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,61,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,524288.0,0.0,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,43380,129024,129024,0,326,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,217636,129024,129024,0,44951,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,165,129024,129024,0,758,129024,129024,0,0,129024,129024,0,0,129024,129024,0,31590,129024,129024,0,869,129024,129024,0,0,129024,129024,0,0,129024,129024,0,172943,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,45013,129024,129024,0,182,129024,129024,524288.0,0.0,44974,0,0,50451205,45213,0,0,50396432,44644,0,0,50008247,46845,0,0,51698206,45302,0,0,51310310,45876,0,0,51123193,44956,0,0,50663996,48692,0,0,53131898,44531,0,0,50562133,46353,0,0,50805001,45172,0,0,50169151,48852,0,0,52528245,46388,0,0,51407825,46848,0,0,51535539,45526,0,0,50897083,48630,0,0,52721520,44794,0,0,50268736,46076,0,0,50557876,42874,0,0,49626372,47116,0,0,51849621,44196,0,0,50814306,45630,0,0,51196600,44799,0,0,50661573,48630,0,0,52773255,44825,0,0,50522691,44676,0,0,50231427,46527,0,0,50542907,47525,0,0,52025141,46628,0,0,51522503,47002,0,0,51433888,45304,0,0,50857284,48655,0,0,52905230,0.0,65536,65537,1,131073,65536,65536,0,131072,65536,65571,35,131107,65536,65536,0,131072,65646,65538,112,131184,65536,65536,0,131072,65591,65537,56,131128,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65568,32,131104,65536,65536,0,131072,65536,65648,112,131184,65536,65536,0,131072,65536,65592,56,131128,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65537,1,131073,65536,65568,32,131104,65536,65536,0,131072,65758,65538,224,131296,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65537,1,131073,65536,65536,0,131072,65536,65568,32,131104,65536,65536,0,131072,65591,65537,56,131128,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131184,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131296,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131128,0,131072,898497,0,524288,3670016,3663263,224,6529,1048576,33554432.0,33554432.0,0.0,33554432.0,30723077.0,29139846.0,0.0,524288.0,224304,538500,8946,896,0,386011,4195054.0,0.0,2097594.0,2097460.0,1048576,1048576,0,524288,0,524288,7340032,0,0.0,0.0,104.0,8388608.0,29949473.0,2097152.0,0.0,208669,0,1214,384836,0,748.0,4194304.0,0.0,2064387.0,25690112,9437184,0,0,0,0,0,0,13312.0,8242176.0,0.0,8388608.0,2097152.0,4194304.0,9735046,0,0,8813,4128768.0,4128768.0,0.0,1495975.0,0,0,0,0,0,0,5767168,1048576,317863449.0,0.0,1479577147.0,0.0,24.0,0.0,0,0,372437,0.0,0.0,1518668.0,0.0,3670016,524288,0,0,0,2621440,524288,178317784,4194304.0,0.0,0.0,0.0,0.0,1159183.0,0,0,0.0,311.0,0.0,606.0,42765489,24117248,0,0,9437184,11010048,0,3145728,0.0,0.0,0.0,0.0,0.0,0.0,0,1572864,0.0,0.0,0.0,203576.0,524288,524288,0,3670016,7340032,603979776,4718592,0,0.0,0.0,0.0,0.0,0.0,0.0,524288,0,2064384.0,0.0,2031623.0,0.0,0,0,524288,0,0,0,0,33554432,0.0,4194304.0,0.0,18968389.0,0.0,0.0,144.0,4128768.0,629239.0,1687939030.0,17600468349438,17618191108316,17618191348476,17600612098596
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,224285,224285,32768,256,0,0,12,24,13888,0x0,0x7fec46c23f80,262480,167842,512,1406262,1678908,504,56,0,32809,32809,2412930.0,183929.0,165.0,0.0,36563.0,32808.0,177616.0,158848.0,262472,174696,32809,0,32809,0,1049888.0,381113.0,0.0,0.0,0,0,560,0,8192,6107,56,2029,23912,0.0,0.0,0.0,4096.0,29040.0,27455.0,0.0,4096.0,128,512,302,33261,2319,0,0.0,59.0,0.0,4600.0,0,0,0,0,0,1024,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,19281.0,4096.0,0,25920,0,0,0,25920,0,0,0,25920,0,0,0,25920,0,0,0,25920,0,0,0,25920,0,0,0,25920,0,0,0,25920,0,0,0,25920,0,0,0,25920,0,0,0,25920,0,0,0,25920,0,0,0,25920,0,0,0,25920,0,0,0,25920,0,0,0,25920,0,0,0,25920,0,0,0,25920,0,0,0,25920,0,0,0,25920,0,0,0,25920,0,0,0,25920,0,0,0,25920,0,0,0,25920,0,0,0,25920,0,0,0,25920,0,0,0,25920,0,0,0,25920,0,0,0,25920,0,0,0,25920,0,0,0,25920,0,0,0,25920,0,0,0,0,0,0.0,0.0,256,0,0,0,256,0,0,0,312,0,0,0,257,0,0,0,256,0,0,0,261,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,4096.0,4096.0,0,92430,0,0,0,90772,0,0,0,111228,0,0,0,96290,0,0,0,85341,0,0,0,93904,0,0,0,91808,0,0,0,97621,0,0,0,82562,0,0,0,92761,0,0,0,84246,0,0,0,421705,0,0,0,170111,0,0,0,99759,0,0,0,88362,0,0,0,96056,0,0,0,92301,0,0,0,92158,0,0,0,93850,0,0,0,148153,0,0,0,205930,0,0,0,117222,0,0,0,83555,0,0,0,94711,0,0,0,83628,0,0,0,94011,0,0,0,90119,0,0,0,94605,0,0,0,162154,0,0,0,87868,0,0,0,108520,0,0,0,92571,0,0,0.0,0.0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4096.0,0,129,129,129,0,128,128,128,0,130,130,130,0,128,128,128,0,128,128,128,222,130,352,352,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,184,184,184,222,130,352,352,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,129,129,129,0,128,128,128,0,128,128,128,0,128,128,128,55,129,184,184,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,352,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,352,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,184,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,684,0,0,512,0,56,456,0,65536.0,65536.0,65536.0,0.0,0.0,0.0,0.0,0.0,4,516,10569,1020,0,23399,4659.0,0.0,499.0,4160.0,512,0,0,0,4096,4096,512,0,0.0,0.0,104.0,16384.0,0.0,16384.0,4096.0,0,0,1343,25079,0,4659.0,0.0,0.0,31.0,35328,26112,0,0,0,0,0,0,104.0,15240.0,0.0,16384.0,16384.0,0.0,0,0,0,21959,0.0,0.0,0.0,0.0,0,0,0,0,0,0,10752,3584,5300056.0,6761580.0,0.0,8192.0,0.0,0.0,0,0,498,0.0,0.0,0.0,0.0,512,4096,0,0,0,512,512,1203146,0.0,0.0,0.0,0.0,0.0,1384.0,0,0,0.0,8263.0,0.0,124.0,14844,32256,0,0,26112,1024,0,1024,0.0,0.0,0.0,0.0,0.0,0.0,0,1024,0.0,0.0,0.0,54034.0,4096,0,4096,512,512,1671168,8192,0,0.0,0.0,0.0,0.0,0.0,0.0,512,0,0.0,0.0,0.0,0.0,0,0,512,0,0,0,0,32768,8192.0,0.0,0.0,217897.0,0.0,4096.0,8206.0,0.0,3539343.0,0.0,17600618353627,17618196121120,17618196134240,17600618831315
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,224285,224285,4194304,256,0,0,12,24,14336,0x7fec49bf6380,0x7fec46c23fc0,1315960,1214589,65536,15710797,85911475,392,56,0,164494,164494,16020810.0,14579469.0,22551.0,1216916.0,13874913.0,13678795.0,14573188.0,12441949.0,1315952,1221094,164494,0,164494,0,5263808.0,4747608.0,0.0,0.0,0,0,448,0,917504,913705,0,3799,153048,0.0,0.0,0.0,524288.0,12991687.0,12961876.0,2204.0,524288.0,16384,65536,302,163852,2306,0,0.0,188.0,0.0,1048968.0,0,0,0,0,0,131072,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,12674630.0,524288.0,0,165039,0,0,0,165039,0,0,0,165039,0,0,0,165039,0,0,0,165039,0,0,0,165039,0,0,0,165039,0,0,0,165039,0,0,0,165039,0,0,0,165039,0,0,0,165039,0,0,0,165039,0,0,0,165039,0,0,0,165039,0,0,0,165039,0,0,0,165039,0,0,0,165039,0,0,0,165039,0,0,0,165039,0,0,0,165039,0,0,0,165039,0,0,0,165039,0,0,0,165039,0,0,0,165039,0,0,0,165039,0,0,0,165039,0,0,0,165039,0,0,0,165039,0,0,0,165039,0,0,0,165039,0,0,0,165039,0,0,0,165039,0,0,0,0,0,0.0,0.0,65536,0,1735,0,65536,0,4044,0,65592,0,2703,0,65537,0,19892,0,65536,0,7133,0,65537,0,2285,0,65536,0,16958,0,65536,0,30945,0,65536,0,1595,0,65538,0,8840,0,65536,0,3610,0,65536,0,1333,0,65537,0,3837,0,65536,0,2419,0,65536,0,4716,0,65536,0,48203,0,65536,0,35035,0,65536,0,20462,0,65596,0,8797,0,65536,0,6165,0,65537,0,5194,0,65536,0,1701,0,65537,0,5050,0,65539,0,2627,0,65540,0,2023,0,65536,0,6415,0,65536,0,7386,0,65600,0,4739,0,65536,0,1453,0,65536,0,27631,0,65536,0,2865,0,65536,0,46683,0,524288.0,524288.0,0,51221496,0,0,0,44783053,0,0,0,38590749,0,0,0,45910336,0,0,0,45810756,0,0,0,40393568,0,0,0,48709919,0,0,0,51681192,0,0,0,45270803,0,0,0,45428147,0,0,0,43704957,0,0,0,46153292,0,0,0,46536195,0,0,0,40193325,0,0,0,44943729,0,0,0,52950536,0,0,0,52635031,0,0,0,47753728,0,0,0,51115585,0,0,0,52027687,0,0,0,52275561,0,0,0,46011046,0,0,0,46292290,0,0,0,43540750,0,0,0,36942231,0,0,0,45832814,0,0,0,37333928,0,0,0,45325537,0,0,0,46327796,0,0,0,41911048,0,0,0,46551000,0,0,0,50079567,0,0,0.0,0.0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,524288.0,0,32769,32769,32769,0,32768,32768,32768,0,32824,32824,32824,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32821,32821,32821,0,32768,32768,32768,0,32824,32824,32824,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32769,32769,32769,0,32768,32768,32768,0,32769,32769,32769,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,166,32770,32936,32936,222,32770,32992,32992,0,32768,32768,32768,0,32768,32768,32768,0,32770,32770,32770,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32936,0,0,32992,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,536029,0,0,65536,63800,56,1680,0,8388608.0,8388608.0,8388608.0,0.0,0.0,0.0,0.0,0.0,171129,181303,10418,2985,0,161298,1049147.0,0.0,388.0,1048759.0,65536,0,0,0,524288,524288,131072,0,0.0,0.0,104.0,2097152.0,0.0,2097152.0,524288.0,67663,0,3636,164949,0,1049133.0,0.0,0.0,31.0,4063232,2883584,0,0,0,0,0,0,6657.0,2027744.0,0.0,2097152.0,2097152.0,0.0,1306344,0,0,14780,0.0,0.0,0.0,0.0,262144,0,0,0,0,0,1507328,458752,930193751.0,2351200536.0,0.0,2097152.0,2.0,0.0,0,0,151120,0.0,0.0,0.0,0.0,65536,524288,0,0,0,65536,65536,46698773,0.0,0.0,0.0,0.0,0.0,4861.0,0,0,0.0,2097344.0,0.0,370.0,44655197,3735552,0,0,2883584,196608,0,131072,0.0,0.0,0.0,0.0,0.0,0.0,0,131072,0.0,0.0,250986.0,766268.0,524288,0,524288,65536,131072,184549376,917504,0,0.0,0.0,0.0,0.0,0.0,0.0,65536,0,0.0,0.0,983047.0,0.0,0,0,65536,0,0,0,0,4194304,2097152.0,0.0,0.0,12761556.0,0.0,524288.0,2097290.0,0.0,1349168126.0,0.0,17600619927057,17618196205120,17618196297920,17600620710537
diff --git a/projects/rocprofiler-compute/tests/workloads/dev0/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/dev0/mi200/prev_analysis/1.csv
index f7f47909ff..a709a69cfb 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev0/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev0/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,3359203.0,3359203.0,3359203.0,7.843408332395092
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,1724962.0,1724962.0,1724962.0,4.027616468509019
 "void benchmark_func<double, 256, 8u, 512u>(double, double*) [clone .kd]",1,1716642.0,1716642.0,1716642.0,4.008190087511643
diff --git a/projects/rocprofiler-compute/tests/workloads/dev0/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/dev0/mi200/prev_analysis/1001.csv
index f475f954a6..fb5988001a 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev0/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev0/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,494.8622754491018,Instr per wave
 VMEM,7.958083832335329,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,0.0,Instr per wave
 SALU,24.520958083832337,Instr per wave
 SMEM,1.8023952095808384,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/dev0/mi200/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/dev0/mi200/prev_analysis/101.csv
index e1d914df70..7886449822 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev0/mi200/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev0/mi200/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx90a
 mi200
 56
 1638.4
-roofline|SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+roofline|SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/dev0/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/dev0/mi200/prev_analysis/1202.csv
index 9e9dd333e4..3015985c80 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev0/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev0/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,18379.615702235056,1876.4345169067383,258464.3599243164,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/dev0/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/dev0/mi200/prev_analysis/1901.csv
index f534cf52d5..4dbb52f25c 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev0/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev0/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,2.0,smem_
 VALU,495.0,valu_
 MFMA,0.0,mfma_
 VMEM,8.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,10.0,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,67894.0,wavefronts_
 Workgroups,16973.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,128.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,0.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,44.0,hbm_rd_
 HBM Wr,0.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,70.0,vl1_coales_
 VL1 Stall,2.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,26.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/dev0/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/dev0/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev0/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev0/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/dev0/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/dev0/mi200/prev_analysis/201.csv
index 0afafa1a1c..41a0b749c0 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev0/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev0/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,58.32499961405379,Pct,100,58.32499961405379
 MFMA Util,0.0,Pct,100,0.0
 VALU Active Threads/Wave,64.0,Threads,64,100.0
 IPC - Issue,1.0,Instr/cycle,5,20.0
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99250938551732,Pct,100,99.99250938551732
 Instr Cache BW,1673.2474012593727,Gb/s,6092.8,27.46270025701439
 Scalar L1D Cache Hit Rate,99.34855886013408,Pct,100,99.34855886013408
diff --git a/projects/rocprofiler-compute/tests/workloads/dev0/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/dev0/mi200/prev_analysis/602.csv
index b88a8b3ca2..ab213c62a6 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev0/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev0/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,16255612.035928143,0,427277590,Simd
 Insufficient SIMD VGPRs,0.0,0,0,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/dev0/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/dev0/mi200/prev_analysis/701.csv
index 12250d77c0..db0925a109 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev0/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev0/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/dev0/mi200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/dev0/mi200/sysinfo.csv
index 6989f7fddd..e57e6a789f 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev0/mi200/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev0/mi200/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-dev0,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:46:37 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,roofline|SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+dev0,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:46:37 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,roofline|SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/dev0/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/dev0/mi200/timestamps.csv
index 7168561a7d..ae8d5d594b 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev0/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev0/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,225228,225228,33554432,256,0,0,4,32,4160,0x0,0x7f9f58604280,17618191082395,17618191108316,17618191348476,17618191437046
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,225228,225228,32768,256,0,0,12,24,13888,0x0,0x7f9f58623f80,17618196106138,17618196121120,17618196134240,17618196153037
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,225228,225228,4194304,256,0,0,12,24,14336,0x7f9f770e3380,0x7f9f58623fc0,17618196155947,17618196205120,17618196297920,17618196300333
diff --git a/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/SQ_IFETCH_LEVEL.csv
index 5899228d27..bd3a4aacf1 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/SQ_IFETCH_LEVEL.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,930064,930069,33554432,256,0,0,8,32,6464,0x0,0x7fc924204180,501625,501625,524288,6291456,791363,101379224,12076511629552996,12076511873640060,12076511873962459,12076511874072021
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,930064,930069,32768,256,0,0,24,24,12480,0x0,0x7fc924235100,28353,28353,512,8192,8985,1155340,12076511888619511,12076511888937326,12076511888943886,12076511888951659
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,930064,930069,4194304,256,0,0,24,24,12928,0x7fca2f751900,0x7fc924235140,214915,214915,65536,917504,139932,17898568,12076511889024354,12076511889248365,12076511889378924,12076511889383012
diff --git a/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/SQ_INST_LEVEL_LDS.csv
index 96468c8b15..4d86eedc75 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/SQ_INST_LEVEL_LDS.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,931859,931864,33554432,256,0,0,8,32,6464,0x0,0x7fa2f4604180,0,0,0,12076538010346649,12076538250264836,12076538250588515,12076538250679036
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,931859,931864,32768,256,0,0,24,24,12480,0x0,0x7fa2f4635100,0,0,0,12076538265124998,12076538265420263,12076538265426823,12076538265432269
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,931859,931864,4194304,256,0,0,24,24,12928,0x7fa40034b900,0x7fa2f4635140,0,0,0,12076538265550439,12076538265717702,12076538265859462,12076538265863321
diff --git a/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/SQ_INST_LEVEL_SMEM.csv
index ea19737cfb..9aee3e1b0b 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/SQ_INST_LEVEL_SMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,931481,931486,33554432,256,0,0,8,32,6464,0x0,0x7f07d2e04180,4194304,3256368,416675080,12076535482203595,12076535726603916,12076535726928235,12076535727038578
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,931481,931486,32768,256,0,0,24,24,12480,0x0,0x7f07d2e35100,512,23210,2955744,12076535741499958,12076535741800904,12076535741806984,12076535741811928
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,931481,931486,4194304,256,0,0,24,24,12928,0x7f0902d9c900,0x7f07d2e35140,65536,175692,22419328,12076535741871739,12076535742100583,12076535742237702,12076535742241807
diff --git a/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/SQ_INST_LEVEL_VMEM.csv
index 5ec3315f7c..58b61eec5a 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/SQ_INST_LEVEL_VMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,931671,931676,33554432,256,0,0,8,32,6464,0x0,0x7f8101a04180,1048576,10991950,1406583256,12076536745644699,12076536990667420,12076536990991419,12076536991092712
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,931671,931676,32768,256,0,0,24,24,12480,0x0,0x7f8101a35100,4096,109855,14068084,12076537005633911,12076537005965694,12076537005972254,12076537005977540
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,931671,931676,4194304,256,0,0,24,24,12928,0x7f820d595900,0x7f8101a35140,524288,10827501,1385924644,12076537006052800,12076537006288733,12076537006426653,12076537006431615
diff --git a/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/SQ_LEVEL_WAVES.csv
index a81f5c4e72..b4f80da426 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/SQ_LEVEL_WAVES.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,932047,932054,33554432,256,0,0,8,32,6464,0x0,0x7f4318204180,502027,502027,17663,4016224,524288,373010853,3812072,0,1506849280,12076539256161927,12076539500209550,12076539500532269,12076539500642792
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,932047,932054,32768,256,0,0,24,24,12480,0x0,0x7f4318235100,28337,28337,21039,226704,512,1125690,76367,0,4517036,12076539515082191,12076539515408737,12076539515415137,12076539515423846
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,932047,932054,4194304,256,0,0,24,24,12928,0x7f4423eba900,0x7f4318235140,214085,214085,21876,1712688,65536,145056154,1546601,0,582037424,12076539515493015,12076539515729376,12076539515859296,12076539515863073
diff --git a/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/pmc_dispatch_info.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/pmc_perf.csv
index 06a5a8adf1..db431c8442 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBuffer.kd,0,0,0,930798,930803,33554432,256,0,0,8,32,6464,0x0,0x7fdd31804180,1048576,0,1048576,9437184,0,4194304,1048576,0,501560,501560,57505185,55166260,216,13492502,54505447,54423975,55132861,53952944,4012480,3818136,501560,0,501560,0,16049920,15187061,0,0,0,0,0,17448924,1048576,0,501145,0,0,0,501145,0,0,0,501145,0,0,0,501145,0,0,0,501145,0,0,0,501145,0,0,0,501145,0,0,0,501145,0,0,0,501145,0,0,0,501145,0,0,0,501145,0,0,0,501145,0,0,0,501145,0,0,0,501145,0,0,0,501145,0,0,0,501145,0,0,0,501145,0,0,0,501145,0,0,0,501145,0,0,0,501145,0,0,0,501145,0,0,0,501145,0,0,0,501145,0,0,0,501145,0,0,0,501145,0,0,0,501145,0,0,0,501145,0,0,0,501145,0,0,0,501145,0,0,0,501145,0,0,0,501145,0,0,0,501145,0,0,0,37411789,0,0,0,0,53,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,155,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,2641,0,0,0,0,0,0,0,0,0,0,0,2,0,0,0,0,0,0,0,1,0,0,0,2380,0,0,0,0,0,0,0,0,0,0,0,48,0,0,0,0,0,0,0,0,0,0,0,2689,0,0,0,0,0,0,0,48,0,0,0,0,0,0,0,2760,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1048576,0,0,3663215,131076,131076,0,2209,131072,131072,0,0,131072,131072,0,0,131080,131080,0,3112826,131072,131072,0,0,131072,131072,0,0,131072,131072,0,21191,131080,131080,0,0,131080,131080,0,0,131072,131072,0,259,131076,131076,0,0,131072,131072,0,0,131072,131072,0,1529,131072,131072,0,871,131072,131072,0,0,131080,131080,0,0,131076,131076,0,781,131076,131076,0,0,131072,131072,0,0,131072,131072,0,2926558,131072,131072,0,0,131076,131076,0,19934,131076,131076,0,0,131076,131076,0,3275375,131072,131072,0,1602,131072,131072,0,0,131072,131072,0,0,131076,131076,0,29690,131084,131084,0,0,131076,131076,0,271,131076,131076,0,0,131076,131076,1048576,0,1631,0,0,17713563,1603,0,0,17621806,1764,0,0,17535225,43137,0,0,29279901,1548,0,0,17750421,1090,0,0,17531680,885,0,0,18247807,50247,0,0,31658681,736,0,0,17506706,892,0,0,17502795,1644,0,0,17278484,1832,0,0,16895622,1604,0,0,17496132,1167,0,0,17544067,1149,0,0,18185671,1671,0,0,18595091,1565,0,0,17058621,835,0,0,16948883,1675,0,0,17318167,992,0,0,16965082,1938,0,0,17522817,908,0,0,17404732,1622,0,0,18354730,1130,0,0,18629201,951,0,0,16972003,792,0,0,16927380,821,0,0,17014136,46518,0,0,29372498,1581,0,0,17552998,1684,0,0,17660114,1678,0,0,18363067,47524,0,0,31579182,1048576,131072,131131,59,262203,131260,131124,240,262384,131072,131072,0,262144,131072,131072,0,262144,131072,133637,2565,264709,131072,131120,48,262192,131072,131072,0,262144,131072,131072,0,262144,131072,133439,2367,264511,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131073,1,262145,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131213,131075,144,262288,131119,131073,48,262192,131072,131072,0,262144,131072,133783,2711,264855,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,133676,2604,264748,131119,131073,48,262192,131072,131072,0,262144,131072,131120,48,262192,131072,131073,1,262145,131072,131072,0,262144,131072,131076,4,262148,131072,131072,0,262144,262144,0,262144,262336,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262288,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,0,0,3145728,524288,32505856,371852390,219120228,120226306,476595,0,0,0,1048576,52374256,52165967,1048576,1048576,131072,524288,755,498886,4309,0,96,10426,0,8388944,32505856,4008656,3803338,56910882,11534336,0,0,14155776,67108864,67108864,0,67108864,54081194,53714975,0,1048576,234540,758828,11689,2090,0,496685,8399656,0,4194727,4204929,13631488,0,3670016,1048576,1048576,0,4194304,9437184,0,0,360,33554432,54263814,4194304,0,0,2453,501954,0,11213,8388608,0,4194385,905969664,6291456,0,0,0,524288,524288,0,15328,16608726,0,16777216,4194304,4194304,0,0,0,17277,4194378,4194378,0,221353,0,0,0,33554432,0,0,0,0,632168181,0,2781089738,0,0,0,0,0,475396,0,0,217731,0,0,8388608,336,144,0,0,0,480,8388608,0,0,0,0,270068,0,0,0,10671,0,21324,0,6291456,6289512,96,2156,1974774,0,0,0,0,0,0,0,0,0,3145728,0,0,0,154149,4194304,4189869,144,4291,2097152,524288,1572864,0,0,0,0,0,0,524288,0,4128820,65533,4063246,0,0,8388608,0,42215095,0,1048576,10480,4194335,12831548,604704111,12076513753284796,12076540386221406,12076540386544923,12076513997177647
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,930798,930803,32768,256,0,0,24,24,12480,0x0,0x7fdd31835100,0,4096,4096,512,0,512,4096,0,29252,29252,1531667,606161,217,117895,88284,72761,598080,577617,234016,87929,29252,0,29252,0,936064,201035,0,0,0,0,0,57670,4096,0,27916,0,0,0,27916,0,0,0,27916,0,0,0,27916,0,0,0,27916,0,0,0,27916,0,0,0,27916,0,0,0,27916,0,0,0,27916,0,0,0,27916,0,0,0,27916,0,0,0,27916,0,0,0,27916,0,0,0,27916,0,0,0,27916,0,0,0,27916,0,0,0,27916,0,0,0,27916,0,0,0,27916,0,0,0,27916,0,0,0,27916,0,0,0,27916,0,0,0,27916,0,0,0,27916,0,0,0,27916,0,0,0,27916,0,0,0,27916,0,0,0,27916,0,0,0,27916,0,0,0,27916,0,0,0,27916,0,0,0,27916,0,0,0,0,256,0,0,0,305,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,377,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,304,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,4096,4096,0,95105,0,0,0,196255,0,0,0,86550,0,0,0,95521,0,0,0,83067,0,0,0,180186,0,0,0,83557,0,0,0,104241,0,0,0,76599,0,0,0,125694,0,0,0,85063,0,0,0,83185,0,0,0,83704,0,0,0,91063,0,0,0,65207,0,0,0,78051,0,0,0,192095,0,0,0,136491,0,0,0,65827,0,0,0,88394,0,0,0,251105,0,0,0,88407,0,0,0,130748,0,0,0,106091,0,0,0,106734,0,0,0,76838,0,0,0,92149,0,0,0,137243,0,0,0,174017,0,0,0,80585,0,0,0,117216,0,0,0,78904,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4096,0,378,378,378,0,304,304,304,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,257,257,257,0,256,256,256,188,260,448,448,0,256,256,256,0,256,256,256,0,256,256,256,188,260,448,448,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,47,257,304,304,0,256,256,256,0,304,304,304,0,257,257,257,0,256,256,256,47,257,304,304,0,256,256,256,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,304,0,0,256,0,0,0,0,512,512,35328,1130873,1077981,16540,11567,0,0,0,4096,66035,62960,4096,4096,128,512,638,27031,4247,0,48,219,0,8624,36352,220136,75154,1061988,26624,0,0,30208,65536,65536,65536,0,0,0,0,0,114,626,11844,1973,0,23127,8891,0,470,8421,1024,0,1024,4096,0,4096,512,512,0,0,360,16384,0,16384,0,0,2689,24916,0,8891,0,0,31,1933312,8192,0,0,0,512,512,0,120,15064,0,16384,16384,0,0,0,0,21098,0,0,0,0,0,0,0,32768,0,0,0,0,13156483,18186851,0,8192,0,0,0,0,694,0,0,0,0,0,1024,432,48,0,0,0,480,0,0,0,0,0,3092,0,0,0,8422,0,440,0,8192,6641,48,1503,1068,0,0,0,0,0,0,0,0,0,2560,0,0,0,47022,512,0,48,464,0,512,0,0,0,0,0,0,0,512,0,0,0,0,0,8192,0,0,451987,0,4096,8421,0,3278868,0,12076514012148084,12076540401193523,12076540401200243,12076514013142103
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,930798,930803,4194304,256,0,0,24,24,12928,0x7fde3d48c900,0x7fdd31835140,0,524288,524288,65536,0,65536,524288,0,219636,219636,24326717,22988977,30980,9538449,22102578,21975424,22971420,20802239,1757088,1605595,219636,0,219636,0,7028352,6293547,0,0,0,0,0,20003150,524288,0,219377,0,0,0,219377,0,0,0,219377,0,0,0,219377,0,0,0,219377,0,0,0,219377,0,0,0,219377,0,0,0,219377,0,0,0,219377,0,0,0,219377,0,0,0,219377,0,0,0,219377,0,0,0,219377,0,0,0,219377,0,0,0,219377,0,0,0,219377,0,0,0,219377,0,0,0,219377,0,0,0,219377,0,0,0,219377,0,0,0,219377,0,0,0,219377,0,0,0,219377,0,0,0,219377,0,0,0,219377,0,0,0,219377,0,0,0,219377,0,0,0,219377,0,0,0,219377,0,0,0,219377,0,0,0,219377,0,0,0,219377,0,0,0,0,65536,0,28852,0,65585,0,6399,0,65540,0,6394,0,65536,0,8022,0,65536,0,16291,0,65536,0,1901,0,65536,0,11468,0,65901,0,31454,0,65536,0,8926,0,65536,0,5716,0,65537,0,7497,0,67177,0,52747,0,65536,0,7972,0,65536,0,524,0,65536,0,10281,0,65536,0,15252,0,65537,0,6605,0,65536,0,27286,0,65536,0,325,0,65536,0,5857,0,65584,0,10904,0,65536,0,0,0,65536,0,8980,0,65536,0,7067,0,65536,0,7838,0,65536,0,7680,0,65536,0,31780,0,66498,0,54044,0,65536,0,1425,0,65536,0,3240,0,65540,0,32746,0,65536,0,20729,0,524288,524288,0,44061570,0,0,0,41333547,0,0,0,38672061,0,0,0,32605638,0,0,0,35518478,0,0,0,36187534,0,0,0,37868050,0,0,0,34666269,0,0,0,30549958,0,0,0,32792239,0,0,0,35144277,0,0,0,36805768,0,0,0,35045705,0,0,0,36048479,0,0,0,38670169,0,0,0,35252802,0,0,0,35312661,0,0,0,35623226,0,0,0,33319841,0,0,0,38684579,0,0,0,36668053,0,0,0,35358960,0,0,0,33617350,0,0,0,40183885,0,0,0,55075265,0,0,0,39480252,0,0,0,32012287,0,0,0,34721578,0,0,0,42284606,0,0,0,34217303,0,0,0,38817797,0,0,0,32199554,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,524288,0,65839,65839,65839,0,65584,65584,65584,188,65540,65728,65728,0,65536,65536,65536,0,67356,67356,67356,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65537,65537,65537,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,66886,66886,66886,47,65537,65584,65584,0,65536,65536,65536,0,65584,65584,65584,0,65537,65537,65537,0,65536,65536,65536,188,65540,65728,65728,0,65536,65536,65536,65536,0,0,65536,0,0,65728,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65728,0,0,65536,0,0,0,0,65536,65536,4128768,119342209,46130033,68952336,208358,0,0,0,524288,22742555,22730249,524288,524288,16384,65536,747,225399,4273,0,48,4620,0,2097536,4259840,1708520,1541363,22877046,3014656,0,0,3473408,8388608,8388608,8388608,0,0,0,0,0,190839,215650,12306,2004,0,209345,2099577,0,423,2099154,131072,0,131072,524288,0,524288,65536,65536,0,0,360,2097152,0,2097152,41315,0,2523,218970,0,2100802,0,0,31,222298112,917504,0,0,0,65536,65536,0,7596,2019877,0,2097152,2097152,0,793994,796783,0,19957,0,0,0,0,0,0,0,4194304,0,0,0,0,1096998266,1872652515,0,2097152,0,0,0,0,190777,0,0,0,0,0,131072,384,48,0,0,0,432,0,0,0,0,0,8200,0,0,0,2102113,0,9904,0,917504,914702,48,7480,183092,0,0,0,0,0,0,0,0,0,327680,0,0,441027,494703,65536,64048,48,1440,0,65536,0,0,0,0,0,0,0,65536,0,0,0,1966091,0,2097152,0,0,17399510,0,524288,2099535,0,1259299125,0,12076514013772666,12076540401262003,12076540401399282,12076514015021428
diff --git a/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/prev_analysis/1.csv
index 12cb2ffc50..7dc2340d3a 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,6057561.0,6057561.0,6057561.0,9.181885909300709
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4526211.0,4526211.0,4526211.0,6.860707305039414
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 256u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,3055501.0,3055501.0,3055501.0,4.63144516047865
diff --git a/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/prev_analysis/1001.csv
index ca08330db0..0e3bf5267e 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,46.862275449101794,Instr per wave
 SMEM,1.8083832335329342,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/prev_analysis/101.csv
index cd2d722827..af6143a315 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx908
 mi100
 48
 1228.8
-SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/prev_analysis/1202.csv
index 8a6bd15df1..0ea3b71704 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,33701.426573519224,2837.008590698242,547911.8947753906,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/prev_analysis/1901.csv
index 07fe0ff9d9..6081175b58 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,2.0,smem_
 VALU,735.0,valu_
 MFMA,,mfma_
 VMEM,8.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,22.0,br_
 VGPR,24.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,67894.0,wavefronts_
 Workgroups,16973.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,163.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,0.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,44.0,hbm_rd_
 HBM Wr,0.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,70.0,vl1_coales_
 VL1 Stall,29.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,37.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/prev_analysis/2001.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/prev_analysis/201.csv
index 934e23774e..e762f0229d 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,59.27505815065561,Pct,100,59.27505815065561
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,63.96805399754944,Threads,64,99.950084371171
 IPC - Issue,0.8437287060051507,Instr/cycle,5,16.874574120103013
-LDS BW,0.0,Gb/sec,23070.72,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,23070.72,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99351101937752,Pct,100,99.99351101937752
 Instr Cache BW,1410.0001369988809,Gb/s,4614.144,30.558217017043262
 Scalar L1D Cache Hit Rate,99.3562044853034,Pct,100,99.3562044853034
diff --git a/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/prev_analysis/602.csv
index c2fe5b05dc..2ce8d66340 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,52552.071856287424,0,795555,Simd
 Insufficient SIMD VGPRs,609426.6347305389,0,29972781,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/prev_analysis/701.csv
index d3f1bff5a3..1071413faa 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,23.976047904191617,8,36,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/sysinfo.csv
index 8658eb71e2..ff890d58db 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-dev01p3,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 11:34:46 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+dev01p3,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 11:34:46 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/timestamps.csv
index 22eb60b118..fc68420048 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev01p3/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,932098,932103,33554432,256,0,0,8,32,6464,0x0,0x7fa24b804180,12076540386173827,12076540386221406,12076540386544923,12076540386650935
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,932098,932103,32768,256,0,0,24,24,12480,0x0,0x7fa24b835100,12076540401083130,12076540401193523,12076540401200243,12076540401205969
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,932098,932103,4194304,256,0,0,24,24,12928,0x7fa37b76c900,0x7fa24b835140,12076540401247406,12076540401262003,12076540401399282,12076540401402695
diff --git a/projects/rocprofiler-compute/tests/workloads/dev1/mi100/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/dev1/mi100/SQ_IFETCH_LEVEL.csv
index 9cd588bb44..f2a569e9a1 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev1/mi100/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev1/mi100/SQ_IFETCH_LEVEL.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,924536,924541,33554432,256,0,0,8,32,6464,0x0,0x7f84a5404180,508009,508009,524288,6291456,792387,101370816,12076394277442031,12076394523449847,12076394523776405,12076394523886678
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,924536,924541,32768,256,0,0,24,24,12480,0x0,0x7f84a5435100,27741,27741,512,8192,8751,1126412,12076394538250372,12076394538559556,12076394538565956,12076394538575757
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,924536,924541,4194304,256,0,0,24,24,12928,0x7f85b1136900,0x7f84a5435140,218843,218843,65536,917504,140602,17958860,12076394538634306,12076394538864355,12076394538997634,12076394539014192
diff --git a/projects/rocprofiler-compute/tests/workloads/dev1/mi100/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/dev1/mi100/SQ_INST_LEVEL_LDS.csv
index e022eca32d..b564abb1bc 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev1/mi100/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev1/mi100/SQ_INST_LEVEL_LDS.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,926331,926336,33554432,256,0,0,8,32,6464,0x0,0x7ff791c04180,0,0,0,12076420714122644,12076420962384227,12076420962708863,12076420962815735
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,926331,926336,32768,256,0,0,24,24,12480,0x0,0x7ff791c35100,0,0,0,12076420977185327,12076420977496048,12076420977502128,12076420977512665
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,926331,926336,4194304,256,0,0,24,24,12928,0x7ff89d82a900,0x7ff791c35140,0,0,0,12076420977573458,12076420977783564,12076420977921643,12076420977925592
diff --git a/projects/rocprofiler-compute/tests/workloads/dev1/mi100/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/dev1/mi100/SQ_INST_LEVEL_SMEM.csv
index d22b682064..fb3d91ac09 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev1/mi100/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev1/mi100/SQ_INST_LEVEL_SMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,925952,925957,33554432,256,0,0,8,32,6464,0x0,0x7f43b7c04180,4194304,3212990,411313336,12076418192507764,12076418439640095,12076418439964893,12076418440076455
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,925952,925957,32768,256,0,0,24,24,12480,0x0,0x7f43b7c35100,512,23098,2956400,12076418454529462,12076418454826820,12076418454833380,12076418454838606
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,925952,925957,4194304,256,0,0,24,24,12928,0x7f43c79e4900,0x7f43b7c35140,65536,171004,21962000,12076418454902736,12076418455122818,12076418455258177,12076418455262033
diff --git a/projects/rocprofiler-compute/tests/workloads/dev1/mi100/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/dev1/mi100/SQ_INST_LEVEL_VMEM.csv
index d750f1ce28..d95931797f 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev1/mi100/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev1/mi100/SQ_INST_LEVEL_VMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,926143,926148,33554432,256,0,0,8,32,6464,0x0,0x7f15cfa04180,1048576,11235576,1438147260,12076419454465812,12076419701214917,12076419701539876,12076419701649649
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,926143,926148,32768,256,0,0,24,24,12480,0x0,0x7f15cfa35100,4096,113930,14569884,12076419716046811,12076419716351528,12076419716357928,12076419716368830
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,926143,926148,4194304,256,0,0,24,24,12928,0x7f16ffbde900,0x7f15cfa35140,524288,9932637,1271377396,12076419716430033,12076419716641287,12076419716781447,12076419716785163
diff --git a/projects/rocprofiler-compute/tests/workloads/dev1/mi100/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/dev1/mi100/SQ_LEVEL_WAVES.csv
index 810c379ceb..de56073b74 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev1/mi100/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev1/mi100/SQ_LEVEL_WAVES.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,926521,926526,33554432,256,0,0,8,32,6464,0x0,0x7fce83a04180,503699,503699,17355,4029600,524288,366928723,3829704,0,1482516916,12076421986929943,12076422230152268,12076422230476426,12076422230582908
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,926521,926526,32768,256,0,0,24,24,12480,0x0,0x7fce83a35100,27109,27109,19731,216880,512,1101208,73761,0,4419008,12076422245266393,12076422245592863,12076422245598943,12076422245607868
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,926521,926526,4194304,256,0,0,24,24,12928,0x7fcfb3b9d900,0x7fce83a35140,225780,225780,18089,1806248,65536,121244525,1637237,0,486787396,12076422245672528,12076422245913181,12076422246051260,12076422246055560
diff --git a/projects/rocprofiler-compute/tests/workloads/dev1/mi100/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/dev1/mi100/pmc_dispatch_info.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev1/mi100/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev1/mi100/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/dev1/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/dev1/mi100/pmc_perf.csv
index dd630f28c6..ea859c0efe 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev1/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev1/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBuffer.kd,0,0,0,925270,925275,33554432,256,0,0,8,32,6464,0x0,0x7fe78f004180,1048576,0,1048576,9437184,0,4194304,1048576,0,505908,505908,58024545,55405720,137,12012236,54380780,54260242,55359680,54175922,4047264,3852760,505908,0,505908,0,16189056,15300083,0,0,0,0,0,17384724,1048576,0,502116,0,0,0,502116,0,0,0,502116,0,0,0,502116,0,0,0,502116,0,0,0,502116,0,0,0,502116,0,0,0,502116,0,0,0,502116,0,0,0,502116,0,0,0,502116,0,0,0,502116,0,0,0,502116,0,0,0,502116,0,0,0,502116,0,0,0,502116,0,0,0,502116,0,0,0,502116,0,0,0,502116,0,0,0,502116,0,0,0,502116,0,0,0,502116,0,0,0,502116,0,0,0,502116,0,0,0,502116,0,0,0,502116,0,0,0,502116,0,0,0,502116,0,0,0,502116,0,0,0,502116,0,0,0,502116,0,0,0,502116,0,0,0,37568746,2786,0,0,0,52,0,0,0,0,0,0,0,0,0,0,0,2591,0,0,0,0,0,0,0,3,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,22,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,3,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2625,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,2674,0,0,0,0,0,0,0,0,0,0,0,97,0,0,0,1048576,0,0,14057,131072,131072,0,1447,131076,131076,0,499,131072,131072,0,0,131076,131076,0,0,131080,131080,0,0,131088,131088,0,0,131072,131072,0,0,131076,131076,0,0,131072,131072,0,303,131080,131080,0,0,131076,131076,0,2898799,131076,131076,0,0,131072,131072,0,3770505,131072,131072,0,0,131072,131072,0,0,131072,131072,0,257,131076,131076,0,3235560,131072,131072,0,0,131076,131076,0,0,131084,131084,0,0,131076,131076,0,0,131076,131076,0,1429,131072,131072,0,3349851,131072,131072,0,0,131084,131084,0,23322,131072,131072,0,263,131076,131076,0,8404,131080,131080,0,1449,131072,131072,0,0,131076,131076,0,0,131072,131072,0,0,131072,131072,1048576,0,2028,0,0,17270636,1204,0,0,17397734,966,0,0,17017579,1203,0,0,17258326,47398,0,0,29712472,1012,0,0,17570655,865,0,0,17597051,956,0,0,18763861,50593,0,0,30483194,937,0,0,17347798,883,0,0,16818728,927,0,0,16879892,885,0,0,17021277,708,0,0,17426006,1035,0,0,17968185,47659,0,0,30875591,793,0,0,16606369,1740,0,0,17090085,785,0,0,16687992,807,0,0,16761220,51312,0,0,31035277,811,0,0,17576352,1149,0,0,17814768,920,0,0,18660957,1120,0,0,16481649,836,0,0,16858659,740,0,0,16829860,900,0,0,16903963,781,0,0,17290561,826,0,0,17425152,904,0,0,17845723,1417,0,0,18838344,1048576,131072,131120,48,262192,131260,131076,192,262336,131072,131073,1,262145,131072,133660,2588,264732,131072,131072,0,262144,131119,131073,48,262192,131072,131073,1,262145,131072,133744,2672,264816,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131073,1,262145,131072,131093,21,262165,131072,131072,0,262144,131213,131075,144,262288,131072,131072,0,262144,131072,133659,2587,264731,131072,131072,0,262144,131072,131120,48,262192,131119,131073,48,262192,131072,131072,0,262144,131072,131076,4,262148,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131120,48,262192,131072,131072,0,262144,131072,133711,2639,264783,262144,0,262144,262336,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262288,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,0,0,3145728,524288,32505856,370936204,218526006,119904342,484914,0,0,0,1048576,52700667,52482064,1048576,1048576,131072,524288,690,507866,4605,0,96,10676,0,8388944,32505856,4014136,3811465,57004928,11534336,0,0,14155776,67108864,67108864,0,67108864,54386118,54091741,0,1048576,244159,768447,11920,1980,0,497510,8399653,0,4194727,4204926,13631488,0,3670016,1048576,1048576,0,4194304,9437184,0,0,360,33554432,54222553,4194304,0,0,2505,501246,0,11067,8388608,0,4194401,905969664,6291456,0,0,0,524288,524288,0,15360,16608363,0,16777216,4194304,4194304,0,0,0,17142,4194384,4194384,0,218120,0,0,0,33554432,0,0,0,0,634300041,0,2772247280,0,0,0,0,0,477773,0,0,220580,0,0,8388608,336,144,0,0,0,480,8388608,0,0,0,0,402108,0,0,0,10686,0,21354,0,6291456,6289467,96,2032,1887327,0,0,0,0,0,0,0,0,0,3145728,0,0,0,152525,4194304,4189867,144,4293,2097152,524288,1572864,0,0,0,0,0,0,524288,0,4128826,65535,4063245,0,0,8388608,0,42261444,0,1048576,10591,4194360,12976339,610326783,12076396376449834,12076423131128016,12076423131454413,12076396625340627
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,925270,925275,32768,256,0,0,24,24,12480,0x0,0x7fe78f035100,0,4096,4096,512,0,512,4096,0,28938,28938,1539887,625859,181,173173,130127,115724,617784,597470,231504,88481,28938,0,28938,0,926016,196085,0,0,0,0,0,63191,4096,0,29534,0,0,0,29534,0,0,0,29534,0,0,0,29534,0,0,0,29534,0,0,0,29534,0,0,0,29534,0,0,0,29534,0,0,0,29534,0,0,0,29534,0,0,0,29534,0,0,0,29534,0,0,0,29534,0,0,0,29534,0,0,0,29534,0,0,0,29534,0,0,0,29534,0,0,0,29534,0,0,0,29534,0,0,0,29534,0,0,0,29534,0,0,0,29534,0,0,0,29534,0,0,0,29534,0,0,0,29534,0,0,0,29534,0,0,0,29534,0,0,0,29534,0,0,0,29534,0,0,0,29534,0,0,0,29534,0,0,0,29534,0,0,0,0,256,0,0,0,304,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,376,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,257,0,0,0,305,0,0,0,4096,4096,0,94910,0,0,0,119703,0,0,0,88641,0,0,0,69843,0,0,0,105280,0,0,0,79114,0,0,0,84636,0,0,0,87030,0,0,0,138231,0,0,0,112067,0,0,0,88548,0,0,0,74261,0,0,0,184231,0,0,0,89723,0,0,0,69589,0,0,0,72793,0,0,0,105053,0,0,0,136913,0,0,0,64439,0,0,0,112647,0,0,0,128526,0,0,0,208884,0,0,0,76823,0,0,0,99350,0,0,0,94471,0,0,0,129503,0,0,0,88583,0,0,0,186863,0,0,0,100374,0,0,0,108083,0,0,0,156695,0,0,0,88185,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4096,0,304,304,304,0,256,256,256,0,257,257,257,0,256,256,256,0,256,256,256,47,257,304,304,0,257,257,257,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,188,261,449,449,0,377,377,377,0,256,256,256,0,256,256,256,188,260,448,448,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,304,304,304,47,257,304,304,0,256,256,256,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,304,0,0,256,0,0,0,0,512,512,35328,1073761,1018686,18723,11428,0,0,0,4096,73825,70809,4096,4096,128,512,624,27150,4334,0,48,220,0,8624,36352,232376,83793,1195063,26624,0,0,30208,65536,65536,65536,0,0,0,0,0,114,626,12494,1984,0,24724,9011,0,470,8541,1024,0,1024,4096,0,4096,512,512,0,0,360,16384,0,16384,0,0,2525,25280,0,8891,0,0,31,1933312,8192,0,0,0,512,512,0,120,15064,0,16384,16384,0,0,0,0,20085,0,0,0,0,0,0,0,32768,0,0,0,0,12333862,17531714,0,8192,0,0,0,0,697,0,0,0,0,0,1024,432,48,0,0,0,480,0,0,0,0,0,3148,0,0,0,8421,0,438,0,8192,6564,48,1580,1068,0,0,0,0,0,0,0,0,0,2560,0,0,0,53453,512,0,48,464,0,512,0,0,0,0,0,0,0,512,0,0,0,0,0,8192,0,0,449350,0,4096,8421,0,3244169,0,12076396640037941,12076423146279107,12076423146286147,12076396641024745
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,925270,925275,4194304,256,0,0,24,24,12928,0x7fe8bef86900,0x7fe78f035140,0,524288,524288,65536,0,65536,524288,0,224609,224609,24941230,23674951,31198,7257166,22742260,22616734,23656824,21492579,1796872,1646265,224609,0,224609,0,7187488,6477286,0,0,0,0,0,21290904,524288,0,226847,0,0,0,226847,0,0,0,226847,0,0,0,226847,0,0,0,226847,0,0,0,226847,0,0,0,226847,0,0,0,226847,0,0,0,226847,0,0,0,226847,0,0,0,226847,0,0,0,226847,0,0,0,226847,0,0,0,226847,0,0,0,226847,0,0,0,226847,0,0,0,226847,0,0,0,226847,0,0,0,226847,0,0,0,226847,0,0,0,226847,0,0,0,226847,0,0,0,226847,0,0,0,226847,0,0,0,226847,0,0,0,226847,0,0,0,226847,0,0,0,226847,0,0,0,226847,0,0,0,226847,0,0,0,226847,0,0,0,226847,0,0,0,0,67134,0,61673,0,65584,0,28253,0,65540,0,7576,0,65536,0,29319,0,65536,0,27814,0,65536,0,32468,0,65536,0,8314,0,65536,0,52949,0,65536,0,10224,0,65536,0,14928,0,65536,0,12065,0,65536,0,16872,0,65656,0,11237,0,65536,0,12264,0,65536,0,10744,0,65536,0,27740,0,65537,0,5867,0,65536,0,10104,0,65536,0,3061,0,65536,0,1160,0,65536,0,6464,0,65536,0,18049,0,65536,0,6754,0,65536,0,44803,0,65536,0,9596,0,65537,0,15934,0,65536,0,3893,0,65536,0,11025,0,66255,0,45986,0,65536,0,5663,0,65540,0,23678,0,65585,0,9156,0,524288,524288,0,28406508,0,0,0,26810013,0,0,0,25139754,0,0,0,25382372,0,0,0,26258270,0,0,0,26594089,0,0,0,26209882,0,0,0,27762650,0,0,0,26302083,0,0,0,25904014,0,0,0,23504033,0,0,0,53147271,0,0,0,26493850,0,0,0,26811991,0,0,0,26754914,0,0,0,28628254,0,0,0,26550585,0,0,0,24725321,0,0,0,26596213,0,0,0,25715475,0,0,0,21783491,0,0,0,25560974,0,0,0,26323901,0,0,0,44499165,0,0,0,26282275,0,0,0,27880820,0,0,0,27597480,0,0,0,27484871,0,0,0,23691192,0,0,0,24849587,0,0,0,26818045,0,0,0,25597477,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,524288,0,65584,65584,65584,0,65536,65536,65536,188,65541,65729,65729,0,68004,68004,68004,0,65536,65536,65536,47,65537,65584,65584,0,65537,65537,65537,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65537,65537,65537,0,65657,65657,65657,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,68299,68299,68299,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65584,65584,65584,188,65540,65728,65728,0,65536,65536,65536,65536,0,0,65536,0,0,65728,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65728,0,0,65536,0,0,0,0,65536,65536,4128768,134789285,50701925,79827520,201066,0,0,0,524288,21783625,21772756,524288,524288,16384,65536,739,219191,4224,0,48,3258,0,2097536,4259840,1841568,1669270,24724340,3014656,0,0,3473408,8388608,8388608,8388608,0,0,0,0,0,155000,189530,12558,2427,0,225963,2102777,0,423,2102354,131072,0,131072,524288,0,524288,65536,65536,0,0,360,2097152,0,2097152,44981,0,2406,214495,0,2100161,0,0,31,222298112,917504,0,0,0,65536,65536,0,7555,2019742,0,2097152,2097152,0,971075,974454,0,20505,0,0,0,0,0,0,0,4194304,0,0,0,0,1180724461,2100967958,0,2097152,0,0,0,0,186247,0,0,0,0,0,131072,384,48,0,0,0,432,0,0,0,0,0,9564,0,0,0,2099817,0,5312,0,917504,914726,48,7448,204833,0,0,0,0,0,0,0,0,0,327680,0,0,756739,809539,65536,64048,48,1440,0,65536,0,0,0,0,0,0,0,65536,0,0,0,1966095,0,2097152,0,0,13847517,0,524288,2102623,0,799284749,0,12076396641658563,12076423146343746,12076423146476545,12076396642905851
diff --git a/projects/rocprofiler-compute/tests/workloads/dev1/mi100/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/dev1/mi100/prev_analysis/1.csv
index e4ef73ca4c..6a7e06cb23 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev1/mi100/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev1/mi100/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,6049710.0,6049710.0,6049710.0,9.18024439315873
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4525243.0,4525243.0,4525243.0,6.866913732795588
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 256u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,3047016.0,3047016.0,3047016.0,4.6237508161325
diff --git a/projects/rocprofiler-compute/tests/workloads/dev1/mi100/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/dev1/mi100/prev_analysis/1001.csv
index ca08330db0..0e3bf5267e 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev1/mi100/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev1/mi100/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,46.862275449101794,Instr per wave
 SMEM,1.8083832335329342,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/dev1/mi100/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/dev1/mi100/prev_analysis/101.csv
index 3359ed784f..34875b6af9 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev1/mi100/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev1/mi100/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx908
 mi100
 48
 1228.8
-SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/dev1/mi100/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/dev1/mi100/prev_analysis/1202.csv
index dd0d786a2e..2e7db39b9d 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev1/mi100/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev1/mi100/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,33605.693945056664,2830.0186462402344,547925.7553710938,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/dev1/mi100/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/dev1/mi100/prev_analysis/1901.csv
index bf13435b5e..657171ec97 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev1/mi100/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev1/mi100/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,2.0,smem_
 VALU,735.0,valu_
 MFMA,,mfma_
 VMEM,8.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,22.0,br_
 VGPR,24.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,67894.0,wavefronts_
 Workgroups,16973.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,163.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,0.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,44.0,hbm_rd_
 HBM Wr,0.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,70.0,vl1_coales_
 VL1 Stall,29.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,35.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/dev1/mi100/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/dev1/mi100/prev_analysis/2001.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev1/mi100/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev1/mi100/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/dev1/mi100/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/dev1/mi100/prev_analysis/201.csv
index 49e1c54549..efbfdb8de6 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev1/mi100/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev1/mi100/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,59.421867628446385,Pct,100,59.421867628446385
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,63.967254135101435,Threads,64,99.948834586096
 IPC - Issue,0.8437211476038775,Instr/cycle,5,16.87442295207755
-LDS BW,0.0,Gb/sec,23070.72,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,23070.72,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99341709921835,Pct,100,99.99341709921835
 Instr Cache BW,1412.9333396984428,Gb/s,4614.144,30.621786829766098
 Scalar L1D Cache Hit Rate,99.35620448529356,Pct,100,99.35620448529356
diff --git a/projects/rocprofiler-compute/tests/workloads/dev1/mi100/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/dev1/mi100/prev_analysis/602.csv
index 07b002c4cf..55a34ea16e 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev1/mi100/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev1/mi100/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,57210.622754491014,0,971075,Simd
 Insufficient SIMD VGPRs,654293.0538922156,0,39594143,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/dev1/mi100/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/dev1/mi100/prev_analysis/701.csv
index d3f1bff5a3..1071413faa 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev1/mi100/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev1/mi100/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,23.976047904191617,8,36,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/dev1/mi100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/dev1/mi100/sysinfo.csv
index f467383f41..98f0badf11 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev1/mi100/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev1/mi100/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-dev1,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 11:32:49 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+dev1,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 11:32:49 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/dev1/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/dev1/mi100/timestamps.csv
index a1e2048948..f996f61653 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev1/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev1/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,926570,926576,33554432,256,0,0,8,32,6464,0x0,0x7f5a66404180,12076423131080852,12076423131128016,12076423131454413,12076423131561175
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,926570,926576,32768,256,0,0,24,24,12480,0x0,0x7f5a66435100,12076423146177755,12076423146279107,12076423146286147,12076423146291897
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,926570,926576,4194304,256,0,0,24,24,12928,0x7f5b720e9900,0x7f5a66435140,12076423146330890,12076423146343746,12076423146476545,12076423146480187
diff --git a/projects/rocprofiler-compute/tests/workloads/dev1/mi200/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/dev1/mi200/SQ_IFETCH_LEVEL.csv
index 95cacd2750..e24a6b8394 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev1/mi200/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev1/mi200/SQ_IFETCH_LEVEL.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,229387,229387,33554432,256,0,0,4,32,4160,0x0,0x7f6c7d404280,382955,382955,524288,4718592,681277,76305216,17703999491386,17703289764389,17704150035092,17704150122942
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,229387,229387,32768,256,0,0,12,24,13888,0x0,0x7f6c7d423f80,33183,33183,512,8192,5968,677612,17704155264803,17704150035092,17704155402300,17704155407109
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,229387,229387,4194304,256,0,0,12,24,14336,0x7f6c80453380,0x7f6c7d423fc0,167502,167502,65536,917504,152335,17093232,17704155444078,17704155402300,17704155777981,17704155780500
diff --git a/projects/rocprofiler-compute/tests/workloads/dev1/mi200/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/dev1/mi200/SQ_INST_LEVEL_LDS.csv
index bc90ffd583..9787eb1633 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev1/mi200/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev1/mi200/SQ_INST_LEVEL_LDS.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,231235,231235,33554432,256,0,0,4,32,4160,0x0,0x7fa30bc04280,0,0,0,17723322357090,17722609008058,17723469569786,17723469683016
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,231235,231235,32768,256,0,0,12,24,13888,0x0,0x7fa30bc23f80,0,0,0,17723474867387,17723469569786,17723474996356,17723475001123
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,231235,231235,4194304,256,0,0,12,24,14336,0x7fa3325bd380,0x7fa30bc23fc0,0,0,0,17723475036342,17723474996356,17723475368197,17723475370774
diff --git a/projects/rocprofiler-compute/tests/workloads/dev1/mi200/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/dev1/mi200/SQ_INST_LEVEL_SMEM.csv
index ee84cdf94d..9ac56cdeb7 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev1/mi200/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev1/mi200/SQ_INST_LEVEL_SMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,229165,229165,33554432,256,0,0,4,32,4160,0x0,0x7fed8e404280,3670016,3210192,359394552,17703062218323,17697497051832,17703209908589,17703210020339
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,229165,229165,32768,256,0,0,12,24,13888,0x0,0x7fed8e423f80,512,102828,11537184,17703215180549,17703209908589,17703215310683,17703215315516
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,229165,229165,4194304,256,0,0,12,24,14336,0x7fed91369380,0x7fed8e423fc0,65536,615618,68994040,17703215349825,17703215310683,17703215686844,17703215689607
diff --git a/projects/rocprofiler-compute/tests/workloads/dev1/mi200/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/dev1/mi200/SQ_INST_LEVEL_VMEM.csv
index 5935d7cff9..7c190e69cb 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev1/mi200/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev1/mi200/SQ_INST_LEVEL_VMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,231013,231013,33554432,256,0,0,4,32,4160,0x0,0x7ff8df004280,524288,5459030,611380564,17722381097853,17720121522829,17722528759638,17722528847088
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,231013,231013,32768,256,0,0,12,24,13888,0x0,0x7ff8df023f80,4096,41280,4619436,17722533966569,17722528759638,17722534094687,17722534099686
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,231013,231013,4194304,256,0,0,12,24,14336,0x7ff8e2075380,0x7ff8df023fc0,524288,10744640,1203364744,17722534135465,17722534094687,17722534465728,17722534468237
diff --git a/projects/rocprofiler-compute/tests/workloads/dev1/mi200/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/dev1/mi200/SQ_LEVEL_WAVES.csv
index c06c4d16a4..78db014b95 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev1/mi200/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev1/mi200/SQ_LEVEL_WAVES.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,229609,229609,33554432,256,0,0,4,32,4160,0x0,0x7fbe34404280,381263,381263,8890,3050112,524288,238895534,2962457,0,971826084,17704936968427,17704230750143,17705081453045,17705081565284
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,229609,229609,32768,256,0,0,12,24,13888,0x0,0x7fbe34423f80,33603,33603,30038,268832,512,1728667,161482,0,6928212,17705086704565,17705081453045,17705086842338,17705086846922
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,229609,229609,4194304,256,0,0,12,24,14336,0x7fbe37412380,0x7fbe34423fc0,165838,165838,13145,1326712,65536,71213297,1218469,0,286591028,17705086889921,17705086842338,17705087234019,17705087236572
diff --git a/projects/rocprofiler-compute/tests/workloads/dev1/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/dev1/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev1/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev1/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/dev1/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/dev1/mi200/pmc_perf.csv
index a63b04c08c..0ed31b0c6d 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev1/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev1/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDI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],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBufferAligned.kd,0,0,0,230375,230375,33554432,256,0,0,4,32,4160,0x0,0x7f6c7ee04280,3071600,2979036,524288,38703273,241699497,392,224,0,383949,383949,38969325.0,37934828.0,6.0,4134527.0,31050920.0,30684336.0,37914212.0,37354473.0,3069889,2985461,383949,0,383949,0,12286368.0,9486912.0,0.0,0.0,0,0,616,0,4718592,4714800,112,3680,375146,0.0,0.0,0.0,524288.0,28466155.0,27732164.0,7993.0,524288.0,131072,524288,301,384305,2315,0,56.0,301.0,0.0,4194696.0,0,0,0,0,0,7340032,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,20035679.0,524288.0,0,383536,0,0,0,383536,0,0,0,383536,0,0,0,383536,0,0,0,383536,0,0,0,383536,0,0,0,383536,0,0,0,383536,0,0,0,383536,0,0,0,383536,0,0,0,383536,0,0,0,383536,0,0,0,383536,0,0,0,383536,0,0,0,383536,0,0,0,383536,0,0,0,383536,0,0,0,383536,0,0,0,383536,0,0,0,383536,0,0,0,383536,0,0,0,383536,0,0,0,383536,0,0,0,383536,0,0,0,383536,0,0,0,383536,0,0,0,383536,0,0,0,383536,0,0,0,383536,0,0,0,383536,0,0,0,383536,0,0,0,383536,0,0,0,0,0,0.0,21161057.0,0,0,0,0,0,0,0,0,0,0,0,0,33,0,0,0,2,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,0,0,112,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,56,0,0,0,35,0,0,0,5,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,33,0,0,0,1,0,0,0,524288.0,0.0,0,0,129024,129024,0,0,129024,129024,0,548511,129024,129024,0,322097,129024,129024,0,328,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,158,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,45616,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,353,129024,129024,0,867,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,29101,129024,129024,0,1030,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,157,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,44072,129024,129024,0,185,129024,129024,524288.0,0.0,43214,0,0,50169003,44794,0,0,50453176,44488,0,0,50130980,46798,0,0,51921553,45513,0,0,51299820,46816,0,0,51736098,45079,0,0,50892139,47377,0,0,52701412,45648,0,0,51097558,45812,0,0,50964258,44279,0,0,50311929,48215,0,0,52428897,45654,0,0,51581806,46936,0,0,51512617,46514,0,0,51176285,50193,0,0,53482912,44125,0,0,50359360,45249,0,0,50736050,44349,0,0,50208163,48145,0,0,52276602,44091,0,0,51034516,45103,0,0,51002146,44824,0,0,50739738,48609,0,0,52807766,46956,0,0,51233891,46679,0,0,51170878,46191,0,0,50706836,48229,0,0,52243131,46444,0,0,51788061,48370,0,0,52131353,46120,0,0,51212403,50744,0,0,53640142,0.0,65536,65568,32,131104,65536,65536,0,131072,65536,65536,0,131072,65536,65538,2,131074,65646,65538,112,131184,65536,65536,0,131072,65536,65592,56,131128,65536,65536,0,131072,65536,65536,0,131072,65536,65680,144,131216,65536,65536,0,131072,65591,65537,56,131128,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65570,34,131106,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65758,65539,225,131297,65536,65536,0,131072,65536,65536,0,131072,65536,65537,1,131073,65536,65536,0,131072,65536,65568,32,131104,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65591,65537,56,131128,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131184,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131296,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131128,0,131072,1017298,0,524288,3670016,3663353,224,6439,1048576,33554432.0,33554432.0,0.0,33554432.0,30245139.0,28609679.0,0.0,524288.0,218732,536014,8668,899,0,383972,4195055.0,0.0,2097594.0,2097461.0,1048576,1048576,0,524288,0,524288,7340032,0,0.0,0.0,104.0,8388608.0,29772237.0,2097152.0,0.0,213893,0,1251,386937,0,749.0,4194304.0,0.0,2064387.0,25690112,9437184,0,0,0,0,0,0,13277.0,8242561.0,0.0,8388608.0,2097152.0,4194304.0,9814776,0,0,8799,4128768.0,4128768.0,0.0,1491219.0,0,0,0,0,0,0,5767168,1048576,319640671.0,0.0,1486667075.0,0.0,26.0,0.0,0,0,377092,0.0,0.0,1535692.0,0.0,3670016,524288,0,0,0,2621440,524288,180039302,4194304.0,0.0,0.0,0.0,0.0,1157549.0,0,0,0.0,311.0,0.0,606.0,42088769,24117248,0,0,9437184,11010048,0,3145728,0.0,0.0,0.0,0.0,0.0,0.0,0,1572864,0.0,0.0,0.0,195098.0,524288,524288,0,3670016,7340032,603979776,4718592,0,0.0,0.0,0.0,0.0,0.0,0.0,524288,0,2064384.0,0.0,2031623.0,0.0,0,0,524288,0,0,0,0,33554432,0.0,4194304.0,0.0,18953583.0,0.0,0.0,140.0,4128768.0,987028.0,1704679592.0,17706367717660,17724136192787,17724136430867,17706513286194
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,230375,230375,32768,256,0,0,12,24,13888,0x0,0x7f6c7ee23f80,274056,167882,512,1480024,1823219,504,56,0,34256,34256,2415888.0,157008.0,153.0,0.0,33074.0,29633.0,150728.0,131950.0,274048,175018,34256,0,34256,0,1096192.0,396805.0,0.0,0.0,0,0,560,0,8192,6214,56,1922,23120,0.0,0.0,0.0,4096.0,29664.0,28223.0,0.0,4096.0,128,512,302,32476,2298,0,0.0,59.0,0.0,4600.0,0,0,0,0,0,1024,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,16676.0,4096.0,0,33249,0,0,0,33249,0,0,0,33249,0,0,0,33249,0,0,0,33249,0,0,0,33249,0,0,0,33249,0,0,0,33249,0,0,0,33249,0,0,0,33249,0,0,0,33249,0,0,0,33249,0,0,0,33249,0,0,0,33249,0,0,0,33249,0,0,0,33249,0,0,0,33249,0,0,0,33249,0,0,0,33249,0,0,0,33249,0,0,0,33249,0,0,0,33249,0,0,0,33249,0,0,0,33249,0,0,0,33249,0,0,0,33249,0,0,0,33249,0,0,0,33249,0,0,0,33249,0,0,0,33249,0,0,0,33249,0,0,0,33249,0,0,0,0,0,0.0,0.0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,312,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,257,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,4096.0,4096.0,0,100380,0,0,0,81345,0,0,0,664311,0,0,0,97521,0,0,0,79141,0,0,0,80900,0,0,0,76799,0,0,0,84344,0,0,0,75545,0,0,0,77247,0,0,0,73731,0,0,0,91915,0,0,0,89328,0,0,0,85393,0,0,0,84609,0,0,0,82964,0,0,0,81732,0,0,0,77182,0,0,0,95392,0,0,0,162328,0,0,0,98676,0,0,0,85231,0,0,0,75640,0,0,0,94324,0,0,0,79620,0,0,0,76625,0,0,0,72123,0,0,0,81784,0,0,0,79116,0,0,0,92851,0,0,0,87580,0,0,0,86880,0,0,0.0,0.0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4096.0,0,128,128,128,0,128,128,128,0,128,128,128,0,129,129,129,0,128,128,128,222,130,352,352,0,128,128,128,0,128,128,128,0,128,128,128,0,184,184,184,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,222,130,352,352,0,128,128,128,0,128,128,128,0,128,128,128,0,129,129,129,0,128,128,128,0,128,128,128,0,128,128,128,0,129,129,129,55,129,184,184,0,128,128,128,0,129,129,129,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,352,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,352,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,184,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,670,0,0,512,0,56,456,0,65536.0,65536.0,65536.0,0.0,0.0,0.0,0.0,0.0,6,518,11902,1062,0,32200,4659.0,0.0,499.0,4160.0,512,0,0,0,4096,4096,512,0,0.0,0.0,104.0,16384.0,0.0,16384.0,4096.0,0,0,1373,31490,0,4659.0,0.0,0.0,31.0,35328,26112,0,0,0,0,0,0,104.0,15240.0,0.0,16384.0,16384.0,0.0,0,0,0,29685,0.0,0.0,0.0,0.0,0,0,0,0,0,0,10752,3584,3977795.0,5273169.0,0.0,8192.0,0.0,0.0,0,0,497,0.0,0.0,0.0,0.0,512,4096,0,0,0,512,512,1691057,0.0,0.0,0.0,0.0,0.0,1554.0,0,0,0.0,8260.0,0.0,118.0,17834,32256,0,0,26112,1024,0,1024,0.0,0.0,0.0,0.0,0.0,0.0,0,1024,0.0,0.0,0.0,52919.0,4096,0,4096,512,512,1671168,8192,0,0.0,0.0,0.0,0.0,0.0,0.0,512,0,0.0,0.0,0.0,0.0,0,0,512,0,0,0,0,32768,8192.0,0.0,0.0,106998.0,0.0,4096.0,8204.0,0.0,3489024.0,0.0,17706519498618,17724141198713,17724141212153,17706519981066
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,230375,230375,4194304,256,0,0,12,24,14336,0x7f6c81e92380,0x7f6c7ee23fc0,1364864,1260923,65536,16295761,95254605,392,56,0,170607,170607,16623126.0,15175995.0,22796.0,780702.0,14779438.0,14713796.0,15169736.0,13031472.0,1364856,1267810,170607,0,170607,0,5459424.0,4929886.0,0.0,0.0,0,0,448,0,917504,913426,0,4078,154723,0.0,0.0,0.0,524288.0,12679913.0,12644108.0,2188.0,524288.0,16384,65536,302,166223,2348,0,0.0,186.0,0.0,1048968.0,0,0,0,0,0,131072,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,10859637.0,524288.0,0,172284,0,0,0,172284,0,0,0,172284,0,0,0,172284,0,0,0,172284,0,0,0,172284,0,0,0,172284,0,0,0,172284,0,0,0,172284,0,0,0,172284,0,0,0,172284,0,0,0,172284,0,0,0,172284,0,0,0,172284,0,0,0,172284,0,0,0,172284,0,0,0,172284,0,0,0,172284,0,0,0,172284,0,0,0,172284,0,0,0,172284,0,0,0,172284,0,0,0,172284,0,0,0,172284,0,0,0,172284,0,0,0,172284,0,0,0,172284,0,0,0,172284,0,0,0,172284,0,0,0,172284,0,0,0,172284,0,0,0,172284,0,0,0,0,0,0.0,0.0,65536,0,14619,0,65536,0,10543,0,65536,0,7407,0,65537,0,23663,0,65536,0,33633,0,65536,0,18682,0,65536,0,17944,0,65536,0,37997,0,65536,0,9461,0,65536,0,17158,0,65536,0,13451,0,65536,0,9280,0,65536,0,18049,0,65592,0,13528,0,65536,0,17965,0,65536,0,20642,0,65536,0,7796,0,65536,0,31944,0,65536,0,6608,0,65536,0,29263,0,65536,0,16167,0,65598,0,18866,0,65537,0,26881,0,65539,0,12809,0,65540,0,6329,0,65536,0,35531,0,65536,0,6075,0,65536,0,11338,0,65536,0,23352,0,65537,0,6924,0,65601,0,15808,0,65536,0,26669,0,524288.0,524288.0,0,44756020,0,0,0,40061066,0,0,0,43532171,0,0,0,45341756,0,0,0,44886384,0,0,0,43752593,0,0,0,43172399,0,0,0,50019969,0,0,0,48223211,0,0,0,41235085,0,0,0,44719986,0,0,0,41610942,0,0,0,44724647,0,0,0,40711643,0,0,0,38399602,0,0,0,47021386,0,0,0,47521668,0,0,0,46155332,0,0,0,46729287,0,0,0,45325246,0,0,0,47517118,0,0,0,41848756,0,0,0,46493996,0,0,0,39510537,0,0,0,36891691,0,0,0,46777131,0,0,0,39862391,0,0,0,41061791,0,0,0,41580409,0,0,0,41080741,0,0,0,41122077,0,0,0,48962761,0,0,0.0,0.0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,524288.0,0,32769,32769,32769,0,32769,32769,32769,0,32768,32768,32768,0,32769,32769,32769,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32824,32824,32824,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32827,32827,32827,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32769,32769,32769,166,32770,32936,32936,222,32770,32992,32992,0,32769,32769,32769,0,32768,32768,32768,0,32830,32830,32830,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32936,0,0,32992,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,883996,0,0,65536,63800,56,1680,0,8388608.0,8388608.0,8388608.0,0.0,0.0,0.0,0.0,0.0,123152,147723,10123,2622,0,161891,1049153.0,0.0,388.0,1048765.0,65536,0,0,0,524288,524288,131072,0,0.0,0.0,104.0,2097152.0,0.0,2097152.0,524288.0,43036,0,3433,161507,0,1049156.0,0.0,0.0,31.0,4063232,2883584,0,0,0,0,0,0,6601.0,2027848.0,0.0,2097152.0,2097152.0,0.0,1771131,0,0,13647,0.0,0.0,0.0,0.0,262144,0,0,0,0,0,1507328,458752,980581883.0,2198177153.0,0.0,2097152.0,92.0,0.0,0,0,148633,0.0,0.0,0.0,0.0,65536,524288,0,0,0,65536,65536,48495524,0.0,0.0,0.0,0.0,0.0,31282.0,0,0,0.0,2097338.0,0.0,358.0,34729268,3735552,0,0,2883584,196608,0,131072,0.0,0.0,0.0,0.0,0.0,0.0,0,131072,0.0,0.0,397756.0,1159675.0,524288,0,524288,65536,131072,184549376,917504,0,0.0,0.0,0.0,0.0,0.0,0.0,65536,0,0.0,0.0,983047.0,0.0,0,0,65536,0,0,0,0,4194304,2097152.0,0.0,0.0,12284890.0,0.0,524288.0,2097273.0,0.0,1467923770.0,0.0,17706521078058,17724141279193,17724141371673,17706521845949
diff --git a/projects/rocprofiler-compute/tests/workloads/dev1/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/dev1/mi200/prev_analysis/1.csv
index ac802f4138..fca17433f3 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev1/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev1/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,3357924.0,3357924.0,3357924.0,7.842469023940134
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,1726563.0,1726563.0,1726563.0,4.032407179370692
 "void benchmark_func<double, 256, 8u, 512u>(double, double*) [clone .kd]",1,1715362.0,1715362.0,1715362.0,4.006247118709058
diff --git a/projects/rocprofiler-compute/tests/workloads/dev1/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/dev1/mi200/prev_analysis/1001.csv
index f475f954a6..fb5988001a 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev1/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev1/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,494.8622754491018,Instr per wave
 VMEM,7.958083832335329,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,0.0,Instr per wave
 SALU,24.520958083832337,Instr per wave
 SMEM,1.8023952095808384,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/dev1/mi200/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/dev1/mi200/prev_analysis/101.csv
index b9a1fd044c..322f82e242 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev1/mi200/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev1/mi200/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx90a
 mi200
 56
 1638.4
-roofline|SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+roofline|SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/dev1/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/dev1/mi200/prev_analysis/1202.csv
index 1d1fcaac3a..faf987865c 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev1/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev1/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,18710.312669262916,1844.0208206176758,257512.73510742188,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/dev1/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/dev1/mi200/prev_analysis/1901.csv
index 74876b784a..67a5196371 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev1/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev1/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,2.0,smem_
 VALU,495.0,valu_
 MFMA,0.0,mfma_
 VMEM,8.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,10.0,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,67894.0,wavefronts_
 Workgroups,16973.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,128.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,0.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,44.0,hbm_rd_
 HBM Wr,0.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,70.0,vl1_coales_
 VL1 Stall,1.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,25.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/dev1/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/dev1/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev1/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev1/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/dev1/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/dev1/mi200/prev_analysis/201.csv
index 98be4f2cbe..c74c69100d 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev1/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev1/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,57.676542261213726,Pct,100,57.676542261213726
 MFMA Util,0.0,Pct,100,0.0
 VALU Active Threads/Wave,64.0,Threads,64,100.0
 IPC - Issue,1.0,Instr/cycle,5,20.0
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99260892771422,Pct,100,99.99260892771422
 Instr Cache BW,1672.988845263023,Gb/s,6092.8,27.45845662524657
 Scalar L1D Cache Hit Rate,99.34855886103351,Pct,100,99.34855886103351
diff --git a/projects/rocprofiler-compute/tests/workloads/dev1/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/dev1/mi200/prev_analysis/602.csv
index 03ca569b27..0ab92268f1 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev1/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev1/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,12406980.437125748,0,369318193,Simd
 Insufficient SIMD VGPRs,0.0,0,0,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/dev1/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/dev1/mi200/prev_analysis/701.csv
index 12250d77c0..db0925a109 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev1/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev1/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/dev1/mi200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/dev1/mi200/sysinfo.csv
index 28ecad088d..e5653ee316 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev1/mi200/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev1/mi200/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-dev1,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:48:23 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,roofline|SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+dev1,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:48:23 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,roofline|SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/dev1/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/dev1/mi200/timestamps.csv
index 3011648e09..ea021c83b1 100644
--- a/projects/rocprofiler-compute/tests/workloads/dev1/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dev1/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,231318,231318,33554432,256,0,0,4,32,4160,0x0,0x7ff759c04280,17724136167316,17724136192787,17724136430867,17724136522737
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,231318,231318,32768,256,0,0,12,24,13888,0x0,0x7ff759c23f80,17724141183450,17724141198713,17724141212153,17724141230479
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,231318,231318,4194304,256,0,0,12,24,14336,0x7ff75cbbb380,0x7ff759c23fc0,17724141234519,17724141279193,17724141371673,17724141373895
diff --git a/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/SQ_IFETCH_LEVEL.csv
index a13c9ad5af..f3001164ba 100644
--- a/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/SQ_IFETCH_LEVEL.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,894519,894524,33554432,256,0,0,8,32,6464,0x0,0x7fbd92804180,500721,500721,524288,6291456,791858,101408836,12075821832194819,12075822077796279,12075822078117717,12075822078232389
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,894519,894524,32768,256,0,0,24,24,12480,0x0,0x7fbd92835100,27875,27875,512,8192,8931,1153012,12075822092747455,12075822093085159,12075822093091559,12075822093100361
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,894519,894524,4194304,256,0,0,24,24,12928,0x7fbe9e487900,0x7fbd92835140,217572,217572,65536,917504,146298,18793520,12075822093156745,12075822093388837,12075822093521476,12075822093524258
diff --git a/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/SQ_INST_LEVEL_LDS.csv
index 5abcfdd772..47ea0ece3f 100644
--- a/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/SQ_INST_LEVEL_LDS.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,896318,896323,33554432,256,0,0,8,32,6464,0x0,0x7f4214204180,0,0,0,12075848456376772,12075848700835421,12075848701157819,12075848701272961
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,896318,896323,32768,256,0,0,24,24,12480,0x0,0x7f4214235100,0,0,0,12075848716121136,12075848716425626,12075848716432345,12075848716441912
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,896318,896323,4194304,256,0,0,24,24,12928,0x7f431ff59900,0x7f4214235140,0,0,0,12075848716497545,12075848716720824,12075848716854103,12075848716856793
diff --git a/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/SQ_INST_LEVEL_SMEM.csv
index 4411085ef9..55ba09e2a0 100644
--- a/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/SQ_INST_LEVEL_SMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,895940,895945,33554432,256,0,0,8,32,6464,0x0,0x7f8794404180,4194304,3152002,403669896,12075845934677406,12075846177430441,12075846177754120,12075846177866412
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,895940,895945,32768,256,0,0,24,24,12480,0x0,0x7f8794435100,512,27418,3505928,12075846192656629,12075846192956214,12075846192963574,12075846192967777
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,895940,895945,4194304,256,0,0,24,24,12928,0x7f88a009c900,0x7f8794435140,65536,187480,23953328,12075846193039831,12075846193263252,12075846193397972,12075846193400972
diff --git a/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/SQ_INST_LEVEL_VMEM.csv
index 442ae44c67..63fa5c752f 100644
--- a/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/SQ_INST_LEVEL_VMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,896130,896135,33554432,256,0,0,8,32,6464,0x0,0x7fd0e6a04180,1048576,11113035,1423723076,12075847189171067,12075847436771904,12075847437096223,12075847437209605
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,896130,896135,32768,256,0,0,24,24,12480,0x0,0x7fd0e6a35100,4096,106978,13696112,12075847451790473,12075847452108439,12075847452114999,12075847452123532
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,896130,896135,4194304,256,0,0,24,24,12928,0x7fd216a7e900,0x7fd0e6a35140,524288,11732531,1501743840,12075847452175839,12075847452398998,12075847452533077,12075847452536279
diff --git a/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/SQ_LEVEL_WAVES.csv
index 8f43712153..c1cc2e0b39 100644
--- a/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/SQ_LEVEL_WAVES.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,896508,896513,33554432,256,0,0,8,32,6464,0x0,0x7fce1aa04180,502309,502309,16285,4018480,524288,366559346,3822785,0,1481022520,12075849713232663,12075849959550332,12075849959873691,12075849959985773
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,896508,896513,32768,256,0,0,24,24,12480,0x0,0x7fce1aa35100,27422,27422,20382,219384,512,1165855,78921,0,4677784,12075849974536505,12075849974861105,12075849974867505,12075849974874844
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,896508,896513,4194304,256,0,0,24,24,12928,0x7fcf4aae6900,0x7fce1aa35140,219277,219277,19662,1754224,65536,133685285,1589660,0,536552300,12075849974944253,12075849975195344,12075849975329423,12075849975332574
diff --git a/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/pmc_dispatch_info.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/pmc_perf.csv
index bb6a86c497..951ddd0540 100644
--- a/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBuffer.kd,0,0,0,895253,895258,33554432,256,0,0,8,32,6464,0x0,0x7f7089004180,1048576,0,1048576,9437184,0,4194304,1048576,0,505082,505082,58030011,55453002,170,13173463,54734165,54644875,55421485,54241424,4040656,3853126,505082,0,505082,0,16162624,15332637,0,0,0,0,0,17792352,1048576,0,504573,0,0,0,504573,0,0,0,504573,0,0,0,504573,0,0,0,504573,0,0,0,504573,0,0,0,504573,0,0,0,504573,0,0,0,504573,0,0,0,504573,0,0,0,504573,0,0,0,504573,0,0,0,504573,0,0,0,504573,0,0,0,504573,0,0,0,504573,0,0,0,504573,0,0,0,504573,0,0,0,504573,0,0,0,504573,0,0,0,504573,0,0,0,504573,0,0,0,504573,0,0,0,504573,0,0,0,504573,0,0,0,504573,0,0,0,504573,0,0,0,504573,0,0,0,504573,0,0,0,504573,0,0,0,504573,0,0,0,504573,0,0,0,37226027,2627,0,0,0,4,0,0,0,0,0,0,0,48,0,0,0,1,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,3,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,2660,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,150,0,0,0,3,0,0,0,0,0,0,0,0,0,0,0,48,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,2229,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,2700,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1048576,0,0,261,131072,131072,0,15559,131072,131072,0,0,131072,131072,0,0,131076,131076,0,6911,131076,131076,0,0,131076,131076,0,829,131080,131080,0,0,131072,131072,0,3013809,131072,131072,0,528887,131072,131072,0,0,131080,131080,0,0,131076,131076,0,288,131080,131080,0,0,131076,131076,0,0,131072,131072,0,3277585,131072,131072,0,0,131072,131072,0,781,131080,131080,0,0,131072,131072,0,3066837,131072,131072,0,3096282,131076,131076,0,0,131076,131076,0,265,131076,131076,0,21680,131072,131072,0,0,131072,131072,0,0,131072,131072,0,0,131076,131076,0,0,131072,131072,0,0,131076,131076,0,0,131072,131072,0,0,131072,131072,0,0,131072,131072,1048576,0,793,0,0,17428731,1117,0,0,17284716,1322,0,0,17445724,47685,0,0,29921838,929,0,0,17455920,1064,0,0,17518588,1063,0,0,18303855,47322,0,0,31454059,818,0,0,17323926,829,0,0,17056076,834,0,0,17098817,1652,0,0,16959703,806,0,0,17406249,1201,0,0,17326616,760,0,0,17855228,855,0,0,18559039,1050,0,0,17044178,1143,0,0,16922295,841,0,0,16850018,1642,0,0,16741102,1685,0,0,17578479,1633,0,0,17420482,1280,0,0,18318722,997,0,0,18520745,1199,0,0,16834770,862,0,0,16884574,1099,0,0,17124185,47719,0,0,29713884,853,0,0,17223977,1465,0,0,17435092,854,0,0,18141738,46992,0,0,31047479,1048576,131072,131120,48,262192,131260,131076,192,262336,131072,131073,1,262145,131072,131072,0,262144,131072,131072,0,262144,131072,131120,48,262192,131072,131072,0,262144,131072,133553,2481,264625,131072,131072,0,262144,131072,131072,0,262144,131119,131073,48,262192,131072,133801,2729,264873,131072,131072,0,262144,131119,131073,48,262192,131072,131073,1,262145,131072,131072,0,262144,131072,131072,0,262144,131213,131075,144,262288,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,133683,2611,264755,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,133748,2676,264820,131072,131123,51,262195,131072,131072,0,262144,131072,131072,0,262144,131072,131097,25,262169,262144,0,262144,262336,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262288,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,0,0,3145728,524288,32505856,372953121,217760756,122686509,484275,0,0,0,1048576,52835112,52629163,1048576,1048576,131072,524288,692,506357,4148,0,96,10818,0,8388944,32505856,4021080,3814404,57115714,11534336,0,0,14155776,67108864,67108864,0,67108864,54475062,54176665,0,1048576,248622,772910,11629,2407,0,498577,8399567,0,4194727,4204840,13631488,0,3670016,1048576,1048576,0,4194304,9437184,0,0,360,33554432,54107828,4194304,0,0,2403,497581,0,10949,8388608,0,4194382,905969664,6291456,0,0,0,524288,524288,0,15310,16608950,0,16777216,4194304,4194304,0,0,0,17482,4194398,4194398,0,214620,0,0,0,33554432,0,0,0,0,639396660,0,2794121063,0,0,0,0,0,477898,0,0,222256,0,0,8388608,336,144,0,0,0,480,8388608,0,0,0,0,372686,0,0,0,10479,0,20940,0,6291456,6289361,96,2238,1829977,0,0,0,0,0,0,0,0,0,3145728,0,0,0,150364,4194304,4189871,144,4289,2097152,524288,1572864,0,0,0,0,0,0,524288,0,4128875,65533,4063247,0,0,8388608,0,42148183,0,1048576,10418,4194344,12619590,610706461,12075824000522671,12075850856374194,12075850856696751,12075824251735288
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,895253,895258,32768,256,0,0,24,24,12480,0x0,0x7f7089035100,0,4096,4096,512,0,512,4096,0,28550,28550,1518947,604052,228,140599,92806,73744,595992,575490,228400,87085,28550,0,28550,0,913600,207441,0,0,0,0,0,62674,4096,0,27807,0,0,0,27807,0,0,0,27807,0,0,0,27807,0,0,0,27807,0,0,0,27807,0,0,0,27807,0,0,0,27807,0,0,0,27807,0,0,0,27807,0,0,0,27807,0,0,0,27807,0,0,0,27807,0,0,0,27807,0,0,0,27807,0,0,0,27807,0,0,0,27807,0,0,0,27807,0,0,0,27807,0,0,0,27807,0,0,0,27807,0,0,0,27807,0,0,0,27807,0,0,0,27807,0,0,0,27807,0,0,0,27807,0,0,0,27807,0,0,0,27807,0,0,0,27807,0,0,0,27807,0,0,0,27807,0,0,0,27807,0,0,0,0,304,0,0,0,256,0,0,0,256,0,0,0,304,0,0,0,257,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,377,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,4096,4096,0,87364,0,0,0,109889,0,0,0,75714,0,0,0,82353,0,0,0,174562,0,0,0,112579,0,0,0,78095,0,0,0,90113,0,0,0,115033,0,0,0,100968,0,0,0,87617,0,0,0,90964,0,0,0,83271,0,0,0,86153,0,0,0,96675,0,0,0,93655,0,0,0,126326,0,0,0,128674,0,0,0,83646,0,0,0,89690,0,0,0,82108,0,0,0,82592,0,0,0,86865,0,0,0,109212,0,0,0,75636,0,0,0,116280,0,0,0,77191,0,0,0,78121,0,0,0,110243,0,0,0,106817,0,0,0,90616,0,0,0,93806,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4096,0,304,304,304,0,256,256,256,0,257,257,257,0,256,256,256,0,256,256,256,0,304,304,304,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,47,257,304,304,0,256,256,256,0,256,256,256,0,256,256,256,188,261,449,449,0,256,256,256,0,256,256,256,0,256,256,256,188,260,448,448,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,47,257,304,304,0,377,377,377,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,304,0,0,256,0,0,0,0,512,512,35328,1156940,1099376,21212,12081,0,0,0,4096,79504,76518,4096,4096,128,512,607,27351,4167,0,48,220,0,8624,36352,220080,69443,974335,26624,0,0,30208,65536,65536,65536,0,0,0,0,0,116,628,11701,2473,0,23459,8844,0,470,8374,1024,0,1024,4096,0,4096,512,512,0,0,360,16384,0,16384,0,0,2427,25004,0,8843,0,0,31,1933312,8192,0,0,0,512,512,0,120,15064,0,16384,16384,0,0,0,0,20673,0,0,0,0,0,0,0,32768,0,0,0,0,12618578,17546113,0,8192,0,0,0,0,697,0,0,0,0,0,1024,432,48,0,0,0,480,0,0,0,0,0,2344,0,0,0,8373,0,342,0,8192,6559,48,1585,1070,0,0,0,0,0,0,0,0,0,2560,0,0,0,50195,512,0,48,464,0,512,0,0,0,0,0,0,0,512,0,0,0,0,0,8192,0,0,430042,0,4096,8421,0,3039311,0,12075824266983356,12075850872330012,12075850872336412,12075824268136940
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,895253,895258,4194304,256,0,0,24,24,12928,0x7f7194bba900,0x7f7089035140,0,524288,524288,65536,0,65536,524288,0,215212,215212,23854427,22696427,31847,12201737,22483026,22454004,22687856,20517208,1721696,1574309,215212,0,215212,0,6886784,6185536,0,0,0,0,0,20295734,524288,0,218140,0,0,0,218140,0,0,0,218140,0,0,0,218140,0,0,0,218140,0,0,0,218140,0,0,0,218140,0,0,0,218140,0,0,0,218140,0,0,0,218140,0,0,0,218140,0,0,0,218140,0,0,0,218140,0,0,0,218140,0,0,0,218140,0,0,0,218140,0,0,0,218140,0,0,0,218140,0,0,0,218140,0,0,0,218140,0,0,0,218140,0,0,0,218140,0,0,0,218140,0,0,0,218140,0,0,0,218140,0,0,0,218140,0,0,0,218140,0,0,0,218140,0,0,0,218140,0,0,0,218140,0,0,0,218140,0,0,0,218140,0,0,0,0,65584,0,11537,0,65536,0,14957,0,65540,0,24556,0,65584,0,27699,0,65537,0,15741,0,65536,0,7339,0,65537,0,10663,0,65536,0,3271,0,65536,0,1809,0,65536,0,4673,0,65536,0,12253,0,65536,0,16325,0,66173,0,51314,0,65536,0,5594,0,65536,0,39017,0,65536,0,20008,0,65921,0,25389,0,65536,0,22222,0,65536,0,5485,0,65536,0,8018,0,65536,0,15567,0,65536,0,10817,0,65537,0,6246,0,65536,0,14333,0,65536,0,5980,0,65536,0,4038,0,65537,0,29446,0,65536,0,5559,0,67280,0,52589,0,65536,0,7082,0,65540,0,7070,0,65536,0,24892,0,524288,524288,0,32434689,0,0,0,33205933,0,0,0,36259596,0,0,0,34563461,0,0,0,36859621,0,0,0,33797325,0,0,0,34243513,0,0,0,33637840,0,0,0,48391286,0,0,0,34695089,0,0,0,34520780,0,0,0,36074107,0,0,0,39523676,0,0,0,39880932,0,0,0,36027477,0,0,0,36959336,0,0,0,37910664,0,0,0,35492226,0,0,0,35710733,0,0,0,41071316,0,0,0,44579532,0,0,0,41057404,0,0,0,34170783,0,0,0,36457037,0,0,0,31064357,0,0,0,42133356,0,0,0,35164279,0,0,0,37993205,0,0,0,29873919,0,0,0,33111845,0,0,0,38619501,0,0,0,36853106,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,524288,0,65584,65584,65584,0,65536,65536,65536,188,65541,65729,65729,0,65536,65536,65536,0,65536,65536,65536,0,65584,65584,65584,0,65536,65536,65536,0,68299,68299,68299,0,65536,65536,65536,0,65536,65536,65536,47,65537,65584,65584,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65537,65537,65537,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,67325,67325,67325,0,65536,65536,65536,0,65536,65536,65536,188,65540,65728,65728,0,65657,65657,65657,65536,0,0,65536,0,0,65728,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65728,0,0,65536,0,0,0,0,65536,65536,4128768,131007930,50172948,76575142,201960,0,0,0,524288,22100060,22089513,524288,524288,16384,65536,764,218862,4088,0,48,3390,0,2097536,4259840,1737664,1567378,23196896,3014656,0,0,3473408,8388608,8388608,8388608,0,0,0,0,0,192113,214697,11396,2461,0,213296,2100282,0,423,2099859,131072,0,131072,524288,0,524288,65536,65536,0,0,360,2097152,0,2097152,31187,0,2592,221158,0,2100916,0,0,31,222298112,917504,0,0,0,65536,65536,0,7609,2015881,0,2097152,2097152,0,560099,561761,0,23994,0,0,0,0,0,0,0,4194304,0,0,0,0,1080419695,1861205017,0,2097152,0,0,0,0,194912,0,0,0,0,0,131072,384,48,0,0,0,432,0,0,0,0,0,4606,0,0,0,2099825,0,5328,0,917504,914910,48,7299,180289,0,0,0,0,0,0,0,0,0,327680,0,0,741383,794577,65536,64048,48,1440,0,65536,0,0,0,0,0,0,0,65536,0,0,0,1966098,0,2097152,0,0,16760349,0,524288,2100114,0,1178887945,0,12075824268777019,12075850872414332,12075850872546010,12075824270231743
diff --git a/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/prev_analysis/1.csv
index 37ffc37168..aa603ead7a 100644
--- a/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,6053876.0,6053876.0,6053876.0,9.171369627431458
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4526687.0,4526687.0,4526687.0,6.857741992847033
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 256u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,3050538.0,3050538.0,3050538.0,4.621437829338676
diff --git a/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/prev_analysis/1001.csv
index ca08330db0..0e3bf5267e 100644
--- a/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,46.862275449101794,Instr per wave
 SMEM,1.8083832335329342,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/prev_analysis/101.csv
index 4fae49c7fd..6b850c1e9a 100644
--- a/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx908
 mi100
 48
 1228.8
-SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/prev_analysis/1202.csv
index 3813619fd8..608e9efc09 100644
--- a/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,33581.08602818472,2845.4065017700195,548021.3848266602,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/prev_analysis/1901.csv
index e9eb959650..3319fd069f 100644
--- a/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,2.0,smem_
 VALU,735.0,valu_
 MFMA,,mfma_
 VMEM,8.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,22.0,br_
 VGPR,24.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,67894.0,wavefronts_
 Workgroups,16973.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,163.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,0.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,44.0,hbm_rd_
 HBM Wr,0.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,70.0,vl1_coales_
 VL1 Stall,32.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,36.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/prev_analysis/2001.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/prev_analysis/201.csv
index 4a31776055..ac6605e980 100644
--- a/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,59.85363036764793,Pct,100,59.85363036764793
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,63.968148082767584,Threads,64,99.95023137932435
 IPC - Issue,0.8437290696679524,Instr/cycle,5,16.874581393359048
-LDS BW,0.0,Gb/sec,23070.72,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,23070.72,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99339467262325,Pct,100,99.99339467262325
 Instr Cache BW,1409.5775738846125,Gb/s,4614.144,30.549059021231514
 Scalar L1D Cache Hit Rate,99.3562044853132,Pct,100,99.3562044853132
diff --git a/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/prev_analysis/602.csv
index 0bb3053c7d..d501c28188 100644
--- a/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,48193.4131736527,0,698263,Simd
 Insufficient SIMD VGPRs,587027.1976047904,0,32079513,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/prev_analysis/701.csv
index d3f1bff5a3..1071413faa 100644
--- a/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,23.976047904191617,8,36,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/sysinfo.csv
index dabec6d658..62cc8278aa 100644
--- a/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-dispatches,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 11:23:17 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+dispatches,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 11:23:17 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/timestamps.csv
index 722e3d081c..bcb8a020ca 100644
--- a/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dispatches/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,896557,896562,33554432,256,0,0,8,32,6464,0x0,0x7f1e26a04180,12075850856331131,12075850856374194,12075850856696751,12075850856805743
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,896557,896562,32768,256,0,0,24,24,12480,0x0,0x7f1e26a35100,12075850872219850,12075850872330012,12075850872336412,12075850872341927
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,896557,896562,4194304,256,0,0,24,24,12928,0x7f1f56b4e900,0x7f1e26a35140,12075850872399754,12075850872414332,12075850872546010,12075850872549482
diff --git a/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/SQ_IFETCH_LEVEL.csv
index 9f2b180f51..d8fe9832ad 100644
--- a/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/SQ_IFETCH_LEVEL.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,194110,194110,33554432,256,0,0,4,32,4160,0x0,0x7fa3acc04280,383677,383677,524288,4718592,681645,76348444,17124839786112,17124128738495,17124987332578,17124987421057
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,194110,194110,32768,256,0,0,12,24,13888,0x0,0x7fa3acc23f80,33756,33756,512,8192,7229,810064,17124992545544,17124987332578,17124992678653,17124992683360
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,194110,194110,4194304,256,0,0,12,24,14336,0x7fa3afc74380,0x7fa3acc23fc0,163849,163849,65536,917504,142064,15925184,17124992722299,17124992678653,17124993055292,17124993058100
diff --git a/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/SQ_INST_LEVEL_LDS.csv
index 89520e5143..418c1d6525 100644
--- a/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/SQ_INST_LEVEL_LDS.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,195958,195958,33554432,256,0,0,4,32,4160,0x0,0x7f11ad604280,0,0,0,17144144393286,17143436477077,17144292173346,17144292290115
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,195958,195958,32768,256,0,0,12,24,13888,0x0,0x7f11ad623f80,0,0,0,17144297420544,17144292173346,17144297545660,17144297550290
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,195958,195958,4194304,256,0,0,12,24,14336,0x7f11b0705380,0x7f11ad623fc0,0,0,0,17144297585079,17144297545660,17144297907260,17144297909620
diff --git a/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/SQ_INST_LEVEL_SMEM.csv
index 470f012df6..20b657539d 100644
--- a/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/SQ_INST_LEVEL_SMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,193888,193888,33554432,256,0,0,4,32,4160,0x0,0x7f43faa04280,3670016,2910634,325909344,17123900714749,17118295798240,17124048883445,17124048997014
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,193888,193888,32768,256,0,0,12,24,13888,0x0,0x7f43faa23f80,512,96458,10808448,17124054175070,17124048883445,17124054303441,17124054308356
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,193888,193888,4194304,256,0,0,12,24,14336,0x7f43fdac3380,0x7f43faa23fc0,65536,674434,75500344,17124054342565,17124054303441,17124054671921,17124054674336
diff --git a/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/SQ_INST_LEVEL_VMEM.csv
index aa4327352e..39975cf285 100644
--- a/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/SQ_INST_LEVEL_VMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,195736,195736,33554432,256,0,0,4,32,4160,0x0,0x7f56c0404280,524288,5431869,608368756,17143202999529,17140899655928,17143355998885,17143356090154
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,195736,195736,32768,256,0,0,12,24,13888,0x0,0x7f56c0423f80,4096,50189,5627580,17143361212472,17143355998885,17143361344800,17143361349528
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,195736,195736,4194304,256,0,0,12,24,14336,0x7f56cec93380,0x7f56c0423fc0,524288,10921699,1223251140,17143361384817,17143361344800,17143361705760,17143361708228
diff --git a/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/SQ_LEVEL_WAVES.csv
index b34e3721f4..4c193f716a 100644
--- a/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/SQ_LEVEL_WAVES.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,194332,194332,33554432,256,0,0,4,32,4160,0x0,0x7fc390804280,381340,381340,8834,3050728,524288,239605293,2963625,0,974680612,17125775589873,17125068730776,17125923761092,17125923874631
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,194332,194332,32768,256,0,0,12,24,13888,0x0,0x7fc390823f80,33330,33330,29863,266648,512,1782276,165375,0,7142768,17125929027678,17125923761092,17125929167969,17125929172374
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,194332,194332,4194304,256,0,0,12,24,14336,0x7fc3937bf380,0x7fc390823fc0,164235,164235,13939,1313888,65536,80435930,1212523,0,323471456,17125929215982,17125929167969,17125929561249,17125929563653
diff --git a/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/pmc_perf.csv
index fd2e54e884..4a8b654927 100644
--- a/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDI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],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBufferAligned.kd,0,0,0,195098,195098,33554432,256,0,0,4,32,4160,0x0,0x7f9b1ac04280,3079128,2993967,524288,38870306,242679603,392,224,0,384890,384890,39163324.0,38181094.0,10.0,4140001.0,31288781.0,30923143.0,38154683.0,37593519.0,3077417,3000369,384890,0,384890,0,12316480.0,9486796.0,0.0,0.0,0,0,616,0,4718592,4714848,112,3632,374698,0.0,0.0,0.0,524288.0,28480224.0,27753351.0,7639.0,524288.0,131072,524288,302,383807,2329,0,56.0,303.0,0.0,4194696.0,0,0,0,0,0,7340032,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,20018145.0,524288.0,0,382527,0,0,0,382527,0,0,0,382527,0,0,0,382527,0,0,0,382527,0,0,0,382527,0,0,0,382527,0,0,0,382527,0,0,0,382527,0,0,0,382527,0,0,0,382527,0,0,0,382527,0,0,0,382527,0,0,0,382527,0,0,0,382527,0,0,0,382527,0,0,0,382527,0,0,0,382527,0,0,0,382527,0,0,0,382527,0,0,0,382527,0,0,0,382527,0,0,0,382527,0,0,0,382527,0,0,0,382527,0,0,0,382527,0,0,0,382527,0,0,0,382527,0,0,0,382527,0,0,0,382527,0,0,0,382527,0,0,0,382527,0,0,0,0,0,0.0,20682483.0,0,0,0,0,0,0,0,0,34,0,0,0,112,0,0,0,2,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,0,0,1,0,0,0,0,0,0,0,56,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,32,0,0,0,0,0,0,0,4,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,0,0,1,0,0,0,1,0,0,0,524288.0,0.0,0,43963,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,331,129024,129024,0,169,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,43690,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,28875,129024,129024,0,214,129024,129024,0,269,129024,129024,0,0,129024,129024,0,289071,129024,129024,0,0,129024,129024,0,0,129024,129024,0,212849,129024,129024,0,158,129024,129024,0,45697,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,186,129024,129024,524288.0,0.0,44898,0,0,51254336,46361,0,0,51582836,43389,0,0,50508534,47484,0,0,52440746,45878,0,0,51902995,46088,0,0,51826069,45630,0,0,51609813,49083,0,0,53910318,45678,0,0,51499913,47013,0,0,51852410,45506,0,0,50925630,48092,0,0,52712402,46414,0,0,52218641,48068,0,0,52577720,47474,0,0,52151988,49699,0,0,53787493,44497,0,0,51270566,46946,0,0,51553665,44877,0,0,50881793,48517,0,0,52844563,43857,0,0,51761653,46816,0,0,52423145,46380,0,0,51739139,48936,0,0,53531721,45875,0,0,51486886,45873,0,0,51424578,45073,0,0,50992493,49454,0,0,53163127,47661,0,0,52582914,47542,0,0,52451370,47638,0,0,52561459,50482,0,0,54046829,0.0,65536,65568,32,131104,65536,65536,0,131072,65536,65537,1,131073,65536,65536,0,131072,65646,65538,112,131184,65536,65536,0,131072,65536,65537,1,131073,65536,65536,0,131072,65536,65536,0,131072,65536,65680,144,131216,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65570,34,131106,65536,65536,0,131072,65536,65592,56,131128,65536,65536,0,131072,65758,65538,224,131296,65536,65538,2,131074,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65568,32,131104,65591,65537,56,131128,65536,65536,0,131072,65536,65536,0,131072,65591,65537,56,131128,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131184,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131296,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131128,0,131072,1149886,0,524288,3670016,3663254,224,6538,1048576,33554432.0,33554432.0,0.0,33554432.0,30295928.0,28658405.0,0.0,524288.0,220714,536717,8675,931,0,384524,4195053.0,0.0,2097594.0,2097459.0,1048576,1048576,0,524288,0,524288,7340032,0,0.0,0.0,104.0,8388608.0,29597683.0,2097152.0,0.0,205117,0,1218,383837,0,751.0,4194304.0,0.0,2064387.0,25690112,9437184,0,0,0,0,0,0,13263.0,8242715.0,0.0,8388608.0,2097152.0,4194304.0,11216840,0,0,8876,4128768.0,4128768.0,0.0,1575829.0,0,0,0,0,0,0,5767168,1048576,318812230.0,0.0,1482100351.0,0.0,37.0,0.0,0,0,376154,0.0,0.0,1532253.0,0.0,3670016,524288,0,0,0,2621440,524288,178847041,4194304.0,0.0,0.0,0.0,0.0,1158886.0,0,0,0.0,313.0,0.0,610.0,43473336,24117248,0,0,9437184,11010048,0,3145728,0.0,0.0,0.0,0.0,0.0,0.0,0,1572864,0.0,0.0,0.0,199669.0,524288,524288,0,3670016,7340032,603979776,4718592,0,0.0,0.0,0.0,0.0,0.0,0.0,524288,0,2064384.0,0.0,2031624.0,0.0,0,0,524288,0,0,0,0,33554432,0.0,4194304.0,0.0,18904249.0,0.0,0.0,141.0,4128768.0,981777.0,1696488483.0,17127214210777,17144954560091,17144954799771,17127358007101
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,195098,195098,32768,256,0,0,12,24,13888,0x0,0x7f9b1ac23f80,262304,157935,512,1358267,1648235,504,56,0,32787,32787,2284152.0,152406.0,183.0,0.0,35932.0,32995.0,146132.0,127354.0,262296,164680,32787,0,32787,0,1049184.0,360603.0,0.0,0.0,0,0,560,0,8192,6242,56,1894,23795,0.0,0.0,0.0,4096.0,30044.0,28512.0,0.0,4096.0,128,512,302,32957,2256,0,0.0,60.0,0.0,4600.0,0,0,0,0,0,1024,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,13239.0,4096.0,0,33746,0,0,0,33746,0,0,0,33746,0,0,0,33746,0,0,0,33746,0,0,0,33746,0,0,0,33746,0,0,0,33746,0,0,0,33746,0,0,0,33746,0,0,0,33746,0,0,0,33746,0,0,0,33746,0,0,0,33746,0,0,0,33746,0,0,0,33746,0,0,0,33746,0,0,0,33746,0,0,0,33746,0,0,0,33746,0,0,0,33746,0,0,0,33746,0,0,0,33746,0,0,0,33746,0,0,0,33746,0,0,0,33746,0,0,0,33746,0,0,0,33746,0,0,0,33746,0,0,0,33746,0,0,0,33746,0,0,0,33746,0,0,0,0,0,0.0,0.0,256,0,0,0,256,0,0,0,257,0,0,0,312,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,258,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,4096.0,4096.0,0,78211,0,0,0,80122,0,0,0,79694,0,0,0,82026,0,0,0,85625,0,0,0,81016,0,0,0,90040,0,0,0,93448,0,0,0,78249,0,0,0,89809,0,0,0,72922,0,0,0,81305,0,0,0,78932,0,0,0,102152,0,0,0,82917,0,0,0,85483,0,0,0,75474,0,0,0,82306,0,0,0,73713,0,0,0,109829,0,0,0,78446,0,0,0,80197,0,0,0,81155,0,0,0,109770,0,0,0,92261,0,0,0,664129,0,0,0,78370,0,0,0,79640,0,0,0,77840,0,0,0,79125,0,0,0,79992,0,0,0,86134,0,0,0.0,0.0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4096.0,0,128,128,128,0,128,128,128,0,129,129,129,0,128,128,128,0,128,128,128,222,130,352,352,0,129,129,129,0,128,128,128,0,128,128,128,0,184,184,184,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,222,130,352,352,0,128,128,128,0,128,128,128,0,128,128,128,0,129,129,129,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,55,131,186,186,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,352,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,352,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,184,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,688,0,0,512,0,56,456,0,65536.0,65536.0,65536.0,0.0,0.0,0.0,0.0,0.0,4,516,11398,1052,0,30923,4661.0,0.0,499.0,4162.0,512,0,0,0,4096,4096,512,0,0.0,0.0,104.0,16384.0,0.0,16384.0,4096.0,0,0,1353,31824,0,4661.0,0.0,0.0,31.0,35328,26112,0,0,0,0,0,0,104.0,15240.0,0.0,16384.0,16384.0,0.0,0,0,0,30073,0.0,0.0,0.0,0.0,0,0,0,0,0,0,10752,3584,3902506.0,5157956.0,0.0,8192.0,0.0,0.0,0,0,497,0.0,0.0,0.0,0.0,512,4096,0,0,0,512,512,1627976,0.0,0.0,0.0,0.0,0.0,1385.0,0,0,0.0,8261.0,0.0,120.0,18174,32256,0,0,26112,1024,0,1024,0.0,0.0,0.0,0.0,0.0,0.0,0,1024,0.0,0.0,0.0,52400.0,4096,0,4096,512,512,1671168,8192,0,0.0,0.0,0.0,0.0,0.0,0.0,512,0,0.0,0.0,0.0,0.0,0,0,512,0,0,0,0,32768,8192.0,0.0,0.0,118255.0,0.0,4096.0,8206.0,0.0,3342443.0,0.0,17127364271077,17144959674163,17144959687443,17127364745554
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,195098,195098,4194304,256,0,0,12,24,14336,0x7f9b1dcc2380,0x7f9b1ac23fc0,1314744,1213285,65536,15694812,76986348,392,56,0,164342,164342,16003780.0,14576305.0,24409.0,582217.0,13437929.0,13150378.0,14570004.0,12433931.0,1314736,1220152,164342,0,164342,0,5258944.0,4720089.0,0.0,0.0,0,0,448,0,917504,912549,0,4955,157300,0.0,0.0,0.0,524288.0,14634857.0,14630490.0,2242.0,524288.0,16384,65536,302,168631,2308,0,0.0,165.0,0.0,1048968.0,0,0,0,0,0,131072,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,10821932.0,524288.0,0,170630,0,0,0,170630,0,0,0,170630,0,0,0,170630,0,0,0,170630,0,0,0,170630,0,0,0,170630,0,0,0,170630,0,0,0,170630,0,0,0,170630,0,0,0,170630,0,0,0,170630,0,0,0,170630,0,0,0,170630,0,0,0,170630,0,0,0,170630,0,0,0,170630,0,0,0,170630,0,0,0,170630,0,0,0,170630,0,0,0,170630,0,0,0,170630,0,0,0,170630,0,0,0,170630,0,0,0,170630,0,0,0,170630,0,0,0,170630,0,0,0,170630,0,0,0,170630,0,0,0,170630,0,0,0,170630,0,0,0,170630,0,0,0,0,0,0.0,0.0,65536,0,18899,0,65537,0,14513,0,65588,0,17962,0,65592,0,13653,0,65536,0,29422,0,65536,0,17478,0,65536,0,16919,0,65536,0,16038,0,65536,0,12289,0,65536,0,12966,0,65536,0,17086,0,65588,0,17444,0,65538,0,17644,0,65536,0,15591,0,65536,0,18313,0,65536,0,17931,0,65536,0,15796,0,65536,0,15328,0,65536,0,14705,0,65536,0,18197,0,65536,0,15288,0,65537,0,16712,0,65536,0,35718,0,65540,0,20736,0,65540,0,17219,0,65536,0,15046,0,65536,0,15135,0,65537,0,17889,0,65536,0,12903,0,65536,0,12823,0,65537,0,16702,0,65536,0,19236,0,524288.0,524288.0,0,43528255,0,0,0,43857365,0,0,0,44618651,0,0,0,46587606,0,0,0,44474733,0,0,0,46906453,0,0,0,45867302,0,0,0,46173659,0,0,0,43991633,0,0,0,44354857,0,0,0,44000630,0,0,0,46450381,0,0,0,44913629,0,0,0,44616925,0,0,0,43785334,0,0,0,44541741,0,0,0,44817902,0,0,0,44780801,0,0,0,42849408,0,0,0,44943943,0,0,0,44249041,0,0,0,45854028,0,0,0,44673171,0,0,0,42101464,0,0,0,42935478,0,0,0,46962239,0,0,0,41245041,0,0,0,44978937,0,0,0,47126861,0,0,0,46066010,0,0,0,45870645,0,0,0,45669685,0,0,0.0,0.0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,524288.0,0,32768,32768,32768,0,32768,32768,32768,0,32769,32769,32769,0,32769,32769,32769,0,32768,32768,32768,0,32768,32768,32768,0,32769,32769,32769,0,32768,32768,32768,0,32768,32768,32768,0,32824,32824,32824,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32830,32830,32830,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,166,32772,32938,32938,222,32770,32992,32992,0,32768,32768,32768,0,32768,32768,32768,0,32828,32828,32828,0,32768,32768,32768,0,32768,32768,32768,0,32769,32769,32769,0,32768,32768,32768,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32936,0,0,32992,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,909847,0,0,65536,63800,56,1680,0,8388608.0,8388608.0,8388608.0,0.0,0.0,0.0,0.0,0.0,168243,178881,10198,2572,0,162464,1049152.0,0.0,388.0,1048764.0,65536,0,0,0,524288,524288,131072,0,0.0,0.0,104.0,2097152.0,0.0,2097152.0,524288.0,45512,0,2411,162277,0,1049149.0,0.0,0.0,31.0,4063232,2883584,0,0,0,0,0,0,6588.0,2027969.0,0.0,2097152.0,2097152.0,0.0,1223700,0,0,14465,0.0,0.0,0.0,0.0,262144,0,0,0,0,0,1507328,458752,998364483.0,2347043814.0,0.0,2097152.0,89.0,0.0,0,0,147698,0.0,0.0,0.0,0.0,65536,524288,0,0,0,65536,65536,48098217,0.0,0.0,0.0,0.0,0.0,19574.0,0,0,0.0,2097345.0,0.0,372.0,26422020,3735552,0,0,2883584,196608,0,131072,0.0,0.0,0.0,0.0,0.0,0.0,0,131072,0.0,0.0,425028.0,1351742.0,524288,0,524288,65536,131072,184549376,917504,0,0.0,0.0,0.0,0.0,0.0,0.0,65536,0,0.0,0.0,983047.0,0.0,0,0,65536,0,0,0,0,4194304,2097152.0,0.0,0.0,12327420.0,0.0,524288.0,2097288.0,0.0,1461619668.0,0.0,17127365842363,17144959760403,17144959853043,17127366601162
diff --git a/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/prev_analysis/1.csv
index 8d08831e18..89d5b4e484 100644
--- a/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,3357916.0,3357916.0,3357916.0,7.842647975878232
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,1724957.0,1724957.0,1724957.0,4.028757873790466
 "void benchmark_func<double, 256, 8u, 512u>(double, double*) [clone .kd]",1,1715198.0,1715198.0,1715198.0,4.005965045858917
diff --git a/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/prev_analysis/1001.csv
index f475f954a6..fb5988001a 100644
--- a/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,494.8622754491018,Instr per wave
 VMEM,7.958083832335329,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,0.0,Instr per wave
 SALU,24.520958083832337,Instr per wave
 SMEM,1.8023952095808384,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/prev_analysis/101.csv
index 8d04ad6ce3..82de310ca5 100644
--- a/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx90a
 mi200
 56
 1638.4
-roofline|SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+roofline|SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/prev_analysis/1202.csv
index 3883e6c846..5d1f43c387 100644
--- a/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,18253.75476087924,1851.498435974121,258022.82287597656,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/prev_analysis/1901.csv
index b41ca960b3..e11000c121 100644
--- a/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,2.0,smem_
 VALU,495.0,valu_
 MFMA,0.0,mfma_
 VMEM,8.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,10.0,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,67894.0,wavefronts_
 Workgroups,16973.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,128.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,0.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,44.0,hbm_rd_
 HBM Wr,0.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,70.0,vl1_coales_
 VL1 Stall,2.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,26.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/prev_analysis/201.csv
index f9b1b4fc29..7296fdc7fd 100644
--- a/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,58.329734106900794,Pct,100,58.329734106900794
 MFMA Util,0.0,Pct,100,0.0
 VALU Active Threads/Wave,64.0,Threads,64,100.0
 IPC - Issue,1.0,Instr/cycle,5,20.0
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99263485878119,Pct,100,99.99263485878119
 Instr Cache BW,1673.039635793147,Gb/s,6092.8,27.45929024082765
 Scalar L1D Cache Hit Rate,99.34855886004414,Pct,100,99.34855886004414
diff --git a/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/prev_analysis/602.csv
index 56cbd78391..3a6b42ab6a 100644
--- a/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,12214659.970059881,0,357851581,Simd
 Insufficient SIMD VGPRs,0.0,0,0,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/prev_analysis/701.csv
index 12250d77c0..db0925a109 100644
--- a/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/sysinfo.csv
index 5e6b909e97..843d18edad 100644
--- a/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-dispatches,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:38:44 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,roofline|SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+dispatches,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:38:44 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,roofline|SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/timestamps.csv
index c975fcc681..8a2ab63030 100644
--- a/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/dispatches/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,196041,196041,33554432,256,0,0,4,32,4160,0x0,0x7f3782804280,17144954536400,17144954560091,17144954799771,17144954888700
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,196041,196041,32768,256,0,0,12,24,13888,0x0,0x7f3782823f80,17144959659018,17144959674163,17144959687443,17144959705747
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,196041,196041,4194304,256,0,0,12,24,14336,0x7f37857eb380,0x7f3782823fc0,17144959710157,17144959760403,17144959853043,17144959855213
diff --git a/projects/rocprofiler-compute/tests/workloads/invdev/mi100/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/invdev/mi100/SQ_IFETCH_LEVEL.csv
index 51232f61b6..901ece13b8 100644
--- a/projects/rocprofiler-compute/tests/workloads/invdev/mi100/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/invdev/mi100/SQ_IFETCH_LEVEL.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,935069,935074,33554432,256,0,0,8,32,6464,0x0,0x7fb1e8e04180,504417,504417,524288,6291456,791548,101536232,12076606776836515,12076607020949616,12076607021273775,12076607021386317
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,935069,935074,32768,256,0,0,24,24,12480,0x0,0x7fb1e8e35100,27457,27457,512,8192,8659,1112808,12076607036018836,12076607036328752,12076607036334672,12076607036343359
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,935069,935074,4194304,256,0,0,24,24,12928,0x7fb2f49b3900,0x7fb1e8e35140,221451,221451,65536,917504,137700,17627108,12076607036410164,12076607036634350,12076607036769870,12076607036773860
diff --git a/projects/rocprofiler-compute/tests/workloads/invdev/mi100/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/invdev/mi100/SQ_INST_LEVEL_LDS.csv
index a5c50f9d7d..43bd832c27 100644
--- a/projects/rocprofiler-compute/tests/workloads/invdev/mi100/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/invdev/mi100/SQ_INST_LEVEL_LDS.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,936874,936879,33554432,256,0,0,8,32,6464,0x0,0x7f608a404180,0,0,0,12076632988700397,12076633233142956,12076633233467755,12076633233577518
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,936874,936879,32768,256,0,0,24,24,12480,0x0,0x7f608a435100,0,0,0,12076633248282761,12076633248580944,12076633248587504,12076633248592868
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,936874,936879,4194304,256,0,0,24,24,12928,0x7f61960b3900,0x7f608a435140,0,0,0,12076633248655084,12076633248875663,12076633249007503,12076633249011156
diff --git a/projects/rocprofiler-compute/tests/workloads/invdev/mi100/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/invdev/mi100/SQ_INST_LEVEL_SMEM.csv
index 7e41ce4fe3..899559f5f6 100644
--- a/projects/rocprofiler-compute/tests/workloads/invdev/mi100/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/invdev/mi100/SQ_INST_LEVEL_SMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,936496,936501,33554432,256,0,0,8,32,6464,0x0,0x7f17e8404180,4194304,3122666,398904176,12076630480743351,12076630718390515,12076630718714354,12076630718822006
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,936496,936501,32768,256,0,0,24,24,12480,0x0,0x7f17e8435100,512,21524,2754256,12076630733442442,12076630733749898,12076630733756458,12076630733761836
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,936496,936501,4194304,256,0,0,24,24,12928,0x7f18f4030900,0x7f17e8435140,65536,146806,18775720,12076630733826656,12076630734045577,12076630734179017,12076630734183330
diff --git a/projects/rocprofiler-compute/tests/workloads/invdev/mi100/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/invdev/mi100/SQ_INST_LEVEL_VMEM.csv
index 1e122b6899..1ed2ab2a19 100644
--- a/projects/rocprofiler-compute/tests/workloads/invdev/mi100/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/invdev/mi100/SQ_INST_LEVEL_VMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,936686,936691,33554432,256,0,0,8,32,6464,0x0,0x7fa3b8c04180,1048576,11096456,1419911252,12076631726864889,12076631974434106,12076631974755065,12076631974864438
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,936686,936691,32768,256,0,0,24,24,12480,0x0,0x7fa3b8c35100,4096,107784,13788356,12076631989518086,12076631989806097,12076631989812497,12076631989817693
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,936686,936691,4194304,256,0,0,24,24,12928,0x7fa4c491a900,0x7fa3b8c35140,524288,10667896,1365491840,12076631989877063,12076631990100976,12076631990238896,12076631990242964
diff --git a/projects/rocprofiler-compute/tests/workloads/invdev/mi100/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/invdev/mi100/SQ_LEVEL_WAVES.csv
index 81491d7959..e14b7313a0 100644
--- a/projects/rocprofiler-compute/tests/workloads/invdev/mi100/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/invdev/mi100/SQ_LEVEL_WAVES.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,937062,937067,33554432,256,0,0,8,32,6464,0x0,0x7f30a5604180,499674,499674,16219,3997400,524288,371768834,3801967,0,1501859028,12076634246773666,12076634492293789,12076634492615709,12076634492722711
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,937062,937067,32768,256,0,0,24,24,12480,0x0,0x7f30a5635100,27467,27467,20214,219744,512,1126759,75366,0,4521000,12076634507281913,12076634507609674,12076634507615914,12076634507624380
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,937062,937067,4194304,256,0,0,24,24,12928,0x7f31b1191900,0x7f30a5635140,217853,217853,21633,1742832,65536,133671007,1576099,0,536498696,12076634507695903,12076634507934314,12076634508067113,12076634508071402
diff --git a/projects/rocprofiler-compute/tests/workloads/invdev/mi100/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/invdev/mi100/pmc_dispatch_info.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/invdev/mi100/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/invdev/mi100/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/invdev/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/invdev/mi100/pmc_perf.csv
index 227bde2f3d..e4889d1423 100644
--- a/projects/rocprofiler-compute/tests/workloads/invdev/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/invdev/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBuffer.kd,0,0,0,935812,935817,33554432,256,0,0,8,32,6464,0x0,0x7f8b11a04180,1048576,0,1048576,9437184,0,4194304,1048576,0,505326,505326,57961202,55652703,176,12449149,54835463,54733125,55615976,54433702,4042608,3849624,505326,0,505326,0,16170432,15331698,0,0,0,0,0,17411526,1048576,0,503249,0,0,0,503249,0,0,0,503249,0,0,0,503249,0,0,0,503249,0,0,0,503249,0,0,0,503249,0,0,0,503249,0,0,0,503249,0,0,0,503249,0,0,0,503249,0,0,0,503249,0,0,0,503249,0,0,0,503249,0,0,0,503249,0,0,0,503249,0,0,0,503249,0,0,0,503249,0,0,0,503249,0,0,0,503249,0,0,0,503249,0,0,0,503249,0,0,0,503249,0,0,0,503249,0,0,0,503249,0,0,0,503249,0,0,0,503249,0,0,0,503249,0,0,0,503249,0,0,0,503249,0,0,0,503249,0,0,0,503249,0,0,0,37363225,0,0,0,0,4,0,0,0,0,0,0,0,204,0,0,0,0,0,0,0,0,0,0,0,2,0,0,0,2735,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,2235,0,0,0,0,0,0,0,0,0,0,0,3,0,0,0,0,0,0,0,0,0,0,0,4,0,0,0,48,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,48,0,0,0,0,0,0,0,0,0,0,0,48,0,0,0,0,0,0,0,2674,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2615,0,0,0,1048576,0,0,0,131080,131080,0,1470,131072,131072,0,263,131072,131072,0,3201342,131074,131074,0,0,131076,131076,0,0,131076,131076,0,359,131076,131076,0,0,131076,131076,0,3088451,131076,131076,0,0,131072,131072,0,0,131072,131072,0,0,131072,131072,0,578988,131072,131072,0,1553,131076,131076,0,0,131072,131072,0,3106186,131072,131072,0,0,131072,131072,0,29397,131072,131072,0,0,131076,131076,0,3267723,131072,131072,0,5412,131080,131080,0,746,131080,131080,0,19788,131072,131072,0,0,131072,131072,0,0,131072,131072,0,0,131072,131072,0,0,131072,131072,0,0,131072,131072,0,262,131076,131076,0,0,131072,131072,0,0,131072,131072,0,0,131076,131076,1048576,0,868,0,0,17401652,902,0,0,17422274,900,0,0,17319650,46113,0,0,29914658,812,0,0,17666830,847,0,0,17499726,1147,0,0,18220566,45684,0,0,30594996,1095,0,0,17350802,1110,0,0,17355810,765,0,0,17166194,815,0,0,16701572,1348,0,0,17353820,1170,0,0,17414156,807,0,0,18251642,1443,0,0,18503825,1771,0,0,16995802,2183,0,0,17085587,904,0,0,17228326,45693,0,0,29433691,1165,0,0,17608847,1700,0,0,17696590,1545,0,0,18340596,1653,0,0,18574435,1101,0,0,16917258,1144,0,0,17082083,784,0,0,17252188,961,0,0,16760716,1171,0,0,17519827,1750,0,0,17555718,1060,0,0,18298687,50736,0,0,31878763,1048576,131072,131072,0,262144,131260,131124,240,262384,131072,131072,0,262144,131072,133602,2530,264674,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,133544,2472,264616,131072,131120,48,262192,131072,131073,1,262145,131072,131072,0,262144,131072,131073,1,262145,131072,131072,0,262144,131072,131072,0,262144,131072,133756,2684,264828,131072,131072,0,262144,131213,131124,193,262337,131072,131076,4,262148,131072,133814,2742,264886,131072,131089,17,262161,131119,131073,48,262192,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131119,131073,48,262192,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,262144,0,262144,262336,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262288,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,0,0,3145728,524288,32505856,374953434,220549976,121897602,478261,0,0,0,1048576,52715049,52515213,1048576,1048576,131072,524288,698,499834,4259,0,96,10474,0,8388944,32505856,4002832,3799993,56808188,11534336,0,0,14155776,67108864,67108864,0,67108864,54162660,53827423,0,1048576,238615,762903,11685,2337,0,494144,8399660,0,4194727,4204933,13631488,0,3670016,1048576,1048576,0,4194304,9437184,0,0,360,33554432,54301946,4194304,0,0,2829,501417,0,11116,8388608,0,4194389,905969664,6291456,0,0,0,524288,524288,0,15343,16608607,0,16777216,4194304,4194304,0,0,0,15343,4194348,4194348,0,220518,0,0,0,33554432,0,0,0,0,625712251,0,2740215351,0,0,0,0,0,472777,0,0,223334,0,0,8388608,336,144,0,0,0,480,8388608,0,0,0,0,326900,0,0,0,10879,0,21740,0,6291456,6289317,96,2718,1992052,0,0,0,0,0,0,0,0,0,3145728,0,0,0,143305,4194304,4189847,144,4313,2097152,524288,1572864,0,0,0,0,0,0,524288,0,4128823,65529,4063253,0,0,8388608,0,42288983,0,1048576,10935,4194345,13157291,615624907,12076608893352653,12076635381273678,12076635381598795,12076609140120491
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,935812,935817,32768,256,0,0,24,24,12480,0x0,0x7f8b11a35100,0,4096,4096,512,0,512,4096,0,27831,27831,1441622,577751,225,120226,48916,28273,569576,548982,222648,81931,27831,0,27831,0,890592,193420,0,0,0,0,0,63814,4096,0,27462,0,0,0,27462,0,0,0,27462,0,0,0,27462,0,0,0,27462,0,0,0,27462,0,0,0,27462,0,0,0,27462,0,0,0,27462,0,0,0,27462,0,0,0,27462,0,0,0,27462,0,0,0,27462,0,0,0,27462,0,0,0,27462,0,0,0,27462,0,0,0,27462,0,0,0,27462,0,0,0,27462,0,0,0,27462,0,0,0,27462,0,0,0,27462,0,0,0,27462,0,0,0,27462,0,0,0,27462,0,0,0,27462,0,0,0,27462,0,0,0,27462,0,0,0,27462,0,0,0,27462,0,0,0,27462,0,0,0,27462,0,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,377,0,0,0,256,0,0,0,256,0,0,0,258,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,304,0,0,0,256,0,0,0,256,0,0,0,304,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,4096,4096,0,114575,0,0,0,83537,0,0,0,94602,0,0,0,85949,0,0,0,106623,0,0,0,88107,0,0,0,123357,0,0,0,99078,0,0,0,84608,0,0,0,78101,0,0,0,92947,0,0,0,81772,0,0,0,87574,0,0,0,85844,0,0,0,67486,0,0,0,80868,0,0,0,93112,0,0,0,113842,0,0,0,69072,0,0,0,91047,0,0,0,179471,0,0,0,84332,0,0,0,109691,0,0,0,101096,0,0,0,120122,0,0,0,138001,0,0,0,85335,0,0,0,72992,0,0,0,86890,0,0,0,85193,0,0,0,98562,0,0,0,91754,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4096,0,256,256,256,0,304,304,304,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,257,257,257,0,256,256,256,0,257,257,257,0,256,256,256,188,260,448,448,0,256,256,256,0,256,256,256,0,305,305,305,188,260,448,448,0,256,256,256,0,376,376,376,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,47,257,304,304,0,256,256,256,0,256,256,256,0,256,256,256,47,257,304,304,0,256,256,256,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,304,0,0,256,0,0,0,0,512,512,35328,1065264,1015507,13405,11187,0,0,0,4096,34344,32236,4096,4096,128,512,607,27004,4313,0,48,171,0,8624,36352,225752,75900,1055045,26624,0,0,30208,65536,65536,65536,0,0,0,0,0,116,628,11772,2357,0,23893,8844,0,470,8374,1024,0,1024,4096,0,4096,512,512,0,0,360,16384,0,16384,0,0,2811,24495,0,8892,0,0,31,1933312,8192,0,0,0,512,512,0,120,15064,0,16384,16384,0,0,0,0,20170,0,0,0,0,0,0,0,32768,0,0,0,0,12504908,17489377,0,8192,0,0,0,0,696,0,0,0,0,0,1024,432,48,0,0,0,480,0,0,0,0,0,2928,0,0,0,8422,0,440,0,8192,6206,48,1938,1112,0,0,0,0,0,0,0,0,0,2560,0,0,0,51412,512,0,48,464,0,512,0,0,0,0,0,0,0,512,0,0,0,0,0,8192,0,0,438226,0,4096,8372,0,3205733,0,12076609155306990,12076635396887551,12076635396894271,12076609156292082
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,935812,935817,4194304,256,0,0,24,24,12928,0x7f8c1d579900,0x7f8b11a35140,0,524288,524288,65536,0,65536,524288,0,214007,214007,23718287,22473681,32643,12584277,22028262,21957008,22461488,20295440,1712056,1565233,214007,0,214007,0,6848224,6134376,0,0,0,0,0,21125188,524288,0,229308,0,0,0,229308,0,0,0,229308,0,0,0,229308,0,0,0,229308,0,0,0,229308,0,0,0,229308,0,0,0,229308,0,0,0,229308,0,0,0,229308,0,0,0,229308,0,0,0,229308,0,0,0,229308,0,0,0,229308,0,0,0,229308,0,0,0,229308,0,0,0,229308,0,0,0,229308,0,0,0,229308,0,0,0,229308,0,0,0,229308,0,0,0,229308,0,0,0,229308,0,0,0,229308,0,0,0,229308,0,0,0,229308,0,0,0,229308,0,0,0,229308,0,0,0,229308,0,0,0,229308,0,0,0,229308,0,0,0,229308,0,0,0,0,65536,0,7608,0,65536,0,9271,0,65540,0,4658,0,65981,0,22068,0,65536,0,16520,0,65536,0,24792,0,65538,0,6794,0,67493,0,47046,0,65536,0,182,0,65536,0,0,0,65537,0,7688,0,65536,0,8665,0,65536,0,10260,0,65536,0,6051,0,65536,0,5410,0,65536,0,22796,0,65536,0,17115,0,65536,0,10204,0,65536,0,1819,0,65536,0,10737,0,65536,0,14772,0,65536,0,4176,0,65584,0,451,0,65536,0,14974,0,65536,0,17133,0,65584,0,10097,0,65536,0,12232,0,65537,0,3575,0,65536,0,7992,0,65536,0,23873,0,65540,0,11577,0,66623,0,55344,0,524288,524288,0,39593917,0,0,0,38258245,0,0,0,41551906,0,0,0,38371716,0,0,0,36791077,0,0,0,35807730,0,0,0,38550195,0,0,0,35241590,0,0,0,43308364,0,0,0,43683875,0,0,0,44762478,0,0,0,45712142,0,0,0,33186474,0,0,0,32776621,0,0,0,34619001,0,0,0,47723164,0,0,0,42988559,0,0,0,40037921,0,0,0,48069689,0,0,0,42434150,0,0,0,43809223,0,0,0,38501593,0,0,0,38904410,0,0,0,39824012,0,0,0,41519521,0,0,0,42390488,0,0,0,33313363,0,0,0,39911447,0,0,0,39141172,0,0,0,46566289,0,0,0,34943428,0,0,0,39409783,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,524288,0,65536,65536,65536,0,65584,65584,65584,188,65540,65728,65728,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,66024,66024,66024,0,65536,65536,65536,0,65537,65537,65537,0,65536,65536,65536,0,65537,65537,65537,0,65536,65536,65536,0,65536,65536,65536,0,67866,67866,67866,0,65536,65536,65536,0,65585,65585,65585,0,65536,65536,65536,0,65536,65536,65536,0,65656,65656,65656,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,47,65537,65584,65584,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,188,65540,65728,65728,0,65536,65536,65536,65536,0,0,65536,0,0,65728,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65728,0,0,65536,0,0,0,0,65536,65536,4128768,126662311,51046312,71356159,199144,0,0,0,524288,21540479,21526077,524288,524288,16384,65536,788,216248,4068,0,48,2772,0,2097536,4259840,1829160,1648848,24360564,3014656,0,0,3473408,8388608,8388608,8388608,0,0,0,0,0,159584,192706,12357,2462,0,224387,2102668,0,423,2102245,131072,0,131072,524288,0,524288,65536,65536,0,0,360,2097152,0,2097152,46248,0,2762,216167,0,2100904,0,0,31,222298112,917504,0,0,0,65536,65536,0,7562,2016931,0,2097152,2097152,0,552088,553796,0,23259,0,0,0,0,0,0,0,4194304,0,0,0,0,1256275581,2318623009,0,2097152,0,0,0,0,182685,0,0,0,0,0,131072,384,48,0,0,0,432,0,0,0,0,0,14722,0,0,0,2100326,0,6330,0,917504,914829,66,5171,237454,0,0,0,0,0,0,0,0,0,327680,0,0,726488,779860,65536,64048,48,1440,0,65536,0,0,0,0,0,0,0,65536,0,0,0,1966107,0,2097152,0,0,13897721,0,524288,2102551,0,792996133,0,12076609156922605,12076635396958910,12076635397089629,12076609158202726
diff --git a/projects/rocprofiler-compute/tests/workloads/invdev/mi100/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/invdev/mi100/prev_analysis/1.csv
index 8a9ec969b8..06f73bba28 100644
--- a/projects/rocprofiler-compute/tests/workloads/invdev/mi100/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/invdev/mi100/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,6059957.0,6059957.0,6059957.0,9.169486064060209
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4525889.0,4525889.0,4525889.0,6.848245971544582
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 256u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,3056459.0,3056459.0,3056459.0,4.624811398145466
diff --git a/projects/rocprofiler-compute/tests/workloads/invdev/mi100/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/invdev/mi100/prev_analysis/1001.csv
index ca08330db0..0e3bf5267e 100644
--- a/projects/rocprofiler-compute/tests/workloads/invdev/mi100/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/invdev/mi100/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,46.862275449101794,Instr per wave
 SMEM,1.8083832335329342,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/invdev/mi100/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/invdev/mi100/prev_analysis/101.csv
index 3124e17d61..8560699452 100644
--- a/projects/rocprofiler-compute/tests/workloads/invdev/mi100/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/invdev/mi100/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx908
 mi100
 48
 1228.8
-SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/invdev/mi100/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/invdev/mi100/prev_analysis/1202.csv
index 66641b57c6..7057775cb1 100644
--- a/projects/rocprofiler-compute/tests/workloads/invdev/mi100/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/invdev/mi100/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,33617.72709436474,2860.667678833008,547916.0441894531,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/invdev/mi100/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/invdev/mi100/prev_analysis/1901.csv
index 4cdd3d5a21..c0e7fd031b 100644
--- a/projects/rocprofiler-compute/tests/workloads/invdev/mi100/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/invdev/mi100/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,2.0,smem_
 VALU,735.0,valu_
 MFMA,,mfma_
 VMEM,8.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,22.0,br_
 VGPR,24.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,67894.0,wavefronts_
 Workgroups,16973.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,163.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,0.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,44.0,hbm_rd_
 HBM Wr,0.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,70.0,vl1_coales_
 VL1 Stall,31.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,34.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/invdev/mi100/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/invdev/mi100/prev_analysis/2001.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/invdev/mi100/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/invdev/mi100/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/invdev/mi100/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/invdev/mi100/prev_analysis/201.csv
index cfc1bcc094..297c8718c1 100644
--- a/projects/rocprofiler-compute/tests/workloads/invdev/mi100/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/invdev/mi100/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,59.71163511528944,Pct,100,59.71163511528944
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,63.967840400497316,Threads,64,99.94975062577706
 IPC - Issue,0.8437262750969097,Instr/cycle,5,16.874525501938194
-LDS BW,0.0,Gb/sec,23070.72,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,23070.72,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99318745374036,Pct,100,99.99318745374036
 Instr Cache BW,1406.6059705869952,Gb/s,4614.144,30.484656971845595
 Scalar L1D Cache Hit Rate,99.35620448519533,Pct,100,99.35620448519533
diff --git a/projects/rocprofiler-compute/tests/workloads/invdev/mi100/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/invdev/mi100/prev_analysis/602.csv
index 1ccefe5036..2ea4322f3d 100644
--- a/projects/rocprofiler-compute/tests/workloads/invdev/mi100/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/invdev/mi100/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,64892.16766467066,0,774244,Simd
 Insufficient SIMD VGPRs,527589.6886227545,0,30743007,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/invdev/mi100/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/invdev/mi100/prev_analysis/701.csv
index d3f1bff5a3..1071413faa 100644
--- a/projects/rocprofiler-compute/tests/workloads/invdev/mi100/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/invdev/mi100/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,23.976047904191617,8,36,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/invdev/mi100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/invdev/mi100/sysinfo.csv
index bf2f99f27f..71b96173a3 100644
--- a/projects/rocprofiler-compute/tests/workloads/invdev/mi100/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/invdev/mi100/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-invdev,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 11:36:21 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+invdev,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 11:36:21 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/invdev/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/invdev/mi100/timestamps.csv
index e075b88af8..65f9bec342 100644
--- a/projects/rocprofiler-compute/tests/workloads/invdev/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/invdev/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,937113,937118,33554432,256,0,0,8,32,6464,0x0,0x7f12eac04180,12076635381227990,12076635381273678,12076635381598795,12076635381689318
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,937113,937118,32768,256,0,0,24,24,12480,0x0,0x7f12eac35100,12076635396787522,12076635396887551,12076635396894271,12076635396915901
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,937113,937118,4194304,256,0,0,24,24,12928,0x7f141aca3900,0x7f12eac35140,12076635396946107,12076635396958910,12076635397089629,12076635397093471
diff --git a/projects/rocprofiler-compute/tests/workloads/invdev/mi200/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/invdev/mi200/SQ_IFETCH_LEVEL.csv
index d344066790..db046c2349 100644
--- a/projects/rocprofiler-compute/tests/workloads/invdev/mi200/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/invdev/mi200/SQ_IFETCH_LEVEL.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,236503,236503,33554432,256,0,0,4,32,4160,0x0,0x7fe83c204280,385832,385832,524288,4718592,682094,76386864,17833173257611,17832460487290,17833324063793,17833324177862
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,236503,236503,32768,256,0,0,12,24,13888,0x0,0x7fe83c223f80,34124,34124,512,8192,5540,624020,17833329373303,17833324063793,17833329503317,17833329508120
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,236503,236503,4194304,256,0,0,12,24,14336,0x7fe83f16b380,0x7fe83c223fc0,166451,166451,65536,917504,140662,15737800,17833329547519,17833329503317,17833329887317,17833329890091
diff --git a/projects/rocprofiler-compute/tests/workloads/invdev/mi200/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/invdev/mi200/SQ_INST_LEVEL_LDS.csv
index b2f20963c9..4d5553569d 100644
--- a/projects/rocprofiler-compute/tests/workloads/invdev/mi200/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/invdev/mi200/SQ_INST_LEVEL_LDS.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,238351,238351,33554432,256,0,0,4,32,4160,0x0,0x7ff888c04280,0,0,0,17852547584485,17851838027568,17852691164011,17852691281181
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,238351,238351,32768,256,0,0,12,24,13888,0x0,0x7ff888c23f80,0,0,0,17852696444493,17852691164011,17852696572335,17852696576630
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,238351,238351,4194304,256,0,0,12,24,14336,0x7ff88bbf2380,0x7ff888c23fc0,0,0,0,17852696612159,17852696572335,17852696936336,17852696938901
diff --git a/projects/rocprofiler-compute/tests/workloads/invdev/mi200/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/invdev/mi200/SQ_INST_LEVEL_SMEM.csv
index 2c1b55db84..28da9ccd40 100644
--- a/projects/rocprofiler-compute/tests/workloads/invdev/mi200/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/invdev/mi200/SQ_INST_LEVEL_SMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,236281,236281,33554432,256,0,0,4,32,4160,0x0,0x7f45e2204280,3670016,2905706,325081704,17832236843728,17803198665120,17832381629870,17832381744199
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,236281,236281,32768,256,0,0,12,24,13888,0x0,0x7f45e2223f80,512,96664,10851288,17832386900391,17832381629870,17832387026519,17832387030968
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,236281,236281,4194304,256,0,0,12,24,14336,0x7f45e517a380,0x7f45e2223fc0,65536,639926,71704992,17832387064037,17832387026519,17832387402360,17832387404639
diff --git a/projects/rocprofiler-compute/tests/workloads/invdev/mi200/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/invdev/mi200/SQ_INST_LEVEL_VMEM.csv
index 1a340ec40b..15181ff373 100644
--- a/projects/rocprofiler-compute/tests/workloads/invdev/mi200/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/invdev/mi200/SQ_INST_LEVEL_VMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,238129,238129,33554432,256,0,0,4,32,4160,0x0,0x7fe2c7e04280,524288,5497472,615656480,17851610507915,17849318958956,17851757718801,17851757807931
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,238129,238129,32768,256,0,0,12,24,13888,0x0,0x7fe2c7e23f80,4096,55920,6257708,17851762985423,17851757718801,17851763112570,17851763117229
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,238129,238129,4194304,256,0,0,12,24,14336,0x7fe2d67ec380,0x7fe2c7e23fc0,524288,10960198,1227561992,17851763151509,17851763112570,17851763483290,17851763485710
diff --git a/projects/rocprofiler-compute/tests/workloads/invdev/mi200/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/invdev/mi200/SQ_LEVEL_WAVES.csv
index 713a9ac828..60df14be90 100644
--- a/projects/rocprofiler-compute/tests/workloads/invdev/mi200/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/invdev/mi200/SQ_LEVEL_WAVES.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,236725,236725,33554432,256,0,0,4,32,4160,0x0,0x7fc8d4204280,388118,388118,8813,3104952,524288,245379700,3015215,0,997822932,17834114824366,17833406340767,17834261594719,17834261709089
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,236725,236725,32768,256,0,0,12,24,13888,0x0,0x7fc8d4223f80,34226,34226,30380,273816,512,1732870,162674,0,6944808,17834266862991,17834261594719,17834267004326,17834267009117
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,236725,236725,4194304,256,0,0,12,24,14336,0x7fc8d71bf380,0x7fc8d4223fc0,166068,166068,13553,1328552,65536,78338107,1221027,0,315083700,17834267052826,17834267004326,17834267413606,17834267416207
diff --git a/projects/rocprofiler-compute/tests/workloads/invdev/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/invdev/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/invdev/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/invdev/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/invdev/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/invdev/mi200/pmc_perf.csv
index b9fb10bc7d..b7b8ff0ed4 100644
--- a/projects/rocprofiler-compute/tests/workloads/invdev/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/invdev/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDI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],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBufferAligned.kd,0,0,0,237491,237491,33554432,256,0,0,4,32,4160,0x0,0x7fa969004280,3111728,3025066,524288,39304593,248286756,392,224,0,388965,388965,39568807.0,38551470.0,14.0,4271837.0,31776277.0,31426026.0,38533194.0,37974658.0,3110017,3031467,388965,0,388965,0,12446880.0,9535974.0,0.0,0.0,0,0,616,0,4718592,4714928,112,3552,381978,0.0,0.0,0.0,524288.0,29140688.0,28466525.0,7707.0,524288.0,131072,524288,302,391168,2291,0,56.0,301.0,0.0,4194696.0,0,0,0,0,0,7340032,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,20891445.0,524288.0,0,390464,0,0,0,390464,0,0,0,390464,0,0,0,390464,0,0,0,390464,0,0,0,390464,0,0,0,390464,0,0,0,390464,0,0,0,390464,0,0,0,390464,0,0,0,390464,0,0,0,390464,0,0,0,390464,0,0,0,390464,0,0,0,390464,0,0,0,390464,0,0,0,390464,0,0,0,390464,0,0,0,390464,0,0,0,390464,0,0,0,390464,0,0,0,390464,0,0,0,390464,0,0,0,390464,0,0,0,390464,0,0,0,390464,0,0,0,390464,0,0,0,390464,0,0,0,390464,0,0,0,390464,0,0,0,390464,0,0,0,390464,0,0,0,0,0,0.0,21925558.0,0,0,0,0,0,0,0,0,0,0,0,0,35,0,0,0,2,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,0,0,1,0,0,0,0,0,0,0,56,0,0,0,112,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,35,0,0,0,4,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,33,0,0,0,1,0,0,0,524288.0,0.0,0,0,129024,129024,0,853,129024,129024,0,0,129024,129024,0,44199,129024,129024,0,327,129024,129024,0,0,129024,129024,0,0,129024,129024,0,273887,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,44531,129024,129024,0,535021,129024,129024,0,321,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,32473,129024,129024,0,853,129024,129024,0,184,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,44803,129024,129024,0,184,129024,129024,524288.0,0.0,45726,0,0,51914240,46385,0,0,51843095,46787,0,0,51964141,48942,0,0,53443788,46574,0,0,52474289,47587,0,0,52795748,46067,0,0,52072282,49885,0,0,54334333,46748,0,0,52505182,47975,0,0,52462841,46096,0,0,51647951,50105,0,0,53789328,47899,0,0,53275350,48303,0,0,52950032,47819,0,0,52594447,50156,0,0,54468606,45273,0,0,51880132,46265,0,0,51922669,45087,0,0,51436459,48783,0,0,53286568,46138,0,0,52482593,46654,0,0,52494537,45568,0,0,51904800,49072,0,0,53929596,45817,0,0,52123122,47571,0,0,52401287,45713,0,0,51495801,50463,0,0,54112470,47123,0,0,52862378,49273,0,0,53277870,47129,0,0,52388550,50062,0,0,54263712,0.0,65536,65536,0,131072,65536,65536,0,131072,65536,65537,1,131073,65536,65569,33,131105,65646,65538,112,131184,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65648,112,131184,65536,65569,33,131105,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65537,1,131073,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65570,34,131106,65758,65538,224,131296,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65591,65537,56,131128,65536,65536,0,131072,65536,65536,0,131072,65536,65592,56,131128,65536,65568,32,131104,65591,65537,56,131128,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131184,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131296,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131128,0,131072,1061331,0,524288,3670016,3663373,224,6419,1048576,33554432.0,33554432.0,0.0,33554432.0,30442431.0,28855071.0,0.0,524288.0,219720,536381,8608,920,0,384082,4195054.0,0.0,2097594.0,2097460.0,1048576,1048576,0,524288,0,524288,7340032,0,0.0,0.0,104.0,8388608.0,30157941.0,2097152.0,0.0,214148,0,1179,388628,0,755.0,4194304.0,0.0,2064387.0,25690112,9437184,0,0,0,0,0,0,13278.0,8242550.0,0.0,8388608.0,2097152.0,4194304.0,10103855,0,0,8834,4128768.0,4128768.0,0.0,1523237.0,0,0,0,0,0,0,5767168,1048576,319921967.0,0.0,1487564705.0,0.0,26.0,0.0,0,0,377331,0.0,0.0,1545252.0,0.0,3670016,524288,0,0,0,2621440,524288,179793053,4194304.0,0.0,0.0,0.0,0.0,1150809.0,0,0,0.0,311.0,0.0,606.0,43594744,24117248,0,0,9437184,11010048,0,3145728,0.0,0.0,0.0,0.0,0.0,0.0,0,1572864,0.0,0.0,0.0,192151.0,524288,524288,0,3670016,7340032,603979776,4718592,0,0.0,0.0,0.0,0.0,0.0,0.0,524288,0,2064384.0,0.0,2031623.0,0.0,0,0,524288,0,0,0,0,33554432,0.0,4194304.0,0.0,18969454.0,0.0,0.0,142.0,4128768.0,643577.0,1700035725.0,17835548493773,17853365250419,17853365490099,17835696624165
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,237491,237491,32768,256,0,0,12,24,13888,0x0,0x7fa969023f80,265176,165559,512,1393761,1722624,504,56,0,33146,33146,2383303.0,160757.0,198.0,0.0,32952.0,29662.0,154484.0,135677.0,265168,172482,33146,0,33146,0,1060672.0,403736.0,0.0,0.0,0,0,560,0,8192,6194,56,1942,24013,0.0,0.0,0.0,4096.0,34040.0,32614.0,0.0,4096.0,128,512,302,33374,2292,0,0.0,60.0,0.0,4600.0,0,0,0,0,0,1024,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,16909.0,4096.0,0,34213,0,0,0,34213,0,0,0,34213,0,0,0,34213,0,0,0,34213,0,0,0,34213,0,0,0,34213,0,0,0,34213,0,0,0,34213,0,0,0,34213,0,0,0,34213,0,0,0,34213,0,0,0,34213,0,0,0,34213,0,0,0,34213,0,0,0,34213,0,0,0,34213,0,0,0,34213,0,0,0,34213,0,0,0,34213,0,0,0,34213,0,0,0,34213,0,0,0,34213,0,0,0,34213,0,0,0,34213,0,0,0,34213,0,0,0,34213,0,0,0,34213,0,0,0,34213,0,0,0,34213,0,0,0,34213,0,0,0,34213,0,0,0,0,0,0.0,0.0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,260,0,0,0,256,0,0,0,312,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,258,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,4096.0,4096.0,0,79475,0,0,0,76314,0,0,0,118056,0,0,0,90569,0,0,0,80650,0,0,0,81201,0,0,0,90735,0,0,0,120386,0,0,0,86313,0,0,0,74484,0,0,0,72113,0,0,0,89069,0,0,0,83746,0,0,0,662037,0,0,0,97703,0,0,0,88385,0,0,0,85807,0,0,0,77175,0,0,0,78105,0,0,0,82902,0,0,0,81605,0,0,0,87055,0,0,0,82288,0,0,0,84714,0,0,0,81334,0,0,0,84580,0,0,0,76264,0,0,0,80216,0,0,0,77338,0,0,0,101966,0,0,0,86447,0,0,0,83820,0,0,0.0,0.0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4096.0,0,128,128,128,0,128,128,128,0,128,128,128,0,129,129,129,0,128,128,128,222,130,352,352,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,184,184,184,0,128,128,128,0,128,128,128,222,130,352,352,0,128,128,128,0,128,128,128,0,129,129,129,0,128,128,128,0,128,128,128,0,128,128,128,0,129,129,129,0,128,128,128,55,129,184,184,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,352,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,352,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,184,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,644,0,0,512,0,56,456,0,65536.0,65536.0,65536.0,0.0,0.0,0.0,0.0,0.0,6,518,11553,1002,0,31729,4661.0,0.0,499.0,4162.0,512,0,0,0,4096,4096,512,0,0.0,0.0,104.0,16384.0,0.0,16384.0,4096.0,0,0,1311,31626,0,4661.0,0.0,0.0,31.0,35328,26112,0,0,0,0,0,0,104.0,15240.0,0.0,16384.0,16384.0,0.0,0,0,0,29595,0.0,0.0,0.0,0.0,0,0,0,0,0,0,10752,3584,4236802.0,5926312.0,0.0,8192.0,0.0,0.0,0,0,499,0.0,0.0,0.0,0.0,512,4096,0,0,0,512,512,1633462,0.0,0.0,0.0,0.0,0.0,1470.0,0,0,0.0,8260.0,0.0,118.0,12307,32256,0,0,26112,1024,0,1024,0.0,0.0,0.0,0.0,0.0,0.0,0,1024,0.0,0.0,0.0,39026.0,4096,0,4096,512,512,1671168,8192,0,0.0,0.0,0.0,0.0,0.0,0.0,512,0,0.0,0.0,0.0,0.0,0,0,512,0,0,0,0,32768,8192.0,0.0,0.0,109838.0,0.0,4096.0,8206.0,0.0,3294406.0,0.0,17835702937098,17853370276021,17853370289461,17835703421426
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,237491,237491,4194304,256,0,0,12,24,14336,0x7fa96bfcf380,0x7fa969023fc0,1313184,1207845,65536,15620178,74728213,392,56,0,164147,164147,15932956.0,14460790.0,25134.0,394139.0,13216891.0,12949400.0,14454354.0,12316789.0,1313176,1214608,164147,0,164147,0,5252704.0,4735367.0,0.0,0.0,0,0,448,0,917504,913931,0,3573,153044,0.0,0.0,0.0,524288.0,13255008.0,13229881.0,2170.0,524288.0,16384,65536,302,164077,2316,0,0.0,180.0,0.0,1048968.0,0,0,0,0,0,131072,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,9409547.0,524288.0,0,175752,0,0,0,175752,0,0,0,175752,0,0,0,175752,0,0,0,175752,0,0,0,175752,0,0,0,175752,0,0,0,175752,0,0,0,175752,0,0,0,175752,0,0,0,175752,0,0,0,175752,0,0,0,175752,0,0,0,175752,0,0,0,175752,0,0,0,175752,0,0,0,175752,0,0,0,175752,0,0,0,175752,0,0,0,175752,0,0,0,175752,0,0,0,175752,0,0,0,175752,0,0,0,175752,0,0,0,175752,0,0,0,175752,0,0,0,175752,0,0,0,175752,0,0,0,175752,0,0,0,175752,0,0,0,175752,0,0,0,175752,0,0,0,0,0,0.0,0.0,65536,0,6078,0,65538,0,24547,0,65537,0,18222,0,65538,0,39503,0,65536,0,14745,0,65536,0,22386,0,65536,0,17485,0,65536,0,25991,0,65536,0,14521,0,65536,0,12701,0,65537,0,9619,0,65536,0,11395,0,65536,0,6514,0,65538,0,18492,0,65536,0,15260,0,65536,0,24575,0,65648,0,18520,0,65538,0,18776,0,65536,0,14539,0,65536,0,14578,0,65536,0,35108,0,65592,0,12607,0,65537,0,5626,0,65539,0,7610,0,65540,0,16374,0,65537,0,20166,0,65536,0,14720,0,65536,0,12485,0,65536,0,9837,0,65536,0,22278,0,65605,0,15443,0,65536,0,34616,0,524288.0,524288.0,0,46200953,0,0,0,45245664,0,0,0,47051490,0,0,0,45671057,0,0,0,47041745,0,0,0,46486491,0,0,0,47000800,0,0,0,47576583,0,0,0,43398506,0,0,0,38596146,0,0,0,39881214,0,0,0,45906827,0,0,0,40946405,0,0,0,47340720,0,0,0,47069604,0,0,0,46899324,0,0,0,46352326,0,0,0,45033212,0,0,0,44534401,0,0,0,40371234,0,0,0,45132866,0,0,0,41977892,0,0,0,42098611,0,0,0,41209554,0,0,0,37909280,0,0,0,43224933,0,0,0,38898205,0,0,0,41568845,0,0,0,47380063,0,0,0,48208274,0,0,0,43636394,0,0,0,46856361,0,0,0.0,0.0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,524288.0,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32769,32769,32769,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32769,32769,32769,0,32824,32824,32824,0,32770,32770,32770,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32769,32769,32769,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32827,32827,32827,0,32768,32768,32768,166,32770,32936,32936,222,32770,32992,32992,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32832,32832,32832,0,32768,32768,32768,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32936,0,0,32992,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,897213,0,0,65536,63800,56,1680,0,8388608.0,8388608.0,8388608.0,0.0,0.0,0.0,0.0,0.0,123661,146121,10232,2531,0,163247,1049151.0,0.0,388.0,1048763.0,65536,0,0,0,524288,524288,131072,0,0.0,0.0,104.0,2097152.0,0.0,2097152.0,524288.0,43548,0,2793,161389,0,1049157.0,0.0,0.0,31.0,4063232,2883584,0,0,0,0,0,0,6585.0,2028322.0,0.0,2097152.0,2097152.0,0.0,1599524,0,0,13808,0.0,0.0,0.0,0.0,262144,0,0,0,0,0,1507328,458752,1011636249.0,2258138828.0,0.0,2097152.0,59.0,0.0,0,0,148771,0.0,0.0,0.0,0.0,65536,524288,0,0,0,65536,65536,48854627,0.0,0.0,0.0,0.0,0.0,14658.0,0,0,0.0,2097339.0,0.0,360.0,22557113,3735552,0,0,2883584,196608,0,131072,0.0,0.0,0.0,0.0,0.0,0.0,0,131072,0.0,0.0,391888.0,1139441.0,524288,0,524288,65536,131072,184549376,917504,0,0.0,0.0,0.0,0.0,0.0,0.0,65536,0,0.0,0.0,983046.0,0.0,0,0,65536,0,0,0,0,4194304,2097152.0,0.0,0.0,12415791.0,0.0,524288.0,2097284.0,0.0,1404552892.0,0.0,17835704516019,17853370360501,17853370452981,17835705292960
diff --git a/projects/rocprofiler-compute/tests/workloads/invdev/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/invdev/mi200/prev_analysis/1.csv
index 824d54e025..1ff9b9a4db 100644
--- a/projects/rocprofiler-compute/tests/workloads/invdev/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/invdev/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,3357122.0,3357122.0,3357122.0,7.840630919671416
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,1724001.0,1724001.0,1724001.0,4.026441560999106
 "void benchmark_func<double, 256, 8u, 512u>(double, double*) [clone .kd]",1,1714881.0,1714881.0,1714881.0,4.005141604075466
diff --git a/projects/rocprofiler-compute/tests/workloads/invdev/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/invdev/mi200/prev_analysis/1001.csv
index f475f954a6..fb5988001a 100644
--- a/projects/rocprofiler-compute/tests/workloads/invdev/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/invdev/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,494.8622754491018,Instr per wave
 VMEM,7.958083832335329,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,0.0,Instr per wave
 SALU,24.520958083832337,Instr per wave
 SMEM,1.8023952095808384,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/invdev/mi200/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/invdev/mi200/prev_analysis/101.csv
index 0371af8313..4f025c3871 100644
--- a/projects/rocprofiler-compute/tests/workloads/invdev/mi200/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/invdev/mi200/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx90a
 mi200
 56
 1638.4
-roofline|SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+roofline|SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/invdev/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/invdev/mi200/prev_analysis/1202.csv
index 5c60dd777b..fd46c0d971 100644
--- a/projects/rocprofiler-compute/tests/workloads/invdev/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/invdev/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,18296.269474052384,1894.2776184082031,258229.23516845703,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/invdev/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/invdev/mi200/prev_analysis/1901.csv
index f43fd536be..165d445079 100644
--- a/projects/rocprofiler-compute/tests/workloads/invdev/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/invdev/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,2.0,smem_
 VALU,495.0,valu_
 MFMA,0.0,mfma_
 VMEM,8.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,10.0,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,67894.0,wavefronts_
 Workgroups,16973.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,128.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,0.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,44.0,hbm_rd_
 HBM Wr,0.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,70.0,vl1_coales_
 VL1 Stall,2.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,25.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/invdev/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/invdev/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/invdev/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/invdev/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/invdev/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/invdev/mi200/prev_analysis/201.csv
index 7ce0414bc6..acc18e7e3f 100644
--- a/projects/rocprofiler-compute/tests/workloads/invdev/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/invdev/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,58.3677767471036,Pct,100,58.3677767471036
 MFMA Util,0.0,Pct,100,0.0
 VALU Active Threads/Wave,64.0,Threads,64,100.0
 IPC - Issue,1.0,Instr/cycle,5,20.0
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99259859947313,Pct,100,99.99259859947313
 Instr Cache BW,1671.978257589768,Gb/s,6092.8,27.441870036596768
 Scalar L1D Cache Hit Rate,99.3485588612334,Pct,100,99.3485588612334
diff --git a/projects/rocprofiler-compute/tests/workloads/invdev/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/invdev/mi200/prev_analysis/602.csv
index b82ca1c5ae..549fa7b3d6 100644
--- a/projects/rocprofiler-compute/tests/workloads/invdev/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/invdev/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,12526180.185628742,0,370304750,Simd
 Insufficient SIMD VGPRs,0.0,0,0,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/invdev/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/invdev/mi200/prev_analysis/701.csv
index 12250d77c0..db0925a109 100644
--- a/projects/rocprofiler-compute/tests/workloads/invdev/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/invdev/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/invdev/mi200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/invdev/mi200/sysinfo.csv
index 212a686c83..559f81f4cd 100644
--- a/projects/rocprofiler-compute/tests/workloads/invdev/mi200/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/invdev/mi200/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-invdev,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:50:32 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,roofline|SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+invdev,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:50:32 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,roofline|SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/invdev/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/invdev/mi200/timestamps.csv
index e636074625..9838b1ee13 100644
--- a/projects/rocprofiler-compute/tests/workloads/invdev/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/invdev/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,238434,238434,33554432,256,0,0,4,32,4160,0x0,0x7fd647c04280,17853365225848,17853365250419,17853365490099,17853365576439
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,238434,238434,32768,256,0,0,12,24,13888,0x0,0x7fd647c23f80,17853370260633,17853370276021,17853370289461,17853370306822
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,238434,238434,4194304,256,0,0,12,24,14336,0x7fd66e582380,0x7fd647c23fc0,17853370311482,17853370360501,17853370452981,17853370455238
diff --git a/projects/rocprofiler-compute/tests/workloads/kernels/mi100/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/kernels/mi100/SQ_IFETCH_LEVEL.csv
index bdb40e79a9..6cd21df7e2 100644
--- a/projects/rocprofiler-compute/tests/workloads/kernels/mi100/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/kernels/mi100/SQ_IFETCH_LEVEL.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,889519,889524,33554432,256,0,0,8,32,6464,0x0,0x7fade3204180,505329,505329,524288,6291456,792877,101561476,12075726469398590,12075726714802415,12075726715127053,12075726715240096
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,889519,889524,32768,256,0,0,24,24,12480,0x0,0x7fade3235100,28706,28706,512,8192,9185,1175988,12075726729418195,12075726729733214,12075726729739934,12075726729747417
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,889519,889524,4194304,256,0,0,24,24,12928,0x7faf1355c900,0x7fade3235140,213227,213227,65536,917504,139653,17875436,12075726729813149,12075726730045212,12075726730174971,12075726730179210
diff --git a/projects/rocprofiler-compute/tests/workloads/kernels/mi100/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/kernels/mi100/SQ_INST_LEVEL_LDS.csv
index 73c53ddd95..3d5806a80d 100644
--- a/projects/rocprofiler-compute/tests/workloads/kernels/mi100/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/kernels/mi100/SQ_INST_LEVEL_LDS.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,891318,891323,33554432,256,0,0,8,32,6464,0x0,0x7fc0d7a04180,0,0,0,12075752974042678,12075753221733652,12075753222060211,12075753222176363
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,891318,891323,32768,256,0,0,24,24,12480,0x0,0x7fc0d7a35100,0,0,0,12075753236901319,12075753237218745,12075753237225305,12075753237239437
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,891318,891323,4194304,256,0,0,24,24,12928,0x7fc207c54900,0x7fc0d7a35140,0,0,0,12075753237289390,12075753237550103,12075753237689623,12075753237693862
diff --git a/projects/rocprofiler-compute/tests/workloads/kernels/mi100/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/kernels/mi100/SQ_INST_LEVEL_SMEM.csv
index d70f0eeabb..2ce6ee2d81 100644
--- a/projects/rocprofiler-compute/tests/workloads/kernels/mi100/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/kernels/mi100/SQ_INST_LEVEL_SMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,890939,890944,33554432,256,0,0,8,32,6464,0x0,0x7f8564a04180,4194304,3065390,392527368,12075750428536136,12075750672999908,12075750673325666,12075750673439498
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,890939,890944,32768,256,0,0,24,24,12480,0x0,0x7f8564a35100,512,19888,2551816,12075750688487414,12075750688799270,12075750688805350,12075750688810875
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,890939,890944,4194304,256,0,0,24,24,12928,0x7f86705c7900,0x7f8564a35140,65536,164124,20967296,12075750688875716,12075750689167108,12075750689305348,12075750689309763
diff --git a/projects/rocprofiler-compute/tests/workloads/kernels/mi100/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/kernels/mi100/SQ_INST_LEVEL_VMEM.csv
index 3a9baba5f2..a8819e414a 100644
--- a/projects/rocprofiler-compute/tests/workloads/kernels/mi100/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/kernels/mi100/SQ_INST_LEVEL_VMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,891129,891134,33554432,256,0,0,8,32,6464,0x0,0x7f6bf5a04180,1048576,11211256,1434098376,12075751698989828,12075751948059256,12075751948385175,12075751948497607
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,891129,891134,32768,256,0,0,24,24,12480,0x0,0x7f6bf5a35100,4096,110042,14095848,12075751963395575,12075751963698309,12075751963704549,12075751963709468
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,891129,891134,4194304,256,0,0,24,24,12928,0x7f6d01626900,0x7f6bf5a35140,524288,12978555,1661180292,12075751963773006,12075751963993988,12075751964122787,12075751964126553
diff --git a/projects/rocprofiler-compute/tests/workloads/kernels/mi100/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/kernels/mi100/SQ_LEVEL_WAVES.csv
index 8f08110418..6e508767e5 100644
--- a/projects/rocprofiler-compute/tests/workloads/kernels/mi100/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/kernels/mi100/SQ_LEVEL_WAVES.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,891508,891513,33554432,256,0,0,8,32,6464,0x0,0x7f3019604180,499350,499350,16307,3994808,524288,366187131,3797807,0,1479546076,12075754251090885,12075754495567939,12075754495889537,12075754496009475
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,891508,891513,32768,256,0,0,24,24,12480,0x0,0x7f3019635100,27998,27998,20958,223992,512,1150884,77352,0,4617544,12075754510868550,12075754511211259,12075754511217979,12075754511227137
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,891508,891513,4194304,256,0,0,24,24,12928,0x7f3125360900,0x7f3019635140,215716,215716,22358,1725736,65536,144148643,1567089,0,578410044,12075754511296295,12075754511540537,12075754511672537,12075754511676271
diff --git a/projects/rocprofiler-compute/tests/workloads/kernels/mi100/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/kernels/mi100/pmc_dispatch_info.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/kernels/mi100/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/kernels/mi100/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/kernels/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/kernels/mi100/pmc_perf.csv
index 9b402fae75..e6670ab0f7 100644
--- a/projects/rocprofiler-compute/tests/workloads/kernels/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/kernels/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBuffer.kd,0,0,0,890253,890258,33554432,256,0,0,8,32,6464,0x0,0x7f06e1804180,1048576,0,1048576,9437184,0,4194304,1048576,0,498787,498787,57244365,54849964,203,12985697,54232540,54158526,54819555,53639018,3990296,3800748,498787,0,498787,0,15961184,15114945,0,0,0,0,0,17749061,1048576,0,505353,0,0,0,505353,0,0,0,505353,0,0,0,505353,0,0,0,505353,0,0,0,505353,0,0,0,505353,0,0,0,505353,0,0,0,505353,0,0,0,505353,0,0,0,505353,0,0,0,505353,0,0,0,505353,0,0,0,505353,0,0,0,505353,0,0,0,505353,0,0,0,505353,0,0,0,505353,0,0,0,505353,0,0,0,505353,0,0,0,505353,0,0,0,505353,0,0,0,505353,0,0,0,505353,0,0,0,505353,0,0,0,505353,0,0,0,505353,0,0,0,505353,0,0,0,505353,0,0,0,505353,0,0,0,505353,0,0,0,505353,0,0,0,37645501,0,0,0,0,52,0,0,0,3,0,0,0,1,0,0,0,0,0,0,0,48,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,21,0,0,0,0,0,0,0,2689,0,0,0,0,0,0,0,0,0,0,0,48,0,0,0,2673,0,0,0,3,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,2609,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2582,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1048576,0,0,0,131076,131076,0,1414,131076,131076,0,0,131080,131080,0,567021,131072,131072,0,1452,131072,131072,0,20837,131076,131076,0,267,131072,131072,0,7421,131076,131076,0,0,131072,131072,0,0,131076,131076,0,0,131072,131072,0,3240108,131077,131077,0,0,131076,131076,0,0,131072,131072,0,0,131072,131072,0,272,131080,131080,0,0,131076,131076,0,3203997,131072,131072,0,262,131076,131076,0,0,131072,131072,0,954,131072,131072,0,0,131076,131076,0,14389,131076,131076,0,3189036,131076,131076,0,0,131080,131080,0,0,131072,131072,0,0,131080,131080,0,2778304,131072,131072,0,0,131072,131072,0,0,131072,131072,0,0,131076,131076,0,0,131076,131076,1048576,0,859,0,0,17333129,761,0,0,17233275,919,0,0,17470448,882,0,0,17058750,1128,0,0,17561962,1138,0,0,17348014,849,0,0,18051338,46110,0,0,30572127,1707,0,0,17234377,1111,0,0,17144594,760,0,0,17151043,48220,0,0,30065106,893,0,0,17379603,1632,0,0,17397349,725,0,0,18047522,755,0,0,18644539,1018,0,0,16916285,1553,0,0,16738075,1165,0,0,17191614,1069,0,0,16938383,998,0,0,17540197,851,0,0,17346241,963,0,0,18187095,48796,0,0,31140028,880,0,0,16824384,1192,0,0,16912844,1122,0,0,17301414,50759,0,0,30372989,830,0,0,17392759,1836,0,0,17332841,1812,0,0,18482466,1042,0,0,18417670,1048576,131072,131120,48,262192,131260,133715,2831,264975,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,133716,2644,264788,131072,131073,1,262145,131119,131073,48,262192,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131120,48,262192,131072,131072,0,262144,131072,131073,1,262145,131072,131072,0,262144,131072,131072,0,262144,131213,131075,144,262288,131072,131073,1,262145,131072,131072,0,262144,131072,131072,0,262144,131072,133770,2698,264842,131072,131072,0,262144,131119,131073,48,262192,131072,131072,0,262144,131072,133704,2632,264776,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131095,23,262167,131072,131072,0,262144,131072,131072,0,262144,262144,0,262144,262336,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262288,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,0,0,3145728,524288,32505856,362749224,216887303,113356065,480056,0,0,0,1048576,52341098,52086538,1048576,1048576,131072,524288,712,500995,5810,0,96,10678,0,8388944,32505856,4001088,3807686,56977616,11534336,0,0,14155776,67108864,67108864,0,67108864,54215012,53863725,0,1048576,231521,755809,10875,1965,0,495960,8399656,0,4194727,4204929,13631488,0,3670016,1048576,1048576,0,4194304,9437184,0,0,360,33554432,54590264,4194304,0,0,2519,502000,0,11120,8388608,0,4194383,905969664,6291456,0,0,0,524288,524288,0,15329,16608722,0,16777216,4194304,4194304,0,0,0,16502,4194372,4194372,0,215646,0,0,0,33554432,0,0,0,0,636636907,0,2772224160,0,0,0,0,0,475998,0,0,228083,0,0,8388608,336,144,0,0,0,480,8388608,0,0,0,0,272449,0,0,0,10762,0,21506,0,6291456,6289503,96,2129,1927609,0,0,0,0,0,0,0,0,0,3145728,0,0,0,147752,4194304,4189860,144,4300,2097152,524288,1572864,0,0,0,0,0,0,524288,0,4128852,65536,4063243,0,0,8388608,0,42150773,0,1048576,10721,4194354,13086419,611019969,12075728572208640,12075755395473365,12075755395797202,12075728817484093
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,890253,890258,32768,256,0,0,24,24,12480,0x0,0x7f06e1835100,0,4096,4096,512,0,512,4096,0,28735,28735,1578347,643149,225,127757,96156,74469,635064,614503,229880,91043,28735,0,28735,0,919520,204988,0,0,0,0,0,138536,4096,0,27907,0,0,0,27907,0,0,0,27907,0,0,0,27907,0,0,0,27907,0,0,0,27907,0,0,0,27907,0,0,0,27907,0,0,0,27907,0,0,0,27907,0,0,0,27907,0,0,0,27907,0,0,0,27907,0,0,0,27907,0,0,0,27907,0,0,0,27907,0,0,0,27907,0,0,0,27907,0,0,0,27907,0,0,0,27907,0,0,0,27907,0,0,0,27907,0,0,0,27907,0,0,0,27907,0,0,0,27907,0,0,0,27907,0,0,0,27907,0,0,0,27907,0,0,0,27907,0,0,0,27907,0,0,0,27907,0,0,0,27907,0,0,0,0,256,0,0,0,304,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,377,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,260,0,0,0,304,0,0,0,257,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,4096,4096,0,128406,0,0,0,90906,0,0,0,71942,0,0,0,78066,0,0,0,96216,0,0,0,117173,0,0,0,81269,0,0,0,239902,0,0,0,82608,0,0,0,89830,0,0,0,74139,0,0,0,79153,0,0,0,100282,0,0,0,87590,0,0,0,68004,0,0,0,73806,0,0,0,88056,0,0,0,125242,0,0,0,69906,0,0,0,83801,0,0,0,83743,0,0,0,117996,0,0,0,87023,0,0,0,86727,0,0,0,268888,0,0,0,98861,0,0,0,98920,0,0,0,86564,0,0,0,208784,0,0,0,110000,0,0,0,93116,0,0,0,83199,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4096,0,304,304,304,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,257,257,257,47,257,304,304,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,188,261,449,449,0,256,256,256,0,256,256,256,0,256,256,256,188,261,449,449,0,256,256,256,0,256,256,256,0,257,257,257,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,376,376,376,47,257,304,304,0,256,256,256,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,304,0,0,256,0,0,0,0,512,512,35328,1173317,953430,183535,12339,0,0,0,4096,280004,277327,4096,4096,128,512,621,26633,4062,0,48,339,0,8624,36352,213304,72810,1026460,26624,0,0,30208,65536,65536,65536,0,0,0,0,0,115,627,11240,1964,0,22435,8891,0,470,8421,1024,0,1024,4096,0,4096,512,512,0,0,360,16384,0,16384,0,0,2711,24419,0,8963,0,0,31,1933312,8192,0,0,0,512,512,0,120,15064,0,16384,16384,0,0,0,0,20664,0,0,0,0,0,0,0,32768,0,0,0,0,12110281,17147335,0,8192,0,0,0,0,695,0,0,0,0,0,1024,432,48,0,0,0,480,0,0,0,0,0,3171,0,0,0,8421,0,438,0,8192,6570,48,1574,1068,0,0,0,0,0,0,0,0,0,2560,0,0,0,53066,512,0,48,464,0,512,0,0,0,0,0,0,0,512,0,0,0,0,0,8192,0,0,421695,0,4096,8421,0,3152823,0,12075728832330435,12075755411649045,12075755411655605,12075728833318040
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,890253,890258,4194304,256,0,0,24,24,12928,0x7f07ed474900,0x7f06e1835140,0,524288,524288,65536,0,65536,524288,0,214565,214565,23666267,22411876,32028,12635432,21756420,21627022,22401560,20230071,1716520,1563373,214565,0,214565,0,6866080,6136269,0,0,0,0,0,19451449,524288,0,222109,0,0,0,222109,0,0,0,222109,0,0,0,222109,0,0,0,222109,0,0,0,222109,0,0,0,222109,0,0,0,222109,0,0,0,222109,0,0,0,222109,0,0,0,222109,0,0,0,222109,0,0,0,222109,0,0,0,222109,0,0,0,222109,0,0,0,222109,0,0,0,222109,0,0,0,222109,0,0,0,222109,0,0,0,222109,0,0,0,222109,0,0,0,222109,0,0,0,222109,0,0,0,222109,0,0,0,222109,0,0,0,222109,0,0,0,222109,0,0,0,222109,0,0,0,222109,0,0,0,222109,0,0,0,222109,0,0,0,222109,0,0,0,0,65536,0,7646,0,65584,0,6540,0,65540,0,8006,0,65536,0,10811,0,65536,0,13732,0,65536,0,6546,0,65536,0,7367,0,65536,0,28162,0,65536,0,4785,0,65536,0,13272,0,65657,0,11844,0,65536,0,4172,0,65536,0,13073,0,65536,0,9986,0,65536,0,5921,0,65584,0,14976,0,67269,0,53873,0,65536,0,40861,0,65536,0,2854,0,65536,0,17102,0,65536,0,2462,0,65537,0,37219,0,66369,0,49182,0,65536,0,23841,0,65536,0,12859,0,65536,0,9994,0,65536,0,18484,0,65536,0,2392,0,65537,0,14295,0,65536,0,4286,0,65540,0,13184,0,65536,0,20595,0,524288,524288,0,23002697,0,0,0,24553905,0,0,0,22866839,0,0,0,22148393,0,0,0,23071249,0,0,0,22654177,0,0,0,23393563,0,0,0,24027936,0,0,0,24305400,0,0,0,23594749,0,0,0,22570285,0,0,0,43972159,0,0,0,22566038,0,0,0,22554677,0,0,0,24013671,0,0,0,25562055,0,0,0,23966486,0,0,0,23177648,0,0,0,21041781,0,0,0,21967652,0,0,0,22915625,0,0,0,22630131,0,0,0,24819564,0,0,0,25415576,0,0,0,21843415,0,0,0,23924017,0,0,0,20962908,0,0,0,47808061,0,0,0,22539774,0,0,0,24048159,0,0,0,24401908,0,0,0,24063364,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,524288,0,65584,65584,65584,0,67994,67994,67994,188,65540,65728,65728,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65537,65537,65537,47,65537,65584,65584,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65537,65537,65537,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65537,65537,65537,0,65536,65536,65536,0,65536,65536,65536,0,65537,65537,65537,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,67581,67581,67581,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65656,65656,65656,188,65540,65728,65728,0,65536,65536,65536,65536,0,0,65536,0,0,65728,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65728,0,0,65536,0,0,0,0,65536,65536,4128768,150960436,55486919,91213677,195816,0,0,0,524288,21958745,21954714,524288,524288,16384,65536,778,212050,3961,0,48,1877,0,2097536,4259840,1790544,1633636,24186384,3014656,0,0,3473408,8388608,8388608,8388608,0,0,0,0,0,158524,191605,11168,1996,0,219829,2101958,0,423,2101535,131072,0,131072,524288,0,524288,65536,65536,0,0,360,2097152,0,2097152,49056,0,2509,212715,0,2099924,0,0,31,222298112,917504,0,0,0,65536,65536,0,7555,2017350,0,2097152,2097152,0,510716,512242,0,21706,0,0,0,0,0,0,0,4194304,0,0,0,0,988283300,1585617841,0,2097152,0,0,0,0,195741,0,0,0,0,0,131072,384,48,0,0,0,432,0,0,0,0,0,4179,0,0,0,2099082,0,3842,0,917504,914713,48,7555,184890,0,0,0,0,0,0,0,0,0,327680,0,0,597365,650647,65536,64048,48,1440,0,65536,0,0,0,0,0,0,0,65536,0,0,0,1966095,0,2097152,0,0,14422757,0,524288,2101960,0,865548290,0,12075728833949313,12075755411733204,12075755411873363,12075728835230083
diff --git a/projects/rocprofiler-compute/tests/workloads/kernels/mi100/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/kernels/mi100/prev_analysis/1.csv
index 33e28e6df9..e408e6d3e5 100644
--- a/projects/rocprofiler-compute/tests/workloads/kernels/mi100/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/kernels/mi100/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,6055628.0,6055628.0,6055628.0,9.164480938887923
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4526201.0,4526201.0,4526201.0,6.849873009054627
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 256u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,3054533.0,3054533.0,3054533.0,4.62267653424288
diff --git a/projects/rocprofiler-compute/tests/workloads/kernels/mi100/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/kernels/mi100/prev_analysis/1001.csv
index ca08330db0..0e3bf5267e 100644
--- a/projects/rocprofiler-compute/tests/workloads/kernels/mi100/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/kernels/mi100/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,46.862275449101794,Instr per wave
 SMEM,1.8083832335329342,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/kernels/mi100/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/kernels/mi100/prev_analysis/101.csv
index cb9c546b5d..8b23f5848c 100644
--- a/projects/rocprofiler-compute/tests/workloads/kernels/mi100/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/kernels/mi100/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx908
 mi100
 48
 1228.8
-SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/kernels/mi100/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/kernels/mi100/prev_analysis/1202.csv
index 02f2cfd8e2..537448c0b2 100644
--- a/projects/rocprofiler-compute/tests/workloads/kernels/mi100/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/kernels/mi100/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,33917.877889484706,2767.5569458007812,547956.5804443359,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/kernels/mi100/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/kernels/mi100/prev_analysis/1901.csv
index e9e5e4aaea..f00cc52cee 100644
--- a/projects/rocprofiler-compute/tests/workloads/kernels/mi100/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/kernels/mi100/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,2.0,smem_
 VALU,735.0,valu_
 MFMA,,mfma_
 VMEM,8.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,22.0,br_
 VGPR,24.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,67894.0,wavefronts_
 Workgroups,16973.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,163.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,0.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,44.0,hbm_rd_
 HBM Wr,0.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,70.0,vl1_coales_
 VL1 Stall,31.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,37.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/kernels/mi100/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/kernels/mi100/prev_analysis/2001.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/kernels/mi100/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/kernels/mi100/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/kernels/mi100/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/kernels/mi100/prev_analysis/201.csv
index 834e6d62da..7334381fa6 100644
--- a/projects/rocprofiler-compute/tests/workloads/kernels/mi100/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/kernels/mi100/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,59.59200061950603,Pct,100,59.59200061950603
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,63.96947733475583,Threads,64,99.95230833555598
 IPC - Issue,0.8437420287965051,Instr/cycle,5,16.8748405759301
-LDS BW,0.0,Gb/sec,23070.72,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,23070.72,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99342432649306,Pct,100,99.99342432649306
 Instr Cache BW,1407.2673827157548,Gb/s,4614.144,30.49899142106867
 Scalar L1D Cache Hit Rate,99.35620448525918,Pct,100,99.35620448525918
diff --git a/projects/rocprofiler-compute/tests/workloads/kernels/mi100/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/kernels/mi100/prev_analysis/602.csv
index b8ba77ef99..e579123d64 100644
--- a/projects/rocprofiler-compute/tests/workloads/kernels/mi100/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/kernels/mi100/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,61976.520958083835,0,735930,Simd
 Insufficient SIMD VGPRs,542399.497005988,0,29155875,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/kernels/mi100/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/kernels/mi100/prev_analysis/701.csv
index d3f1bff5a3..1071413faa 100644
--- a/projects/rocprofiler-compute/tests/workloads/kernels/mi100/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/kernels/mi100/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,23.976047904191617,8,36,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/kernels/mi100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/kernels/mi100/sysinfo.csv
index a461b47b32..ebd8a6cc82 100644
--- a/projects/rocprofiler-compute/tests/workloads/kernels/mi100/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/kernels/mi100/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-kernels,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 11:21:41 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+kernels,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 11:21:41 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/kernels/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/kernels/mi100/timestamps.csv
index 3ee98d4c25..a9ce6224c2 100644
--- a/projects/rocprofiler-compute/tests/workloads/kernels/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/kernels/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,891557,891562,33554432,256,0,0,8,32,6464,0x0,0x7fbba9204180,12075755395432052,12075755395473365,12075755395797202,12075755395906163
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,891557,891562,32768,256,0,0,24,24,12480,0x0,0x7fbba9235100,12075755411537444,12075755411649045,12075755411655605,12075755411661073
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,891557,891562,4194304,256,0,0,24,24,12928,0x7fbcb4f48900,0x7fbba9235140,12075755411717368,12075755411733204,12075755411873363,12075755411876484
diff --git a/projects/rocprofiler-compute/tests/workloads/kernels/mi200/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/kernels/mi200/SQ_IFETCH_LEVEL.csv
index e24a6a3b92..5faa6f9f07 100644
--- a/projects/rocprofiler-compute/tests/workloads/kernels/mi200/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/kernels/mi200/SQ_IFETCH_LEVEL.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,188020,188020,33554432,256,0,0,4,32,4160,0x0,0x7ff003604280,381872,381872,524288,4718592,680045,76238404,17018811649857,17018099819752,17018955121694,17018955231973
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,188020,188020,32768,256,0,0,12,24,13888,0x0,0x7ff003623f80,32726,32726,512,8192,7488,835840,17018960426954,17018955121694,17018960558647,17018960563330
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,188020,188020,4194304,256,0,0,12,24,14336,0x7ff0066f6380,0x7ff003623fc0,165172,165172,65536,917504,152878,17126672,17018960599629,17018960558647,17018960927606,17018960930139
diff --git a/projects/rocprofiler-compute/tests/workloads/kernels/mi200/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/kernels/mi200/SQ_INST_LEVEL_LDS.csv
index 46027f0a9a..e43c7a1525 100644
--- a/projects/rocprofiler-compute/tests/workloads/kernels/mi200/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/kernels/mi200/SQ_INST_LEVEL_LDS.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,189868,189868,33554432,256,0,0,4,32,4160,0x0,0x7f8aad404280,0,0,0,17038275188179,17037561541743,17038422398116,17038422510425
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,189868,189868,32768,256,0,0,12,24,13888,0x0,0x7f8aad423f80,0,0,0,17038427681418,17038422398116,17038427809460,17038427814184
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,189868,189868,4194304,256,0,0,12,24,14336,0x7f8ab035f380,0x7f8aad423fc0,0,0,0,17038427847943,17038427809460,17038428182419,17038428185163
diff --git a/projects/rocprofiler-compute/tests/workloads/kernels/mi200/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/kernels/mi200/SQ_INST_LEVEL_SMEM.csv
index ebadfe7d2e..8d4348c1d8 100644
--- a/projects/rocprofiler-compute/tests/workloads/kernels/mi200/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/kernels/mi200/SQ_INST_LEVEL_SMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,187798,187798,33554432,256,0,0,4,32,4160,0x0,0x7fdf25a04280,3670016,2898156,324749792,17017871486203,17004563619503,17018017050409,17018017164238
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,187798,187798,32768,256,0,0,12,24,13888,0x0,0x7fdf25a23f80,512,100390,11234352,17018022229652,17018017050409,17018022366561,17018022371497
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,187798,187798,4194304,256,0,0,12,24,14336,0x7fdf28a16380,0x7fdf25a23fc0,65536,646794,72359192,17018022406216,17018022366561,17018022736641,17018022739477
diff --git a/projects/rocprofiler-compute/tests/workloads/kernels/mi200/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/kernels/mi200/SQ_INST_LEVEL_VMEM.csv
index 6cb57c233c..18640bb740 100644
--- a/projects/rocprofiler-compute/tests/workloads/kernels/mi200/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/kernels/mi200/SQ_INST_LEVEL_VMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,189646,189646,33554432,256,0,0,4,32,4160,0x0,0x7f9d56804280,524288,5490901,614983748,17037332490146,17034965056754,17037481413903,17037481526322
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,189646,189646,32768,256,0,0,12,24,13888,0x0,0x7f9d56823f80,4096,35384,3967344,17037486684195,17037481413903,17037486810049,17037486814861
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,189646,189646,4194304,256,0,0,12,24,14336,0x7f9d5979f380,0x7f9d56823fc0,524288,10971179,1228733104,17037486847540,17037486810049,17037487179488,17037487182511
diff --git a/projects/rocprofiler-compute/tests/workloads/kernels/mi200/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/kernels/mi200/SQ_LEVEL_WAVES.csv
index 118ae2fa3c..b0a795cfe4 100644
--- a/projects/rocprofiler-compute/tests/workloads/kernels/mi200/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/kernels/mi200/SQ_LEVEL_WAVES.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,188242,188242,33554432,256,0,0,4,32,4160,0x0,0x7fd4a6804280,388284,388284,8778,3106280,524288,244967804,3019488,0,996171404,17019739890511,17019036428116,17019885027682,17019885140781
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,188242,188242,32768,256,0,0,12,24,13888,0x0,0x7fd4a6823f80,33728,33728,30230,269832,512,1693019,164026,0,6785384,17019890314053,17019885027682,17019890453268,17019890458139
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,188242,188242,4194304,256,0,0,12,24,14336,0x7fd4a9882380,0x7fd4a6823fc0,164607,164607,14285,1316864,65536,82622429,1217167,0,332218900,17019890502057,17019890453268,17019890848147,17019890850967
diff --git a/projects/rocprofiler-compute/tests/workloads/kernels/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/kernels/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/kernels/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/kernels/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/kernels/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/kernels/mi200/pmc_perf.csv
index c9c281a833..c17f436832 100644
--- a/projects/rocprofiler-compute/tests/workloads/kernels/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/kernels/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDI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],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBufferAligned.kd,0,0,0,189008,189008,33554432,256,0,0,4,32,4160,0x0,0x7f0752404280,3126656,3041434,524288,39424114,248589192,392,224,0,390831,390831,39781578.0,38740019.0,3.0,4317539.0,31892289.0,31540139.0,38713034.0,38150859.0,3124945,3047839,390831,0,390831,0,12506592.0,9604424.0,0.0,0.0,0,0,616,0,4718592,4715039,112,3441,375930,0.0,0.0,0.0,524288.0,28506881.0,27755732.0,7725.0,524288.0,131072,524288,302,385322,2589,0,56.0,305.0,0.0,4194696.0,0,0,0,0,0,7340032,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,20680739.0,524288.0,0,389607,0,0,0,389607,0,0,0,389607,0,0,0,389607,0,0,0,389607,0,0,0,389607,0,0,0,389607,0,0,0,389607,0,0,0,389607,0,0,0,389607,0,0,0,389607,0,0,0,389607,0,0,0,389607,0,0,0,389607,0,0,0,389607,0,0,0,389607,0,0,0,389607,0,0,0,389607,0,0,0,389607,0,0,0,389607,0,0,0,389607,0,0,0,389607,0,0,0,389607,0,0,0,389607,0,0,0,389607,0,0,0,389607,0,0,0,389607,0,0,0,389607,0,0,0,389607,0,0,0,389607,0,0,0,389607,0,0,0,389607,0,0,0,0,0,0.0,21746762.0,0,0,0,0,0,0,0,0,0,0,0,0,33,0,0,0,2,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,33,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,112,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,35,0,0,0,6,0,0,0,56,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,0,0,2,0,0,0,524288.0,0.0,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,44471,129024,129024,0,327,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,175,129024,129024,0,46450,129024,129024,0,193736,129024,129024,0,0,129024,129024,0,0,129024,129024,0,193,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,307304,129024,129024,0,1024,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,44574,129024,129024,0,487,129024,129024,524288.0,0.0,47780,0,0,53343048,47764,0,0,53135213,46838,0,0,52793382,49326,0,0,54349739,47308,0,0,53753542,48777,0,0,53960605,46736,0,0,53190103,51344,0,0,55732153,47089,0,0,53287432,48729,0,0,53588687,48041,0,0,53077319,51652,0,0,55153603,48788,0,0,54372741,49078,0,0,54050335,48046,0,0,53637271,51382,0,0,55575021,46233,0,0,52983887,48045,0,0,53462494,47980,0,0,53059032,49675,0,0,54553738,47140,0,0,53782968,48999,0,0,54071909,47413,0,0,53260993,51908,0,0,55656881,48180,0,0,53472763,48860,0,0,53713026,48308,0,0,53323756,51633,0,0,55074394,48642,0,0,54227353,49921,0,0,54341329,48437,0,0,53766848,51828,0,0,55649581,0.0,65536,65568,32,131104,65536,65537,1,131073,65536,65536,0,131072,65536,65537,1,131073,65646,65538,112,131184,65536,65537,1,131073,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65568,32,131104,65536,65536,0,131072,65536,65536,0,131072,65536,65592,56,131128,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65572,36,131108,65536,65536,0,131072,65536,65648,112,131184,65536,65536,0,131072,65758,65539,225,131297,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65568,32,131104,65591,65537,56,131128,65536,65536,0,131072,65536,65536,0,131072,65591,65537,56,131128,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131184,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131296,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131128,0,131072,1038628,0,524288,3670016,3663334,224,6458,1048576,33554432.0,33554432.0,0.0,33554432.0,30473379.0,28889762.0,0.0,524288.0,220346,537514,8669,917,0,384371,4195054.0,0.0,2097594.0,2097460.0,1048576,1048576,0,524288,0,524288,7340032,0,0.0,0.0,104.0,8388608.0,30059391.0,2097152.0,0.0,210115,0,1180,388051,0,753.0,4194304.0,0.0,2064387.0,25690112,9437184,0,0,0,0,0,0,13312.0,8242176.0,0.0,8388608.0,2097152.0,4194304.0,10582012,0,0,9051,4128768.0,4128768.0,0.0,1548385.0,0,0,0,0,0,0,5767168,1048576,319107096.0,0.0,1485341335.0,0.0,32.0,0.0,0,0,375543,0.0,0.0,1535515.0,0.0,3670016,524288,0,0,0,2621440,524288,179794189,4194304.0,0.0,0.0,0.0,0.0,1158363.0,0,0,0.0,309.0,0.0,602.0,43749987,24117248,0,0,9437184,11010048,0,3145728,0.0,0.0,0.0,0.0,0.0,0.0,0,1572864,0.0,0.0,0.0,192511.0,524288,524288,0,3670016,7340032,603979776,4718592,0,0.0,0.0,0.0,0.0,0.0,0.0,524288,0,2064384.0,0.0,2031623.0,0.0,0,0,524288,0,0,0,0,33554432,0.0,4194304.0,0.0,19001680.0,0.0,0.0,143.0,4128768.0,990899.0,1703109384.0,17021160214770,17039094324187,17039094564027,17021310007672
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,189008,189008,32768,256,0,0,12,24,13888,0x0,0x7f0752423f80,267776,156873,512,1353036,1676711,504,56,0,33471,33471,2275102.0,138338.0,177.0,0.0,33110.0,29691.0,132044.0,113256.0,267768,164606,33471,0,33471,0,1071072.0,357865.0,0.0,0.0,0,0,560,0,8192,6196,56,1940,24011,0.0,0.0,0.0,4096.0,34308.0,32977.0,0.0,4096.0,128,512,302,33398,2299,0,0.0,62.0,0.0,4600.0,0,0,0,0,0,1024,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,14872.0,4096.0,0,33311,0,0,0,33311,0,0,0,33311,0,0,0,33311,0,0,0,33311,0,0,0,33311,0,0,0,33311,0,0,0,33311,0,0,0,33311,0,0,0,33311,0,0,0,33311,0,0,0,33311,0,0,0,33311,0,0,0,33311,0,0,0,33311,0,0,0,33311,0,0,0,33311,0,0,0,33311,0,0,0,33311,0,0,0,33311,0,0,0,33311,0,0,0,33311,0,0,0,33311,0,0,0,33311,0,0,0,33311,0,0,0,33311,0,0,0,33311,0,0,0,33311,0,0,0,33311,0,0,0,33311,0,0,0,33311,0,0,0,33311,0,0,0,0,0,0.0,0.0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,312,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,258,0,0,0,258,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,4096.0,4096.0,0,75838,0,0,0,86580,0,0,0,85834,0,0,0,86810,0,0,0,89690,0,0,0,89475,0,0,0,80694,0,0,0,100350,0,0,0,83391,0,0,0,91661,0,0,0,92791,0,0,0,81235,0,0,0,83408,0,0,0,651261,0,0,0,87396,0,0,0,93475,0,0,0,91397,0,0,0,84561,0,0,0,102914,0,0,0,81022,0,0,0,85582,0,0,0,85043,0,0,0,86720,0,0,0,99767,0,0,0,76961,0,0,0,78660,0,0,0,70917,0,0,0,86934,0,0,0,87999,0,0,0,98412,0,0,0,91335,0,0,0,76452,0,0,0.0,0.0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4096.0,0,128,128,128,0,128,128,128,0,128,128,128,0,129,129,129,0,128,128,128,222,131,353,353,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,222,130,352,352,0,128,128,128,0,128,128,128,0,128,128,128,0,130,130,130,0,128,128,128,0,184,184,184,0,128,128,128,0,129,129,129,55,129,184,184,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,352,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,352,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,184,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,662,0,0,512,0,56,456,0,65536.0,65536.0,65536.0,0.0,0.0,0.0,0.0,0.0,6,518,11530,1043,0,31750,4659.0,0.0,499.0,4160.0,512,0,0,0,4096,4096,512,0,0.0,0.0,104.0,16384.0,0.0,16384.0,4096.0,0,0,1317,31861,0,4661.0,0.0,0.0,31.0,35328,26112,0,0,0,0,0,0,104.0,15240.0,0.0,16384.0,16384.0,0.0,0,0,0,30863,0.0,0.0,0.0,0.0,0,0,0,0,0,0,10752,3584,3767106.0,5181012.0,0.0,8192.0,2.0,0.0,0,0,496,0.0,0.0,0.0,0.0,512,4096,0,0,0,512,512,1659228,0.0,0.0,0.0,0.0,0.0,1482.0,0,0,0.0,8260.0,0.0,118.0,14089,32256,0,0,26112,1024,0,1024,0.0,0.0,0.0,0.0,0.0,0.0,0,1024,0.0,0.0,0.0,31748.0,4096,0,4096,512,512,1671168,8192,0,0.0,0.0,0.0,0.0,0.0,0.0,512,0,0.0,0.0,0.0,0.0,0,0,512,0,0,0,0,32768,8192.0,0.0,0.0,95603.0,0.0,4096.0,8207.0,0.0,3272622.0,0.0,17021316202244,17039099412016,17039099425136,17021316687810
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,189008,189008,4194304,256,0,0,12,24,14336,0x7f0755333380,0x7f0752423fc0,1313112,1210486,65536,15668970,75617464,392,56,0,164138,164138,15970833.0,14531028.0,23911.0,665105.0,12991134.0,12628085.0,14524098.0,12389301.0,1313104,1217734,164138,0,164138,0,5252416.0,4739941.0,0.0,0.0,0,0,448,0,917504,913852,0,3652,154163,0.0,0.0,0.0,524288.0,12866794.0,12833684.0,2198.0,524288.0,16384,65536,302,164415,2243,0,0.0,191.0,0.0,1048968.0,0,0,0,0,0,131072,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,11862188.0,524288.0,0,166420,0,0,0,166420,0,0,0,166420,0,0,0,166420,0,0,0,166420,0,0,0,166420,0,0,0,166420,0,0,0,166420,0,0,0,166420,0,0,0,166420,0,0,0,166420,0,0,0,166420,0,0,0,166420,0,0,0,166420,0,0,0,166420,0,0,0,166420,0,0,0,166420,0,0,0,166420,0,0,0,166420,0,0,0,166420,0,0,0,166420,0,0,0,166420,0,0,0,166420,0,0,0,166420,0,0,0,166420,0,0,0,166420,0,0,0,166420,0,0,0,166420,0,0,0,166420,0,0,0,166420,0,0,0,166420,0,0,0,166420,0,0,0,0,0,0.0,0.0,65536,0,6056,0,65536,0,7788,0,65536,0,4628,0,65537,0,14332,0,65536,0,32708,0,65536,0,13530,0,65536,0,22313,0,65536,0,12625,0,65536,0,3162,0,65536,0,10671,0,65536,0,5606,0,65536,0,6349,0,65538,0,8912,0,65536,0,10680,0,65536,0,11886,0,65536,0,3632,0,65592,0,6440,0,65536,0,7555,0,65536,0,6925,0,65536,0,5955,0,65537,0,33971,0,65594,0,9682,0,65538,0,10491,0,65539,0,7651,0,65540,0,4380,0,65536,0,6172,0,65536,0,2110,0,65536,0,11894,0,65536,0,7541,0,65536,0,11572,0,65595,0,15012,0,65536,0,5101,0,524288.0,524288.0,0,39920201,0,0,0,41508451,0,0,0,43087703,0,0,0,38269043,0,0,0,52336319,0,0,0,48701749,0,0,0,52334849,0,0,0,47230209,0,0,0,40252728,0,0,0,36689389,0,0,0,36865178,0,0,0,38228904,0,0,0,39253244,0,0,0,50143057,0,0,0,48474770,0,0,0,45590808,0,0,0,43148946,0,0,0,41567636,0,0,0,38904191,0,0,0,39914117,0,0,0,40636052,0,0,0,41133917,0,0,0,50031478,0,0,0,38906085,0,0,0,38880819,0,0,0,38499131,0,0,0,37565958,0,0,0,39929094,0,0,0,39891928,0,0,0,43808828,0,0,0,42021015,0,0,0,45679122,0,0,0.0,0.0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,524288.0,0,32768,32768,32768,0,32770,32770,32770,0,32768,32768,32768,0,32769,32769,32769,0,32768,32768,32768,0,32769,32769,32769,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32827,32827,32827,0,32768,32768,32768,0,32824,32824,32824,0,32768,32768,32768,0,32769,32769,32769,166,32770,32936,32936,222,32770,32992,32992,0,32768,32768,32768,0,32768,32768,32768,0,32833,32833,32833,0,32768,32768,32768,0,32769,32769,32769,0,32768,32768,32768,0,32768,32768,32768,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32936,0,0,32992,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,907636,0,0,65536,63800,56,1680,0,8388608.0,8388608.0,8388608.0,0.0,0.0,0.0,0.0,0.0,123490,147918,9914,2452,0,162971,1049155.0,0.0,388.0,1048767.0,65536,0,0,0,524288,524288,131072,0,0.0,0.0,104.0,2097152.0,0.0,2097152.0,524288.0,42451,0,2813,161785,0,1049154.0,0.0,0.0,31.0,4063232,2883584,0,0,0,0,0,0,6570.0,2026154.0,0.0,2097152.0,2097152.0,0.0,1608300,0,0,14592,0.0,0.0,0.0,0.0,262144,0,0,0,0,0,1507328,458752,965586661.0,2314784368.0,0.0,2097152.0,145.0,0.0,0,0,148422,0.0,0.0,0.0,0.0,65536,524288,0,0,0,65536,65536,47486987,0.0,0.0,0.0,0.0,0.0,15523.0,0,0,0.0,2097344.0,0.0,370.0,31983471,3735552,0,0,2883584,196608,0,131072,0.0,0.0,0.0,0.0,0.0,0.0,0,131072,0.0,0.0,343658.0,1007416.0,524288,0,524288,65536,131072,184549376,917504,0,0.0,0.0,0.0,0.0,0.0,0.0,65536,0,0.0,0.0,983047.0,0.0,0,0,65536,0,0,0,0,4194304,2097152.0,0.0,0.0,12416697.0,0.0,524288.0,2097285.0,0.0,1452080249.0,0.0,17021317785328,17039099497936,17039099590576,17021318551896
diff --git a/projects/rocprofiler-compute/tests/workloads/kernels/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/kernels/mi200/prev_analysis/1.csv
index 574928c9a9..9dae675d12 100644
--- a/projects/rocprofiler-compute/tests/workloads/kernels/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/kernels/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,3356953.0,3356953.0,3356953.0,7.844214293382022
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,1724636.0,1724636.0,1724636.0,4.02996835585163
 "void benchmark_func<double, 256, 8u, 512u>(double, double*) [clone .kd]",1,1715197.0,1715197.0,1715197.0,4.007912182078797
diff --git a/projects/rocprofiler-compute/tests/workloads/kernels/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/kernels/mi200/prev_analysis/1001.csv
index f475f954a6..fb5988001a 100644
--- a/projects/rocprofiler-compute/tests/workloads/kernels/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/kernels/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,494.8622754491018,Instr per wave
 VMEM,7.958083832335329,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,0.0,Instr per wave
 SALU,24.520958083832337,Instr per wave
 SMEM,1.8023952095808384,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/kernels/mi200/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/kernels/mi200/prev_analysis/101.csv
index 76a6ea8114..1419cf4899 100644
--- a/projects/rocprofiler-compute/tests/workloads/kernels/mi200/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/kernels/mi200/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx90a
 mi200
 56
 1638.4
-roofline|SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+roofline|SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/kernels/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/kernels/mi200/prev_analysis/1202.csv
index 037c25f49e..d7b4d342a6 100644
--- a/projects/rocprofiler-compute/tests/workloads/kernels/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/kernels/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,18383.545308552817,1896.5850219726562,258014.9185180664,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/kernels/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/kernels/mi200/prev_analysis/1901.csv
index 6252eb1168..21e4c2ba9d 100644
--- a/projects/rocprofiler-compute/tests/workloads/kernels/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/kernels/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,2.0,smem_
 VALU,495.0,valu_
 MFMA,0.0,mfma_
 VMEM,8.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,10.0,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,67894.0,wavefronts_
 Workgroups,16973.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,128.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,0.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,44.0,hbm_rd_
 HBM Wr,0.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,70.0,vl1_coales_
 VL1 Stall,2.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,26.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/kernels/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/kernels/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/kernels/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/kernels/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/kernels/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/kernels/mi200/prev_analysis/201.csv
index a45ee45cee..035813a084 100644
--- a/projects/rocprofiler-compute/tests/workloads/kernels/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/kernels/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,58.383802523427974,Pct,100,58.383802523427974
 MFMA Util,0.0,Pct,100,0.0
 VALU Active Threads/Wave,64.0,Threads,64,100.0
 IPC - Issue,1.0,Instr/cycle,5,20.0
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.9926058738864,Pct,100,99.9926058738864
 Instr Cache BW,1674.7745445510106,Gb/s,6092.8,27.487764977531032
 Scalar L1D Cache Hit Rate,99.34855886084364,Pct,100,99.34855886084364
diff --git a/projects/rocprofiler-compute/tests/workloads/kernels/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/kernels/mi200/prev_analysis/602.csv
index ae6a75b924..7c073002d4 100644
--- a/projects/rocprofiler-compute/tests/workloads/kernels/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/kernels/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,12620403.994011976,0,383533081,Simd
 Insufficient SIMD VGPRs,0.0,0,0,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/kernels/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/kernels/mi200/prev_analysis/701.csv
index 12250d77c0..db0925a109 100644
--- a/projects/rocprofiler-compute/tests/workloads/kernels/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/kernels/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/kernels/mi200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/kernels/mi200/sysinfo.csv
index 9fc8b1e1f3..569313c9ab 100644
--- a/projects/rocprofiler-compute/tests/workloads/kernels/mi200/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/kernels/mi200/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-kernels,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:36:58 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,roofline|SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+kernels,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:36:58 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,roofline|SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/kernels/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/kernels/mi200/timestamps.csv
index 417f62ed8e..4cb6845106 100644
--- a/projects/rocprofiler-compute/tests/workloads/kernels/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/kernels/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,189951,189951,33554432,256,0,0,4,32,4160,0x0,0x7fefa1004280,17039094299446,17039094324187,17039094564027,17039094645986
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,189951,189951,32768,256,0,0,12,24,13888,0x0,0x7fefa1023f80,17039099396231,17039099412016,17039099425136,17039099444229
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,189951,189951,4194304,256,0,0,12,24,14336,0x7fefa40a4380,0x7fefa1023fc0,17039099447889,17039099497936,17039099590576,17039099592655
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/SQ_IFETCH_LEVEL.csv
index f7b47f7dbd..e5e537847f 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/SQ_IFETCH_LEVEL.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,746327,746332,33554432,256,0,0,8,32,6464,0x0,0x7f3319204180,500953,500953,524288,6291456,792994,101695980,12073172382107123,12073172629300944,12073172629623022,12073172629738095
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,746327,746332,32768,256,0,0,24,24,12480,0x0,0x7f3319235100,27081,27081,512,8192,9933,1272264,12073172644318466,12073172644642895,12073172644648815,12073172644657947
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,746327,746332,4194304,256,0,0,24,24,12928,0x7f3424d9e900,0x7f3319235140,215542,215542,65536,917504,141630,18080276,12073172644714753,12073172644951053,12073172645082253,12073172645086052
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/SQ_INST_LEVEL_LDS.csv
index 1897b7164c..cba949c75d 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/SQ_INST_LEVEL_LDS.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,748123,748128,33554432,256,0,0,8,32,6464,0x0,0x7f14cf204180,0,0,0,12073198620537158,12073198863702901,12073198864028179,12073198864137881
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,748123,748128,32768,256,0,0,24,24,12480,0x0,0x7f14cf235100,0,0,0,12073198878460684,12073198878747260,12073198878753660,12073198878758598
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,748123,748128,4194304,256,0,0,24,24,12928,0x7f15ff400900,0x7f14cf235140,0,0,0,12073198878825182,12073198879050299,12073198879181658,12073198879185611
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/SQ_INST_LEVEL_SMEM.csv
index f48750283c..ffe7713cfe 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/SQ_INST_LEVEL_SMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,747744,747749,33554432,256,0,0,8,32,6464,0x0,0x7f064ba04180,4194304,3076172,393679528,12073196115389249,12073196360017531,12073196360339289,12073196360448031
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,747744,747749,32768,256,0,0,24,24,12480,0x0,0x7f064ba35100,512,22348,2859312,12073196375206414,12073196375506653,12073196375512733,12073196375518183
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,747744,747749,4194304,256,0,0,24,24,12928,0x7f077bc5d900,0x7f064ba35140,65536,165008,21035712,12073196375582593,12073196375793532,12073196375922491,12073196375926542
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/SQ_INST_LEVEL_VMEM.csv
index 2c7236fcd4..bdae5a0283 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/SQ_INST_LEVEL_VMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,747934,747939,33554432,256,0,0,8,32,6464,0x0,0x7fe2d6a04180,1048576,11096515,1420097720,12073197371357776,12073197611777712,12073197612102990,12073197612215562
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,747934,747939,32768,256,0,0,24,24,12480,0x0,0x7fe2d6a35100,4096,112341,14385376,12073197626636267,12073197626938001,12073197626944561,12073197626949650
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,747934,747939,4194304,256,0,0,24,24,12928,0x7fe3e26d0900,0x7fe2d6a35140,524288,11212591,1435255616,12073197627020481,12073197627236559,12073197627374159,12073197627378076
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/SQ_LEVEL_WAVES.csv
index cbd17c8c11..27e276c387 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/SQ_LEVEL_WAVES.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,748312,748319,33554432,256,0,0,8,32,6464,0x0,0x7f3c0aa04180,503306,503306,17725,4026456,524288,375798045,3819357,0,1517962732,12073199871254167,12073200113818842,12073200114142520,12073200114264253
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,748312,748319,32768,256,0,0,24,24,12480,0x0,0x7f3c0aa35100,28541,28541,21238,228336,512,1179999,79975,0,4734320,12073200128639954,12073200128959679,12073200128966559,12073200128974816
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,748312,748319,4194304,256,0,0,24,24,12928,0x7f3d1673c900,0x7f3c0aa35140,218845,218845,23962,1750768,65536,146513990,1578289,0,587869304,12073200129048984,12073200129290877,12073200129424317,12073200129428369
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/pmc_dispatch_info.csv
index 90cd5504cd..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/pmc_dispatch_info.csv
@@ -1,2 +1,168 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
+1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
+2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
+3,"void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 0u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",0
+4,"void benchmark_func<double, 256, 8u, 0u>(double, double*) [clone .kd]",0
+5,"void benchmark_func<__half2, 256, 8u, 0u>(__half2, __half2*) [clone .kd]",0
+6,"void benchmark_func<int, 256, 8u, 0u>(int, int*) [clone .kd]",0
+7,"void benchmark_func<float, 256, 8u, 1u>(float, float*) [clone .kd]",0
+8,"void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 1u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",0
+9,"void benchmark_func<double, 256, 8u, 1u>(double, double*) [clone .kd]",0
+10,"void benchmark_func<__half2, 256, 8u, 1u>(__half2, __half2*) [clone .kd]",0
+11,"void benchmark_func<int, 256, 8u, 1u>(int, int*) [clone .kd]",0
+12,"void benchmark_func<float, 256, 8u, 2u>(float, float*) [clone .kd]",0
+13,"void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 2u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",0
+14,"void benchmark_func<double, 256, 8u, 2u>(double, double*) [clone .kd]",0
+15,"void benchmark_func<__half2, 256, 8u, 2u>(__half2, __half2*) [clone .kd]",0
+16,"void benchmark_func<int, 256, 8u, 2u>(int, int*) [clone .kd]",0
+17,"void benchmark_func<float, 256, 8u, 3u>(float, float*) [clone .kd]",0
+18,"void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 3u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",0
+19,"void benchmark_func<double, 256, 8u, 3u>(double, double*) [clone .kd]",0
+20,"void benchmark_func<__half2, 256, 8u, 3u>(__half2, __half2*) [clone .kd]",0
+21,"void benchmark_func<int, 256, 8u, 3u>(int, int*) [clone .kd]",0
+22,"void benchmark_func<float, 256, 8u, 4u>(float, float*) [clone .kd]",0
+23,"void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 4u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",0
+24,"void benchmark_func<double, 256, 8u, 4u>(double, double*) [clone .kd]",0
+25,"void benchmark_func<__half2, 256, 8u, 4u>(__half2, __half2*) [clone .kd]",0
+26,"void benchmark_func<int, 256, 8u, 4u>(int, int*) [clone .kd]",0
+27,"void benchmark_func<float, 256, 8u, 5u>(float, float*) [clone .kd]",0
+28,"void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 5u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",0
+29,"void benchmark_func<double, 256, 8u, 5u>(double, double*) [clone .kd]",0
+30,"void benchmark_func<__half2, 256, 8u, 5u>(__half2, __half2*) [clone .kd]",0
+31,"void benchmark_func<int, 256, 8u, 5u>(int, int*) [clone .kd]",0
+32,"void benchmark_func<float, 256, 8u, 6u>(float, float*) [clone .kd]",0
+33,"void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 6u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",0
+34,"void benchmark_func<double, 256, 8u, 6u>(double, double*) [clone .kd]",0
+35,"void benchmark_func<__half2, 256, 8u, 6u>(__half2, __half2*) [clone .kd]",0
+36,"void benchmark_func<int, 256, 8u, 6u>(int, int*) [clone .kd]",0
+37,"void benchmark_func<float, 256, 8u, 7u>(float, float*) [clone .kd]",0
+38,"void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 7u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",0
+39,"void benchmark_func<double, 256, 8u, 7u>(double, double*) [clone .kd]",0
+40,"void benchmark_func<__half2, 256, 8u, 7u>(__half2, __half2*) [clone .kd]",0
+41,"void benchmark_func<int, 256, 8u, 7u>(int, int*) [clone .kd]",0
+42,"void benchmark_func<float, 256, 8u, 8u>(float, float*) [clone .kd]",0
+43,"void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 8u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",0
+44,"void benchmark_func<double, 256, 8u, 8u>(double, double*) [clone .kd]",0
+45,"void benchmark_func<__half2, 256, 8u, 8u>(__half2, __half2*) [clone .kd]",0
+46,"void benchmark_func<int, 256, 8u, 8u>(int, int*) [clone .kd]",0
+47,"void benchmark_func<float, 256, 8u, 9u>(float, float*) [clone .kd]",0
+48,"void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 9u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",0
+49,"void benchmark_func<double, 256, 8u, 9u>(double, double*) [clone .kd]",0
+50,"void benchmark_func<__half2, 256, 8u, 9u>(__half2, __half2*) [clone .kd]",0
+51,"void benchmark_func<int, 256, 8u, 9u>(int, int*) [clone .kd]",0
+52,"void benchmark_func<float, 256, 8u, 10u>(float, float*) [clone .kd]",0
+53,"void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 10u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",0
+54,"void benchmark_func<double, 256, 8u, 10u>(double, double*) [clone .kd]",0
+55,"void benchmark_func<__half2, 256, 8u, 10u>(__half2, __half2*) [clone .kd]",0
+56,"void benchmark_func<int, 256, 8u, 10u>(int, int*) [clone .kd]",0
+57,"void benchmark_func<float, 256, 8u, 11u>(float, float*) [clone .kd]",0
+58,"void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 11u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",0
+59,"void benchmark_func<double, 256, 8u, 11u>(double, double*) [clone .kd]",0
+60,"void benchmark_func<__half2, 256, 8u, 11u>(__half2, __half2*) [clone .kd]",0
+61,"void benchmark_func<int, 256, 8u, 11u>(int, int*) [clone .kd]",0
+62,"void benchmark_func<float, 256, 8u, 12u>(float, float*) [clone .kd]",0
+63,"void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 12u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",0
+64,"void benchmark_func<double, 256, 8u, 12u>(double, double*) [clone .kd]",0
+65,"void benchmark_func<__half2, 256, 8u, 12u>(__half2, __half2*) [clone .kd]",0
+66,"void benchmark_func<int, 256, 8u, 12u>(int, int*) [clone .kd]",0
+67,"void benchmark_func<float, 256, 8u, 13u>(float, float*) [clone .kd]",0
+68,"void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 13u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",0
+69,"void benchmark_func<double, 256, 8u, 13u>(double, double*) [clone .kd]",0
+70,"void benchmark_func<__half2, 256, 8u, 13u>(__half2, __half2*) [clone .kd]",0
+71,"void benchmark_func<int, 256, 8u, 13u>(int, int*) [clone .kd]",0
+72,"void benchmark_func<float, 256, 8u, 14u>(float, float*) [clone .kd]",0
+73,"void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 14u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",0
+74,"void benchmark_func<double, 256, 8u, 14u>(double, double*) [clone .kd]",0
+75,"void benchmark_func<__half2, 256, 8u, 14u>(__half2, __half2*) [clone .kd]",0
+76,"void benchmark_func<int, 256, 8u, 14u>(int, int*) [clone .kd]",0
+77,"void benchmark_func<float, 256, 8u, 15u>(float, float*) [clone .kd]",0
+78,"void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 15u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",0
+79,"void benchmark_func<double, 256, 8u, 15u>(double, double*) [clone .kd]",0
+80,"void benchmark_func<__half2, 256, 8u, 15u>(__half2, __half2*) [clone .kd]",0
+81,"void benchmark_func<int, 256, 8u, 15u>(int, int*) [clone .kd]",0
+82,"void benchmark_func<float, 256, 8u, 16u>(float, float*) [clone .kd]",0
+83,"void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 16u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",0
+84,"void benchmark_func<double, 256, 8u, 16u>(double, double*) [clone .kd]",0
+85,"void benchmark_func<__half2, 256, 8u, 16u>(__half2, __half2*) [clone .kd]",0
+86,"void benchmark_func<int, 256, 8u, 16u>(int, int*) [clone .kd]",0
+87,"void benchmark_func<float, 256, 8u, 17u>(float, float*) [clone .kd]",0
+88,"void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 17u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",0
+89,"void benchmark_func<double, 256, 8u, 17u>(double, double*) [clone .kd]",0
+90,"void benchmark_func<__half2, 256, 8u, 17u>(__half2, __half2*) [clone .kd]",0
+91,"void benchmark_func<int, 256, 8u, 17u>(int, int*) [clone .kd]",0
+92,"void benchmark_func<float, 256, 8u, 18u>(float, float*) [clone .kd]",0
+93,"void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 18u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",0
+94,"void benchmark_func<double, 256, 8u, 18u>(double, double*) [clone .kd]",0
+95,"void benchmark_func<__half2, 256, 8u, 18u>(__half2, __half2*) [clone .kd]",0
+96,"void benchmark_func<int, 256, 8u, 18u>(int, int*) [clone .kd]",0
+97,"void benchmark_func<float, 256, 8u, 20u>(float, float*) [clone .kd]",0
+98,"void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 20u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",0
+99,"void benchmark_func<double, 256, 8u, 20u>(double, double*) [clone .kd]",0
+100,"void benchmark_func<__half2, 256, 8u, 20u>(__half2, __half2*) [clone .kd]",0
+101,"void benchmark_func<int, 256, 8u, 20u>(int, int*) [clone .kd]",0
+102,"void benchmark_func<float, 256, 8u, 22u>(float, float*) [clone .kd]",0
+103,"void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 22u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",0
+104,"void benchmark_func<double, 256, 8u, 22u>(double, double*) [clone .kd]",0
+105,"void benchmark_func<__half2, 256, 8u, 22u>(__half2, __half2*) [clone .kd]",0
+106,"void benchmark_func<int, 256, 8u, 22u>(int, int*) [clone .kd]",0
+107,"void benchmark_func<float, 256, 8u, 24u>(float, float*) [clone .kd]",0
+108,"void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 24u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",0
+109,"void benchmark_func<double, 256, 8u, 24u>(double, double*) [clone .kd]",0
+110,"void benchmark_func<__half2, 256, 8u, 24u>(__half2, __half2*) [clone .kd]",0
+111,"void benchmark_func<int, 256, 8u, 24u>(int, int*) [clone .kd]",0
+112,"void benchmark_func<float, 256, 8u, 28u>(float, float*) [clone .kd]",0
+113,"void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 28u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",0
+114,"void benchmark_func<double, 256, 8u, 28u>(double, double*) [clone .kd]",0
+115,"void benchmark_func<__half2, 256, 8u, 28u>(__half2, __half2*) [clone .kd]",0
+116,"void benchmark_func<int, 256, 8u, 28u>(int, int*) [clone .kd]",0
+117,"void benchmark_func<float, 256, 8u, 32u>(float, float*) [clone .kd]",0
+118,"void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 32u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",0
+119,"void benchmark_func<double, 256, 8u, 32u>(double, double*) [clone .kd]",0
+120,"void benchmark_func<__half2, 256, 8u, 32u>(__half2, __half2*) [clone .kd]",0
+121,"void benchmark_func<int, 256, 8u, 32u>(int, int*) [clone .kd]",0
+122,"void benchmark_func<float, 256, 8u, 40u>(float, float*) [clone .kd]",0
+123,"void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 40u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",0
+124,"void benchmark_func<double, 256, 8u, 40u>(double, double*) [clone .kd]",0
+125,"void benchmark_func<__half2, 256, 8u, 40u>(__half2, __half2*) [clone .kd]",0
+126,"void benchmark_func<int, 256, 8u, 40u>(int, int*) [clone .kd]",0
+127,"void benchmark_func<float, 256, 8u, 48u>(float, float*) [clone .kd]",0
+128,"void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 48u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",0
+129,"void benchmark_func<double, 256, 8u, 48u>(double, double*) [clone .kd]",0
+130,"void benchmark_func<__half2, 256, 8u, 48u>(__half2, __half2*) [clone .kd]",0
+131,"void benchmark_func<int, 256, 8u, 48u>(int, int*) [clone .kd]",0
+132,"void benchmark_func<float, 256, 8u, 56u>(float, float*) [clone .kd]",0
+133,"void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 56u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",0
+134,"void benchmark_func<double, 256, 8u, 56u>(double, double*) [clone .kd]",0
+135,"void benchmark_func<__half2, 256, 8u, 56u>(__half2, __half2*) [clone .kd]",0
+136,"void benchmark_func<int, 256, 8u, 56u>(int, int*) [clone .kd]",0
+137,"void benchmark_func<float, 256, 8u, 64u>(float, float*) [clone .kd]",0
+138,"void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 64u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",0
+139,"void benchmark_func<double, 256, 8u, 64u>(double, double*) [clone .kd]",0
+140,"void benchmark_func<__half2, 256, 8u, 64u>(__half2, __half2*) [clone .kd]",0
+141,"void benchmark_func<int, 256, 8u, 64u>(int, int*) [clone .kd]",0
+142,"void benchmark_func<float, 256, 8u, 80u>(float, float*) [clone .kd]",0
+143,"void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 80u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",0
+144,"void benchmark_func<double, 256, 8u, 80u>(double, double*) [clone .kd]",0
+145,"void benchmark_func<__half2, 256, 8u, 80u>(__half2, __half2*) [clone .kd]",0
+146,"void benchmark_func<int, 256, 8u, 80u>(int, int*) [clone .kd]",0
+147,"void benchmark_func<float, 256, 8u, 96u>(float, float*) [clone .kd]",0
+148,"void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 96u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",0
+149,"void benchmark_func<double, 256, 8u, 96u>(double, double*) [clone .kd]",0
+150,"void benchmark_func<__half2, 256, 8u, 96u>(__half2, __half2*) [clone .kd]",0
+151,"void benchmark_func<int, 256, 8u, 96u>(int, int*) [clone .kd]",0
+152,"void benchmark_func<float, 256, 8u, 128u>(float, float*) [clone .kd]",0
+153,"void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 128u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",0
+154,"void benchmark_func<double, 256, 8u, 128u>(double, double*) [clone .kd]",0
+155,"void benchmark_func<__half2, 256, 8u, 128u>(__half2, __half2*) [clone .kd]",0
+156,"void benchmark_func<int, 256, 8u, 128u>(int, int*) [clone .kd]",0
+157,"void benchmark_func<float, 256, 8u, 256u>(float, float*) [clone .kd]",0
+158,"void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 256u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",0
+159,"void benchmark_func<double, 256, 8u, 256u>(double, double*) [clone .kd]",0
+160,"void benchmark_func<__half2, 256, 8u, 256u>(__half2, __half2*) [clone .kd]",0
+161,"void benchmark_func<int, 256, 8u, 256u>(int, int*) [clone .kd]",0
+162,"void benchmark_func<float, 256, 8u, 512u>(float, float*) [clone .kd]",0
+163,"void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",0
+164,"void benchmark_func<double, 256, 8u, 512u>(double, double*) [clone .kd]",0
+165,"void benchmark_func<__half2, 256, 8u, 512u>(__half2, __half2*) [clone .kd]",0
+166,"void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/pmc_perf.csv
index 6695a0e0db..63b34d17c1 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBuffer.kd,0,0,0,747061,747066,33554432,256,0,0,8,32,6464,0x0,0x7ff402804180,1048576,0,1048576,9437184,0,4194304,1048576,0,507356,507356,58216838,55449569,99,12087866,54597466,54499249,55409452,54234150,4058848,3867142,507356,0,507356,0,16235392,15352576,0,0,0,0,0,17891851,1048576,0,505664,0,0,0,505664,0,0,0,505664,0,0,0,505664,0,0,0,505664,0,0,0,505664,0,0,0,505664,0,0,0,505664,0,0,0,505664,0,0,0,505664,0,0,0,505664,0,0,0,505664,0,0,0,505664,0,0,0,505664,0,0,0,505664,0,0,0,505664,0,0,0,505664,0,0,0,505664,0,0,0,505664,0,0,0,505664,0,0,0,505664,0,0,0,505664,0,0,0,505664,0,0,0,505664,0,0,0,505664,0,0,0,505664,0,0,0,505664,0,0,0,505664,0,0,0,505664,0,0,0,505664,0,0,0,505664,0,0,0,505664,0,0,0,37698905,0,0,0,0,52,0,0,0,0,0,0,0,0,0,0,0,2697,0,0,0,0,0,0,0,3,0,0,0,0,0,0,0,2722,0,0,0,0,0,0,0,0,0,0,0,48,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,2393,0,0,0,1,0,0,0,3,0,0,0,0,0,0,0,0,0,0,0,2713,0,0,0,0,0,0,0,2,0,0,0,0,0,0,0,94,0,0,0,0,0,0,0,48,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1048576,0,0,14049,131072,131072,0,1407,131076,131076,0,541203,131076,131076,0,0,131084,131084,0,2946453,131076,131076,0,0,131076,131076,0,0,131072,131072,0,0,131072,131072,0,2997643,131072,131072,0,0,131072,131072,0,0,131084,131084,0,20263,131080,131080,0,0,131080,131080,0,0,131072,131072,0,0,131072,131072,0,3175095,131072,131072,0,0,131072,131072,0,784,131072,131072,0,0,131080,131080,0,0,131084,131084,0,3369961,131072,131072,0,0,131072,131072,0,2161,131072,131072,0,0,131072,131072,0,7504,131073,131073,0,0,131072,131072,0,258,131072,131072,0,0,131084,131084,0,0,131076,131076,0,0,131076,131076,0,1481,131072,131072,0,0,131076,131076,1048576,0,2087,0,0,17110462,1613,0,0,17159067,1952,0,0,17342396,1925,0,0,17533324,1880,0,0,17285056,876,0,0,17143613,1711,0,0,18118277,1635,0,0,18889461,1048,0,0,17078567,935,0,0,17186526,46197,0,0,29405988,870,0,0,17172137,50731,0,0,30168616,985,0,0,17193455,1371,0,0,17998835,791,0,0,19004953,43928,0,0,29134050,1533,0,0,16812760,849,0,0,17066178,830,0,0,17151188,1160,0,0,17140652,815,0,0,17166089,45950,0,0,30942380,839,0,0,18785687,810,0,0,16535747,737,0,0,16531427,1616,0,0,17233960,822,0,0,17088202,843,0,0,16949996,900,0,0,17190036,935,0,0,17948097,891,0,0,19030860,1048576,131072,131072,0,262144,131260,131125,241,262385,131072,131072,0,262144,131072,133524,2452,264596,131072,131073,1,262145,131072,131072,0,262144,131072,131072,0,262144,131072,133652,2580,264724,131072,131073,1,262145,131072,131072,0,262144,131072,131072,0,262144,131119,131073,48,262192,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131213,131075,144,262288,131119,131073,48,262192,131072,131093,21,262165,131072,131120,48,262192,131072,131072,0,262144,131072,131075,3,262147,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,133641,2569,264713,131072,131073,1,262145,131072,131072,0,262144,131072,131072,0,262144,131072,133731,2659,264803,262144,0,262144,262336,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262288,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,0,0,3145728,524288,32505856,367183016,217364533,117312627,478261,0,0,0,1048576,52314004,52072027,1048576,1048576,131072,524288,714,500520,4314,0,96,10571,0,8388944,32505856,4027728,3828219,57176899,11534336,0,0,14155776,67108864,67108864,0,67108864,54016112,53648997,0,1048576,244205,768493,11701,2407,0,499118,8399400,0,4194727,4204673,13631488,0,3670016,1048576,1048576,0,4194304,9437184,0,0,360,33554432,54286500,4194304,0,0,2811,503926,0,11260,8388608,0,4194360,905969664,6291456,0,0,0,524288,524288,0,15326,16608770,0,16777216,4194304,4194304,0,0,0,17886,4194388,4194388,0,213847,0,0,0,33554432,0,0,0,0,647451242,0,2831667234,0,0,0,0,0,476496,0,0,220907,0,0,8388608,336,144,0,0,0,480,8388608,0,0,0,0,375381,0,0,0,10706,0,21394,0,6291456,6289344,96,2294,1874777,0,0,0,0,0,0,0,0,0,3145728,0,0,0,151226,4194304,4189860,144,4300,2097152,524288,1572864,0,0,0,0,0,0,524288,0,4128839,65534,4063249,0,0,8388608,0,42247133,0,1048576,10356,4194392,12827737,608858630,12073174511329738,12073201000180193,12073201000506430,12073174757039069
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,747061,747066,32768,256,0,0,24,24,12480,0x0,0x7ff402835100,0,4096,4096,512,0,512,4096,0,28352,28352,1546487,638657,212,115092,87853,68000,630524,610025,226816,88917,28352,0,28352,0,907264,208570,0,0,0,0,0,57435,4096,0,27708,0,0,0,27708,0,0,0,27708,0,0,0,27708,0,0,0,27708,0,0,0,27708,0,0,0,27708,0,0,0,27708,0,0,0,27708,0,0,0,27708,0,0,0,27708,0,0,0,27708,0,0,0,27708,0,0,0,27708,0,0,0,27708,0,0,0,27708,0,0,0,27708,0,0,0,27708,0,0,0,27708,0,0,0,27708,0,0,0,27708,0,0,0,27708,0,0,0,27708,0,0,0,27708,0,0,0,27708,0,0,0,27708,0,0,0,27708,0,0,0,27708,0,0,0,27708,0,0,0,27708,0,0,0,27708,0,0,0,27708,0,0,0,0,256,0,0,0,304,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,304,0,0,0,257,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,377,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,4096,4096,0,146877,0,0,0,92453,0,0,0,85201,0,0,0,93450,0,0,0,135313,0,0,0,97919,0,0,0,91660,0,0,0,88443,0,0,0,85121,0,0,0,80663,0,0,0,84800,0,0,0,95685,0,0,0,86151,0,0,0,87331,0,0,0,68637,0,0,0,70305,0,0,0,95324,0,0,0,84977,0,0,0,81644,0,0,0,117934,0,0,0,97547,0,0,0,120626,0,0,0,135464,0,0,0,80239,0,0,0,167719,0,0,0,95474,0,0,0,80080,0,0,0,82349,0,0,0,90644,0,0,0,78643,0,0,0,98936,0,0,0,83375,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4096,0,256,256,256,0,305,305,305,0,256,256,256,0,256,256,256,0,257,257,257,0,256,256,256,0,256,256,256,0,256,256,256,0,257,257,257,0,256,256,256,0,256,256,256,47,257,304,304,0,256,256,256,0,256,256,256,188,260,448,448,0,256,256,256,0,256,256,256,0,256,256,256,188,260,448,448,0,376,376,376,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,257,257,257,0,256,256,256,47,257,304,304,0,256,256,256,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,304,0,0,256,0,0,0,0,512,512,35328,1125663,1072080,17231,11441,0,0,0,4096,70622,67586,4096,4096,128,512,623,27607,4281,0,48,219,0,8624,36352,227216,79157,1082223,26624,0,0,30208,65536,65536,65536,0,0,0,0,0,117,629,12004,2410,0,23964,8892,0,470,8422,1024,0,1024,4096,0,4096,512,512,0,0,360,16384,0,16384,0,0,2864,24619,0,8892,0,0,31,1933312,8192,0,0,0,512,512,0,120,15064,0,16384,16384,0,0,0,0,20378,0,0,0,0,0,0,0,32768,0,0,0,0,11985783,17113899,0,8192,0,0,0,0,695,0,0,0,0,0,1024,432,48,0,0,0,480,0,0,0,0,0,3242,0,0,0,8422,0,440,0,8192,6659,48,1485,1106,0,0,0,0,0,0,0,0,0,2560,0,0,0,45764,512,0,48,464,0,512,0,0,0,0,0,0,0,512,0,0,0,0,0,8192,0,0,475983,0,4096,8421,0,3598176,0,12073174771991181,12073201015052373,12073201015059573,12073174772986751
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,747061,747066,4194304,256,0,0,24,24,12928,0x7ff532858900,0x7ff402835140,0,524288,524288,65536,0,65536,524288,0,216477,216477,23699477,22471677,31876,12746407,22019644,21922899,22462012,20292395,1731816,1563467,216477,0,216477,0,6927264,6159508,0,0,0,0,0,18852691,524288,0,214938,0,0,0,214938,0,0,0,214938,0,0,0,214938,0,0,0,214938,0,0,0,214938,0,0,0,214938,0,0,0,214938,0,0,0,214938,0,0,0,214938,0,0,0,214938,0,0,0,214938,0,0,0,214938,0,0,0,214938,0,0,0,214938,0,0,0,214938,0,0,0,214938,0,0,0,214938,0,0,0,214938,0,0,0,214938,0,0,0,214938,0,0,0,214938,0,0,0,214938,0,0,0,214938,0,0,0,214938,0,0,0,214938,0,0,0,214938,0,0,0,214938,0,0,0,214938,0,0,0,214938,0,0,0,214938,0,0,0,214938,0,0,0,0,65536,0,21662,0,65584,0,9063,0,65540,0,24918,0,65536,0,9912,0,66217,0,62985,0,65536,0,9333,0,65536,0,32599,0,65536,0,22096,0,65536,0,12332,0,65536,0,13548,0,65536,0,14247,0,65584,0,22327,0,65537,0,13097,0,65536,0,4751,0,65536,0,16346,0,65536,0,15269,0,65537,0,33185,0,65536,0,31888,0,65536,0,24519,0,65536,0,11518,0,66396,0,28539,0,65536,0,7718,0,65537,0,14066,0,65536,0,12590,0,65838,0,25610,0,65536,0,24956,0,65536,0,26821,0,65536,0,3875,0,65537,0,35028,0,65536,0,5575,0,65540,0,32012,0,65536,0,36202,0,524288,524288,0,36318959,0,0,0,40827334,0,0,0,34852776,0,0,0,37904143,0,0,0,47296927,0,0,0,38158305,0,0,0,39508615,0,0,0,45613325,0,0,0,32309570,0,0,0,30383654,0,0,0,38514503,0,0,0,40221114,0,0,0,29838651,0,0,0,36890640,0,0,0,37243410,0,0,0,35072148,0,0,0,43598114,0,0,0,32756614,0,0,0,37733325,0,0,0,36292838,0,0,0,46050214,0,0,0,42708067,0,0,0,35658476,0,0,0,34613061,0,0,0,38075678,0,0,0,32215847,0,0,0,30045931,0,0,0,30927300,0,0,0,31116013,0,0,0,31255559,0,0,0,43049186,0,0,0,39782113,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,524288,0,65536,65536,65536,0,65585,65585,65585,188,65540,65728,65728,0,68172,68172,68172,0,65537,65537,65537,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65537,65537,65537,0,65536,65536,65536,0,65536,65536,65536,47,65537,65584,65584,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65657,65657,65657,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65537,65537,65537,0,65536,65536,65536,188,65540,65728,65728,0,67079,67079,67079,65536,0,0,65536,0,0,65728,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65728,0,0,65536,0,0,0,0,65536,65536,4128768,128866211,46587143,78019228,207846,0,0,0,524288,22814145,22803525,524288,524288,16384,65536,763,226334,4446,0,48,4602,0,2097536,4259840,1749072,1576923,23322928,3014656,0,0,3473408,8388608,8388608,8388608,0,0,0,0,0,189465,212384,11598,2453,0,214348,2100402,0,423,2099979,131072,0,131072,524288,0,524288,65536,65536,0,0,360,2097152,0,2097152,38218,0,2812,213468,0,2100020,0,0,31,222298112,917504,0,0,0,65536,65536,0,7525,2016290,0,2097152,2097152,0,580283,581980,0,21767,0,0,0,0,0,0,0,4194304,0,0,0,0,1131100680,1970394530,0,2097152,0,0,0,0,192117,0,0,0,0,0,131072,384,48,0,0,0,432,0,0,0,0,0,6677,0,0,0,2099585,0,4848,0,917504,914757,48,7366,187766,0,0,0,0,0,0,0,0,0,327680,0,0,331608,385141,65536,64048,48,1440,0,65536,0,0,0,0,0,0,0,65536,0,0,0,1966110,0,2097152,0,0,17941084,0,524288,2099174,0,1221247788,0,12073174773621320,12073201015131092,12073201015261491,12073174774852708
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/prev_analysis/1.csv
index 87bf1cda52..66aac4a5bd 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,6055314.0,6055314.0,6055314.0,9.185688398954278
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4527485.0,4527485.0,4527485.0,6.868028056173389
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 256u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,3053897.0,3053897.0,3053897.0,4.632649313396675
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/prev_analysis/1001.csv
index ca08330db0..0e3bf5267e 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,46.862275449101794,Instr per wave
 SMEM,1.8083832335329342,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/prev_analysis/101.csv
index ec8596afcc..529e7916d4 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx908
 mi100
 48
 1228.8
-SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/prev_analysis/1202.csv
index a238fc585c..d0f9c72bd2 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,33585.542547717065,2801.3840942382812,547991.7166137695,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/prev_analysis/1901.csv
index 82ece20abb..34522cb2f3 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,2.0,smem_
 VALU,735.0,valu_
 MFMA,,mfma_
 VMEM,8.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,22.0,br_
 VGPR,24.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,67894.0,wavefronts_
 Workgroups,16973.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,163.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,0.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,44.0,hbm_rd_
 HBM Wr,0.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,70.0,vl1_coales_
 VL1 Stall,30.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,35.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/prev_analysis/2001.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/prev_analysis/201.csv
index cc98257f36..afa6395b49 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,59.29457905446075,Pct,100,59.29457905446075
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,63.968137417334695,Threads,64,99.95021471458546
 IPC - Issue,0.8437291252710385,Instr/cycle,5,16.87458250542077
-LDS BW,0.0,Gb/sec,23070.72,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,23070.72,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99346139480204,Pct,100,99.99346139480204
 Instr Cache BW,1410.6080136676471,Gb/s,4614.144,30.571391219425465
 Scalar L1D Cache Hit Rate,99.35620448525918,Pct,100,99.35620448525918
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/prev_analysis/602.csv
index 85ecbcb925..303c984b46 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,53994.51497005988,0,695554,Simd
 Insufficient SIMD VGPRs,598051.6107784432,0,48149082,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/prev_analysis/701.csv
index d3f1bff5a3..1071413faa 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,23.976047904191617,8,36,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/sysinfo.csv
index d9ab33dd5f..34fd794499 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-mixbench,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 10:39:07 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+mixbench,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 10:39:07 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/timestamps.csv
index e9e6868ed4..56a9c6393c 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,748363,748368,33554432,256,0,0,8,32,6464,0x0,0x7f38e2e04180,12073201000131337,12073201000180193,12073201000506430,12073201000570132
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,748363,748368,32768,256,0,0,24,24,12480,0x0,0x7f38e2e35100,12073201014938530,12073201015052373,12073201015059573,12073201015064624
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,748363,748368,4194304,256,0,0,24,24,12928,0x7f3a12de0900,0x7f38e2e35140,12073201015114908,12073201015131092,12073201015261491,12073201015264916
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/SQ_IFETCH_LEVEL.csv
index b98e5fa635..a5c51b3f26 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/SQ_IFETCH_LEVEL.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,21628,21628,33554432,256,0,0,4,32,4160,0x0,0x7fb388204280,386456,386456,524288,4718592,682294,76313024,14214950724382,14214326191617,14215097854019,14215097943239
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,21628,21628,32768,256,0,0,12,24,13888,0x0,0x7fb388223f80,34296,34296,512,8192,7593,846628,14215103103013,14215097854019,14215103238826,14215103243910
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,21628,21628,4194304,256,0,0,12,24,14336,0x7fb3a6bcd380,0x7fb388223fc0,165334,165334,65536,917504,140628,15755044,14215103282580,14215103238826,14215103620427,14215103623193
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/SQ_INST_LEVEL_LDS.csv
index 10d9b5d247..c59a0020d6 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/SQ_INST_LEVEL_LDS.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,23312,23312,33554432,256,0,0,4,32,4160,0x0,0x7feaad204280,0,0,0,14233267445370,14232642250674,14233414720083,14233414811963
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,23312,23312,32768,256,0,0,12,24,13888,0x0,0x7feaad223f80,0,0,0,14233420005197,14233414720083,14233420131141,14233420134244
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,23312,23312,4194304,256,0,0,12,24,14336,0x7feab02cc380,0x7feaad223fc0,0,0,0,14233420170393,14233420131141,14233420457702,14233420460207
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/SQ_INST_LEVEL_SMEM.csv
index 95d1561e87..e459db10cf 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/SQ_INST_LEVEL_SMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,21447,21447,33554432,256,0,0,4,32,4160,0x0,0x7f998ee04280,3670016,2904094,324911544,14214097043918,14095491412894,14214245793171,14214245909711
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,21447,21447,32768,256,0,0,12,24,13888,0x0,0x7f998ee23f80,512,94148,10565528,14214251057535,14214245793171,14214251188702,14214251193482
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,21447,21447,4194304,256,0,0,12,24,14336,0x7f9991d71380,0x7f998ee23fc0,65536,639506,71642904,14214251227932,14214251188702,14214251559583,14214251562255
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/SQ_INST_LEVEL_VMEM.csv
index 40f3aac020..335c081f32 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/SQ_INST_LEVEL_VMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,23131,23131,33554432,256,0,0,4,32,4160,0x0,0x7ffac3c04280,524288,5452804,610783816,14232413425811,14230701438840,14232561205204,14232561296504
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,23131,23131,32768,256,0,0,12,24,13888,0x0,0x7ffac3c23f80,4096,41990,4703636,14232566502467,14232561205204,14232566633060,14232566637894
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,23131,23131,4194304,256,0,0,12,24,14336,0x7ffada195380,0x7ffac3c23fc0,524288,10975998,1229254820,14232566672914,14232566633060,14232567013222,14232567016057
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/SQ_LEVEL_WAVES.csv
index 0bfcb05982..25484a347d 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/SQ_LEVEL_WAVES.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,21809,21809,33554432,256,0,0,4,32,4160,0x0,0x7f3a14e04280,385763,385763,8974,3086112,524288,244533185,2998195,0,994394308,14215812549360,14215179720453,14215963214144,14215963327574
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,21809,21809,32768,256,0,0,12,24,13888,0x0,0x7f3a14e23f80,33946,33946,30436,271576,512,1721991,169799,0,6901404,14215968483638,14215963214144,14215968617832,14215968622655
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,21809,21809,4194304,256,0,0,12,24,14336,0x7f3a17d97380,0x7f3a14e23fc0,165078,165078,14670,1320632,65536,87142760,1215873,0,350302572,14215968665954,14215968617832,14215969006152,14215969008677
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/pmc_perf.csv
index 3c6b886d88..765607bdfe 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDI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],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBufferAligned.kd,0,0,0,22534,22534,33554432,256,0,0,4,32,4160,0x0,0x7fa7d2e04280,3089424,3002605,524288,38998176,245315223,392,224,0,386177,386177,39274526.0,38310912.0,12.0,4277565.0,31473401.0,31123631.0,38285421.0,37723016.0,3087713,3009011,386177,0,386177,0,12357664.0,9556998.0,0.0,0.0,0,0,616,0,4718592,4714946,112,3534,381751,0.0,0.0,0.0,524288.0,29288902.0,28612446.0,7826.0,524288.0,131072,524288,301,390816,2263,0,56.0,305.0,0.0,4194696.0,0,0,0,0,0,7340032,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,20789945.0,524288.0,0,388832,0,0,0,388832,0,0,0,388832,0,0,0,388832,0,0,0,388832,0,0,0,388832,0,0,0,388832,0,0,0,388832,0,0,0,388832,0,0,0,388832,0,0,0,388832,0,0,0,388832,0,0,0,388832,0,0,0,388832,0,0,0,388832,0,0,0,388832,0,0,0,388832,0,0,0,388832,0,0,0,388832,0,0,0,388832,0,0,0,388832,0,0,0,388832,0,0,0,388832,0,0,0,388832,0,0,0,388832,0,0,0,388832,0,0,0,388832,0,0,0,388832,0,0,0,388832,0,0,0,388832,0,0,0,388832,0,0,0,388832,0,0,0,0,0,0.0,21567629.0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,0,0,2,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,56,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,36,0,0,0,4,0,0,0,113,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,0,0,1,0,0,0,524288.0,0.0,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,43591,129024,129024,0,649,129024,129024,0,0,129024,129024,0,0,129024,129024,0,265,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,44940,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,277831,129024,129024,0,0,129024,129024,0,0,129024,129024,0,32840,129024,129024,0,856,129024,129024,0,184,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,198413,129024,129024,0,0,129024,129024,0,0,129024,129024,0,45631,129024,129024,0,184,129024,129024,524288.0,0.0,46173,0,0,52256208,47845,0,0,52601949,47168,0,0,52322512,48537,0,0,53735925,46600,0,0,52717776,47804,0,0,53055042,46498,0,0,52453784,49813,0,0,54570060,46668,0,0,52753723,48279,0,0,52756001,46946,0,0,52185596,50280,0,0,54369392,48145,0,0,53564919,49520,0,0,53520836,48524,0,0,52921708,51371,0,0,54983869,45231,0,0,51954282,47815,0,0,52631743,45673,0,0,51813147,48164,0,0,53504736,45908,0,0,53000312,47462,0,0,53297643,47092,0,0,52482482,49780,0,0,54265066,47448,0,0,52464137,48363,0,0,52716053,48029,0,0,52284986,49553,0,0,53930788,47277,0,0,53092189,49403,0,0,53875807,47370,0,0,52905553,51356,0,0,54827860,0.0,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65568,32,131104,65646,65538,112,131184,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65568,32,131104,65536,65536,0,131072,65536,65536,0,131072,65536,65592,56,131128,65591,65537,56,131128,65536,65536,0,131072,65536,65648,112,131184,65536,65537,1,131073,65536,65536,0,131072,65536,65571,35,131107,65758,65540,226,131298,65536,65536,0,131072,65536,65537,1,131073,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65568,32,131104,65591,65537,56,131128,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131184,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131296,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131128,0,131072,1135593,0,524288,3670016,3663203,224,6589,1048576,33554432.0,33554432.0,0.0,33554432.0,30785462.0,29225195.0,0.0,524288.0,229464,536014,8490,950,0,389414,4195055.0,0.0,2097594.0,2097461.0,1048576,1048576,0,524288,0,524288,7340032,0,0.0,0.0,104.0,8388608.0,30342141.0,2097152.0,0.0,215694,0,1186,389956,0,752.0,4194304.0,0.0,2064387.0,25690112,9437184,0,0,0,0,0,0,13284.0,8242484.0,0.0,8388608.0,2097152.0,4194304.0,10077484,0,0,9233,4128768.0,4128768.0,0.0,1531180.0,0,0,0,0,0,0,5767168,1048576,319528479.0,0.0,1483411288.0,0.0,40.0,0.0,0,0,379159,0.0,0.0,1527214.0,0.0,3670016,524288,0,0,0,2621440,524288,178671167,4194304.0,0.0,0.0,0.0,0.0,1165062.0,0,0,0.0,311.0,0.0,606.0,44553053,24117248,0,0,9437184,11010048,0,3145728,0.0,0.0,0.0,0.0,0.0,0.0,0,1572864,0.0,0.0,0.0,198452.0,524288,524288,0,3670016,7340032,603979776,4718592,0,0.0,0.0,0.0,0.0,0.0,0.0,524288,0,2064384.0,0.0,2031623.0,0.0,0,0,524288,0,0,0,0,33554432,0.0,4194304.0,0.0,18827312.0,0.0,0.0,142.0,4128768.0,663892.0,1693937750.0,14217183562495,14234006575542,14234006812983,14217331380828
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,22534,22534,32768,256,0,0,12,24,13888,0x0,0x7fa7d2e23f80,270952,169796,512,1436746,1784682,504,56,0,33868,33868,2438696.0,166158.0,194.0,0.0,32914.0,29799.0,159896.0,141087.0,270944,176768,33868,0,33868,0,1083776.0,414506.0,0.0,0.0,0,0,560,0,8192,6201,56,1935,23797,0.0,0.0,0.0,4096.0,29082.0,27613.0,0.0,4096.0,128,512,302,33108,2288,0,0.0,60.0,0.0,4600.0,0,0,0,0,0,1024,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,11988.0,4096.0,0,32348,0,0,0,32348,0,0,0,32348,0,0,0,32348,0,0,0,32348,0,0,0,32348,0,0,0,32348,0,0,0,32348,0,0,0,32348,0,0,0,32348,0,0,0,32348,0,0,0,32348,0,0,0,32348,0,0,0,32348,0,0,0,32348,0,0,0,32348,0,0,0,32348,0,0,0,32348,0,0,0,32348,0,0,0,32348,0,0,0,32348,0,0,0,32348,0,0,0,32348,0,0,0,32348,0,0,0,32348,0,0,0,32348,0,0,0,32348,0,0,0,32348,0,0,0,32348,0,0,0,32348,0,0,0,32348,0,0,0,32348,0,0,0,0,0,0.0,0.0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,261,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,314,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,4096.0,4096.0,0,82327,0,0,0,94178,0,0,0,112991,0,0,0,83198,0,0,0,78923,0,0,0,82711,0,0,0,83798,0,0,0,88746,0,0,0,77954,0,0,0,80296,0,0,0,76287,0,0,0,80773,0,0,0,88774,0,0,0,88870,0,0,0,82413,0,0,0,111876,0,0,0,92281,0,0,0,84211,0,0,0,82438,0,0,0,85632,0,0,0,80548,0,0,0,92436,0,0,0,80548,0,0,0,95296,0,0,0,83412,0,0,0,77595,0,0,0,75631,0,0,0,654453,0,0,0,82408,0,0,0,108081,0,0,0,124299,0,0,0,92312,0,0,0.0,0.0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4096.0,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,222,130,352,352,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,222,130,352,352,0,128,128,128,0,128,128,128,0,128,128,128,0,184,184,184,0,129,129,129,0,128,128,128,0,130,130,130,0,129,129,129,55,129,184,184,0,129,129,129,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,352,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,352,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,184,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,652,0,0,512,0,56,456,0,65536.0,65536.0,65536.0,0.0,0.0,0.0,0.0,0.0,6,518,11226,1432,0,32152,4661.0,0.0,499.0,4162.0,512,0,0,0,4096,4096,512,0,0.0,0.0,104.0,16384.0,0.0,16384.0,4096.0,0,0,1271,32432,0,4662.0,0.0,0.0,31.0,35328,26112,0,0,0,0,0,0,104.0,15240.0,0.0,16384.0,16384.0,0.0,0,0,0,30737,0.0,0.0,0.0,0.0,0,0,0,0,0,0,10752,3584,4116575.0,5547835.0,0.0,8192.0,2.0,0.0,0,0,498,0.0,0.0,0.0,0.0,512,4096,0,0,0,512,512,1679168,0.0,0.0,0.0,0.0,0.0,1422.0,0,0,0.0,8262.0,0.0,122.0,14828,32256,0,0,26112,1024,0,1024,0.0,0.0,0.0,0.0,0.0,0.0,0,1024,0.0,0.0,0.0,38567.0,4096,0,4096,512,512,1671168,8192,0,0.0,0.0,0.0,0.0,0.0,0.0,512,0,0.0,0.0,0.0,0.0,0,0,512,0,0,0,0,32768,8192.0,0.0,0.0,123081.0,0.0,4096.0,8207.0,0.0,3113119.0,0.0,14217337595321,14234011579879,14234011592839,14217338084901
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,22534,22534,4194304,256,0,0,12,24,14336,0x7fa7d5e37380,0x7fa7d2e23fc0,1310896,1206676,65536,15614397,84610719,392,56,0,163861,163861,15917720.0,14485700.0,24376.0,705787.0,13639461.0,13451436.0,14479368.0,12344271.0,1310888,1213436,163861,0,163861,0,5243552.0,4734600.0,0.0,0.0,0,0,448,0,917504,913723,0,3781,154163,0.0,0.0,0.0,524288.0,12097327.0,12053439.0,2059.0,524288.0,16384,65536,302,164851,2278,0,0.0,180.0,0.0,1048968.0,0,0,0,0,0,131072,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,10650327.0,524288.0,0,172520,0,0,0,172520,0,0,0,172520,0,0,0,172520,0,0,0,172520,0,0,0,172520,0,0,0,172520,0,0,0,172520,0,0,0,172520,0,0,0,172520,0,0,0,172520,0,0,0,172520,0,0,0,172520,0,0,0,172520,0,0,0,172520,0,0,0,172520,0,0,0,172520,0,0,0,172520,0,0,0,172520,0,0,0,172520,0,0,0,172520,0,0,0,172520,0,0,0,172520,0,0,0,172520,0,0,0,172520,0,0,0,172520,0,0,0,172520,0,0,0,172520,0,0,0,172520,0,0,0,172520,0,0,0,172520,0,0,0,172520,0,0,0,0,0,0.0,0.0,65536,0,29594,0,65537,0,5012,0,65536,0,7660,0,65536,0,7153,0,65537,0,23334,0,65538,0,13776,0,65536,0,24157,0,65536,0,6548,0,65536,0,22832,0,65536,0,7219,0,65536,0,9781,0,65536,0,8667,0,65537,0,6877,0,65536,0,13120,0,65538,0,17760,0,65536,0,9824,0,65536,0,7708,0,65536,0,5647,0,65537,0,4066,0,65536,0,28352,0,65538,0,24427,0,65595,0,12944,0,65536,0,33883,0,65654,0,14380,0,65540,0,9534,0,65536,0,24486,0,65536,0,5657,0,65536,0,5515,0,65536,0,6651,0,65536,0,8144,0,65596,0,27366,0,65536,0,16202,0,524288.0,524288.0,0,40128386,0,0,0,39494684,0,0,0,46793996,0,0,0,46309975,0,0,0,46182766,0,0,0,47144230,0,0,0,40525433,0,0,0,41903101,0,0,0,41915041,0,0,0,42936948,0,0,0,48031198,0,0,0,41443128,0,0,0,40946707,0,0,0,39197538,0,0,0,37880919,0,0,0,48499739,0,0,0,45344029,0,0,0,45264143,0,0,0,46909322,0,0,0,42903208,0,0,0,45308359,0,0,0,41345929,0,0,0,44358009,0,0,0,41203310,0,0,0,39011202,0,0,0,45219415,0,0,0,40247546,0,0,0,46363953,0,0,0,43164555,0,0,0,43529128,0,0,0,41538716,0,0,0,46859443,0,0,0.0,0.0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,524288.0,0,32768,32768,32768,0,32768,32768,32768,0,32769,32769,32769,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32824,32824,32824,0,32769,32769,32769,0,32770,32770,32770,0,32829,32829,32829,0,32769,32769,32769,166,32770,32936,32936,222,32771,32993,32993,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32828,32828,32828,0,32768,32768,32768,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32936,0,0,32992,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,914699,0,0,65536,63800,56,1680,0,8388608.0,8388608.0,8388608.0,0.0,0.0,0.0,0.0,0.0,124471,147137,9963,3159,0,161913,1049149.0,0.0,388.0,1048761.0,65536,0,0,0,524288,524288,131072,0,0.0,0.0,104.0,2097152.0,0.0,2097152.0,524288.0,41626,0,3013,162097,0,1049157.0,0.0,0.0,31.0,4063232,2883584,0,0,0,0,0,0,6612.0,2027025.0,0.0,2097152.0,2097152.0,0.0,1316704,0,0,14984,0.0,0.0,0.0,0.0,262144,0,0,0,0,0,1507328,458752,980471664.0,2304842678.0,0.0,2097152.0,76.0,0.0,0,0,146946,0.0,0.0,0.0,0.0,65536,524288,0,0,0,65536,65536,47384575,0.0,0.0,0.0,0.0,0.0,38058.0,0,0,0.0,2097346.0,0.0,374.0,25756413,3735552,0,0,2883584,196608,0,131072,0.0,0.0,0.0,0.0,0.0,0.0,0,131072,0.0,0.0,492745.0,1472339.0,524288,0,524288,65536,131072,184549376,917504,0,0.0,0.0,0.0,0.0,0.0,0.0,65536,0,0.0,0.0,983047.0,0.0,0,0,65536,0,0,0,0,4194304,2097152.0,0.0,0.0,12458662.0,0.0,524288.0,2097285.0,0.0,1379391007.0,0.0,14217339173729,14234011664520,14234011757320,14217339919414
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/prev_analysis/1.csv
index f046a95655..565024f483 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,3356652.0,3356652.0,3356652.0,7.843408309322819
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,1725607.0,1725607.0,1725607.0,4.032184534597456
 "void benchmark_func<double, 256, 8u, 512u>(double, double*) [clone .kd]",1,1714726.0,1714726.0,1714726.0,4.006759162585779
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/prev_analysis/1001.csv
index f475f954a6..fb5988001a 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,494.8622754491018,Instr per wave
 VMEM,7.958083832335329,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,0.0,Instr per wave
 SALU,24.520958083832337,Instr per wave
 SMEM,1.8023952095808384,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/prev_analysis/101.csv
index ec53d8a85d..5ce0109bdb 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx90a
 mi200
 56
 1638.4
-roofline|SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+roofline|SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/prev_analysis/1202.csv
index aeb8322097..f4f054d61e 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,18419.51861494601,1871.6066207885742,257965.85125732422,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/prev_analysis/1901.csv
index 216f7f77e0..43770bdcea 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,2.0,smem_
 VALU,495.0,valu_
 MFMA,0.0,mfma_
 VMEM,8.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,10.0,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,67894.0,wavefronts_
 Workgroups,16973.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,128.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,0.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,44.0,hbm_rd_
 HBM Wr,0.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,70.0,vl1_coales_
 VL1 Stall,2.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,26.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/prev_analysis/201.csv
index 64f357eab5..bd1c4b7a5f 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,58.39724587605327,Pct,100,58.39724587605327
 MFMA Util,0.0,Pct,100,0.0
 VALU Active Threads/Wave,64.0,Threads,64,100.0
 IPC - Issue,1.0,Instr/cycle,5,20.0
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99260270867096,Pct,100,99.99260270867096
 Instr Cache BW,1674.6009481188678,Gb/s,6092.8,27.48491577138373
 Scalar L1D Cache Hit Rate,99.34855885953442,Pct,100,99.34855885953442
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/prev_analysis/602.csv
index 5625a3353f..2920415997 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,12008755.239520958,0,381642532,Simd
 Insufficient SIMD VGPRs,0.0,0,0,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/prev_analysis/701.csv
index 12250d77c0..db0925a109 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/sysinfo.csv
index e96e566c8b..44a06ad84c 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-mixbench,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 19:50:13 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,roofline|SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+mixbench,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 19:50:13 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,roofline|SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/timestamps.csv
index 03f961027c..6576dd6e25 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,23354,23354,33554432,256,0,0,4,32,4160,0x0,0x7f4663004280,14234006550491,14234006575542,14234006812983,14234006923263
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,23354,23354,32768,256,0,0,12,24,13888,0x0,0x7f4663023f80,14234011564888,14234011579879,14234011592839,14234011610787
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,23354,23354,4194304,256,0,0,12,24,14336,0x7f466603c380,0x7f4663023fc0,14234011615137,14234011664520,14234011757320,14234011759374
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/SQ_IFETCH_LEVEL.csv
index 68f71a81cc..b54f1f28f4 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/SQ_IFETCH_LEVEL.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,758500,758505,33554432,256,0,0,8,32,6464,0x0,0x7f7559a04180,502025,502025,524288,6291456,794052,101467620,12073347399839839,12073347643968623,12073347644291341,12073347644403873
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,758500,758505,32768,256,0,0,24,24,12480,0x0,0x7f7559a35100,28068,28068,512,8192,9319,1198588,12073347659044891,12073347659367851,12073347659374571,12073347659383340
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,758500,758505,4194304,256,0,0,24,24,12928,0x7f76655c5900,0x7f7559a35140,216739,216739,65536,917504,144440,18450532,12073347659442149,12073347659676169,12073347659808328,12073347659812297
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/SQ_INST_LEVEL_LDS.csv
index 1b90ecddc7..aa18d3885e 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/SQ_INST_LEVEL_LDS.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,760307,760312,33554432,256,0,0,8,32,6464,0x0,0x7f0a03a04180,0,0,0,12073373706548791,12073373951177370,12073373951501368,12073373951611411
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,760307,760312,32768,256,0,0,24,24,12480,0x0,0x7f0a03a35100,0,0,0,12073373965893753,12073373966201733,12073373966208773,12073373966219919
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,760307,760312,4194304,256,0,0,24,24,12928,0x7f0b33d44900,0x7f0a03a35140,0,0,0,12073373966280211,12073373966497732,12073373966636931,12073373966640911
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/SQ_INST_LEVEL_SMEM.csv
index 7e307530c6..882e1c3823 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/SQ_INST_LEVEL_SMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,759929,759934,33554432,256,0,0,8,32,6464,0x0,0x7fd40fa04180,4194304,3210336,411223016,12073371192092238,12073371432548179,12073371432871378,12073371432980200
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,759929,759934,32768,256,0,0,24,24,12480,0x0,0x7fd40fa35100,512,26450,3374080,12073371447235171,12073371447542389,12073371447549269,12073371447557791
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,759929,759934,4194304,256,0,0,24,24,12928,0x7fd53fc20900,0x7fd40fa35140,65536,197886,25315808,12073371447611902,12073371447832788,12073371447965907,12073371447969917
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/SQ_INST_LEVEL_VMEM.csv
index b7838c63cf..4185542869 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/SQ_INST_LEVEL_VMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,760119,760124,33554432,256,0,0,8,32,6464,0x0,0x7f8d7a804180,1048576,11210730,1434519032,12073372448537795,12073372693751982,12073372694076620,12073372694185923
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,760119,760124,32768,256,0,0,24,24,12480,0x0,0x7f8d7a835100,4096,127570,16336324,12073372708597826,12073372708902789,12073372708909349,12073372708914554
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,760119,760124,4194304,256,0,0,24,24,12928,0x7f8eaa803900,0x7f8d7a835140,524288,12691811,1624514652,12073372709024839,12073372709206147,12073372709337347,12073372709341438
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/SQ_LEVEL_WAVES.csv
index 9489899572..8cdad1b720 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/SQ_LEVEL_WAVES.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,760495,760502,33554432,256,0,0,8,32,6464,0x0,0x7f76c6a04180,504911,504911,16455,4039296,524288,373196986,3831476,0,1507598624,12073374958791827,12073375207820211,12073375208145489,12073375208258983
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,760495,760502,32768,256,0,0,24,24,12480,0x0,0x7f76c6a35100,27225,27225,19980,217808,512,1136173,76065,0,4559060,12073375222773026,12073375223115652,12073375223121892,12073375223137152
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,760495,760502,4194304,256,0,0,24,24,12928,0x7f77d26ce900,0x7f76c6a35140,224277,224277,23205,1794224,65536,138977639,1624444,0,557718588,12073375223197174,12073375223485090,12073375223622370,12073375223627704
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/pmc_dispatch_info.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/pmc_perf.csv
index 01ec68573e..58d4cf67d0 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBuffer.kd,0,0,0,759234,759239,33554432,256,0,0,8,32,6464,0x0,0x7f3ec6004180,1048576,0,1048576,9437184,0,4194304,1048576,0,499954,499954,57368724,55169509,208,13195814,54444950,54355501,55134848,53952159,3999632,3809036,499954,0,499954,0,15998528,15177958,0,0,0,0,0,17557448,1048576,0,505967,0,0,0,505967,0,0,0,505967,0,0,0,505967,0,0,0,505967,0,0,0,505967,0,0,0,505967,0,0,0,505967,0,0,0,505967,0,0,0,505967,0,0,0,505967,0,0,0,505967,0,0,0,505967,0,0,0,505967,0,0,0,505967,0,0,0,505967,0,0,0,505967,0,0,0,505967,0,0,0,505967,0,0,0,505967,0,0,0,505967,0,0,0,505967,0,0,0,505967,0,0,0,505967,0,0,0,505967,0,0,0,505967,0,0,0,505967,0,0,0,505967,0,0,0,505967,0,0,0,505967,0,0,0,505967,0,0,0,505967,0,0,0,37258526,48,0,0,0,5,0,0,0,2577,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2594,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2554,0,0,0,1,0,0,0,1,0,0,0,6,0,0,0,2642,0,0,0,0,0,0,0,0,0,0,0,23,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,48,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,1048576,0,0,3919716,131072,131072,0,1406,131072,131072,0,0,131072,131072,0,0,131076,131076,0,3083040,131072,131072,0,0,131076,131076,0,0,131072,131072,0,0,131080,131080,0,0,131072,131072,0,0,131072,131072,0,2109,131072,131072,0,0,131072,131072,0,8385,131072,131072,0,0,131076,131076,0,1123,131076,131076,0,0,131080,131080,0,0,131072,131072,0,781,131076,131076,0,0,131072,131072,0,0,131072,131072,0,1478,131076,131076,0,0,131072,131072,0,20057,131072,131072,0,0,131076,131076,0,3218765,131076,131076,0,0,131072,131072,0,0,131072,131072,0,0,131072,131072,0,2905078,131076,131076,0,0,131072,131072,0,272,131076,131076,0,19546,131076,131076,1048576,0,1983,0,0,17327561,1013,0,0,16918000,747,0,0,17332502,1178,0,0,17175141,1506,0,0,17488768,1286,0,0,17114384,1713,0,0,18347325,944,0,0,18451248,828,0,0,17284166,1085,0,0,16920602,985,0,0,17252393,45378,0,0,29149708,701,0,0,17602442,46504,0,0,29747789,1110,0,0,18268132,1147,0,0,18547344,1624,0,0,16850435,48637,0,0,29843842,1183,0,0,17300683,823,0,0,16885996,901,0,0,17397794,749,0,0,17216482,2106,0,0,18418989,48230,0,0,31301340,872,0,0,16903813,761,0,0,16740244,1409,0,0,17300448,1000,0,0,16849465,764,0,0,17316080,1409,0,0,17118424,876,0,0,18129653,783,0,0,18428425,1048576,131072,131072,0,262144,131260,131124,240,262384,131072,131072,0,262144,131072,131072,0,262144,131072,133733,2661,264805,131072,131072,0,262144,131072,131072,0,262144,131072,131120,48,262192,131072,133689,2617,264761,131072,131072,0,262144,131072,131075,3,262147,131119,131074,49,262193,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,133699,2627,264771,131072,131072,0,262144,131213,131075,144,262288,131072,131072,0,262144,131072,131072,0,262144,131072,133755,2683,264827,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131087,15,262159,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131119,131073,48,262192,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,262144,0,262144,262336,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262288,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,0,0,3145728,524288,32505856,376643535,220109540,124028139,478265,0,0,0,1048576,52525778,52330213,1048576,1048576,131072,524288,712,500703,4313,0,96,10397,0,8388944,32505856,4021776,3815038,57063066,11534336,0,0,14155776,67108864,67108864,0,67108864,54170242,53850679,0,1048576,238380,762668,11781,2339,0,498394,8399693,0,4194727,4204966,13631488,0,3670016,1048576,1048576,0,4194304,9437184,0,0,360,33554432,54581329,4194304,0,0,2408,504184,0,11326,8388608,0,4194338,905969664,6291456,0,0,0,524288,524288,0,15338,16608580,0,16777216,4194304,4194304,0,0,0,18165,4194348,4194348,0,222480,0,0,0,33554432,0,0,0,0,644677036,0,2816287853,0,0,0,0,0,474252,0,0,216197,0,0,8388608,336,144,0,0,0,480,8388608,0,0,0,0,352453,0,0,0,11042,0,22066,0,6291456,6289552,96,2029,2085871,0,0,0,0,0,0,0,0,0,3145728,0,0,0,152681,4194304,4189865,144,4295,2097152,524288,1572864,0,0,0,0,0,0,524288,0,4128816,65532,4063247,0,0,8388608,0,42585385,0,1048576,10734,4194352,12945151,608053680,12073349528697231,12073376112577260,12073376112901737,12073349770897962
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,759234,759239,32768,256,0,0,24,24,12480,0x0,0x7f3ec6035100,0,4096,4096,512,0,512,4096,0,27881,27881,1472267,645861,161,130577,86784,68798,637800,617326,223048,83971,27881,0,27881,0,892192,206991,0,0,0,0,0,55107,4096,0,28170,0,0,0,28170,0,0,0,28170,0,0,0,28170,0,0,0,28170,0,0,0,28170,0,0,0,28170,0,0,0,28170,0,0,0,28170,0,0,0,28170,0,0,0,28170,0,0,0,28170,0,0,0,28170,0,0,0,28170,0,0,0,28170,0,0,0,28170,0,0,0,28170,0,0,0,28170,0,0,0,28170,0,0,0,28170,0,0,0,28170,0,0,0,28170,0,0,0,28170,0,0,0,28170,0,0,0,28170,0,0,0,28170,0,0,0,28170,0,0,0,28170,0,0,0,28170,0,0,0,28170,0,0,0,28170,0,0,0,28170,0,0,0,0,304,0,0,0,257,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,261,0,0,0,256,0,0,0,256,0,0,0,377,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,257,0,0,0,4096,4096,0,116512,0,0,0,142508,0,0,0,73137,0,0,0,91529,0,0,0,85161,0,0,0,164708,0,0,0,98544,0,0,0,90748,0,0,0,99455,0,0,0,93216,0,0,0,76348,0,0,0,96549,0,0,0,204776,0,0,0,91992,0,0,0,89928,0,0,0,79716,0,0,0,131902,0,0,0,121382,0,0,0,80495,0,0,0,121803,0,0,0,116636,0,0,0,119444,0,0,0,131865,0,0,0,99656,0,0,0,89673,0,0,0,86118,0,0,0,91498,0,0,0,73161,0,0,0,80023,0,0,0,77851,0,0,0,81497,0,0,0,96958,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4096,0,256,256,256,0,304,304,304,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,257,257,257,0,256,256,256,0,256,256,256,188,260,448,448,0,256,256,256,0,256,256,256,0,256,256,256,188,260,448,448,0,256,256,256,0,257,257,257,0,256,256,256,0,256,256,256,0,256,256,256,0,377,377,377,0,256,256,256,0,256,256,256,0,256,256,256,47,257,304,304,0,256,256,256,47,257,304,304,0,256,256,256,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,304,0,0,256,0,0,0,0,512,512,35328,1161164,1105697,19115,11825,0,0,0,4096,64927,61919,4096,4096,128,512,638,27678,4476,0,48,220,0,8624,36352,226296,78761,1095897,26624,0,0,30208,65536,65536,65536,0,0,0,0,0,116,628,12000,2106,0,23875,8891,0,470,8421,1024,0,1024,4096,0,4096,512,512,0,0,360,16384,0,16384,0,0,2374,25472,0,8963,0,0,31,1933312,8192,0,0,0,512,512,0,120,15064,0,16384,16384,0,0,0,0,21458,0,0,0,0,0,0,0,32768,0,0,0,0,12528197,17337981,0,8192,0,0,0,0,695,0,0,0,0,0,1024,432,48,0,0,0,480,0,0,0,0,0,2863,0,0,0,8541,0,678,0,8192,6591,48,1553,1090,0,0,0,0,0,0,0,0,0,2560,0,0,0,53416,512,0,48,464,0,512,0,0,0,0,0,0,0,512,0,0,0,0,0,8192,0,0,468266,0,4096,8420,0,3437427,0,12073349785862412,12073376127912772,12073376127919491,12073349786853854
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,759234,759239,4194304,256,0,0,24,24,12928,0x7f3fd1bdb900,0x7f3ec6035140,0,524288,524288,65536,0,65536,524288,0,222628,222628,24806387,23646636,29809,6902063,23245767,23166242,23636052,21477714,1781024,1636925,222628,0,222628,0,7124096,6434867,0,0,0,0,0,20158238,524288,0,215767,0,0,0,215767,0,0,0,215767,0,0,0,215767,0,0,0,215767,0,0,0,215767,0,0,0,215767,0,0,0,215767,0,0,0,215767,0,0,0,215767,0,0,0,215767,0,0,0,215767,0,0,0,215767,0,0,0,215767,0,0,0,215767,0,0,0,215767,0,0,0,215767,0,0,0,215767,0,0,0,215767,0,0,0,215767,0,0,0,215767,0,0,0,215767,0,0,0,215767,0,0,0,215767,0,0,0,215767,0,0,0,215767,0,0,0,215767,0,0,0,215767,0,0,0,215767,0,0,0,215767,0,0,0,215767,0,0,0,215767,0,0,0,0,65584,0,0,0,65537,0,3716,0,65541,0,11079,0,65536,0,4993,0,65536,0,17980,0,65536,0,4374,0,65536,0,7696,0,65536,0,10604,0,65536,0,0,0,67967,0,88752,0,65536,0,5995,0,65536,0,15575,0,65536,0,10278,0,65536,0,8702,0,67208,0,52546,0,65536,0,2048,0,65537,0,422,0,65536,0,10311,0,65537,0,4301,0,65536,0,1093,0,65536,0,4886,0,65657,0,5816,0,65536,0,5035,0,65536,0,0,0,65536,0,1785,0,65536,0,3774,0,65536,0,1359,0,65536,0,2459,0,65536,0,4194,0,65536,0,7656,0,65540,0,6166,0,65537,0,3244,0,524288,524288,0,49628431,0,0,0,36062672,0,0,0,33343795,0,0,0,33997175,0,0,0,33904621,0,0,0,40944448,0,0,0,35226439,0,0,0,32297513,0,0,0,29926715,0,0,0,31813196,0,0,0,33720673,0,0,0,33605246,0,0,0,31652245,0,0,0,39910515,0,0,0,32586877,0,0,0,37159627,0,0,0,31663864,0,0,0,37122507,0,0,0,32331610,0,0,0,34201762,0,0,0,31762129,0,0,0,37575814,0,0,0,37274504,0,0,0,32311508,0,0,0,36963230,0,0,0,42853776,0,0,0,32572380,0,0,0,32068402,0,0,0,42129250,0,0,0,30144900,0,0,0,34372257,0,0,0,36925471,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,524288,0,65536,65536,65536,0,65584,65584,65584,188,65540,65728,65728,0,65536,65536,65536,0,66589,66589,66589,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65537,65537,65537,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,66206,66206,66206,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65657,65657,65657,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,47,65537,65584,65584,0,65536,65536,65536,188,65540,65728,65728,0,65536,65536,65536,65536,0,0,65536,0,0,65728,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65728,0,0,65536,0,0,0,0,65536,65536,4128768,156396332,51854971,100281521,200125,0,0,0,524288,22725474,22723074,524288,524288,16384,65536,802,218184,4289,0,48,2813,0,2097536,4259840,1792096,1616555,23952693,3014656,0,0,3473408,8388608,8388608,8388608,0,0,0,0,0,154774,188035,11966,2554,0,219742,2101932,0,423,2101509,131072,0,131072,524288,0,524288,65536,65536,0,0,360,2097152,0,2097152,48861,0,2868,211073,0,2099560,0,0,31,222298112,917504,0,0,0,65536,65536,0,7618,2017308,0,2097152,2097152,0,696156,698364,0,23592,0,0,0,0,0,0,0,4194304,0,0,0,0,984967684,1648843082,0,2097152,0,0,0,0,193107,0,0,0,0,0,131072,384,48,0,0,0,432,0,0,0,0,0,5955,0,0,0,2100130,0,5938,0,917504,915019,48,7199,178512,0,0,0,0,0,0,0,0,0,327680,0,0,422549,475795,65536,64048,48,1440,0,65536,0,0,0,0,0,0,0,65536,0,0,0,1966100,0,2097152,0,0,13945394,0,524288,2101995,0,855343029,0,12073349787490798,12073376127985571,12073376128118210,12073349788734820
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/prev_analysis/1.csv
index dc2b71189d..b70f271584 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,6055636.0,6055636.0,6055636.0,9.154838625309887
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4526048.0,4526048.0,4526048.0,6.842425642889792
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 256u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,3053578.0,3053578.0,3053578.0,4.616362974887612
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/prev_analysis/1001.csv
index ca08330db0..0e3bf5267e 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,46.862275449101794,Instr per wave
 SMEM,1.8083832335329342,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/prev_analysis/101.csv
index de0e090884..743af3d69f 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx908
 mi100
 48
 1228.8
-SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/prev_analysis/1202.csv
index 0fed2dac2d..1694156ad7 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,33809.10240525114,2873.562126159668,547953.1559448242,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/prev_analysis/1901.csv
index deeb507de9..2cc4fdb5f7 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,2.0,smem_
 VALU,735.0,valu_
 MFMA,,mfma_
 VMEM,8.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,22.0,br_
 VGPR,24.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,67894.0,wavefronts_
 Workgroups,16973.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,163.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,0.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,44.0,hbm_rd_
 HBM Wr,0.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,70.0,vl1_coales_
 VL1 Stall,30.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,35.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/prev_analysis/2001.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/prev_analysis/201.csv
index 6083dd4dce..da9c1800df 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,59.66032992298727,Pct,100,59.66032992298727
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,63.96711447565662,Threads,64,99.94861636821348
 IPC - Issue,0.8437200043615126,Instr/cycle,5,16.874400087230253
-LDS BW,0.0,Gb/sec,23070.72,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,23070.72,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99346241688589,Pct,100,99.99346241688589
 Instr Cache BW,1407.913501244597,Gb/s,4614.144,30.51299441986633
 Scalar L1D Cache Hit Rate,99.35620448528375,Pct,100,99.35620448528375
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/prev_analysis/602.csv
index 1601edcf26..57d0f526e3 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,60861.4131736527,0,696156,Simd
 Insufficient SIMD VGPRs,652798.8443113773,0,37562897,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/prev_analysis/701.csv
index d3f1bff5a3..1071413faa 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,23.976047904191617,8,36,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/sysinfo.csv
index e6aff62148..8dfe2eefc6 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-mixbench1,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 10:42:02 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+mixbench1,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 10:42:02 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/timestamps.csv
index 1501973320..fc3e687c65 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench1/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,760546,760551,33554432,256,0,0,8,32,6464,0x0,0x7f3c31e04180,12073376112529333,12073376112577260,12073376112901737,12073376113022259
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,760546,760551,32768,256,0,0,24,24,12480,0x0,0x7f3c31e35100,12073376127807245,12073376127912772,12073376127919491,12073376127924924
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,760546,760551,4194304,256,0,0,24,24,12928,0x7f3d3d9a9900,0x7f3c31e35140,12073376127971200,12073376127985571,12073376128118210,12073376128121519
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench1/mi200/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/mixbench1/mi200/SQ_IFETCH_LEVEL.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench1/mi200/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench1/mi200/SQ_IFETCH_LEVEL.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench1/mi200/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/mixbench1/mi200/SQ_INST_LEVEL_LDS.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench1/mi200/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench1/mi200/SQ_INST_LEVEL_LDS.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench1/mi200/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/mixbench1/mi200/SQ_INST_LEVEL_SMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench1/mi200/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench1/mi200/SQ_INST_LEVEL_SMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench1/mi200/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/mixbench1/mi200/SQ_INST_LEVEL_VMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench1/mi200/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench1/mi200/SQ_INST_LEVEL_VMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench1/mi200/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/mixbench1/mi200/SQ_LEVEL_WAVES.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench1/mi200/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench1/mi200/SQ_LEVEL_WAVES.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench1/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/mixbench1/mi200/pmc_perf.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench1/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench1/mi200/pmc_perf.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench1/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/mixbench1/mi200/timestamps.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench1/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench1/mi200/timestamps.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/SQ_IFETCH_LEVEL.csv
index 3672861b1d..6f721dbd87 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/SQ_IFETCH_LEVEL.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,763517,763522,33554432,256,0,0,8,32,6464,0x0,0x7f1e10e04180,505857,505857,524288,6291456,792695,101403392,12073442306812763,12073442552623215,12073442552948813,12073442553060085
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,763517,763522,32768,256,0,0,24,24,12480,0x0,0x7f1e10e35100,28539,28539,512,8192,9217,1173568,12073442567379506,12073442567681010,12073442567687570,12073442567692658
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,763517,763522,4194304,256,0,0,24,24,12928,0x7f1f1ca96900,0x7f1e10e35140,214259,214259,65536,917504,142240,18192764,12073442567759682,12073442567986768,12073442568117488,12073442568121335
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/SQ_INST_LEVEL_LDS.csv
index 9bd3f6d2a0..4233f42f53 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/SQ_INST_LEVEL_LDS.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,765313,765318,33554432,256,0,0,8,32,6464,0x0,0x7ff8ae404180,0,0,0,12073468737376926,12073468985213188,12073468985537186,12073468985669598
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,765313,765318,32768,256,0,0,24,24,12480,0x0,0x7ff8ae435100,0,0,0,12073469000047208,12073469000350751,12073469000356671,12073469000362053
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,765313,765318,4194304,256,0,0,24,24,12928,0x7ff9ba03a900,0x7ff8ae435140,0,0,0,12073469000421423,12073469000627550,12073469000756829,12073469000760573
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/SQ_INST_LEVEL_SMEM.csv
index 2fe12be401..3f50caef77 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/SQ_INST_LEVEL_SMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,764935,764940,33554432,256,0,0,8,32,6464,0x0,0x7f8a19404180,4194304,3088996,395039432,12073466213072332,12073466456014836,12073466456339634,12073466456458346
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,764935,764940,32768,256,0,0,24,24,12480,0x0,0x7f8a19435100,512,22210,2831400,12073466471032120,12073466471333596,12073466471340476,12073466471353988
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,764935,764940,4194304,256,0,0,24,24,12928,0x7f8b25119900,0x7f8a19435140,65536,171692,21946688,12073466471404091,12073466471620475,12073466471755514,12073466471759442
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/SQ_INST_LEVEL_VMEM.csv
index 8b4c4ec851..1a1467a0d7 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/SQ_INST_LEVEL_VMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,765125,765130,33554432,256,0,0,8,32,6464,0x0,0x7f1f67204180,1048576,11164777,1429239040,12073467472462070,12073467715806481,12073467716131280,12073467716223251
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,765125,765130,32768,256,0,0,24,24,12480,0x0,0x7f1f67235100,4096,115725,14817852,12073467730930413,12073467731240451,12073467731247011,12073467731258703
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,765125,765130,4194304,256,0,0,24,24,12928,0x7f20972e5900,0x7f1f67235140,524288,11904931,1523805584,12073467731354080,12073467731525889,12073467731659649,12073467731663165
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/SQ_LEVEL_WAVES.csv
index e755024ec2..2914d9e484 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/SQ_LEVEL_WAVES.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,765503,765510,33554432,256,0,0,8,32,6464,0x0,0x7f65f6004180,501856,501856,16346,4014856,524288,366708977,3812433,0,1481613900,12073470011139173,12073470255482540,12073470255805098,12073470255915021
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,765503,765510,32768,256,0,0,24,24,12480,0x0,0x7f65f6035100,27403,27403,19985,219232,512,1137524,75847,0,4564300,12073470270607725,12073470270932615,12073470270939015,12073470270947537
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,765503,765510,4194304,256,0,0,24,24,12928,0x7f6701ba7900,0x7f65f6035140,221893,221893,21442,1775152,65536,112188834,1606361,0,450565024,12073470271020893,12073470271291013,12073470271426372,12073470271430685
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/pmc_dispatch_info.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/pmc_perf.csv
index 2866d701ea..c0a9b305f5 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBuffer.kd,0,0,0,764251,764256,33554432,256,0,0,8,32,6464,0x0,0x7f93b8204180,1048576,0,1048576,9437184,0,4194304,1048576,0,507779,507779,58229879,55465888,153,11617062,54416483,54289627,55399407,54217516,4062232,3866448,507779,0,507779,0,16248928,15340904,0,0,0,0,0,17090006,1048576,0,501423,0,0,0,501423,0,0,0,501423,0,0,0,501423,0,0,0,501423,0,0,0,501423,0,0,0,501423,0,0,0,501423,0,0,0,501423,0,0,0,501423,0,0,0,501423,0,0,0,501423,0,0,0,501423,0,0,0,501423,0,0,0,501423,0,0,0,501423,0,0,0,501423,0,0,0,501423,0,0,0,501423,0,0,0,501423,0,0,0,501423,0,0,0,501423,0,0,0,501423,0,0,0,501423,0,0,0,501423,0,0,0,501423,0,0,0,501423,0,0,0,501423,0,0,0,501423,0,0,0,501423,0,0,0,501423,0,0,0,501423,0,0,0,37320958,0,0,0,0,52,0,0,0,1,0,0,0,2555,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,2574,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,48,0,0,0,0,0,0,0,0,0,0,0,21,0,0,0,2,0,0,0,3,0,0,0,0,0,0,0,2560,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,2671,0,0,0,1048576,0,0,566684,131072,131072,0,20661,131072,131072,0,0,131072,131072,0,0,131076,131076,0,6999,131080,131080,0,0,131072,131072,0,0,131072,131072,0,0,131076,131076,0,3354879,131077,131077,0,0,131076,131076,0,0,131076,131076,0,0,131072,131072,0,0,131072,131072,0,0,131072,131072,0,0,131076,131076,0,3371276,131076,131076,0,1171,131072,131072,0,784,131076,131076,0,0,131076,131076,0,3136737,131088,131088,0,3169549,131072,131072,0,1408,131084,131084,0,0,131072,131072,0,390,131072,131072,0,258,131076,131076,0,0,131076,131076,0,0,131076,131076,0,0,131076,131076,0,0,131080,131080,0,0,131076,131076,0,0,131076,131076,0,0,131076,131076,1048576,0,940,0,0,16795145,774,0,0,17065247,725,0,0,17334615,851,0,0,17228244,1595,0,0,17277549,1107,0,0,17534990,844,0,0,18008256,1709,0,0,18811563,1114,0,0,16844911,823,0,0,17301348,1046,0,0,17088608,1097,0,0,16977251,46882,0,0,29804142,903,0,0,17477736,908,0,0,18052572,750,0,0,18771445,47195,0,0,29552521,1067,0,0,16768820,799,0,0,17084488,954,0,0,17182065,762,0,0,16965227,893,0,0,17253335,42445,0,0,30325153,904,0,0,18781505,1086,0,0,16682810,1847,0,0,16862130,1410,0,0,16867246,1148,0,0,17050848,46907,0,0,29752311,806,0,0,17411772,1612,0,0,18188074,1337,0,0,18877157,1048576,131072,131123,51,262195,131260,133568,2684,264828,131072,131072,0,262144,131072,131120,48,262192,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131119,131073,48,262192,131072,131072,0,262144,131072,131120,48,262192,131072,133779,2707,264851,131072,131073,1,262145,131072,131072,0,262144,131072,131072,0,262144,131213,133717,2786,264930,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131119,131073,48,262192,131072,131072,0,262144,131072,131144,72,262216,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,133686,2614,264758,131072,131073,1,262145,131072,131072,0,262144,262144,0,262144,262336,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262288,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,0,0,3145728,524288,32505856,372113542,218514571,121093115,483253,0,0,0,1048576,52935456,52708180,1048576,1048576,131072,524288,696,504857,4299,0,96,10801,0,8388944,32505856,4020496,3809596,56984872,11534336,0,0,14155776,67108864,67108864,0,67108864,54246125,53926498,0,1048576,232760,757048,12065,2014,0,498402,8399722,0,4194727,4204995,13631488,0,3670016,1048576,1048576,0,4194304,9437184,0,0,360,33554432,54025452,4194304,0,0,2832,500961,0,11166,8388608,0,4194390,905969664,6291456,0,0,0,524288,524288,0,15346,16608587,0,16777216,4194304,4194304,0,0,0,17015,4194384,4194384,0,220853,0,0,0,33554432,0,0,0,0,649295553,0,2836890478,0,0,0,0,0,479419,0,0,229904,0,0,8388608,336,144,0,0,0,480,8388608,0,0,0,0,360510,0,0,0,10763,0,21508,0,6291456,6289506,96,2044,1906692,0,0,0,0,0,0,0,0,0,3145728,0,0,0,142517,4194304,4189863,144,4297,2097152,524288,1572864,0,0,0,0,0,0,524288,0,4128822,65536,4063247,0,0,8388608,0,42418791,0,1048576,10897,4194392,13019053,610659940,12073444420576705,12073471150180445,12073471150503642,12073444668915885
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,764251,764256,32768,256,0,0,24,24,12480,0x0,0x7f93b8235100,0,4096,4096,512,0,512,4096,0,29352,29352,1525067,616680,244,121371,85554,68583,608592,588008,234816,87499,29352,0,29352,0,939264,208239,0,0,0,0,0,94949,4096,0,27371,0,0,0,27371,0,0,0,27371,0,0,0,27371,0,0,0,27371,0,0,0,27371,0,0,0,27371,0,0,0,27371,0,0,0,27371,0,0,0,27371,0,0,0,27371,0,0,0,27371,0,0,0,27371,0,0,0,27371,0,0,0,27371,0,0,0,27371,0,0,0,27371,0,0,0,27371,0,0,0,27371,0,0,0,27371,0,0,0,27371,0,0,0,27371,0,0,0,27371,0,0,0,27371,0,0,0,27371,0,0,0,27371,0,0,0,27371,0,0,0,27371,0,0,0,27371,0,0,0,27371,0,0,0,27371,0,0,0,27371,0,0,0,0,256,0,0,0,304,0,0,0,257,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,260,0,0,0,376,0,0,0,256,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,257,0,0,0,256,0,0,0,4096,4096,0,151685,0,0,0,148252,0,0,0,90012,0,0,0,91964,0,0,0,172311,0,0,0,131726,0,0,0,101799,0,0,0,97329,0,0,0,81222,0,0,0,79394,0,0,0,107916,0,0,0,94263,0,0,0,87831,0,0,0,76001,0,0,0,70709,0,0,0,80587,0,0,0,144927,0,0,0,90860,0,0,0,74347,0,0,0,92038,0,0,0,99788,0,0,0,97049,0,0,0,92084,0,0,0,90373,0,0,0,121520,0,0,0,97757,0,0,0,79110,0,0,0,76628,0,0,0,117015,0,0,0,126415,0,0,0,86907,0,0,0,81011,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4096,0,304,304,304,0,256,256,256,0,256,256,256,0,304,304,304,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,188,261,449,449,0,256,256,256,0,256,256,256,0,256,256,256,188,260,448,448,0,256,256,256,0,256,256,256,47,257,304,304,0,256,256,256,0,377,377,377,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,47,258,305,305,0,256,256,256,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,304,0,0,256,0,0,0,0,512,512,35328,1059819,1008300,15167,11052,0,0,0,4096,61940,58885,4096,4096,128,512,607,26266,4267,0,48,219,0,8624,36352,220832,73063,1033620,26624,0,0,30208,65536,65536,65536,0,0,0,0,0,114,626,12346,2019,0,23271,8891,0,470,8421,1024,0,1024,4096,0,4096,512,512,0,0,360,16384,0,16384,0,0,2895,24628,0,8892,0,0,31,1933312,8192,0,0,0,512,512,0,120,15064,0,16384,16384,0,0,0,0,20858,0,0,0,0,0,0,0,32768,0,0,0,0,10642704,13238519,0,8192,0,0,0,0,694,0,0,0,0,0,1024,432,48,0,0,0,480,0,0,0,0,0,2908,0,0,0,8422,0,440,0,8192,6560,48,1584,1078,0,0,0,0,0,0,0,0,0,2560,0,0,0,50160,512,0,48,464,0,512,0,0,0,0,0,0,0,512,0,0,0,0,0,8192,0,0,423411,0,4096,8420,0,3117642,0,12073444683773506,12073471165655391,12073471165662111,12073444684782150
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,764251,764256,4194304,256,0,0,24,24,12928,0x7f94c36a2900,0x7f93b8235140,0,524288,524288,65536,0,65536,524288,0,225276,225276,24956867,23725295,30334,6577381,22885504,22754200,23711904,21549263,1802208,1647805,225276,0,225276,0,7208832,6495459,0,0,0,0,0,20951393,524288,0,226618,0,0,0,226618,0,0,0,226618,0,0,0,226618,0,0,0,226618,0,0,0,226618,0,0,0,226618,0,0,0,226618,0,0,0,226618,0,0,0,226618,0,0,0,226618,0,0,0,226618,0,0,0,226618,0,0,0,226618,0,0,0,226618,0,0,0,226618,0,0,0,226618,0,0,0,226618,0,0,0,226618,0,0,0,226618,0,0,0,226618,0,0,0,226618,0,0,0,226618,0,0,0,226618,0,0,0,226618,0,0,0,226618,0,0,0,226618,0,0,0,226618,0,0,0,226618,0,0,0,226618,0,0,0,226618,0,0,0,226618,0,0,0,0,65536,0,0,0,65584,0,6893,0,65541,0,1080,0,67460,0,55444,0,65537,0,18993,0,65536,0,0,0,65536,0,4614,0,65536,0,4185,0,65536,0,5438,0,65536,0,3867,0,65536,0,3016,0,65536,0,732,0,65536,0,2675,0,65536,0,2965,0,65536,0,3360,0,65656,0,3405,0,65536,0,7056,0,65536,0,3942,0,65536,0,1587,0,68308,0,71648,0,65537,0,182,0,65536,0,2610,0,65536,0,6068,0,65536,0,2527,0,65537,0,4468,0,65536,0,3,0,65536,0,422,0,65536,0,4454,0,65536,0,3848,0,65537,0,641,0,65540,0,18906,0,65536,0,1388,0,524288,524288,0,37451158,0,0,0,34485548,0,0,0,34052769,0,0,0,40547591,0,0,0,41623262,0,0,0,33492800,0,0,0,34165019,0,0,0,38956514,0,0,0,51132491,0,0,0,29706411,0,0,0,31242167,0,0,0,29240010,0,0,0,33623783,0,0,0,32235023,0,0,0,30163896,0,0,0,34173510,0,0,0,31450937,0,0,0,33143346,0,0,0,31110599,0,0,0,32292674,0,0,0,36948637,0,0,0,31725056,0,0,0,36104575,0,0,0,30700405,0,0,0,31862024,0,0,0,37570616,0,0,0,31905466,0,0,0,36717370,0,0,0,28324976,0,0,0,27073433,0,0,0,33502029,0,0,0,32208892,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,524288,0,65584,65584,65584,0,65536,65536,65536,188,65540,65728,65728,0,65584,65584,65584,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,67486,67486,67486,0,65537,65537,65537,0,65536,65536,65536,0,65536,65536,65536,0,66712,66712,66712,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,47,65537,65584,65584,0,65536,65536,65536,0,65846,65846,65846,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,188,65541,65729,65729,0,65536,65536,65536,65536,0,0,65536,0,0,65728,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65728,0,0,65536,0,0,0,0,65536,65536,4128768,119668832,46548185,68860807,206057,0,0,0,524288,22098672,22084685,524288,524288,16384,65536,771,223679,4119,0,48,4233,0,2097536,4259840,1752928,1580722,23430796,3014656,0,0,3473408,8388608,8388608,8388608,0,0,0,0,0,197756,221510,12344,2162,0,214910,2100578,0,423,2100155,131072,0,131072,524288,0,524288,65536,65536,0,0,360,2097152,0,2097152,39426,0,2807,213814,0,2100270,0,0,31,222298112,917504,0,0,0,65536,65536,0,7603,2018752,0,2097152,2097152,0,638576,640789,0,22664,0,0,0,0,0,0,0,4194304,0,0,0,0,1077667862,1831347907,0,2097152,0,0,0,0,190310,0,0,0,0,0,131072,384,48,0,0,0,432,0,0,0,0,0,8154,0,0,0,2099868,0,5414,0,917504,914820,66,5156,100141,0,0,0,0,0,0,0,0,0,327680,0,0,250355,303735,65536,64048,48,1440,0,65536,0,0,0,0,0,0,0,65536,0,0,0,1966099,0,2097152,0,0,16339422,0,524288,2100159,0,1114629258,0,12073444685415698,12073471165728510,12073471165861469,12073444686662144
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/prev_analysis/1.csv
index 708e9859e4..8e8174e3a7 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,6054357.0,6054357.0,6054357.0,9.182914276725624
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4527167.0,4527167.0,4527167.0,6.86655684120066
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 256u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,3052618.0,3052618.0,3052618.0,4.630042366776458
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/prev_analysis/1001.csv
index ca08330db0..0e3bf5267e 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,46.862275449101794,Instr per wave
 SMEM,1.8083832335329342,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/prev_analysis/101.csv
index 8f2cdcdd25..216962f889 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx908
 mi100
 48
 1228.8
-SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/prev_analysis/1202.csv
index 0e0b352af9..0a379c33c6 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,33616.59130155826,2839.001022338867,547893.5391845703,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/prev_analysis/1901.csv
index e3a2433b0c..b7c8354da6 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,2.0,smem_
 VALU,735.0,valu_
 MFMA,,mfma_
 VMEM,8.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,22.0,br_
 VGPR,24.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,67894.0,wavefronts_
 Workgroups,16973.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,163.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,0.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,44.0,hbm_rd_
 HBM Wr,0.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,70.0,vl1_coales_
 VL1 Stall,29.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,36.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/prev_analysis/2001.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/prev_analysis/201.csv
index adcf6e24ee..46b321dc6b 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,59.534571435160466,Pct,100,59.534571435160466
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,63.96928081497505,Threads,64,99.95200127339852
 IPC - Issue,0.8437395592663128,Instr/cycle,5,16.874791185326256
-LDS BW,0.0,Gb/sec,23070.72,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,23070.72,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99338612907806,Pct,100,99.99338612907806
 Instr Cache BW,1411.4356645209625,Gb/s,4614.144,30.58932847611523
 Scalar L1D Cache Hit Rate,99.35620448527392,Pct,100,99.35620448527392
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/prev_analysis/602.csv
index b4cb3c7a71..6b080488c5 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,65504.748502994014,0,685113,Simd
 Insufficient SIMD VGPRs,638510.4790419162,0,48660107,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/prev_analysis/701.csv
index d3f1bff5a3..1071413faa 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,23.976047904191617,8,36,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/sysinfo.csv
index 21f471901d..8fca3d146c 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-mixbench2,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 10:43:37 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+mixbench2,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 10:43:37 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/timestamps.csv
index e81c9afc51..23f6485d8e 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench2/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,765554,765559,33554432,256,0,0,8,32,6464,0x0,0x7f0e76604180,12073471150134913,12073471150180445,12073471150503642,12073471150608594
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,765554,765559,32768,256,0,0,24,24,12480,0x0,0x7f0e76635100,12073471165551002,12073471165655391,12073471165662111,12073471165667819
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,765554,765559,4194304,256,0,0,24,24,12928,0x7f0f82213900,0x7f0e76635140,12073471165715197,12073471165728510,12073471165861469,12073471165864916
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench2/mi200/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/mixbench2/mi200/SQ_IFETCH_LEVEL.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench2/mi200/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench2/mi200/SQ_IFETCH_LEVEL.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench2/mi200/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/mixbench2/mi200/SQ_INST_LEVEL_LDS.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench2/mi200/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench2/mi200/SQ_INST_LEVEL_LDS.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench2/mi200/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/mixbench2/mi200/SQ_INST_LEVEL_SMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench2/mi200/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench2/mi200/SQ_INST_LEVEL_SMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench2/mi200/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/mixbench2/mi200/SQ_INST_LEVEL_VMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench2/mi200/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench2/mi200/SQ_INST_LEVEL_VMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench2/mi200/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/mixbench2/mi200/SQ_LEVEL_WAVES.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench2/mi200/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench2/mi200/SQ_LEVEL_WAVES.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench2/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/mixbench2/mi200/pmc_perf.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench2/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench2/mi200/pmc_perf.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/mixbench2/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/mixbench2/mi200/timestamps.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/mixbench2/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/mixbench2/mi200/timestamps.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/SQ_IFETCH_LEVEL.csv
index 257d4ba8e7..854d90f9d7 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/SQ_IFETCH_LEVEL.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,901964,901969,33554432,256,0,0,8,32,6464,0x0,0x7fed4a404180,501457,501457,524288,6291456,793160,101524016,12075961505626104,12075961751812588,12075961752134666,12075961752247178
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,901964,901969,32768,256,0,0,24,24,12480,0x0,0x7fed4a435100,28249,28249,512,8192,8694,1111424,12075961766559127,12075961766877182,12075961766883422,12075961766892236
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,901964,901969,4194304,256,0,0,24,24,12928,0x7fee5611e900,0x7fed4a435140,212555,212555,65536,917504,140582,17993116,12075961766953830,12075961767182781,12075961767312060,12075961767316504
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/SQ_INST_LEVEL_LDS.csv
index 0be6bee558..cc0639b45b 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/SQ_INST_LEVEL_LDS.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,903759,903764,33554432,256,0,0,8,32,6464,0x0,0x7f53db204180,0,0,0,12075987805386063,12075988049722700,12075988050044458,12075988050184580
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,903759,903764,32768,256,0,0,24,24,12480,0x0,0x7f53db235100,0,0,0,12075988064789753,12075988065097744,12075988065104144,12075988065109137
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,903759,903764,4194304,256,0,0,24,24,12928,0x7f550b3e9900,0x7f53db235140,0,0,0,12075988065169810,12075988065389102,12075988065521902,12075988065525811
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/SQ_INST_LEVEL_SMEM.csv
index cf10ea3175..3f3a6830e3 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/SQ_INST_LEVEL_SMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,903381,903386,33554432,256,0,0,8,32,6464,0x0,0x7f512de04180,4194304,3112556,398242416,12075985296706634,12075985540551694,12075985540880492,12075985540990244
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,903381,903386,32768,256,0,0,24,24,12480,0x0,0x7f512de35100,512,24156,3071728,12075985555688149,12075985555990096,12075985555996496,12075985556017181
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,903381,903386,4194304,256,0,0,24,24,12928,0x7f5239af0900,0x7f512de35140,65536,176006,22562976,12075985556066773,12075985556279854,12075985556419054,12075985556423245
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/SQ_INST_LEVEL_VMEM.csv
index ae35d4ca3a..2a5c3ae92f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/SQ_INST_LEVEL_VMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,903571,903576,33554432,256,0,0,8,32,6464,0x0,0x7fb41e804180,1048576,11136750,1425940888,12075986545718036,12075986791214310,12075986791537028,12075986791644820
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,903571,903576,32768,256,0,0,24,24,12480,0x0,0x7fb41e835100,4096,118604,15186140,12075986805999137,12075986806313157,12075986806319717,12075986806328910
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,903571,903576,4194304,256,0,0,24,24,12928,0x7fb52a37a900,0x7fb41e835140,524288,12244426,1567291836,12075986806388330,12075986806599875,12075986806732035,12075986806736137
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/SQ_LEVEL_WAVES.csv
index f04448c7e5..d25917d0d4 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/SQ_LEVEL_WAVES.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,903948,903955,33554432,256,0,0,8,32,6464,0x0,0x7f1d04204180,504333,504333,16091,4034672,524288,369062523,3831335,0,1491090904,12075989053419759,12075989299925092,12075989300249571,12075989300363653
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,903948,903955,32768,256,0,0,24,24,12480,0x0,0x7f1d04235100,28712,28712,21410,229704,512,1109874,73578,0,4453612,12075989314689156,12075989315026631,12075989315033031,12075989315038996
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,903948,903955,4194304,256,0,0,24,24,12928,0x7f1e0f6ce900,0x7f1d04235140,224220,224220,22555,1793768,65536,141478865,1619962,0,567727788,12075989315114106,12075989315351110,12075989315487749,12075989315491117
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/pmc_dispatch_info.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/pmc_perf.csv
index 9d65ba2102..c7fe3cc3bb 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBuffer.kd,0,0,0,902698,902703,33554432,256,0,0,8,32,6464,0x0,0x7f3d29004180,1048576,0,1048576,9437184,0,4194304,1048576,0,501891,501891,57539917,55320286,141,12592926,54516693,54424345,55289399,54115139,4015128,3820460,501891,0,501891,0,16060512,15175500,0,0,0,0,0,17229619,1048576,0,502311,0,0,0,502311,0,0,0,502311,0,0,0,502311,0,0,0,502311,0,0,0,502311,0,0,0,502311,0,0,0,502311,0,0,0,502311,0,0,0,502311,0,0,0,502311,0,0,0,502311,0,0,0,502311,0,0,0,502311,0,0,0,502311,0,0,0,502311,0,0,0,502311,0,0,0,502311,0,0,0,502311,0,0,0,502311,0,0,0,502311,0,0,0,502311,0,0,0,502311,0,0,0,502311,0,0,0,502311,0,0,0,502311,0,0,0,502311,0,0,0,502311,0,0,0,502311,0,0,0,502311,0,0,0,502311,0,0,0,502311,0,0,0,37282640,1,0,0,0,4,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,1,0,0,0,2589,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,2516,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,3,0,0,0,0,0,0,0,0,0,0,0,48,0,0,0,3,0,0,0,1,0,0,0,2510,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,2703,0,0,0,0,0,0,0,0,0,0,0,48,0,0,0,14,0,0,0,1048576,0,0,261,131072,131072,0,19397,131072,131072,0,0,131076,131076,0,0,131076,131076,0,2875657,131080,131080,0,0,131076,131076,0,0,131076,131076,0,0,131076,131076,0,3099239,131078,131078,0,0,131072,131072,0,833,131072,131072,0,290,131076,131076,0,272,131080,131080,0,0,131072,131072,0,0,131072,131072,0,3103180,131076,131076,0,0,131072,131072,0,530139,131072,131072,0,0,131072,131072,0,0,131084,131084,0,3294823,131076,131076,0,1432,131076,131076,0,0,131072,131072,0,0,131080,131080,0,5886,131076,131076,0,1530,131072,131072,0,259,131072,131072,0,0,131080,131080,0,0,131072,131072,0,0,131072,131072,0,0,131072,131072,0,0,131076,131076,1048576,0,643,0,0,17220448,1024,0,0,17141714,813,0,0,17356772,935,0,0,17086970,888,0,0,17238688,822,0,0,17289580,890,0,0,18251740,45451,0,0,31174717,881,0,0,17162991,946,0,0,17234056,806,0,0,17197057,46678,0,0,29979137,799,0,0,17234439,780,0,0,17235439,849,0,0,18196798,1240,0,0,18682876,1130,0,0,16726288,996,0,0,16696337,909,0,0,17183294,961,0,0,16855044,969,0,0,17272004,706,0,0,17255962,822,0,0,18166271,40070,0,0,29549882,857,0,0,16666551,1548,0,0,16838626,1853,0,0,17352802,50927,0,0,30734366,1543,0,0,17215296,1421,0,0,17386113,1816,0,0,18571042,1852,0,0,18680837,1048576,131072,131120,48,262192,131260,131076,192,262336,131072,131072,0,262144,131072,133611,2539,264683,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,133644,2572,264716,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,133700,2628,264772,131072,131072,0,262144,131307,131126,289,262433,131072,131072,0,262144,131072,133769,2697,264841,131072,131086,14,262158,131072,131072,0,262144,131072,131073,1,262145,131072,131072,0,262144,131072,131120,48,262192,131072,131072,0,262144,131072,131073,1,262145,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,262144,0,262144,262336,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262288,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,0,0,3145728,524288,32505856,374003152,218707438,122789858,478136,0,0,0,1048576,52562969,52346239,1048576,1048576,131072,524288,714,500345,4505,0,96,10711,0,8388944,32505856,4010760,3815412,57119507,11534336,0,0,14155776,67108864,67108864,0,67108864,54166852,53789583,0,1048576,235577,759865,11472,2153,0,496946,8399596,0,4194727,4204869,13631488,0,3670016,1048576,1048576,0,4194304,9437184,0,0,360,33554432,53799780,4194304,0,0,2968,494203,0,10912,8388608,0,4194378,905969664,6291456,0,0,0,524288,524288,0,15329,16608752,0,16777216,4194304,4194304,0,0,0,16670,4194384,4194384,0,215535,0,0,0,33554432,0,0,0,0,629895819,0,2767330584,0,0,0,0,0,479219,0,0,225748,0,0,8388608,336,144,0,0,0,480,8388608,0,0,0,0,394865,0,0,0,10957,0,21896,0,6291456,6289290,96,2785,2015814,0,0,0,0,0,0,0,0,0,3145728,0,0,0,149685,4194304,4189871,144,4289,2097152,524288,1572864,0,0,0,0,0,0,524288,0,4128813,65535,4063244,0,0,8388608,0,42239851,0,1048576,10808,4194349,13234081,606549390,12075963627546128,12075990193119383,12075990193445140,12075963871373381
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,902698,902703,32768,256,0,0,24,24,12480,0x0,0x7f3d29035100,0,4096,4096,512,0,512,4096,0,29340,29340,1448027,560942,184,104380,54713,33919,552836,532377,234720,82359,29340,0,29340,0,938880,188591,0,0,0,0,0,59638,4096,0,27514,0,0,0,27514,0,0,0,27514,0,0,0,27514,0,0,0,27514,0,0,0,27514,0,0,0,27514,0,0,0,27514,0,0,0,27514,0,0,0,27514,0,0,0,27514,0,0,0,27514,0,0,0,27514,0,0,0,27514,0,0,0,27514,0,0,0,27514,0,0,0,27514,0,0,0,27514,0,0,0,27514,0,0,0,27514,0,0,0,27514,0,0,0,27514,0,0,0,27514,0,0,0,27514,0,0,0,27514,0,0,0,27514,0,0,0,27514,0,0,0,27514,0,0,0,27514,0,0,0,27514,0,0,0,27514,0,0,0,27514,0,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,304,0,0,0,256,0,0,0,257,0,0,0,304,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,376,0,0,0,4096,4096,0,87937,0,0,0,104493,0,0,0,82844,0,0,0,112989,0,0,0,89785,0,0,0,79321,0,0,0,138303,0,0,0,104619,0,0,0,79722,0,0,0,110715,0,0,0,96012,0,0,0,71056,0,0,0,79406,0,0,0,85711,0,0,0,69878,0,0,0,71403,0,0,0,108402,0,0,0,84802,0,0,0,75567,0,0,0,94203,0,0,0,137593,0,0,0,83534,0,0,0,91931,0,0,0,91774,0,0,0,176022,0,0,0,139670,0,0,0,71935,0,0,0,88721,0,0,0,89315,0,0,0,86224,0,0,0,74528,0,0,0,77631,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4096,0,304,304,304,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,257,257,257,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,188,260,448,448,0,256,256,256,0,256,256,256,47,306,353,353,188,260,448,448,0,256,256,256,0,376,376,376,0,256,256,256,0,257,257,257,0,256,256,256,0,256,256,256,0,256,256,256,0,257,257,257,0,256,256,256,0,256,256,256,0,256,256,256,47,257,304,304,0,256,256,256,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,304,0,0,256,0,0,0,0,512,512,35328,1117102,1057705,23045,11823,0,0,0,4096,81515,78556,4096,4096,128,512,607,28930,4428,0,48,220,0,8624,36352,232784,74775,1020714,26624,0,0,30208,65536,65536,65536,0,0,0,0,0,116,628,11950,2517,0,24757,8843,0,470,8373,1024,0,1024,4096,0,4096,512,512,0,0,360,16384,0,16384,0,0,2765,24863,0,8891,0,0,31,1933312,8192,0,0,0,512,512,0,120,15064,0,16384,16384,0,0,0,0,20732,0,0,0,0,0,0,0,32768,0,0,0,0,12087997,17195064,0,8192,0,0,0,0,699,0,0,0,0,0,1024,432,48,0,0,0,480,0,0,0,0,0,3183,0,0,0,8422,0,440,0,8192,6553,48,1591,1072,0,0,0,0,0,0,0,0,0,2560,0,0,0,50337,512,0,48,464,0,512,0,0,0,0,0,0,0,512,0,0,0,0,0,8192,0,0,460656,0,4096,8373,0,3132561,0,12075963886388906,12075990208226449,12075990208233329,12075963887384456
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,902698,902703,4194304,256,0,0,24,24,12928,0x7f3e34d08900,0x7f3d29035140,0,524288,524288,65536,0,65536,524288,0,224208,224208,24896007,23634136,31221,6619506,22752732,22587189,23619656,21456041,1793664,1643673,224208,0,224208,0,7174656,6454881,0,0,0,0,0,19142130,524288,0,215865,0,0,0,215865,0,0,0,215865,0,0,0,215865,0,0,0,215865,0,0,0,215865,0,0,0,215865,0,0,0,215865,0,0,0,215865,0,0,0,215865,0,0,0,215865,0,0,0,215865,0,0,0,215865,0,0,0,215865,0,0,0,215865,0,0,0,215865,0,0,0,215865,0,0,0,215865,0,0,0,215865,0,0,0,215865,0,0,0,215865,0,0,0,215865,0,0,0,215865,0,0,0,215865,0,0,0,215865,0,0,0,215865,0,0,0,215865,0,0,0,215865,0,0,0,215865,0,0,0,215865,0,0,0,215865,0,0,0,215865,0,0,0,0,65537,0,8136,0,65536,0,32004,0,65540,0,4984,0,65536,0,16403,0,65536,0,13103,0,65537,0,12953,0,65537,0,15230,0,65936,0,40514,0,65536,0,14443,0,65536,0,9381,0,65537,0,22403,0,65536,0,41908,0,65536,0,35337,0,65536,0,47382,0,65536,0,12850,0,65536,0,21412,0,65536,0,6325,0,65536,0,44939,0,65536,0,1339,0,65536,0,22602,0,65584,0,9288,0,65536,0,10484,0,65537,0,40454,0,65584,0,11670,0,65536,0,19025,0,65536,0,29249,0,65536,0,17382,0,67576,0,84718,0,65536,0,3046,0,65536,0,5321,0,65540,0,13942,0,65656,0,15500,0,524288,524288,0,33287425,0,0,0,33170815,0,0,0,33829258,0,0,0,31351248,0,0,0,45726656,0,0,0,35486099,0,0,0,34171846,0,0,0,32341560,0,0,0,33708521,0,0,0,34142033,0,0,0,34955390,0,0,0,34289538,0,0,0,32133782,0,0,0,40390580,0,0,0,41365063,0,0,0,35456623,0,0,0,44053010,0,0,0,37192303,0,0,0,31964028,0,0,0,30445439,0,0,0,48562767,0,0,0,45010283,0,0,0,43037649,0,0,0,40282645,0,0,0,36436390,0,0,0,37528495,0,0,0,32173037,0,0,0,32146174,0,0,0,38739880,0,0,0,34567108,0,0,0,34339999,0,0,0,32403201,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,524288,0,65584,65584,65584,0,65536,65536,65536,188,65540,65728,65728,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,66094,66094,66094,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,66152,66152,66152,0,65536,65536,65536,47,65586,65633,65633,0,65536,65536,65536,0,65536,65536,65536,0,65656,65656,65656,0,65536,65536,65536,0,65537,65537,65537,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65537,65537,65537,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,188,65540,65728,65728,0,65536,65536,65536,65536,0,0,65536,0,0,65728,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65728,0,0,65536,0,0,0,0,65536,65536,4128768,111277673,43050380,63967453,210410,0,0,0,524288,22549278,22533397,524288,524288,16384,65536,787,229025,4491,0,48,5344,0,2097536,4259840,1805928,1639224,24251000,3014656,0,0,3473408,8388608,8388608,8388608,0,0,0,0,0,156551,190641,11613,2095,0,221280,2102573,0,423,2102150,131072,0,131072,524288,0,524288,65536,65536,0,0,360,2097152,0,2097152,37198,0,2363,220450,0,2101447,0,0,31,222298112,917504,0,0,0,65536,65536,0,7592,2018066,0,2097152,2097152,0,748366,750932,0,23363,0,0,0,0,0,0,0,4194304,0,0,0,0,872369486,1375120274,0,2097152,0,0,0,0,200043,0,0,0,0,0,131072,384,48,0,0,0,432,0,0,0,0,0,2743,0,0,0,2099653,0,4984,0,917504,914601,48,7407,226460,0,0,0,0,0,0,0,0,0,327680,0,0,249788,303032,65536,64048,48,1440,0,65536,0,0,0,0,0,0,0,65536,0,0,0,1966101,0,2097152,0,0,14938959,0,524288,2101634,0,909854422,0,12075963888018294,12075990208297008,12075990208434447,12075963889240506
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/prev_analysis/1.csv
index 4b7be7a01c..dbdf03d31f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,6055313.0,6055313.0,6055313.0,9.182541583389895
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4526366.0,4526366.0,4526366.0,6.863979453521591
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 256u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,3050376.0,3050376.0,3050376.0,4.625723635586556
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/prev_analysis/1001.csv
index ca08330db0..0e3bf5267e 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,46.862275449101794,Instr per wave
 SMEM,1.8083832335329342,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/prev_analysis/101.csv
index fd894e3bcc..5f903c7608 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx908
 mi100
 48
 1228.8
-SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/prev_analysis/1202.csv
index 4782ad8e54..daa106804d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,33382.60340890485,2853.4176025390625,547867.893737793,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/prev_analysis/1901.csv
index 75444f53ae..4a45370d79 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,2.0,smem_
 VALU,735.0,valu_
 MFMA,,mfma_
 VMEM,8.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,22.0,br_
 VGPR,24.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,67894.0,wavefronts_
 Workgroups,16973.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,163.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,0.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,44.0,hbm_rd_
 HBM Wr,0.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,70.0,vl1_coales_
 VL1 Stall,29.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,36.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/prev_analysis/2001.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/prev_analysis/201.csv
index 51037fecc5..e00ebcddf8 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,59.33325072296532,Pct,100,59.33325072296532
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,63.96797796142581,Threads,64,99.94996556472783
 IPC - Issue,0.8437276931049974,Instr/cycle,5,16.874553862099948
-LDS BW,0.0,Gb/sec,23070.72,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,23070.72,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99343229326712,Pct,100,99.99343229326712
 Instr Cache BW,1412.509294420872,Gb/s,4614.144,30.612596711781688
 Scalar L1D Cache Hit Rate,99.3562044853132,Pct,100,99.3562044853132
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/prev_analysis/602.csv
index ac76c25483..d68c062dce 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,50330.94610778443,0,748366,Simd
 Insufficient SIMD VGPRs,585102.0538922156,0,24218898,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/prev_analysis/701.csv
index d3f1bff5a3..1071413faa 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,23.976047904191617,8,36,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/sysinfo.csv
index c642134beb..4469605c50 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-no_roof_Axes1,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 11:25:36 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+no_roof_Axes1,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 11:25:36 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/timestamps.csv
index 4b2aa121d7..607ea1c757 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,904000,904005,33554432,256,0,0,8,32,6464,0x0,0x7fca35a04180,12075990193071892,12075990193119383,12075990193445140,12075990193551032
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,904000,904005,32768,256,0,0,24,24,12480,0x0,0x7fca35a35100,12075990208121941,12075990208226449,12075990208233329,12075990208238829
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,904000,904005,4194304,256,0,0,24,24,12928,0x7fcb41588900,0x7fca35a35140,12075990208283181,12075990208297008,12075990208434447,12075990208437748
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/SQ_IFETCH_LEVEL.csv
index ea9cf75c26..d96abd7875 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/SQ_IFETCH_LEVEL.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,202849,202849,33554432,256,0,0,4,32,4160,0x0,0x7fcd29804280,381667,381667,524288,4718592,682294,76370516,17278994191774,17278287081202,17279143614630,17279143727960
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,202849,202849,32768,256,0,0,12,24,13888,0x0,0x7fcd29823f80,32959,32959,512,8192,6007,667404,17279148852263,17279143614630,17279148980233,17279148984999
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,202849,202849,4194304,256,0,0,12,24,14336,0x7fcd2c7bb380,0x7fcd29823fc0,164889,164889,65536,917504,140706,15802100,17279149023648,17279148980233,17279149359434,17279149362029
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/SQ_INST_LEVEL_LDS.csv
index 0f20eb338f..127103fefa 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/SQ_INST_LEVEL_LDS.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,204697,204697,33554432,256,0,0,4,32,4160,0x0,0x7fa408004280,0,0,0,17298409910264,17297703175387,17298553394415,17298553506115
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,204697,204697,32768,256,0,0,12,24,13888,0x0,0x7fa408023f80,0,0,0,17298558672447,17298553394415,17298558803377,17298558807934
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,204697,204697,4194304,256,0,0,12,24,14336,0x7fa4268fa380,0x7fa408023fc0,0,0,0,17298558842103,17298558803377,17298559174898,17298559177304
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/SQ_INST_LEVEL_SMEM.csv
index c3a5644a95..d6231e1719 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/SQ_INST_LEVEL_SMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,202627,202627,33554432,256,0,0,4,32,4160,0x0,0x7f168de04280,3670016,2892396,324457912,17278052229909,17250066954363,17278205820393,17278205912303
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,202627,202627,32768,256,0,0,12,24,13888,0x0,0x7f168de23f80,512,94150,10555080,17278211068634,17278205820393,17278211199437,17278211204361
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,202627,202627,4194304,256,0,0,12,24,14336,0x7f1690e2b380,0x7f168de23fc0,65536,613004,68820144,17278211239220,17278211199437,17278211571278,17278211574201
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/SQ_INST_LEVEL_VMEM.csv
index 2b17bcf8fe..2466be2481 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/SQ_INST_LEVEL_VMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,204475,204475,33554432,256,0,0,4,32,4160,0x0,0x7f1b72e04280,524288,5474912,613144444,17297469215862,17295115031052,17297622560071,17297622677000
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,204475,204475,32768,256,0,0,12,24,13888,0x0,0x7f1b72e23f80,4096,39998,4479208,17297627858321,17297622560071,17297627985508,17297627990358
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,204475,204475,4194304,256,0,0,12,24,14336,0x7f1b75d2b380,0x7f1b72e23fc0,524288,10747322,1203631160,17297628024577,17297627985508,17297628355268,17297628357868
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/SQ_LEVEL_WAVES.csv
index 5170d9d4f3..ea2fdea448 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/SQ_LEVEL_WAVES.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,203071,203071,33554432,256,0,0,4,32,4160,0x0,0x7f6f72c04280,381480,381480,9023,3051848,524288,239681120,2963097,0,974974376,17279936818967,17279225430784,17280084486671,17280084596181
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,203071,203071,32768,256,0,0,12,24,13888,0x0,0x7f6f72c23f80,33212,33212,29763,265704,512,1702332,167308,0,6822812,17280089756852,17280084486671,17280089890996,17280089896429
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,203071,203071,4194304,256,0,0,12,24,14336,0x7f6f75c45380,0x7f6f72c23fc0,164480,164480,13812,1315848,65536,73207207,1205817,0,294563716,17280089940508,17280089890996,17280090294196,17280090296778
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/pmc_perf.csv
index a27e3abdd6..28bc9ab34c 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDI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],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBufferAligned.kd,0,0,0,203837,203837,33554432,256,0,0,4,32,4160,0x0,0x7f97b5604280,3089144,3003041,524288,38995901,244136375,392,224,0,386142,386142,39280753.0,38248546.0,14.0,4163327.0,31367218.0,31001782.0,38224816.0,37664148.0,3087433,3009437,386142,0,386142,0,12356544.0,9493819.0,0.0,0.0,0,0,616,0,4718592,4714874,112,3606,377946,0.0,0.0,0.0,524288.0,28653980.0,27933136.0,7658.0,524288.0,131072,524288,302,386909,2346,0,56.0,301.0,0.0,4194696.0,0,0,0,0,0,7340032,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,19983351.0,524288.0,0,382436,0,0,0,382436,0,0,0,382436,0,0,0,382436,0,0,0,382436,0,0,0,382436,0,0,0,382436,0,0,0,382436,0,0,0,382436,0,0,0,382436,0,0,0,382436,0,0,0,382436,0,0,0,382436,0,0,0,382436,0,0,0,382436,0,0,0,382436,0,0,0,382436,0,0,0,382436,0,0,0,382436,0,0,0,382436,0,0,0,382436,0,0,0,382436,0,0,0,382436,0,0,0,382436,0,0,0,382436,0,0,0,382436,0,0,0,382436,0,0,0,382436,0,0,0,382436,0,0,0,382436,0,0,0,382436,0,0,0,382436,0,0,0,0,0,0.0,21345864.0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,0,0,2,0,0,0,1,0,0,0,1,0,0,0,56,0,0,0,0,0,0,0,112,0,0,0,0,0,0,0,0,0,0,0,33,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,35,0,0,0,5,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,32,0,0,0,1,0,0,0,524288.0,0.0,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,43495,129024,129024,0,495,129024,129024,0,169,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,283092,129024,129024,0,0,129024,129024,0,43988,129024,129024,0,0,129024,129024,0,0,129024,129024,0,876,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,28231,129024,129024,0,1039,129024,129024,0,185,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,493673,129024,129024,0,0,129024,129024,0,0,129024,129024,0,45251,129024,129024,0,186,129024,129024,524288.0,0.0,44657,0,0,50731790,45522,0,0,50699288,44582,0,0,50185935,46192,0,0,51670756,45391,0,0,51232426,46376,0,0,51428477,45414,0,0,50936023,48529,0,0,53194990,45345,0,0,51170639,47103,0,0,51399783,46232,0,0,50743672,48265,0,0,52482812,45298,0,0,51513746,48930,0,0,52231699,46001,0,0,51152690,48775,0,0,53043569,44357,0,0,50604105,44862,0,0,50591233,43384,0,0,49914107,46213,0,0,51825437,45035,0,0,51227508,45671,0,0,51276269,44843,0,0,50792979,48011,0,0,52803192,45756,0,0,50981875,46179,0,0,51002044,45171,0,0,50386820,49179,0,0,52684917,46527,0,0,51830989,47085,0,0,51638394,45735,0,0,51142325,49700,0,0,53331942,0.0,65536,65536,0,131072,65536,65536,0,131072,65591,65538,57,131129,65536,65568,32,131104,65646,65538,112,131184,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65592,56,131128,65536,65536,0,131072,65536,65537,1,131073,65536,65568,32,131104,65536,65536,0,131072,65536,65648,112,131184,65536,65536,0,131072,65536,65536,0,131072,65536,65537,1,131073,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65571,35,131107,65758,65538,224,131296,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65568,32,131104,65591,65538,57,131129,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131184,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131296,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131128,0,131072,1117033,0,524288,3670016,3663159,224,6633,1048576,33554432.0,33554432.0,0.0,33554432.0,30181274.0,28542687.0,0.0,524288.0,218354,536250,8453,948,0,384413,4195055.0,0.0,2097594.0,2097461.0,1048576,1048576,0,524288,0,524288,7340032,0,0.0,0.0,104.0,8388608.0,29600118.0,2097152.0,0.0,202303,0,1264,383419,0,749.0,4194304.0,0.0,2064387.0,25690112,9437184,0,0,0,0,0,0,13289.0,8242429.0,0.0,8388608.0,2097152.0,4194304.0,9640159,0,0,8904,4128768.0,4128768.0,0.0,1465250.0,0,0,0,0,0,0,5767168,1048576,319275803.0,0.0,1487387656.0,0.0,39.0,0.0,0,0,378675,0.0,0.0,1509428.0,0.0,3670016,524288,0,0,0,2621440,524288,178956767,4194304.0,0.0,0.0,0.0,0.0,1187708.0,0,0,0.0,312.0,0.0,608.0,43268266,24117248,0,0,9437184,11010048,0,3145728,0.0,0.0,0.0,0.0,0.0,0.0,0,1572864,0.0,0.0,0.0,216611.0,524288,524288,0,3670016,7340032,603979776,4718592,0,0.0,0.0,0.0,0.0,0.0,0.0,524288,0,2064384.0,0.0,2031623.0,0.0,0,0,524288,0,0,0,0,33554432,0.0,4194304.0,0.0,19066259.0,0.0,0.0,142.0,4128768.0,990875.0,1658317146.0,17281372871098,17299222041700,17299222281220,17281523188546
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,203837,203837,32768,256,0,0,12,24,13888,0x0,0x7f97b5623f80,273560,168302,512,1421853,1800690,504,56,0,34194,34194,2418923.0,142222.0,189.0,0.0,33018.0,29492.0,135920.0,117102.0,273552,175178,34194,0,34194,0,1094208.0,400885.0,0.0,0.0,0,0,560,0,8192,6145,56,1991,23009,0.0,0.0,0.0,4096.0,30165.0,28744.0,0.0,4096.0,128,512,302,32552,2629,0,0.0,60.0,0.0,4600.0,0,0,0,0,0,1024,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,12165.0,4096.0,0,32824,0,0,0,32824,0,0,0,32824,0,0,0,32824,0,0,0,32824,0,0,0,32824,0,0,0,32824,0,0,0,32824,0,0,0,32824,0,0,0,32824,0,0,0,32824,0,0,0,32824,0,0,0,32824,0,0,0,32824,0,0,0,32824,0,0,0,32824,0,0,0,32824,0,0,0,32824,0,0,0,32824,0,0,0,32824,0,0,0,32824,0,0,0,32824,0,0,0,32824,0,0,0,32824,0,0,0,32824,0,0,0,32824,0,0,0,32824,0,0,0,32824,0,0,0,32824,0,0,0,32824,0,0,0,32824,0,0,0,32824,0,0,0,0,0,0.0,0.0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,260,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,312,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,257,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,4096.0,4096.0,0,78412,0,0,0,76945,0,0,0,78911,0,0,0,79902,0,0,0,91062,0,0,0,96277,0,0,0,89879,0,0,0,96385,0,0,0,76383,0,0,0,79483,0,0,0,76067,0,0,0,106528,0,0,0,79243,0,0,0,87581,0,0,0,87006,0,0,0,86974,0,0,0,89214,0,0,0,81059,0,0,0,77752,0,0,0,82934,0,0,0,80147,0,0,0,82509,0,0,0,89191,0,0,0,99797,0,0,0,88030,0,0,0,79843,0,0,0,72971,0,0,0,669905,0,0,0,78674,0,0,0,92906,0,0,0,85783,0,0,0,86203,0,0,0.0,0.0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4096.0,0,128,128,128,0,128,128,128,0,129,129,129,0,128,128,128,0,128,128,128,222,130,352,352,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,222,186,408,408,0,128,128,128,0,128,128,128,0,129,129,129,0,128,128,128,0,128,128,128,0,128,128,128,0,130,130,130,0,128,128,128,55,129,184,184,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,129,129,129,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,352,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,352,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,184,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,678,0,0,512,0,56,456,0,65536.0,65536.0,65536.0,0.0,0.0,0.0,0.0,0.0,6,518,11257,1043,0,29988,4660.0,0.0,499.0,4161.0,512,0,0,0,4096,4096,512,0,0.0,0.0,104.0,16384.0,0.0,16384.0,4096.0,0,0,1347,31609,0,4660.0,0.0,0.0,31.0,35328,26112,0,0,0,0,0,0,104.0,15240.0,0.0,16384.0,16384.0,0.0,0,0,0,29588,0.0,0.0,0.0,0.0,0,0,0,0,0,0,10752,3584,4101350.0,5839526.0,0.0,8192.0,0.0,0.0,0,0,498,0.0,0.0,0.0,0.0,512,4096,0,0,0,512,512,1554561,0.0,0.0,0.0,0.0,0.0,1285.0,0,0,0.0,8261.0,0.0,120.0,15893,32256,0,0,26112,1024,0,1024,0.0,0.0,0.0,0.0,0.0,0.0,0,1024,0.0,0.0,0.0,36613.0,4096,0,4096,512,512,1671168,8192,0,0.0,0.0,0.0,0.0,0.0,0.0,512,0,0.0,0.0,0.0,0.0,0,0,512,0,0,0,0,32768,8192.0,0.0,0.0,103524.0,0.0,4096.0,8204.0,0.0,3377286.0,0.0,17281529417249,17299227083300,17299227096580,17281529883047
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,203837,203837,4194304,256,0,0,12,24,14336,0x7f97b864b380,0x7f97b5623fc0,1308784,1210311,65536,15636707,75661019,392,56,0,163597,163597,15965170.0,14492513.0,25063.0,499584.0,13247377.0,12944510.0,14486122.0,12349709.0,1308776,1217054,163597,0,163597,0,5235104.0,4744501.0,0.0,0.0,0,0,448,0,917504,913895,0,3609,153384,0.0,0.0,0.0,524288.0,13889032.0,13875674.0,2109.0,524288.0,16384,65536,302,163927,2249,0,0.0,183.0,0.0,1048968.0,0,0,0,0,0,131072,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,11722365.0,524288.0,0,176799,0,0,0,176799,0,0,0,176799,0,0,0,176799,0,0,0,176799,0,0,0,176799,0,0,0,176799,0,0,0,176799,0,0,0,176799,0,0,0,176799,0,0,0,176799,0,0,0,176799,0,0,0,176799,0,0,0,176799,0,0,0,176799,0,0,0,176799,0,0,0,176799,0,0,0,176799,0,0,0,176799,0,0,0,176799,0,0,0,176799,0,0,0,176799,0,0,0,176799,0,0,0,176799,0,0,0,176799,0,0,0,176799,0,0,0,176799,0,0,0,176799,0,0,0,176799,0,0,0,176799,0,0,0,176799,0,0,0,176799,0,0,0,0,0,0.0,0.0,65537,0,18871,0,65538,0,17007,0,65536,0,26992,0,65536,0,17980,0,65536,0,28559,0,65536,0,23915,0,65539,0,8771,0,65536,0,26176,0,65536,0,15279,0,65648,0,16680,0,65536,0,14045,0,65536,0,25154,0,65541,0,17134,0,65536,0,24911,0,65536,0,40582,0,65536,0,32264,0,65536,0,28092,0,65536,0,11948,0,65536,0,18464,0,65536,0,8691,0,65539,0,6524,0,65596,0,14768,0,65536,0,10517,0,65540,0,17336,0,65540,0,15647,0,65536,0,27308,0,65536,0,20087,0,65540,0,14415,0,65536,0,14065,0,65536,0,33077,0,65597,0,27540,0,65536,0,24183,0,524288.0,524288.0,0,44343804,0,0,0,40265374,0,0,0,51854532,0,0,0,49088012,0,0,0,42382846,0,0,0,48109521,0,0,0,44633635,0,0,0,52210820,0,0,0,49848131,0,0,0,41529957,0,0,0,44059759,0,0,0,39103993,0,0,0,39668528,0,0,0,39243271,0,0,0,39575372,0,0,0,53218799,0,0,0,51806640,0,0,0,48726058,0,0,0,49518848,0,0,0,40127541,0,0,0,50141626,0,0,0,40941376,0,0,0,48004615,0,0,0,40161402,0,0,0,37125986,0,0,0,44944328,0,0,0,37014225,0,0,0,42597050,0,0,0,42647179,0,0,0,44716760,0,0,0,42799997,0,0,0,49855881,0,0,0.0,0.0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,524288.0,0,32768,32768,32768,0,32768,32768,32768,0,32769,32769,32769,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32770,32770,32770,0,32768,32768,32768,0,32768,32768,32768,0,32824,32824,32824,0,32768,32768,32768,0,32768,32768,32768,0,32769,32769,32769,0,32768,32768,32768,0,32769,32769,32769,0,32768,32768,32768,0,32828,32828,32828,0,32768,32768,32768,166,32770,32936,32936,222,32770,32992,32992,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32825,32825,32825,0,32769,32769,32769,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32936,0,0,32992,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,884803,0,0,65536,63800,56,1680,0,8388608.0,8388608.0,8388608.0,0.0,0.0,0.0,0.0,0.0,175974,183969,10026,2784,0,164508,1049129.0,0.0,388.0,1048741.0,65536,0,0,0,524288,524288,131072,0,0.0,0.0,104.0,2097152.0,0.0,2097152.0,524288.0,42978,0,2380,160879,0,1049156.0,0.0,0.0,31.0,4063232,2883584,0,0,0,0,0,0,6608.0,2027339.0,0.0,2097152.0,2097152.0,0.0,1317244,0,0,13815,0.0,0.0,0.0,0.0,262144,0,0,0,0,0,1507328,458752,989354620.0,2181492216.0,0.0,2097152.0,95.0,0.0,0,0,148726,0.0,0.0,0.0,0.0,65536,524288,0,0,0,65536,65536,47175732,0.0,0.0,0.0,0.0,0.0,25952.0,0,0,0.0,2097332.0,0.0,346.0,23829710,3735552,0,0,2883584,196608,0,131072,0.0,0.0,0.0,0.0,0.0,0.0,0,131072,0.0,0.0,601489.0,1665739.0,524288,0,524288,65536,131072,184549376,917504,0,0.0,0.0,0.0,0.0,0.0,0.0,65536,0,0.0,0.0,983046.0,0.0,0,0,65536,0,0,0,0,4194304,2097152.0,0.0,0.0,12320611.0,0.0,524288.0,2097263.0,0.0,1483449127.0,0.0,17281530984047,17299227171300,17299227264420,17281531729947
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/prev_analysis/1.csv
index 6b595510a4..59fc02fbd2 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,3357601.0,3357601.0,3357601.0,7.841753114285133
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,1724320.0,1724320.0,1724320.0,4.0271883794483445
 "void benchmark_func<double, 256, 8u, 512u>(double, double*) [clone .kd]",1,1716481.0,1716481.0,1716481.0,4.008880217560472
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/prev_analysis/1001.csv
index f475f954a6..fb5988001a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,494.8622754491018,Instr per wave
 VMEM,7.958083832335329,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,0.0,Instr per wave
 SALU,24.520958083832337,Instr per wave
 SMEM,1.8023952095808384,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/prev_analysis/101.csv
index 485846a748..1b52bbe896 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx90a
 mi200
 56
 1638.4
-SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/prev_analysis/1202.csv
index 2d2410dccc..610247c960 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,18313.5073947107,1862.6127243041992,258370.62451171875,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/prev_analysis/1901.csv
index 906ae7192f..92ad68e4f5 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,2.0,smem_
 VALU,495.0,valu_
 MFMA,0.0,mfma_
 VMEM,8.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,10.0,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,67894.0,wavefronts_
 Workgroups,16973.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,128.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,0.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,44.0,hbm_rd_
 HBM Wr,0.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,70.0,vl1_coales_
 VL1 Stall,2.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,26.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/prev_analysis/201.csv
index 41eed6c6cd..eba6c8aa28 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,58.495540920935206,Pct,100,58.495540920935206
 MFMA Util,0.0,Pct,100,0.0
 VALU Active Threads/Wave,64.0,Threads,64,100.0
 IPC - Issue,1.0,Instr/cycle,5,20.0
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99254524991618,Pct,100,99.99254524991618
 Instr Cache BW,1673.173964141486,Gb/s,6092.8,27.461494947175126
 Scalar L1D Cache Hit Rate,99.34855885909467,Pct,100,99.34855885909467
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/prev_analysis/602.csv
index 2fe8b7725c..1df8133709 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,12373562.413173653,0,366808577,Simd
 Insufficient SIMD VGPRs,0.0,0,0,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/prev_analysis/701.csv
index 12250d77c0..db0925a109 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/sysinfo.csv
index 925ef61efa..200b803712 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-no_roof_Axes1,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:41:18 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+no_roof_Axes1,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:41:18 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/timestamps.csv
index b75343b8ae..6b3778dcfc 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes1/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,204780,204780,33554432,256,0,0,4,32,4160,0x0,0x7f2fd1e04280,17299222015870,17299222041700,17299222281220,17299222392340
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,204780,204780,32768,256,0,0,12,24,13888,0x0,0x7f2fd1e23f80,17299227068125,17299227083300,17299227096580,17299227114114
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,204780,204780,4194304,256,0,0,12,24,14336,0x7f2fd4d53380,0x7f2fd1e23fc0,17299227119413,17299227171300,17299227264420,17299227266590
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/SQ_IFETCH_LEVEL.csv
index 157a72a595..3fbf0f1679 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/SQ_IFETCH_LEVEL.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,906969,906974,33554432,256,0,0,8,32,6464,0x0,0x7fdf43004180,508129,508129,524288,6291456,794474,101409308,12076057504854103,12076057752760190,12076057753085788,12076057753177621
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,906969,906974,32768,256,0,0,24,24,12480,0x0,0x7fdf43035100,28559,28559,512,8192,9202,1193156,12076057767468250,12076057767783635,12076057767789875,12076057767797432
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,906969,906974,4194304,256,0,0,24,24,12928,0x7fe072fba900,0x7fdf43035140,231916,231916,65536,917504,139567,17883016,12076057767872050,12076057768089714,12076057768231313,12076057768235426
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/SQ_INST_LEVEL_LDS.csv
index b730a9df54..ffc402918c 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/SQ_INST_LEVEL_LDS.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,908765,908770,33554432,256,0,0,8,32,6464,0x0,0x7fe4ce804180,0,0,0,12076083744480056,12076083990526988,12076083990850666,12076083990960058
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,908765,908770,32768,256,0,0,24,24,12480,0x0,0x7fe4ce835100,0,0,0,12076084005786202,12076084006099461,12076084006105381,12076084006115163
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,908765,908770,4194304,256,0,0,24,24,12928,0x7fe5da3f1900,0x7fe4ce835140,0,0,0,12076084006176026,12076084006390019,12076084006521859,12076084006525947
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/SQ_INST_LEVEL_SMEM.csv
index dee29e82bd..e78f65ac9d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/SQ_INST_LEVEL_SMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,908386,908391,33554432,256,0,0,8,32,6464,0x0,0x7f3522c04180,4194304,3177606,406682344,12076081221407006,12076081467941357,12076081468265195,12076081468376168
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,908386,908391,32768,256,0,0,24,24,12480,0x0,0x7f3522c35100,512,23872,3051744,12076081482875274,12076081483185437,12076081483191997,12076081483200648
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,908386,908391,4194304,256,0,0,24,24,12928,0x7f3652be6900,0x7f3522c35140,65536,180484,23148344,12076081483259207,12076081483477756,12076081483608635,12076081483612794
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/SQ_INST_LEVEL_VMEM.csv
index d8c0a2352a..2311813c9d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/SQ_INST_LEVEL_VMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,908576,908581,33554432,256,0,0,8,32,6464,0x0,0x7f38e6e04180,1048576,11214207,1435402180,12076082491102149,12076082733115582,12076082733441020,12076082733553063
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,908576,908581,32768,256,0,0,24,24,12480,0x0,0x7f38e6e35100,4096,103819,13284948,12076082748431904,12076082748733178,12076082748739898,12076082748744566
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,908576,908581,4194304,256,0,0,24,24,12928,0x7f3a16ebb900,0x7f38e6e35140,524288,11864181,1518501416,12076082748806901,12076082749027736,12076082749161496,12076082749165047
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/SQ_LEVEL_WAVES.csv
index 9c6a46c89a..6bafd0eb27 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/SQ_LEVEL_WAVES.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,908953,908958,33554432,256,0,0,8,32,6464,0x0,0x7fe452604180,509642,509642,15590,4077144,524288,376476537,3880130,0,1520702332,12076085014643528,12076085259277341,12076085259605339,12076085259719111
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,908953,908958,32768,256,0,0,24,24,12480,0x0,0x7fe452635100,27516,27516,20403,220136,512,1208749,80497,0,4849168,12076085274579067,12076085274910023,12076085274916583,12076085274925731
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,908953,908958,4194304,256,0,0,24,24,12928,0x7fe55e26d900,0x7fe452635140,222444,222444,21185,1779560,65536,145061388,1612832,0,582054584,12076085274995511,12076085275254182,12076085275390661,12076085275394513
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/pmc_dispatch_info.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/pmc_perf.csv
index 0832d25822..a5a1ff3041 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBuffer.kd,0,0,0,907703,907708,33554432,256,0,0,8,32,6464,0x0,0x7fa635004180,1048576,0,1048576,9437184,0,4194304,1048576,0,502389,502389,57645321,55358241,154,13109458,54659838,54574191,55332788,54153748,4019112,3827476,502389,0,502389,0,16076448,15245973,0,0,0,0,0,17347451,1048576,0,506049,0,0,0,506049,0,0,0,506049,0,0,0,506049,0,0,0,506049,0,0,0,506049,0,0,0,506049,0,0,0,506049,0,0,0,506049,0,0,0,506049,0,0,0,506049,0,0,0,506049,0,0,0,506049,0,0,0,506049,0,0,0,506049,0,0,0,506049,0,0,0,506049,0,0,0,506049,0,0,0,506049,0,0,0,506049,0,0,0,506049,0,0,0,506049,0,0,0,506049,0,0,0,506049,0,0,0,506049,0,0,0,506049,0,0,0,506049,0,0,0,506049,0,0,0,506049,0,0,0,506049,0,0,0,506049,0,0,0,506049,0,0,0,37027847,2549,0,0,0,52,0,0,0,0,0,0,0,0,0,0,0,2642,0,0,0,1,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,3,0,0,0,0,0,0,0,0,0,0,0,2659,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2649,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,67,0,0,0,0,0,0,0,4,0,0,0,0,0,0,0,1048576,0,0,3203136,131072,131072,0,15091,131072,131072,0,2510,131072,131072,0,21421,131076,131076,0,0,131072,131072,0,0,131072,131072,0,0,131080,131080,0,0,131076,131076,0,0,131080,131080,0,0,131080,131080,0,263,131072,131072,0,0,131072,131072,0,2863026,131072,131072,0,0,131072,131072,0,0,131072,131072,0,0,131076,131076,0,13484,131076,131076,0,986,131080,131080,0,804,131072,131072,0,0,131072,131072,0,0,131084,131084,0,0,131072,131072,0,0,131072,131072,0,0,131076,131076,0,3107249,131076,131076,0,0,131076,131076,0,564767,131072,131072,0,0,131072,131072,0,3202726,131072,131072,0,0,131072,131072,0,0,131076,131076,0,0,131072,131072,1048576,0,50312,0,0,30678153,1802,0,0,17233103,947,0,0,16976992,1793,0,0,17395947,926,0,0,16876809,742,0,0,17231473,1698,0,0,17886516,1599,0,0,18711818,1168,0,0,16982921,788,0,0,17017284,858,0,0,16725232,695,0,0,16982853,44005,0,0,29360971,814,0,0,17215018,945,0,0,17725579,741,0,0,18676429,906,0,0,16671171,1050,0,0,16757538,1207,0,0,16718006,1120,0,0,17067070,807,0,0,16988570,835,0,0,17237872,922,0,0,17707735,918,0,0,18650249,46522,0,0,29386874,1172,0,0,16882686,884,0,0,16811274,842,0,0,17237455,46245,0,0,30176468,1041,0,0,17426566,758,0,0,17745140,731,0,0,18663293,1048576,131072,131072,0,262144,131260,131125,241,262385,131072,131072,0,262144,131072,133620,2548,264692,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,133838,2766,264910,131072,131072,0,262144,131072,131072,0,262144,131072,131073,1,262145,131072,131072,0,262144,131072,131073,1,262145,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131073,1,262145,131213,131075,144,262288,131072,131074,2,262146,131072,131090,18,262162,131072,131072,0,262144,131072,131072,0,262144,131119,131073,48,262192,131072,131072,0,262144,131072,131072,0,262144,131119,131121,96,262240,131072,131072,0,262144,131072,133619,2547,264691,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,133680,2608,264752,262144,0,262144,262336,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262288,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,0,0,3145728,524288,32505856,368995248,219259397,117229995,482228,0,0,0,1048576,52352946,52112220,1048576,1048576,131072,524288,728,505025,4796,0,96,10467,0,8388944,32505856,4023560,3815029,56987984,11534336,0,0,14155776,67108864,67108864,0,67108864,54210099,53874147,0,1048576,237269,761557,11348,3440,0,498681,8399544,0,4194727,4204817,13631488,0,3670016,1048576,1048576,0,4194304,9437184,0,0,360,33554432,53988210,4194304,0,0,2812,501426,0,10990,8388608,0,4194362,905969664,6291456,0,0,0,524288,524288,0,15326,16608730,0,16777216,4194304,4194304,0,0,0,16562,4194356,4194356,0,219751,0,0,0,33554432,0,0,0,0,633616906,0,2779626367,0,0,0,0,0,475069,0,0,209057,0,0,8388608,336,144,0,0,0,480,8388608,0,0,0,0,330966,0,0,0,10601,0,21184,0,6291456,6289530,96,2027,1966832,0,0,0,0,0,0,0,0,0,3145728,0,0,0,144562,4194304,4189867,144,4293,2097152,524288,1572864,0,0,0,0,0,0,524288,0,4128826,65534,4063245,0,0,8388608,0,42090646,0,1048576,10859,4194361,13325928,609349046,12076059619795338,12076086146753232,12076086147076749,12076059869125016
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,907703,907708,32768,256,0,0,24,24,12480,0x0,0x7fa635035100,0,4096,4096,512,0,512,4096,0,27909,27909,1503647,623385,204,143376,119397,105764,615272,594941,223272,86061,27909,0,27909,0,893088,205434,0,0,0,0,0,38232,4096,0,27936,0,0,0,27936,0,0,0,27936,0,0,0,27936,0,0,0,27936,0,0,0,27936,0,0,0,27936,0,0,0,27936,0,0,0,27936,0,0,0,27936,0,0,0,27936,0,0,0,27936,0,0,0,27936,0,0,0,27936,0,0,0,27936,0,0,0,27936,0,0,0,27936,0,0,0,27936,0,0,0,27936,0,0,0,27936,0,0,0,27936,0,0,0,27936,0,0,0,27936,0,0,0,27936,0,0,0,27936,0,0,0,27936,0,0,0,27936,0,0,0,27936,0,0,0,27936,0,0,0,27936,0,0,0,27936,0,0,0,27936,0,0,0,0,257,0,0,0,304,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,376,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,4096,4096,0,123506,0,0,0,99955,0,0,0,68116,0,0,0,155572,0,0,0,84166,0,0,0,94914,0,0,0,71347,0,0,0,167690,0,0,0,87089,0,0,0,89364,0,0,0,77641,0,0,0,83547,0,0,0,90505,0,0,0,81632,0,0,0,69918,0,0,0,75191,0,0,0,185322,0,0,0,106676,0,0,0,94930,0,0,0,89820,0,0,0,80615,0,0,0,124970,0,0,0,90120,0,0,0,93619,0,0,0,135277,0,0,0,97076,0,0,0,94585,0,0,0,74773,0,0,0,106932,0,0,0,86873,0,0,0,89199,0,0,0,84033,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4096,0,256,256,256,0,305,305,305,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,257,257,257,0,256,256,256,0,257,257,257,0,256,256,256,188,260,448,448,0,256,256,256,0,257,257,257,0,256,256,256,188,260,448,448,0,376,376,376,0,256,256,256,0,256,256,256,47,257,304,304,0,256,256,256,0,256,256,256,0,304,304,304,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,47,257,304,304,0,256,256,256,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,304,0,0,256,0,0,0,0,512,512,35328,1062189,1007071,18766,11306,0,0,0,4096,66201,63169,4096,4096,128,512,594,27070,4257,0,48,172,0,8624,36352,223640,73575,1027374,26624,0,0,30208,65536,65536,65536,0,0,0,0,0,115,627,11656,2390,0,23693,8892,0,470,8422,1024,0,1024,4096,0,4096,512,512,0,0,360,16384,0,16384,0,0,2769,25966,0,8892,0,0,31,1933312,8192,0,0,0,512,512,0,120,15064,0,16384,16384,0,0,0,0,20714,0,0,0,0,0,0,0,32768,0,0,0,0,11426483,16411334,0,8192,0,0,0,0,697,0,0,0,0,0,1024,432,48,0,0,0,480,0,0,0,0,0,3216,0,0,0,8422,0,440,0,8192,6641,48,1503,1104,0,0,0,0,0,0,0,0,0,2560,0,0,0,49370,512,0,48,464,0,512,0,0,0,0,0,0,0,512,0,0,0,0,0,8192,0,0,471941,0,4096,8373,0,3660447,0,12076059884051927,12076086162418931,12076086162425171,12076059885056905
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,907703,907708,4194304,256,0,0,24,24,12928,0x7fa740bc6900,0x7fa635035140,0,524288,524288,65536,0,65536,524288,0,226908,226908,25125347,23787928,29320,6377395,22422044,22202323,23766592,21605288,1815264,1659037,226908,0,226908,0,7261056,6526565,0,0,0,0,0,20797810,524288,0,230956,0,0,0,230956,0,0,0,230956,0,0,0,230956,0,0,0,230956,0,0,0,230956,0,0,0,230956,0,0,0,230956,0,0,0,230956,0,0,0,230956,0,0,0,230956,0,0,0,230956,0,0,0,230956,0,0,0,230956,0,0,0,230956,0,0,0,230956,0,0,0,230956,0,0,0,230956,0,0,0,230956,0,0,0,230956,0,0,0,230956,0,0,0,230956,0,0,0,230956,0,0,0,230956,0,0,0,230956,0,0,0,230956,0,0,0,230956,0,0,0,230956,0,0,0,230956,0,0,0,230956,0,0,0,230956,0,0,0,230956,0,0,0,0,68219,0,102390,0,65584,0,4297,0,65540,0,5553,0,65536,0,9408,0,65536,0,12317,0,65536,0,6653,0,65536,0,10001,0,65537,0,6846,0,65536,0,190,0,65537,0,945,0,65536,0,0,0,65536,0,0,0,65537,0,0,0,65536,0,0,0,65536,0,736,0,65536,0,2225,0,65536,0,3296,0,65536,0,7502,0,65536,0,11176,0,65536,0,5724,0,65536,0,4411,0,65536,0,8073,0,65536,0,1371,0,65536,0,5338,0,66559,0,37191,0,65536,0,4014,0,65536,0,1639,0,65536,0,1290,0,65656,0,16044,0,65536,0,12473,0,65540,0,0,0,65536,0,682,0,524288,524288,0,41274704,0,0,0,34797256,0,0,0,32726378,0,0,0,41133430,0,0,0,34236297,0,0,0,34773539,0,0,0,37300673,0,0,0,41209427,0,0,0,37507573,0,0,0,37865636,0,0,0,37350599,0,0,0,33745834,0,0,0,54401593,0,0,0,40660006,0,0,0,37755823,0,0,0,37798415,0,0,0,37276856,0,0,0,37308420,0,0,0,33862706,0,0,0,39251342,0,0,0,38542265,0,0,0,36257428,0,0,0,36039071,0,0,0,37407112,0,0,0,35309773,0,0,0,37893115,0,0,0,35210201,0,0,0,35563125,0,0,0,40679240,0,0,0,36784481,0,0,0,38255991,0,0,0,41502291,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,524288,0,65536,65536,65536,0,65585,65585,65585,188,65540,65728,65728,0,68179,68179,68179,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65537,65537,65537,0,65536,65536,65536,0,65537,65537,65537,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65537,65537,65537,0,65536,65536,65536,0,65536,65536,65536,0,65656,65656,65656,0,65536,65536,65536,0,65536,65536,65536,47,65537,65584,65584,0,65536,65536,65536,0,65536,65536,65536,0,65584,65584,65584,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,188,65540,65728,65728,0,67044,67044,67044,65536,0,0,65536,0,0,65728,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65728,0,0,65536,0,0,0,0,65536,65536,4128768,115473141,43767662,67445639,209002,0,0,0,524288,22107264,22090279,524288,524288,16384,65536,758,227289,4197,0,48,4880,0,2097536,4259840,1731152,1564077,23172914,3014656,0,0,3473408,8388608,8388608,8388608,0,0,0,0,0,173294,202427,11843,2990,0,212267,2100058,0,423,2099635,131072,0,131072,524288,0,524288,65536,65536,0,0,360,2097152,0,2097152,56571,0,3070,214031,0,2099779,0,0,31,222298112,917504,0,0,0,65536,65536,0,7605,2019606,0,2097152,2097152,0,847513,850453,0,19649,0,0,0,0,0,0,0,4194304,0,0,0,0,1088566318,1913195842,0,2097152,0,0,0,0,192371,0,0,0,0,0,131072,384,48,0,0,0,432,0,0,0,0,0,10980,0,0,0,2100735,0,7148,0,917504,914876,48,7335,188079,0,0,0,0,0,0,0,0,0,327680,0,0,402687,455884,65536,64048,48,1440,0,65536,0,0,0,0,0,0,0,65536,0,0,0,1966101,0,2097152,0,0,17178686,0,524288,2099732,0,1168437211,0,12076059885686685,12076086162483891,12076086162615730,12076059886945885
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/prev_analysis/1.csv
index 9932324036..6a6aebee71 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,6051313.0,6051313.0,6051313.0,9.173648749440606
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4525245.0,4525245.0,4525245.0,6.860165411235933
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 256u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,3047816.0,3047816.0,3047816.0,4.62041765761002
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/prev_analysis/1001.csv
index ca08330db0..0e3bf5267e 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,46.862275449101794,Instr per wave
 SMEM,1.8083832335329342,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/prev_analysis/101.csv
index 27222a3d9e..477b9cf00f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx908
 mi100
 48
 1228.8
-SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/prev_analysis/1202.csv
index e847f9c995..af0fe76f6a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,33672.598979653,2815.2103271484375,547963.2384033203,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/prev_analysis/1901.csv
index 6ffbacddb1..4a07cebf15 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,2.0,smem_
 VALU,735.0,valu_
 MFMA,,mfma_
 VMEM,8.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,22.0,br_
 VGPR,24.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,67894.0,wavefronts_
 Workgroups,16973.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,163.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,0.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,44.0,hbm_rd_
 HBM Wr,0.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,70.0,vl1_coales_
 VL1 Stall,28.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,37.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/prev_analysis/2001.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/prev_analysis/201.csv
index 081a11fbcd..150d351e07 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,59.578259277544056,Pct,100,59.578259277544056
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,63.96956720806362,Threads,64,99.95244876259942
 IPC - Issue,0.8437421032127602,Instr/cycle,5,16.874842064255205
-LDS BW,0.0,Gb/sec,23070.72,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,23070.72,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99346404719937,Pct,100,99.99346404719937
 Instr Cache BW,1409.9881150445665,Gb/s,4614.144,30.557956471331767
 Scalar L1D Cache Hit Rate,99.35620448529356,Pct,100,99.35620448529356
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/prev_analysis/602.csv
index 6156e10e92..bc0e94d5d3 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,56404.26946107784,0,847513,Simd
 Insufficient SIMD VGPRs,599171.3592814371,0,33461964,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/prev_analysis/701.csv
index d3f1bff5a3..1071413faa 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,23.976047904191617,8,36,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/sysinfo.csv
index bda5624976..1d116e02a0 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-no_roof_Axes2,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 11:27:12 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+no_roof_Axes2,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 11:27:12 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/timestamps.csv
index 59d1c39e6f..cc8a3df714 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,909004,909009,33554432,256,0,0,8,32,6464,0x0,0x7f283d604180,12076086146705435,12076086146753232,12076086147076749,12076086147182061
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,909004,909009,32768,256,0,0,24,24,12480,0x0,0x7f283d635100,12076086162295699,12076086162418931,12076086162425171,12076086162431722
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,909004,909009,4194304,256,0,0,24,24,12928,0x7f29491c1900,0x7f283d635140,12076086162469292,12076086162483891,12076086162615730,12076086162619431
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/SQ_IFETCH_LEVEL.csv
index 2dca44e262..c5f9fda37e 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/SQ_IFETCH_LEVEL.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,208939,208939,33554432,256,0,0,4,32,4160,0x0,0x7f9dc8604280,380770,380770,524288,4718592,682467,76404388,17384917522740,17384213998881,17385067779097,17385067864757
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,208939,208939,32768,256,0,0,12,24,13888,0x0,0x7f9dc8623f80,33748,33748,512,8192,7452,827356,17385072982613,17385067779097,17385073103429,17385073106769
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,208939,208939,4194304,256,0,0,12,24,14336,0x7f9de6da5380,0x7f9dc8623fc0,165197,165197,65536,917504,140670,15737760,17385073143218,17385073103429,17385073442949,17385073444511
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/SQ_INST_LEVEL_LDS.csv
index 5d31f3ce21..4e596b56af 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/SQ_INST_LEVEL_LDS.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,210787,210787,33554432,256,0,0,4,32,4160,0x0,0x7fccd6804280,0,0,0,17404351107863,17403642565868,17404499572150,17404499686679
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,210787,210787,32768,256,0,0,12,24,13888,0x0,0x7fccd6823f80,0,0,0,17404504835295,17404499572150,17404504961427,17404504966261
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,210787,210787,4194304,256,0,0,12,24,14336,0x7fccd9778380,0x7fccd6823fc0,0,0,0,17404505000561,17404504961427,17404505322707,17404505325272
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/SQ_INST_LEVEL_SMEM.csv
index 208066daf3..78a20968ef 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/SQ_INST_LEVEL_SMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,208717,208717,33554432,256,0,0,4,32,4160,0x0,0x7f6b36404280,3670016,3090462,346532144,17383986805503,17355477132551,17384133435323,17384133547443
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,208717,208717,32768,256,0,0,12,24,13888,0x0,0x7f6b36423f80,512,92366,10332240,17384138634319,17384133435323,17384138773413,17384138778276
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,208717,208717,4194304,256,0,0,12,24,14336,0x7f6b39351380,0x7f6b36423fc0,65536,623274,69778592,17384138812755,17384138773413,17384139144454,17384139146886
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/SQ_INST_LEVEL_VMEM.csv
index 2d6367417b..5af3a4b749 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/SQ_INST_LEVEL_VMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,210565,210565,33554432,256,0,0,4,32,4160,0x0,0x7faae5604280,524288,5500327,616072820,17403413139662,17401146001708,17403561774224,17403561885524
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,210565,210565,32768,256,0,0,12,24,13888,0x0,0x7faae5623f80,4096,42444,4759008,17403567043359,17403561774224,17403567174711,17403567179545
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,210565,210565,4194304,256,0,0,12,24,14336,0x7faae8700380,0x7faae5623fc0,524288,10437825,1169063608,17403567213434,17403567174711,17403567543031,17403567545696
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/SQ_LEVEL_WAVES.csv
index ba8a409b67..6f9c625510 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/SQ_LEVEL_WAVES.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,209161,209161,33554432,256,0,0,4,32,4160,0x0,0x7f715d804280,381901,381901,8883,3055216,524288,239900398,2967676,0,975825440,17385866337917,17385148427241,17386016599484,17386016711164
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,209161,209161,32768,256,0,0,12,24,13888,0x0,0x7f715d823f80,33545,33545,30048,268368,512,1711068,162790,0,6857808,17386021891078,17386016599484,17386022026374,17386022030935
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,209161,209161,4194304,256,0,0,12,24,14336,0x7f7160908380,0x7f715d823fc0,163291,163291,13088,1306336,65536,74569519,1204279,0,300012068,17386022074443,17386022026374,17386022425735,17386022428214
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/pmc_perf.csv
index 4bf9be716c..6e0f6a4f20 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDI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],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBufferAligned.kd,0,0,0,209927,209927,33554432,256,0,0,4,32,4160,0x0,0x7f9a2a004280,3129144,3044341,524288,39551778,249260301,392,224,0,391142,391142,39817978.0,38359076.0,11.0,4230089.0,31513651.0,31153333.0,38341810.0,37784445.0,3127433,3050739,391142,0,391142,0,12516544.0,9465932.0,0.0,0.0,0,0,616,0,4718592,4714867,112,3613,368650,0.0,0.0,0.0,524288.0,27588611.0,26794307.0,7719.0,524288.0,131072,524288,302,377888,2260,0,56.0,306.0,0.0,4194696.0,0,0,0,0,0,7340032,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,20258750.0,524288.0,0,385742,0,0,0,385742,0,0,0,385742,0,0,0,385742,0,0,0,385742,0,0,0,385742,0,0,0,385742,0,0,0,385742,0,0,0,385742,0,0,0,385742,0,0,0,385742,0,0,0,385742,0,0,0,385742,0,0,0,385742,0,0,0,385742,0,0,0,385742,0,0,0,385742,0,0,0,385742,0,0,0,385742,0,0,0,385742,0,0,0,385742,0,0,0,385742,0,0,0,385742,0,0,0,385742,0,0,0,385742,0,0,0,385742,0,0,0,385742,0,0,0,385742,0,0,0,385742,0,0,0,385742,0,0,0,385742,0,0,0,385742,0,0,0,0,0,0.0,21151598.0,32,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2,0,0,0,2,0,0,0,112,0,0,0,0,0,0,0,0,0,0,0,32,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,32,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,4,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,56,0,0,0,32,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,524288.0,0.0,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,44445,129024,129024,0,329,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,447291,129024,129024,0,44565,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,196,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,28229,129024,129024,0,886,129024,129024,0,221,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,910,129024,129024,0,0,129024,129024,0,0,129024,129024,0,44326,129024,129024,0,282540,129024,129024,524288.0,0.0,43643,0,0,50458135,46126,0,0,50891758,44411,0,0,50075743,47139,0,0,52121767,45133,0,0,51355302,46933,0,0,51848612,43650,0,0,50582339,48329,0,0,53100402,44518,0,0,50723405,46817,0,0,51167073,44822,0,0,50368456,47103,0,0,52057070,45740,0,0,51595653,46997,0,0,51724582,46190,0,0,51350818,47673,0,0,52946871,44623,0,0,50592009,46578,0,0,51162827,43358,0,0,49986836,46935,0,0,51991105,44344,0,0,51104562,45681,0,0,51447602,44946,0,0,50908686,47221,0,0,52700102,45389,0,0,51002495,45384,0,0,50931578,45192,0,0,50509935,48201,0,0,52280558,46120,0,0,51649390,46755,0,0,51561176,46022,0,0,51332743,48859,0,0,53155734,0.0,65536,65568,32,131104,65536,65536,0,131072,65536,65536,0,131072,65536,65537,1,131073,65646,65538,112,131184,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65568,32,131104,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65537,1,131073,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65571,35,131107,65536,65592,56,131128,65536,65536,0,131072,65536,65536,0,131072,65758,65539,225,131297,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65591,65569,88,131160,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65591,65649,168,131240,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131184,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131296,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131128,0,131072,1069468,0,524288,3670016,3663359,224,6433,1048576,33554432.0,33554432.0,0.0,33554432.0,30059349.0,28414135.0,0.0,524288.0,215047,535075,8578,885,0,381527,4195055.0,0.0,2097594.0,2097461.0,1048576,1048576,0,524288,0,524288,7340032,0,0.0,0.0,104.0,8388608.0,29246807.0,2097152.0,0.0,198162,0,1216,381948,0,749.0,4194304.0,0.0,2064387.0,25690112,9437184,0,0,0,0,0,0,13286.0,8242462.0,0.0,8388608.0,2097152.0,4194304.0,9974850,0,0,8851,4128768.0,4128768.0,0.0,1491069.0,0,0,0,0,0,0,5767168,1048576,316331520.0,0.0,1473909140.0,0.0,41.0,0.0,0,0,374831,0.0,0.0,1493190.0,0.0,3670016,524288,0,0,0,2621440,524288,177476455,4194304.0,0.0,0.0,0.0,0.0,1218706.0,0,0,0.0,312.0,0.0,608.0,41625335,24117248,0,0,9437184,11010048,0,3145728,0.0,0.0,0.0,0.0,0.0,0.0,0,1572864,0.0,0.0,0.0,195862.0,524288,524288,0,3670016,7340032,603979776,4718592,0,0.0,0.0,0.0,0.0,0.0,0.0,524288,0,2064384.0,0.0,2031623.0,0.0,0,0,524288,0,0,0,0,33554432,0.0,4194304.0,0.0,19075829.0,0.0,0.0,142.0,4128768.0,651981.0,1653600325.0,17387299636236,17405169023666,17405169263026,17387442830652
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,209927,209927,32768,256,0,0,12,24,13888,0x0,0x7f9a2a023f80,268104,159566,512,1442922,1779126,504,56,0,33512,33512,2305420.0,175579.0,176.0,0.0,39600.0,36382.0,169280.0,150440.0,268096,166516,33512,0,33512,0,1072384.0,380908.0,0.0,0.0,0,0,560,0,8192,6149,56,1987,23684,0.0,0.0,0.0,4096.0,36718.0,35315.0,0.0,4096.0,128,512,302,32790,2218,0,0.0,60.0,0.0,4600.0,0,0,0,0,0,1024,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,14734.0,4096.0,0,33279,0,0,0,33279,0,0,0,33279,0,0,0,33279,0,0,0,33279,0,0,0,33279,0,0,0,33279,0,0,0,33279,0,0,0,33279,0,0,0,33279,0,0,0,33279,0,0,0,33279,0,0,0,33279,0,0,0,33279,0,0,0,33279,0,0,0,33279,0,0,0,33279,0,0,0,33279,0,0,0,33279,0,0,0,33279,0,0,0,33279,0,0,0,33279,0,0,0,33279,0,0,0,33279,0,0,0,33279,0,0,0,33279,0,0,0,33279,0,0,0,33279,0,0,0,33279,0,0,0,33279,0,0,0,33279,0,0,0,33279,0,0,0,0,0,0.0,0.0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,261,0,0,0,312,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,4096.0,4096.0,0,77460,0,0,0,79751,0,0,0,78663,0,0,0,80093,0,0,0,79550,0,0,0,79710,0,0,0,82090,0,0,0,85990,0,0,0,77168,0,0,0,94128,0,0,0,75666,0,0,0,663070,0,0,0,84825,0,0,0,80857,0,0,0,80758,0,0,0,86029,0,0,0,80340,0,0,0,111448,0,0,0,79981,0,0,0,84830,0,0,0,84979,0,0,0,84893,0,0,0,79045,0,0,0,88124,0,0,0,79065,0,0,0,85413,0,0,0,79690,0,0,0,91227,0,0,0,90647,0,0,0,84269,0,0,0,82674,0,0,0,85798,0,0,0.0,0.0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4096.0,0,128,128,128,0,128,128,128,0,128,128,128,0,129,129,129,0,128,128,128,222,130,352,352,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,129,129,129,222,130,352,352,0,128,128,128,0,128,128,128,0,128,128,128,0,130,130,130,0,128,128,128,0,128,128,128,0,128,128,128,0,129,129,129,55,129,184,184,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,184,184,184,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,352,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,352,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,184,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,660,0,0,512,0,56,456,0,65536.0,65536.0,65536.0,0.0,0.0,0.0,0.0,0.0,6,518,11143,1033,0,30019,4659.0,0.0,499.0,4160.0,512,0,0,0,4096,4096,512,0,0.0,0.0,104.0,16384.0,0.0,16384.0,4096.0,0,0,1306,31774,0,4659.0,0.0,0.0,31.0,35328,26112,0,0,0,0,0,0,104.0,15240.0,0.0,16384.0,16384.0,0.0,0,0,0,29675,0.0,0.0,0.0,0.0,0,0,0,0,0,0,10752,3584,3814073.0,5140477.0,0.0,8192.0,0.0,0.0,0,0,499,0.0,0.0,0.0,0.0,512,4096,0,0,0,512,512,1662429,0.0,0.0,0.0,0.0,0.0,1432.0,0,0,0.0,8261.0,0.0,120.0,13904,32256,0,0,26112,1024,0,1024,0.0,0.0,0.0,0.0,0.0,0.0,0,1024,0.0,0.0,0.0,52468.0,4096,0,4096,512,512,1671168,8192,0,0.0,0.0,0.0,0.0,0.0,0.0,512,0,0.0,0.0,0.0,0.0,0,0,512,0,0,0,0,32768,8192.0,0.0,0.0,116921.0,0.0,4096.0,8207.0,0.0,3404489.0,0.0,17387449056929,17405174031030,17405174043990,17387449533726
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,209927,209927,4194304,256,0,0,12,24,14336,0x7f9a2d07e380,0x7f9a2a023fc0,1318680,1213954,65536,15693282,71403541,392,56,0,164834,164834,16012360.0,14557444.0,22566.0,851262.0,12150593.0,11575474.0,14550944.0,12419242.0,1318672,1220325,164834,0,164834,0,5274688.0,4757855.0,0.0,0.0,0,0,448,0,917504,913279,0,4225,153608,0.0,0.0,0.0,524288.0,13300855.0,13276390.0,2108.0,524288.0,16384,65536,302,164107,2254,0,0.0,183.0,0.0,1048968.0,0,0,0,0,0,131072,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,10694997.0,524288.0,0,170049,0,0,0,170049,0,0,0,170049,0,0,0,170049,0,0,0,170049,0,0,0,170049,0,0,0,170049,0,0,0,170049,0,0,0,170049,0,0,0,170049,0,0,0,170049,0,0,0,170049,0,0,0,170049,0,0,0,170049,0,0,0,170049,0,0,0,170049,0,0,0,170049,0,0,0,170049,0,0,0,170049,0,0,0,170049,0,0,0,170049,0,0,0,170049,0,0,0,170049,0,0,0,170049,0,0,0,170049,0,0,0,170049,0,0,0,170049,0,0,0,170049,0,0,0,170049,0,0,0,170049,0,0,0,170049,0,0,0,170049,0,0,0,0,0,0.0,0.0,65537,0,37224,0,65536,0,23342,0,65536,0,33270,0,65536,0,14860,0,65536,0,30474,0,65537,0,23014,0,65592,0,20060,0,65536,0,28053,0,65536,0,20664,0,65536,0,19341,0,65536,0,6804,0,65536,0,24551,0,65536,0,11823,0,65536,0,32411,0,65537,0,30480,0,65536,0,20542,0,65536,0,25991,0,65536,0,26591,0,65596,0,12003,0,65536,0,19290,0,65537,0,20778,0,65536,0,29329,0,65536,0,24960,0,65539,0,36884,0,65540,0,19153,0,65536,0,27185,0,65536,0,11854,0,65601,0,17613,0,65536,0,25000,0,65536,0,48443,0,65536,0,30045,0,65536,0,32666,0,524288.0,524288.0,0,48278863,0,0,0,45795200,0,0,0,44975820,0,0,0,44031972,0,0,0,50756481,0,0,0,49256485,0,0,0,49004065,0,0,0,48514037,0,0,0,44406120,0,0,0,41761763,0,0,0,39630711,0,0,0,48752592,0,0,0,41272916,0,0,0,49193685,0,0,0,48655123,0,0,0,49136889,0,0,0,46600864,0,0,0,52170566,0,0,0,38763923,0,0,0,49236842,0,0,0,41876413,0,0,0,42962906,0,0,0,49529574,0,0,0,41172415,0,0,0,39299013,0,0,0,50953320,0,0,0,40830614,0,0,0,39309682,0,0,0,49175302,0,0,0,45768116,0,0,0,50892168,0,0,0,47773594,0,0,0.0,0.0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,524288.0,0,32768,32768,32768,0,32769,32769,32769,0,32768,32768,32768,0,32769,32769,32769,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32769,32769,32769,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32827,32827,32827,0,32769,32769,32769,0,32768,32768,32768,0,32768,32768,32768,0,32769,32769,32769,166,32770,32936,32936,222,32770,32992,32992,0,32768,32768,32768,0,32768,32768,32768,0,32832,32832,32832,0,32769,32769,32769,0,32768,32768,32768,0,32768,32768,32768,0,32824,32824,32824,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32936,0,0,32992,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,878330,0,0,65536,63800,56,1680,0,8388608.0,8388608.0,8388608.0,0.0,0.0,0.0,0.0,0.0,125247,146094,10031,2420,0,161856,1049153.0,0.0,388.0,1048765.0,65536,0,0,0,524288,524288,131072,0,0.0,0.0,104.0,2097152.0,0.0,2097152.0,524288.0,53174,0,2836,162238,0,1049152.0,0.0,0.0,31.0,4063232,2883584,0,0,0,0,0,0,6588.0,2028143.0,0.0,2097152.0,2097152.0,0.0,1290815,0,0,14062,0.0,0.0,0.0,0.0,262144,0,0,0,0,0,1507328,458752,963604450.0,2311119479.0,0.0,2097152.0,169.0,0.0,0,0,147930,0.0,0.0,0.0,0.0,65536,524288,0,0,0,65536,65536,46344147,0.0,0.0,0.0,0.0,0.0,5625.0,0,0,0.0,2097325.0,0.0,332.0,25840325,3735552,0,0,2883584,196608,0,131072,0.0,0.0,0.0,0.0,0.0,0.0,0,131072,0.0,0.0,402780.0,1244424.0,524288,0,524288,65536,131072,184549376,917504,0,0.0,0.0,0.0,0.0,0.0,0.0,65536,0,0.0,0.0,983047.0,0.0,0,0,65536,0,0,0,0,4194304,2097152.0,0.0,0.0,12379405.0,0.0,524288.0,2097286.0,0.0,1405487286.0,0.0,17387450632558,17405174120951,17405174213431,17387451439047
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/prev_analysis/1.csv
index b4e6073cf0..7e0d69843c 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,3356324.0,3356324.0,3356324.0,7.83888141459186
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,1725121.0,1725121.0,1725121.0,4.029116064129126
 "void benchmark_func<double, 256, 8u, 512u>(double, double*) [clone .kd]",1,1716002.0,1716002.0,1716002.0,4.007818132338374
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/prev_analysis/1001.csv
index f475f954a6..fb5988001a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,494.8622754491018,Instr per wave
 VMEM,7.958083832335329,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,0.0,Instr per wave
 SALU,24.520958083832337,Instr per wave
 SMEM,1.8023952095808384,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/prev_analysis/101.csv
index 4fa9ba5456..7a2bbf2932 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx90a
 mi200
 56
 1638.4
-SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/prev_analysis/1202.csv
index ad79967389..cddd9d71fc 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,18191.751434371858,1901.705177307129,258413.38092041016,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/prev_analysis/1901.csv
index 872f40aedb..ecca2bb8c1 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,2.0,smem_
 VALU,495.0,valu_
 MFMA,0.0,mfma_
 VMEM,8.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,10.0,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,67894.0,wavefronts_
 Workgroups,16973.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,128.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,0.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,44.0,hbm_rd_
 HBM Wr,0.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,70.0,vl1_coales_
 VL1 Stall,2.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,25.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/prev_analysis/201.csv
index 884a4e6f51..7a61ea7e9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,58.32427090133267,Pct,100,58.32427090133267
 MFMA Util,0.0,Pct,100,0.0
 VALU Active Threads/Wave,64.0,Threads,64,100.0
 IPC - Issue,1.0,Instr/cycle,5,20.0
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99255114520308,Pct,100,99.99255114520308
 Instr Cache BW,1673.4367696692586,Gb/s,6092.8,27.46580832571656
 Scalar L1D Cache Hit Rate,99.34855886109348,Pct,100,99.34855886109348
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/prev_analysis/602.csv
index 9a31d1be43..5d3652a042 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,11800302.550898204,0,360375643,Simd
 Insufficient SIMD VGPRs,0.0,0,0,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/prev_analysis/701.csv
index 12250d77c0..db0925a109 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/sysinfo.csv
index c5a9a6a85c..c6a29da70b 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-no_roof_Axes2,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:43:04 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+no_roof_Axes2,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:43:04 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/timestamps.csv
index 6a554d495e..0e1b50823e 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes2/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,210870,210870,33554432,256,0,0,4,32,4160,0x0,0x7f84fd804280,17405168998305,17405169023666,17405169263026,17405169346376
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,210870,210870,32768,256,0,0,12,24,13888,0x0,0x7f84fd823f80,17405174015724,17405174031030,17405174043990,17405174060933
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,210870,210870,4194304,256,0,0,12,24,14336,0x7f85007d2380,0x7f84fd823fc0,17405174065833,17405174120951,17405174213431,17405174215899
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/SQ_IFETCH_LEVEL.csv
index a73c6c094c..8848ad39fb 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/SQ_IFETCH_LEVEL.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,911962,911967,33554432,256,0,0,8,32,6464,0x0,0x7fb2c2004180,504753,504753,524288,6291456,799116,102238468,12076153591940549,12076153837017121,12076153837341599,12076153837463061
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,911962,911967,32768,256,0,0,24,24,12480,0x0,0x7fb2c2035100,27176,27176,512,8192,9278,1193980,12076153851904480,12076153852225916,12076153852231996,12076153852241857
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,911962,911967,4194304,256,0,0,24,24,12928,0x7fb3cdcae900,0x7fb2c2035140,217995,217995,65536,917504,140854,18024520,12076153852306297,12076153852527514,12076153852660313,12076153852664362
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/SQ_INST_LEVEL_LDS.csv
index 3cb2a0b596..c0f5bb6f74 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/SQ_INST_LEVEL_LDS.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,913760,913765,33554432,256,0,0,8,32,6464,0x0,0x7f5ef4604180,0,0,0,12076179931865913,12076180176628460,12076180176951339,12076180177063542
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,913760,913765,32768,256,0,0,24,24,12480,0x0,0x7f5ef4635100,0,0,0,12076180191753222,12076180192060270,12076180192066830,12076180192077755
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,913760,913765,4194304,256,0,0,24,24,12928,0x7f6000317900,0x7f5ef4635140,0,0,0,12076180192136635,12076180192356428,12076180192490028,12076180192493949
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/SQ_INST_LEVEL_SMEM.csv
index c514a0cb77..ce3feb2422 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/SQ_INST_LEVEL_SMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,913382,913387,33554432,256,0,0,8,32,6464,0x0,0x7f1da9e04180,4194304,3116158,398829112,12076177400554202,12076177645817867,12076177646143626,12076177646229429
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,913382,913387,32768,256,0,0,24,24,12480,0x0,0x7f1da9e35100,512,23398,2983472,12076177660644919,12076177660951477,12076177660957557,12076177660969292
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,913382,913387,4194304,256,0,0,24,24,12928,0x7f1eb5b0e900,0x7f1da9e35140,65536,172884,22162008,12076177661022682,12076177661274195,12076177661413555,12076177661417726
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/SQ_INST_LEVEL_VMEM.csv
index 832a634da8..b2f723fa21 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/SQ_INST_LEVEL_VMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,913572,913577,33554432,256,0,0,8,32,6464,0x0,0x7f8f52004180,1048576,11079013,1417261840,12076178667920927,12076178913805984,12076178914131103,12076178914242705
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,913572,913577,32768,256,0,0,24,24,12480,0x0,0x7f8f52035100,4096,107588,13764736,12076178928948285,12076178929272757,12076178929279157,12076178929287716
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,913572,913577,4194304,256,0,0,24,24,12928,0x7f905dc9f900,0x7f8f52035140,524288,12228909,1565146912,12076178929346024,12076178929563796,12076178929696435,12076178929700252
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/SQ_LEVEL_WAVES.csv
index 81a1cbd83e..1e7068cae0 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/SQ_LEVEL_WAVES.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,913948,913955,33554432,256,0,0,8,32,6464,0x0,0x7f216f204180,503056,503056,16633,4024456,524288,373245425,3816248,0,1507795840,12076181191358164,12076181435056998,12076181435380356,12076181435488459
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,913948,913955,32768,256,0,0,24,24,12480,0x0,0x7f216f235100,29559,29559,22245,236480,512,1204372,80453,0,4831408,12076181450133997,12076181450469559,12076181450476439,12076181450481753
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,913948,913955,4194304,256,0,0,24,24,12928,0x7f229f435900,0x7f216f235140,220620,220620,23758,1764968,65536,139508018,1588877,0,559844332,12076181450552154,12076181450796917,12076181450930836,12076181450934855
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/pmc_dispatch_info.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/pmc_perf.csv
index e6fb4bb4c1..90060b1b51 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBuffer.kd,0,0,0,912696,912701,33554432,256,0,0,8,32,6464,0x0,0x7fa032804180,1048576,0,1048576,9437184,0,4194304,1048576,0,507911,507911,58403199,55826933,64,12430065,54888792,54784136,55776274,54593854,4063288,3877998,507911,0,507911,0,16253152,15422042,0,0,0,0,0,17491334,1048576,0,507356,0,0,0,507356,0,0,0,507356,0,0,0,507356,0,0,0,507356,0,0,0,507356,0,0,0,507356,0,0,0,507356,0,0,0,507356,0,0,0,507356,0,0,0,507356,0,0,0,507356,0,0,0,507356,0,0,0,507356,0,0,0,507356,0,0,0,507356,0,0,0,507356,0,0,0,507356,0,0,0,507356,0,0,0,507356,0,0,0,507356,0,0,0,507356,0,0,0,507356,0,0,0,507356,0,0,0,507356,0,0,0,507356,0,0,0,507356,0,0,0,507356,0,0,0,507356,0,0,0,507356,0,0,0,507356,0,0,0,507356,0,0,0,37113988,2603,0,0,0,4,0,0,0,49,0,0,0,49,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,2551,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,22,0,0,0,3,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,48,0,0,0,0,0,0,0,2490,0,0,0,4,0,0,0,1,0,0,0,0,0,0,0,2621,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1048576,0,0,0,131076,131076,0,15084,131072,131072,0,0,131072,131072,0,3382212,131076,131076,0,272,131076,131076,0,0,131072,131072,0,0,131084,131084,0,2831670,131078,131078,0,260,131072,131072,0,0,131072,131072,0,0,131072,131072,0,1606,131072,131072,0,565933,131072,131072,0,0,131076,131076,0,0,131072,131072,0,66241,131076,131076,0,0,131072,131072,0,784,131080,131080,0,0,131076,131076,0,3301749,131072,131072,0,0,131084,131084,0,0,131084,131084,0,0,131072,131072,0,0,131076,131076,0,0,131084,131084,0,0,131076,131076,0,0,131072,131072,0,0,131072,131072,0,738,131072,131072,0,23864,131072,131072,0,0,131072,131072,0,3442355,131076,131076,1048576,0,899,0,0,16973849,1587,0,0,17329866,47410,0,0,29907646,849,0,0,17429058,833,0,0,17115856,1163,0,0,17323874,945,0,0,17799504,885,0,0,18783308,1001,0,0,17159846,1642,0,0,17296004,1551,0,0,16595700,857,0,0,16993505,1180,0,0,17164311,1177,0,0,17392362,47101,0,0,30411333,1522,0,0,18855879,939,0,0,16617092,1173,0,0,16967821,48338,0,0,30136091,873,0,0,17259429,1003,0,0,17234315,1188,0,0,17285328,889,0,0,17752073,910,0,0,18727192,854,0,0,16550582,1643,0,0,16778543,1675,0,0,16668962,1654,0,0,17245641,855,0,0,17051752,1115,0,0,17149950,48215,0,0,30539659,943,0,0,18810852,1048576,131072,131120,48,262192,131260,131076,192,262336,131072,131075,3,262147,131072,131072,0,262144,131072,131091,19,262163,131072,131072,0,262144,131119,131073,48,262192,131072,131072,0,262144,131072,133712,2640,264784,131072,131072,0,262144,131072,131073,1,262145,131072,131072,0,262144,131072,131073,1,262145,131072,131072,0,262144,131072,131072,0,262144,131072,133679,2607,264751,131072,131073,1,262145,131213,131075,144,262288,131072,131072,0,262144,131072,133618,2546,264690,131072,133542,2470,264614,131072,131072,0,262144,131072,131072,0,262144,131072,131120,48,262192,131072,131072,0,262144,131072,131072,0,262144,131072,131120,48,262192,131072,131072,0,262144,131072,131072,0,262144,131119,131073,48,262192,131072,131072,0,262144,131072,131072,0,262144,262144,0,262144,262336,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262288,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,0,0,3145728,524288,32505856,369544293,218800718,118237719,481976,0,0,0,1048576,52485996,52238620,1048576,1048576,131072,524288,714,504484,4460,0,96,10590,0,8388944,32505856,4020736,3816818,57078345,11534336,0,0,14155776,67108864,67108864,0,67108864,54376467,54068511,0,1048576,239377,763665,11718,2418,0,498136,8399656,0,4194727,4204929,13631488,0,3670016,1048576,1048576,0,4194304,9437184,0,0,360,33554432,54472810,4194304,0,0,2827,504447,0,11192,8388608,0,4194415,905969664,6291456,0,0,0,524288,524288,0,15324,16608816,0,16777216,4194304,4194304,0,0,0,16500,4194350,4194350,0,224218,0,0,0,33554432,0,0,0,0,636295480,0,2797499070,0,0,0,0,0,478778,0,0,212790,0,0,8388608,336,144,0,0,0,480,8388608,0,0,0,0,371672,0,0,0,10700,0,21382,0,6291456,6289592,96,1976,1959390,0,0,0,0,0,0,0,0,0,3145728,0,0,0,153226,4194304,4189862,144,4298,2097152,524288,1572864,0,0,0,0,0,0,524288,0,4128909,65533,4063247,0,0,8388608,0,42103463,0,1048576,10687,4194398,13095176,610457054,12076155701746479,12076182316374996,12076182316698353,12076155950446367
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,912696,912701,32768,256,0,0,24,24,12480,0x0,0x7fa032835100,0,4096,4096,512,0,512,4096,0,27917,27917,1508387,629449,201,120480,86405,65880,621336,600815,223336,86379,27917,0,27917,0,893344,203363,0,0,0,0,0,64596,4096,0,28606,0,0,0,28606,0,0,0,28606,0,0,0,28606,0,0,0,28606,0,0,0,28606,0,0,0,28606,0,0,0,28606,0,0,0,28606,0,0,0,28606,0,0,0,28606,0,0,0,28606,0,0,0,28606,0,0,0,28606,0,0,0,28606,0,0,0,28606,0,0,0,28606,0,0,0,28606,0,0,0,28606,0,0,0,28606,0,0,0,28606,0,0,0,28606,0,0,0,28606,0,0,0,28606,0,0,0,28606,0,0,0,28606,0,0,0,28606,0,0,0,28606,0,0,0,28606,0,0,0,28606,0,0,0,28606,0,0,0,28606,0,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,305,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,376,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,304,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,4096,4096,0,93693,0,0,0,111924,0,0,0,78614,0,0,0,73761,0,0,0,79684,0,0,0,112022,0,0,0,81139,0,0,0,90086,0,0,0,78784,0,0,0,82219,0,0,0,94283,0,0,0,80979,0,0,0,168875,0,0,0,85104,0,0,0,99638,0,0,0,193897,0,0,0,117355,0,0,0,131230,0,0,0,65004,0,0,0,70299,0,0,0,119191,0,0,0,113266,0,0,0,80695,0,0,0,86867,0,0,0,127909,0,0,0,105781,0,0,0,88720,0,0,0,88897,0,0,0,83747,0,0,0,153414,0,0,0,114690,0,0,0,91680,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4096,0,304,304,304,0,256,256,256,0,256,256,256,0,256,256,256,0,377,377,377,0,256,256,256,47,257,304,304,0,256,256,256,0,256,256,256,0,256,256,256,0,257,257,257,0,256,256,256,0,257,257,257,0,256,256,256,188,260,448,448,0,256,256,256,0,257,257,257,0,256,256,256,188,260,448,448,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,304,304,304,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,47,257,304,304,0,256,256,256,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,304,0,0,256,0,0,0,0,512,512,35328,1070783,1017945,16486,11059,0,0,0,4096,68100,65055,4096,4096,128,512,609,27706,4337,0,48,171,0,8624,36352,228160,73985,1032321,26624,0,0,30208,65536,65536,65536,0,0,0,0,0,119,631,11825,2774,0,24218,8892,0,470,8422,1024,0,1024,4096,0,4096,512,512,0,0,360,16384,0,16384,0,0,2814,25254,0,8844,0,0,31,1933312,8192,0,0,0,512,512,0,120,15064,0,16384,16384,0,0,0,0,21575,0,0,0,0,0,0,0,32768,0,0,0,0,11804390,16153553,0,8192,0,0,0,0,696,0,0,0,0,0,1024,432,48,0,0,0,480,0,0,0,0,0,2780,0,0,0,8541,0,678,0,8192,6545,48,1599,1088,0,0,0,0,0,0,0,0,0,2560,0,0,0,50217,512,0,48,464,0,512,0,0,0,0,0,0,0,512,0,0,0,0,0,8192,0,0,409333,0,4096,8372,0,3135447,0,12076155965358481,12076182331822481,12076182331829361,12076155966482660
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,912696,912701,4194304,256,0,0,24,24,12928,0x7fa13e502900,0x7fa032835140,0,524288,524288,65536,0,65536,524288,0,215650,215650,23870297,22617689,32029,12353297,21741321,21644960,22601284,20429068,1725200,1575367,215650,0,215650,0,6900800,6178818,0,0,0,0,0,20052539,524288,0,215255,0,0,0,215255,0,0,0,215255,0,0,0,215255,0,0,0,215255,0,0,0,215255,0,0,0,215255,0,0,0,215255,0,0,0,215255,0,0,0,215255,0,0,0,215255,0,0,0,215255,0,0,0,215255,0,0,0,215255,0,0,0,215255,0,0,0,215255,0,0,0,215255,0,0,0,215255,0,0,0,215255,0,0,0,215255,0,0,0,215255,0,0,0,215255,0,0,0,215255,0,0,0,215255,0,0,0,215255,0,0,0,215255,0,0,0,215255,0,0,0,215255,0,0,0,215255,0,0,0,215255,0,0,0,215255,0,0,0,215255,0,0,0,0,65536,0,1,0,65536,0,9442,0,65541,0,22693,0,65585,0,130,0,65536,0,8690,0,65536,0,4035,0,65536,0,7254,0,65536,0,15016,0,65536,0,8711,0,65536,0,7573,0,65536,0,2290,0,65537,0,2010,0,67652,0,81449,0,65536,0,8794,0,65536,0,2020,0,65536,0,1500,0,65656,0,24251,0,65536,0,6978,0,65536,0,0,0,65536,0,12281,0,65536,0,10894,0,65536,0,15660,0,65584,0,12116,0,65536,0,19126,0,65536,0,3439,0,65536,0,5268,0,65537,0,15699,0,65536,0,12506,0,66955,0,47843,0,65536,0,6645,0,65540,0,10262,0,65536,0,11386,0,524288,524288,0,27507015,0,0,0,30666053,0,0,0,24478667,0,0,0,41642729,0,0,0,28051816,0,0,0,34586580,0,0,0,28028953,0,0,0,33060788,0,0,0,29107478,0,0,0,31180226,0,0,0,26331715,0,0,0,28140496,0,0,0,29018043,0,0,0,30269794,0,0,0,27644019,0,0,0,32625231,0,0,0,27566316,0,0,0,28772540,0,0,0,25939182,0,0,0,52944067,0,0,0,27299008,0,0,0,31042207,0,0,0,28511487,0,0,0,33294645,0,0,0,28349188,0,0,0,31218611,0,0,0,30181696,0,0,0,27944787,0,0,0,24277617,0,0,0,29985399,0,0,0,32092930,0,0,0,33546798,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,524288,0,65584,65584,65584,0,65536,65536,65536,188,65540,65728,65728,0,65536,65536,65536,0,65658,65658,65658,0,65536,65536,65536,47,65537,65584,65584,0,65536,65536,65536,0,66797,66797,66797,0,65536,65536,65536,0,65537,65537,65537,0,65536,65536,65536,0,65537,65537,65537,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65537,65537,65537,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,68221,68221,68221,0,65536,65536,65536,0,65536,65536,65536,0,65584,65584,65584,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,188,65540,65728,65728,0,65536,65536,65536,65536,0,0,65536,0,0,65728,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65728,0,0,65536,0,0,0,0,65536,65536,4128768,115711948,43557839,67894269,208958,0,0,0,524288,22725675,22711717,524288,524288,16384,65536,761,226798,4256,0,48,4965,0,2097536,4259840,1780904,1615263,23904388,3014656,0,0,3473408,8388608,8388608,8388608,0,0,0,0,0,160671,198291,11308,2413,0,218405,2101629,0,423,2101206,131072,0,131072,524288,0,524288,65536,65536,0,0,360,2097152,0,2097152,35968,0,2884,221610,0,2101202,0,0,31,222298112,917504,0,0,0,65536,65536,0,7543,2016033,0,2097152,2097152,0,604294,606131,0,21236,0,0,0,0,0,0,0,4194304,0,0,0,0,886199836,1388133349,0,2097152,0,0,0,0,200086,0,0,0,0,0,131072,384,48,0,0,0,432,0,0,0,0,0,5497,0,0,0,2099916,0,5510,0,917504,914685,48,7549,176449,0,0,0,0,0,0,0,0,0,327680,0,0,515570,569277,65536,64048,48,1440,0,65536,0,0,0,0,0,0,0,65536,0,0,0,1966102,0,2097152,0,0,14924808,0,524288,2101779,0,906918715,0,12076155967096901,12076182331892560,12076182332025999,12076155968510749
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/prev_analysis/1.csv
index 2b49e8645d..298e431db2 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,6051307.0,6051307.0,6051307.0,9.17513838010089
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4525560.0,4525560.0,4525560.0,6.86176378878966
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 256u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,3047013.0,3047013.0,3047013.0,4.619954981785977
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/prev_analysis/1001.csv
index ca08330db0..0e3bf5267e 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,46.862275449101794,Instr per wave
 SMEM,1.8083832335329342,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/prev_analysis/101.csv
index 2aba454155..afa6302dcb 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx908
 mi100
 48
 1228.8
-SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/prev_analysis/1202.csv
index 491d881fa2..745cf6d96d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,33514.45351190624,2819.3992080688477,547898.5025024414,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/prev_analysis/1901.csv
index 59c0e8144c..6c33bdf929 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,2.0,smem_
 VALU,735.0,valu_
 MFMA,,mfma_
 VMEM,8.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,22.0,br_
 VGPR,24.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,67894.0,wavefronts_
 Workgroups,16973.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,163.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,0.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,44.0,hbm_rd_
 HBM Wr,0.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,70.0,vl1_coales_
 VL1 Stall,30.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,36.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/prev_analysis/2001.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/prev_analysis/201.csv
index 4cea38ac59..82d8ffdc9d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,59.32241838170016,Pct,100,59.32241838170016
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,63.96822159582798,Threads,64,99.95034624348122
 IPC - Issue,0.8437299410926439,Instr/cycle,5,16.874598821852878
-LDS BW,0.0,Gb/sec,23070.72,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,23070.72,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99340397078224,Pct,100,99.99340397078224
 Instr Cache BW,1409.3189194958572,Gb/s,4614.144,30.54345333600029
 Scalar L1D Cache Hit Rate,99.356204485269,Pct,100,99.356204485269
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/prev_analysis/602.csv
index 3be294d678..76dfa26d82 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,68786.13173652695,0,632030,Simd
 Insufficient SIMD VGPRs,604764.0239520958,0,40744842,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/prev_analysis/701.csv
index d3f1bff5a3..1071413faa 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,23.976047904191617,8,36,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/sysinfo.csv
index a6b235d986..117fae5ffa 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-no_roof_Axes3,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 11:28:48 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+no_roof_Axes3,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 11:28:48 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/timestamps.csv
index 71ab0bdfeb..880c7ce42d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,913999,914004,33554432,256,0,0,8,32,6464,0x0,0x7fc2bb204180,12076182316331086,12076182316374996,12076182316698353,12076182316803594
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,913999,914004,32768,256,0,0,24,24,12480,0x0,0x7fc2bb235100,12076182331718924,12076182331822481,12076182331829361,12076182331835510
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,913999,914004,4194304,256,0,0,24,24,12928,0x7fc3eb372900,0x7fc2bb235140,12076182331879292,12076182331892560,12076182332025999,12076182332030022
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/SQ_IFETCH_LEVEL.csv
index 3200c219e2..64e9d5a7a5 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/SQ_IFETCH_LEVEL.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,214397,214397,33554432,256,0,0,4,32,4160,0x0,0x7f7b4a604280,379644,379644,524288,4718592,685822,76774196,17463231756954,17462527571207,17463375206268,17463375316388
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,214397,214397,32768,256,0,0,12,24,13888,0x0,0x7f7b4a623f80,24999,24999,512,8192,7719,871720,17463380640669,17463375206268,17463380770117,17463380775136
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,214397,214397,4194304,256,0,0,12,24,14336,0x7f7b4d582380,0x7f7b4a623fc0,164653,164653,65536,917504,140986,15749028,17463380816355,17463380770117,17463381159078,17463381162406
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/SQ_INST_LEVEL_LDS.csv
index 2536cc6e8e..a2933539ec 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/SQ_INST_LEVEL_LDS.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,216245,216245,33554432,256,0,0,4,32,4160,0x0,0x7fa740c04280,0,0,0,17482412532945,17481714777627,17482560220522,17482560285571
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,216245,216245,32768,256,0,0,12,24,13888,0x0,0x7fa740c23f80,0,0,0,17482565534566,17482560220522,17482565658130,17482565663113
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,216245,216245,4194304,256,0,0,12,24,14336,0x7fa743c69380,0x7fa740c23fc0,0,0,0,17482565699202,17482565658130,17482566048850,17482566051723
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/SQ_INST_LEVEL_SMEM.csv
index 11d6700a7c..c6f6310a3c 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/SQ_INST_LEVEL_SMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,214175,214175,33554432,256,0,0,4,32,4160,0x0,0x7f6659604280,3670016,2712340,304187944,17462297674138,17433887214017,17462445968337,17462446053487
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,214175,214175,32768,256,0,0,12,24,13888,0x0,0x7f6659623f80,512,63888,7179400,17462451307840,17462445968337,17462451436343,17462451441437
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,214175,214175,4194304,256,0,0,12,24,14336,0x7f665c578380,0x7f6659623fc0,65536,407250,45596944,17462451477206,17462451436343,17462451811864,17462451814907
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/SQ_INST_LEVEL_VMEM.csv
index 9da6babf3f..c272dba6ac 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/SQ_INST_LEVEL_VMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,216023,216023,33554432,256,0,0,4,32,4160,0x0,0x7fdbb6e04280,524288,5453952,610773796,17481487101406,17479182930152,17481634570907,17481634683416
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,216023,216023,32768,256,0,0,12,24,13888,0x0,0x7fdbb6e23f80,4096,51240,5747212,17481639879632,17481634570907,17481640005313,17481640010649
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,216023,216023,4194304,256,0,0,12,24,14336,0x7fdbb9ea1380,0x7fdbb6e23fc0,524288,11681165,1308340480,17481640046538,17481640005313,17481640375553,17481640378699
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/SQ_LEVEL_WAVES.csv
index b9152b4a9a..a5235552c3 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/SQ_LEVEL_WAVES.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,214619,214619,33554432,256,0,0,4,32,4160,0x0,0x7fa9f5204280,378608,378608,8666,3028872,524288,236781304,2939528,0,963353808,17464155345524,17463458061698,17464301622125,17464301739445
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,214619,214619,32768,256,0,0,12,24,13888,0x0,0x7fa9f5223f80,26146,26146,22486,209176,512,1368516,113964,0,5487876,17464306981359,17464301622125,17464307120055,17464307125296
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,214619,214619,4194304,256,0,0,12,24,14336,0x7fa9f8277380,0x7fa9f5223fc0,164177,164177,13829,1313424,65536,89987119,1206540,0,361685532,17464307173594,17464307120055,17464307524696,17464307527625
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/pmc_perf.csv
index 792c3eb308..4e3415fcdd 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDI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],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBufferAligned.kd,0,0,0,215385,215385,33554432,256,0,0,4,32,4160,0x0,0x7f5fc0604280,3072296,2983514,524288,38763271,242071455,392,224,0,384036,384036,39028189.0,38224703.0,6.0,4160281.0,31342600.0,30974024.0,38208507.0,37650847.0,3070585,2989919,384036,0,384036,0,12289152.0,9410055.0,0.0,0.0,0,0,616,0,4718592,4714905,112,3575,373914,0.0,0.0,0.0,524288.0,28534855.0,27802915.0,7673.0,524288.0,131072,524288,302,383331,2471,0,56.0,300.0,0.0,4194696.0,0,0,0,0,0,7340032,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,20161363.0,524288.0,0,382654,0,0,0,382654,0,0,0,382654,0,0,0,382654,0,0,0,382654,0,0,0,382654,0,0,0,382654,0,0,0,382654,0,0,0,382654,0,0,0,382654,0,0,0,382654,0,0,0,382654,0,0,0,382654,0,0,0,382654,0,0,0,382654,0,0,0,382654,0,0,0,382654,0,0,0,382654,0,0,0,382654,0,0,0,382654,0,0,0,382654,0,0,0,382654,0,0,0,382654,0,0,0,382654,0,0,0,382654,0,0,0,382654,0,0,0,382654,0,0,0,382654,0,0,0,382654,0,0,0,382654,0,0,0,382654,0,0,0,382654,0,0,0,0,0,0.0,20975495.0,32,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,144,0,0,0,57,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,34,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,524288.0,0.0,0,43944,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,329,129024,129024,0,0,129024,129024,0,0,129024,129024,0,574197,129024,129024,0,0,129024,129024,0,44686,129024,129024,0,159,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,163,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,28359,129024,129024,0,0,129024,129024,0,200,129024,129024,0,0,129024,129024,0,885,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,45964,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,1120,129024,129024,524288.0,0.0,44652,0,0,50533435,44713,0,0,50372670,44179,0,0,49945775,47189,0,0,51762509,44091,0,0,50873585,44952,0,0,51062565,45882,0,0,50817084,47545,0,0,52519398,44591,0,0,50557039,45481,0,0,50887468,44179,0,0,49929368,48571,0,0,52251921,46933,0,0,51708067,46373,0,0,51410399,45755,0,0,50975983,48698,0,0,52953947,43688,0,0,50448485,45099,0,0,50369012,44393,0,0,50142085,45639,0,0,51561445,44309,0,0,50832625,46960,0,0,51408008,43563,0,0,50261125,47494,0,0,52568113,45686,0,0,50886618,46373,0,0,50843980,46005,0,0,50375162,49061,0,0,52533429,45869,0,0,51480687,47073,0,0,51430305,45738,0,0,50810595,48697,0,0,52801607,0.0,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65568,32,131104,65646,65594,168,131240,65536,65538,2,131074,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65537,1,131073,65536,65568,32,131104,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65648,112,131184,65536,65536,0,131072,65536,65537,1,131073,65536,65569,33,131105,65813,65539,280,131352,65536,65536,0,131072,65536,65536,0,131072,65536,65538,2,131074,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65568,32,131104,65591,65537,56,131128,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131184,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131296,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131128,0,131072,930567,0,524288,3670016,3663246,224,6546,1048576,33554432.0,33554432.0,0.0,33554432.0,30046301.0,28403480.0,0.0,524288.0,213312,535903,8814,924,0,380489,4195054.0,0.0,2097594.0,2097460.0,1048576,1048576,0,524288,0,524288,7340032,0,0.0,0.0,104.0,8388608.0,29852416.0,2097152.0,0.0,207761,0,1212,383961,0,749.0,4194304.0,0.0,2064387.0,25690112,9437184,0,0,0,0,0,0,13312.0,8242176.0,0.0,8388608.0,2097152.0,4194304.0,9599376,0,0,8848,4128768.0,4128768.0,0.0,1474808.0,0,0,0,0,0,0,5767168,1048576,316132121.0,0.0,1474353861.0,0.0,34.0,0.0,0,0,371091,0.0,0.0,1471133.0,0.0,3670016,524288,0,0,0,2621440,524288,175498226,4194304.0,0.0,0.0,0.0,0.0,1221550.0,0,0,0.0,313.0,0.0,610.0,41657648,24117248,0,0,9437184,11010048,0,3145728,0.0,0.0,0.0,0.0,0.0,0.0,0,1572864,0.0,0.0,0.0,188152.0,524288,524288,0,3670016,7340032,603979776,4718592,0,0.0,0.0,0.0,0.0,0.0,0.0,524288,0,2064384.0,0.0,2031623.0,0.0,0,0,524288,0,0,0,0,33554432,0.0,4194304.0,0.0,18921176.0,0.0,0.0,141.0,4128768.0,532478.0,1690203451.0,17465618824646,17483220271567,17483220509487,17465766547823
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,215385,215385,32768,256,0,0,12,24,13888,0x0,0x7f5fc0623f80,199408,101502,512,1056268,1298668,504,56,0,24925,24925,1550887.0,279264.0,186.0,0.0,51394.0,48457.0,272960.0,254136.0,199400,108474,24925,0,24925,0,797600.0,243544.0,0.0,0.0,0,0,560,0,8192,6186,56,1950,15053,0.0,0.0,0.0,4096.0,32134.0,30599.0,0.0,4096.0,128,512,301,24322,2435,0,0.0,60.0,0.0,4600.0,0,0,0,0,0,1024,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,29310.0,4096.0,0,25130,0,0,0,25130,0,0,0,25130,0,0,0,25130,0,0,0,25130,0,0,0,25130,0,0,0,25130,0,0,0,25130,0,0,0,25130,0,0,0,25130,0,0,0,25130,0,0,0,25130,0,0,0,25130,0,0,0,25130,0,0,0,25130,0,0,0,25130,0,0,0,25130,0,0,0,25130,0,0,0,25130,0,0,0,25130,0,0,0,25130,0,0,0,25130,0,0,0,25130,0,0,0,25130,0,0,0,25130,0,0,0,25130,0,0,0,25130,0,0,0,25130,0,0,0,25130,0,0,0,25130,0,0,0,25130,0,0,0,25130,0,0,0,0,0,0.0,0.0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,312,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,258,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,258,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,4096.0,4096.0,0,87709,0,0,0,117147,0,0,0,129799,0,0,0,97502,0,0,0,81587,0,0,0,81942,0,0,0,101026,0,0,0,447950,0,0,0,80138,0,0,0,87180,0,0,0,96651,0,0,0,122363,0,0,0,82410,0,0,0,89557,0,0,0,82581,0,0,0,87128,0,0,0,83140,0,0,0,84824,0,0,0,81449,0,0,0,93614,0,0,0,83749,0,0,0,87473,0,0,0,84377,0,0,0,89804,0,0,0,80364,0,0,0,86987,0,0,0,78271,0,0,0,91667,0,0,0,102964,0,0,0,147593,0,0,0,83631,0,0,0,88062,0,0,0.0,0.0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4096.0,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,222,131,353,353,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,222,130,352,352,0,128,128,128,0,128,128,128,0,128,128,128,0,184,184,184,0,128,128,128,0,129,129,129,0,129,129,129,0,128,128,128,55,129,184,184,0,128,128,128,0,129,129,129,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,352,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,352,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,184,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,652,0,0,512,0,56,456,0,65536.0,65536.0,65536.0,0.0,0.0,0.0,0.0,0.0,6,518,10403,992,0,21836,4660.0,0.0,499.0,4161.0,512,0,0,0,4096,4096,512,0,0.0,0.0,104.0,16384.0,0.0,16384.0,4096.0,0,0,2121,23923,0,4659.0,0.0,0.0,31.0,35328,26112,0,0,0,0,0,0,104.0,15240.0,0.0,16384.0,16384.0,0.0,0,0,0,22861,0.0,0.0,0.0,0.0,0,0,0,0,0,0,10752,3584,5939674.0,7576905.0,0.0,8192.0,2.0,0.0,0,0,497,0.0,0.0,0.0,0.0,512,4096,0,0,0,512,512,1188879,0.0,0.0,0.0,0.0,0.0,1669.0,0,0,0.0,8260.0,0.0,118.0,13637,32256,0,0,26112,1024,0,1024,0.0,0.0,0.0,0.0,0.0,0.0,0,1024,0.0,0.0,0.0,52952.0,4096,0,4096,512,512,1671168,8192,0,0.0,0.0,0.0,0.0,0.0,0.0,512,0,0.0,0.0,0.0,0.0,0,0,512,0,0,0,0,32768,8192.0,0.0,0.0,189288.0,0.0,4096.0,8205.0,0.0,3326246.0,0.0,17465772950518,17483225344691,17483225353491,17465773455455
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,215385,215385,4194304,256,0,0,12,24,14336,0x7f5fdf0ef380,0x7f5fc0623fc0,1308096,1197171,65536,15485650,74890602,392,56,0,163511,163511,15798712.0,14774057.0,25621.0,538191.0,13758048.0,13470598.0,14767796.0,12630755.0,1308088,1204618,163511,0,163511,0,5232352.0,4693600.0,0.0,0.0,0,0,448,0,917504,913495,0,4009,152037,0.0,0.0,0.0,524288.0,14517965.0,14510795.0,2053.0,524288.0,16384,65536,302,163063,2483,0,0.0,186.0,0.0,1048968.0,0,0,0,0,0,131072,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,12514599.0,524288.0,0,168466,0,0,0,168466,0,0,0,168466,0,0,0,168466,0,0,0,168466,0,0,0,168466,0,0,0,168466,0,0,0,168466,0,0,0,168466,0,0,0,168466,0,0,0,168466,0,0,0,168466,0,0,0,168466,0,0,0,168466,0,0,0,168466,0,0,0,168466,0,0,0,168466,0,0,0,168466,0,0,0,168466,0,0,0,168466,0,0,0,168466,0,0,0,168466,0,0,0,168466,0,0,0,168466,0,0,0,168466,0,0,0,168466,0,0,0,168466,0,0,0,168466,0,0,0,168466,0,0,0,168466,0,0,0,168466,0,0,0,168466,0,0,0,0,0,0.0,0.0,65536,0,36772,0,65537,0,14109,0,65536,0,39246,0,65537,0,29597,0,65538,0,15516,0,65536,0,13368,0,65536,0,27505,0,65536,0,16553,0,65536,0,17718,0,65648,0,17497,0,65539,0,17922,0,65536,0,27915,0,65536,0,11556,0,65537,0,27250,0,65536,0,28647,0,65536,0,21210,0,65537,0,7067,0,65536,0,10107,0,65601,0,19589,0,65536,0,6210,0,65536,0,20627,0,65536,0,35126,0,65536,0,15074,0,65543,0,9603,0,65540,0,12085,0,65536,0,21249,0,65536,0,36788,0,65593,0,9833,0,65536,0,22633,0,65536,0,16415,0,65536,0,26810,0,65536,0,18765,0,524288.0,524288.0,0,40884786,0,0,0,41284780,0,0,0,38236938,0,0,0,43376295,0,0,0,40687778,0,0,0,42791550,0,0,0,44705858,0,0,0,54155758,0,0,0,42458597,0,0,0,40259724,0,0,0,39913374,0,0,0,39846917,0,0,0,40478908,0,0,0,37364812,0,0,0,36688426,0,0,0,54432524,0,0,0,52282291,0,0,0,41380726,0,0,0,40041901,0,0,0,37860700,0,0,0,45968131,0,0,0,40083911,0,0,0,41923998,0,0,0,38447876,0,0,0,44438511,0,0,0,43414439,0,0,0,38589112,0,0,0,43668562,0,0,0,39496327,0,0,0,41009899,0,0,0,39496488,0,0,0,53770880,0,0,0.0,0.0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,524288.0,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32769,32769,32769,0,32768,32768,32768,0,32769,32769,32769,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32770,32770,32770,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32824,32824,32824,0,32768,32768,32768,0,32769,32769,32769,0,32825,32825,32825,0,32768,32768,32768,166,32770,32936,32936,222,32770,32992,32992,0,32769,32769,32769,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32831,32831,32831,0,32768,32768,32768,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32936,0,0,32992,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,457276,0,0,65536,63800,56,1680,0,8388608.0,8388608.0,8388608.0,0.0,0.0,0.0,0.0,0.0,212432,206221,9982,2091,0,162001,1049147.0,0.0,388.0,1048759.0,65536,0,0,0,524288,524288,131072,0,0.0,0.0,104.0,2097152.0,0.0,2097152.0,524288.0,65453,0,2455,161416,0,1049148.0,0.0,0.0,31.0,4063232,2883584,0,0,0,0,0,0,6655.0,2027153.0,0.0,2097152.0,2097152.0,0.0,1864382,0,0,14970,0.0,0.0,0.0,0.0,262144,0,0,0,0,0,1507328,458752,1049804772.0,2181005191.0,0.0,2097152.0,4.0,0.0,0,0,147788,0.0,0.0,0.0,0.0,65536,524288,0,0,0,65536,65536,47086562,0.0,0.0,0.0,0.0,0.0,5445.0,0,0,0.0,2097339.0,0.0,360.0,43183485,3735552,0,0,2883584,196608,0,131072,0.0,0.0,0.0,0.0,0.0,0.0,0,131072,0.0,0.0,442748.0,1401447.0,524288,0,524288,65536,131072,184549376,917504,0,0.0,0.0,0.0,0.0,0.0,0.0,65536,0,0.0,0.0,983047.0,0.0,0,0,65536,0,0,0,0,4194304,2097152.0,0.0,0.0,12603512.0,0.0,524288.0,2097288.0,0.0,1411626085.0,0.0,17465774555386,17483225425972,17483225517812,17465775372235
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/prev_analysis/1.csv
index e47bcc6dc3..950b287c20 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,3354883.0,3354883.0,3354883.0,7.874978721558364
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,1722402.0,1722402.0,1722402.0,4.043025971388442
 "void benchmark_func<double, 256, 8u, 512u>(double, double*) [clone .kd]",1,1712642.0,1712642.0,1712642.0,4.0201161434384325
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/prev_analysis/1001.csv
index f475f954a6..fb5988001a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,494.8622754491018,Instr per wave
 VMEM,7.958083832335329,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,0.0,Instr per wave
 SALU,24.520958083832337,Instr per wave
 SMEM,1.8023952095808384,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/prev_analysis/101.csv
index f5d967f91f..6fd6611821 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx90a
 mi200
 56
 1638.4
-SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/prev_analysis/1202.csv
index 8d0185db12..72ef09bf78 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,18743.836616150635,1846.8586349487305,258307.513671875,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/prev_analysis/1901.csv
index 863f5f57b4..7392c9a064 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,2.0,smem_
 VALU,495.0,valu_
 MFMA,0.0,mfma_
 VMEM,8.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,10.0,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,67894.0,wavefronts_
 Workgroups,16973.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,128.0,il1_fetch_
 IL1 Hit,99.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,0.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,44.0,hbm_rd_
 HBM Wr,0.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,70.0,vl1_coales_
 VL1 Stall,3.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,27.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/prev_analysis/201.csv
index eb35f541a4..37c19e25a1 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,58.59574601561671,Pct,100,58.59574601561671
 MFMA Util,0.0,Pct,100,0.0
 VALU Active Threads/Wave,64.0,Threads,64,100.0
 IPC - Issue,1.0,Instr/cycle,5,20.0
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.9924986039522,Pct,100,99.9924986039522
 Instr Cache BW,1688.5833758537349,Gb/s,6092.8,27.71440677280946
 Scalar L1D Cache Hit Rate,99.34855885996417,Pct,100,99.34855885996417
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/prev_analysis/602.csv
index ccb14f4da8..9ed5c7fc37 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,16398005.988023952,0,417419910,Simd
 Insufficient SIMD VGPRs,0.0,0,0,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/prev_analysis/701.csv
index 12250d77c0..db0925a109 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/sysinfo.csv
index fb4733db8f..ecf24646c9 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-no_roof_Axes3,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:44:22 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+no_roof_Axes3,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:44:22 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/timestamps.csv
index 660ebf6acf..9ff5b16272 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes3/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,216328,216328,33554432,256,0,0,4,32,4160,0x0,0x7f1872e04280,17483220242836,17483220271567,17483220509487,17483220597517
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,216328,216328,32768,256,0,0,12,24,13888,0x0,0x7f1872e23f80,17483225329135,17483225344691,17483225353491,17483225376724
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,216328,216328,4194304,256,0,0,12,24,14336,0x7f1875b62380,0x7f1872e23fc0,17483225377814,17483225425972,17483225517812,17483225520420
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/SQ_IFETCH_LEVEL.csv
index e34efbfc4a..06fa359a75 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/SQ_IFETCH_LEVEL.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,916966,916971,33554432,256,0,0,8,32,6464,0x0,0x7fcfed204180,499889,499889,524288,6291456,791115,101359524,12076249698094358,12076249940354231,12076249940675349,12076249940786912
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,916966,916971,32768,256,0,0,24,24,12480,0x0,0x7fcfed235100,27745,27745,512,8192,9149,1178424,12076249955161617,12076249955468031,12076249955474111,12076249955482493
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,916966,916971,4194304,256,0,0,24,24,12928,0x7fd0f8d84900,0x7fcfed235140,228835,228835,65536,917504,145911,18662536,12076249955547093,12076249955770429,12076249955910268,12076249955913945
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/SQ_INST_LEVEL_LDS.csv
index bb6ac41857..f0caa07a4c 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/SQ_INST_LEVEL_LDS.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,918775,918780,33554432,256,0,0,8,32,6464,0x0,0x7f61ea604180,0,0,0,12076276081291842,12076276325959331,12076276326282529,12076276326392531
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,918775,918780,32768,256,0,0,24,24,12480,0x0,0x7f61ea635100,0,0,0,12076276340662571,12076276340968258,12076276340974338,12076276340979711
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,918775,918780,4194304,256,0,0,24,24,12928,0x7f62f61df900,0x7f61ea635140,0,0,0,12076276341051234,12076276341276897,12076276341417536,12076276341421822
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/SQ_INST_LEVEL_SMEM.csv
index 375f0b1c89..61f5c175e2 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/SQ_INST_LEVEL_SMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,918397,918402,33554432,256,0,0,8,32,6464,0x0,0x7f4f0ba04180,4194304,3137306,401609096,12076273566191420,12076273812354944,12076273812679102,12076273812785844
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,918397,918402,32768,256,0,0,24,24,12480,0x0,0x7f4f0ba35100,512,25334,3243720,12076273827074399,12076273827374232,12076273827380632,12076273827385768
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,918397,918402,4194304,256,0,0,24,24,12928,0x7f503baa0900,0x7f4f0ba35140,65536,178656,22860416,12076273827446871,12076273827660470,12076273827799510,12076273827803244
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/SQ_INST_LEVEL_VMEM.csv
index 410582b4f7..dd94bb93fe 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/SQ_INST_LEVEL_VMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,918587,918592,33554432,256,0,0,8,32,6464,0x0,0x7f770da04180,1048576,11249780,1440135096,12076274826600845,12076275070934392,12076275071259831,12076275071378924
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,918587,918592,32768,256,0,0,24,24,12480,0x0,0x7f770da35100,4096,108920,13949244,12076275085916642,12076275086225284,12076275086231684,12076275086244130
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,918587,918592,4194304,256,0,0,24,24,12928,0x7f78195ef900,0x7f770da35140,524288,11784859,1508390456,12076275086297229,12076275086517123,12076275086651362,12076275086655284
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/SQ_LEVEL_WAVES.csv
index 8a632cb4c9..560ea2f2ae 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/SQ_LEVEL_WAVES.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,918964,918971,33554432,256,0,0,8,32,6464,0x0,0x7f489b804180,505098,505098,17164,4040792,524288,370696609,3840639,0,1497567228,12076277331535465,12076277579431443,12076277579756081,12076277579865204
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,918964,918971,32768,256,0,0,24,24,12480,0x0,0x7f489b835100,26939,26939,19565,215520,512,1152010,76288,0,4622216,12076277594196869,12076277594515288,12076277594521368,12076277594530579
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,918964,918971,4194304,256,0,0,24,24,12928,0x7f49cb902900,0x7f489b835140,219364,219364,22210,1754920,65536,145565664,1586943,0,584074712,12076277594594809,12076277594833366,12076277594966806,12076277594970737
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/pmc_dispatch_info.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/pmc_perf.csv
index 297e247f7d..d44bb47485 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBuffer.kd,0,0,0,917700,917705,33554432,256,0,0,8,32,6464,0x0,0x7f88dda04180,1048576,0,1048576,9437184,0,4194304,1048576,0,500996,500996,57476361,55177851,175,12573592,54442261,54350678,55140018,53961025,4007968,3816216,500996,0,500996,0,16031872,15204610,0,0,0,0,0,17446168,1048576,0,502866,0,0,0,502866,0,0,0,502866,0,0,0,502866,0,0,0,502866,0,0,0,502866,0,0,0,502866,0,0,0,502866,0,0,0,502866,0,0,0,502866,0,0,0,502866,0,0,0,502866,0,0,0,502866,0,0,0,502866,0,0,0,502866,0,0,0,502866,0,0,0,502866,0,0,0,502866,0,0,0,502866,0,0,0,502866,0,0,0,502866,0,0,0,502866,0,0,0,502866,0,0,0,502866,0,0,0,502866,0,0,0,502866,0,0,0,502866,0,0,0,502866,0,0,0,502866,0,0,0,502866,0,0,0,502866,0,0,0,502866,0,0,0,37794043,48,0,0,0,52,0,0,0,1,0,0,0,0,0,0,0,48,0,0,0,0,0,0,0,2840,0,0,0,0,0,0,0,1,0,0,0,1,0,0,0,2824,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,3,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2312,0,0,0,0,0,0,0,0,0,0,0,4,0,0,0,2531,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,68,0,0,0,0,0,0,0,1048576,0,0,3027581,131080,131080,0,1400,131072,131072,0,809,131072,131072,0,25527,131076,131076,0,0,131072,131072,0,0,131072,131072,0,1719,131072,131072,0,0,131072,131072,0,0,131072,131072,0,0,131072,131072,0,258,131080,131080,0,0,131072,131072,0,2982789,131072,131072,0,0,131072,131072,0,0,131072,131072,0,0,131080,131080,0,8435,131072,131072,0,877,131072,131072,0,0,131072,131072,0,0,131076,131076,0,0,131076,131076,0,0,131072,131072,0,562020,131076,131076,0,0,131072,131072,0,2991537,131072,131072,0,0,131072,131072,0,0,131072,131072,0,0,131076,131076,0,3257453,131072,131072,0,1696,131072,131072,0,0,131076,131076,0,0,131076,131076,1048576,0,47698,0,0,29773854,1643,0,0,17304727,853,0,0,17015562,773,0,0,16993275,850,0,0,17101999,726,0,0,17460965,704,0,0,18096626,1031,0,0,18492486,788,0,0,16894177,1924,0,0,17390574,764,0,0,16778182,1649,0,0,16846627,42373,0,0,29226222,901,0,0,17363287,1540,0,0,17813133,929,0,0,18551528,2155,0,0,16697842,986,0,0,16770121,858,0,0,16713568,1611,0,0,16792912,1660,0,0,17140408,689,0,0,17196421,1644,0,0,17925046,1596,0,0,18505625,48786,0,0,29566532,1614,0,0,16953629,1694,0,0,16990703,879,0,0,16837219,46613,0,0,30093998,2099,0,0,17575603,792,0,0,17903125,909,0,0,18554664,1048576,131072,131120,48,262192,131260,131124,240,262384,131072,131075,3,262147,131072,133806,2734,264878,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,133726,2654,264798,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131119,131073,48,262192,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131213,131075,144,262288,131072,131072,0,262144,131072,131137,65,262209,131072,131073,1,262145,131072,131072,0,262144,131072,131073,1,262145,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131121,49,262193,131072,133551,2479,264623,131072,131072,0,262144,131119,131073,48,262192,131072,131072,0,262144,131072,133714,2642,264786,262144,0,262144,262336,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262288,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,0,0,3145728,524288,32505856,370812825,217785540,120521429,479922,0,0,0,1048576,52556757,52325211,1048576,1048576,131072,524288,685,501398,4005,0,96,10599,0,8388944,32505856,4006344,3810767,57038979,11534336,0,0,14155776,67108864,67108864,0,67108864,54292842,53971223,0,1048576,237534,761822,11008,2290,0,496677,8399573,0,4194727,4204846,13631488,0,3670016,1048576,1048576,0,4194304,9437184,0,0,360,33554432,53954143,4194304,0,0,2815,497386,0,10963,8388608,0,4194398,905969664,6291456,0,0,0,524288,524288,0,15317,16608911,0,16777216,4194304,4194304,0,0,0,16621,4194374,4194374,0,226209,0,0,0,33554432,0,0,0,0,634117264,0,2777978617,0,0,0,0,0,475561,0,0,216351,0,0,8388608,336,144,0,0,0,480,8388608,0,0,0,0,348683,0,0,0,10695,0,21372,0,6291456,6289477,96,2157,2033065,0,0,0,0,0,0,0,0,0,3145728,0,0,0,147383,4194304,4189866,144,4294,2097152,524288,1572864,0,0,0,0,0,0,524288,0,4128857,65535,4063244,0,0,8388608,0,42253921,0,1048576,10520,4194372,12989380,613100426,12076251830861682,12076278471768969,12076278472093126,12076252078625340
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,917700,917705,32768,256,0,0,24,24,12480,0x0,0x7f88dda35100,0,4096,4096,512,0,512,4096,0,28233,28233,1496987,585323,238,120350,84927,65275,577212,556660,225864,85621,28233,0,28233,0,903456,205681,0,0,0,0,0,51593,4096,0,28283,0,0,0,28283,0,0,0,28283,0,0,0,28283,0,0,0,28283,0,0,0,28283,0,0,0,28283,0,0,0,28283,0,0,0,28283,0,0,0,28283,0,0,0,28283,0,0,0,28283,0,0,0,28283,0,0,0,28283,0,0,0,28283,0,0,0,28283,0,0,0,28283,0,0,0,28283,0,0,0,28283,0,0,0,28283,0,0,0,28283,0,0,0,28283,0,0,0,28283,0,0,0,28283,0,0,0,28283,0,0,0,28283,0,0,0,28283,0,0,0,28283,0,0,0,28283,0,0,0,28283,0,0,0,28283,0,0,0,28283,0,0,0,0,304,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,304,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,261,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,378,0,0,0,256,0,0,0,4096,4096,0,151884,0,0,0,85397,0,0,0,95266,0,0,0,114436,0,0,0,100363,0,0,0,126364,0,0,0,105424,0,0,0,139182,0,0,0,87539,0,0,0,133028,0,0,0,98269,0,0,0,78618,0,0,0,122637,0,0,0,104094,0,0,0,69644,0,0,0,94209,0,0,0,173716,0,0,0,110925,0,0,0,69907,0,0,0,136945,0,0,0,133999,0,0,0,78755,0,0,0,77799,0,0,0,82136,0,0,0,93838,0,0,0,80802,0,0,0,83623,0,0,0,85507,0,0,0,83044,0,0,0,80827,0,0,0,91200,0,0,0,88971,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4096,0,304,304,304,0,304,304,304,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,47,257,304,304,0,256,256,256,188,260,448,448,0,256,256,256,0,256,256,256,0,256,256,256,188,260,448,448,0,377,377,377,0,257,257,257,0,256,256,256,0,257,257,257,0,256,256,256,0,256,256,256,0,256,256,256,0,257,257,257,0,256,256,256,0,256,256,256,0,256,256,256,47,257,304,304,0,256,256,256,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,304,0,0,256,0,0,0,0,512,512,35328,1107070,1054356,16362,11948,0,0,0,4096,70881,67855,4096,4096,128,512,611,27237,4151,0,48,172,0,8624,36352,215360,72182,1011630,26624,0,0,30208,65536,65536,65536,0,0,0,0,0,116,628,11139,2094,0,22894,8891,0,470,8421,1024,0,1024,4096,0,4096,512,512,0,0,360,16384,0,16384,0,0,2803,25879,0,8892,0,0,31,1933312,8192,0,0,0,512,512,0,120,15064,0,16384,16384,0,0,0,0,21328,0,0,0,0,0,0,0,32768,0,0,0,0,12838688,17320759,0,8192,0,0,0,0,695,0,0,0,0,0,1024,432,48,0,0,0,480,0,0,0,0,0,2596,0,0,0,8541,0,678,0,8192,6568,48,1576,1108,0,0,0,0,0,0,0,0,0,2560,0,0,0,48497,512,0,48,464,0,512,0,0,0,0,0,0,0,512,0,0,0,0,0,8192,0,0,447005,0,4096,8420,0,3223642,0,12076252093450111,12076278486804817,12076278486811377,12076252094462532
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,917700,917705,4194304,256,0,0,24,24,12928,0x7f89e95e6900,0x7f88dda35140,0,524288,524288,65536,0,65536,524288,0,222386,222386,24734327,23534631,29856,8033140,22787079,22678033,23521268,21362100,1779088,1632969,222386,0,222386,0,7116352,6403046,0,0,0,0,0,21265839,524288,0,224220,0,0,0,224220,0,0,0,224220,0,0,0,224220,0,0,0,224220,0,0,0,224220,0,0,0,224220,0,0,0,224220,0,0,0,224220,0,0,0,224220,0,0,0,224220,0,0,0,224220,0,0,0,224220,0,0,0,224220,0,0,0,224220,0,0,0,224220,0,0,0,224220,0,0,0,224220,0,0,0,224220,0,0,0,224220,0,0,0,224220,0,0,0,224220,0,0,0,224220,0,0,0,224220,0,0,0,224220,0,0,0,224220,0,0,0,224220,0,0,0,224220,0,0,0,224220,0,0,0,224220,0,0,0,224220,0,0,0,224220,0,0,0,0,65584,0,4185,0,65536,0,20177,0,65541,0,28333,0,65536,0,8040,0,65584,0,9652,0,65536,0,3149,0,66072,0,54889,0,65536,0,15894,0,65537,0,8822,0,65537,0,18465,0,65536,0,18227,0,65536,0,6426,0,65536,0,10086,0,65536,0,15229,0,65536,0,0,0,65536,0,16768,0,65536,0,19520,0,65536,0,1192,0,65537,0,8765,0,65536,0,35635,0,65536,0,3275,0,65536,0,49546,0,65536,0,4221,0,65536,0,9532,0,65536,0,3825,0,65536,0,15816,0,67231,0,53507,0,65536,0,40343,0,65536,0,5019,0,65536,0,3229,0,65784,0,27183,0,65536,0,23201,0,524288,524288,0,33383320,0,0,0,34930443,0,0,0,34249558,0,0,0,33767590,0,0,0,32618309,0,0,0,33199404,0,0,0,32425941,0,0,0,41047054,0,0,0,32720583,0,0,0,37611782,0,0,0,30454182,0,0,0,32618180,0,0,0,41880829,0,0,0,34302670,0,0,0,37821966,0,0,0,33383500,0,0,0,38181011,0,0,0,32277190,0,0,0,30126730,0,0,0,38760467,0,0,0,33002285,0,0,0,35408942,0,0,0,31767209,0,0,0,32784541,0,0,0,33220011,0,0,0,42493966,0,0,0,34063728,0,0,0,35129358,0,0,0,48788581,0,0,0,35692029,0,0,0,32921759,0,0,0,43536929,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,524288,0,65584,65584,65584,0,65584,65584,65584,188,65540,65728,65728,0,66461,66461,66461,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,47,65537,65584,65584,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65834,65834,65834,0,65537,65537,65537,0,65536,65536,65536,0,65537,65537,65537,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65537,65537,65537,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,188,65540,65728,65728,0,67691,67691,67691,65536,0,0,65536,0,0,65728,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65728,0,0,65536,0,0,0,0,65536,65536,4128768,146948941,55276304,87412797,196670,0,0,0,524288,21757822,21751805,524288,524288,16384,65536,734,213611,3975,0,48,1837,0,2097536,4259840,1734584,1575147,23335641,3014656,0,0,3473408,8388608,8388608,8388608,0,0,0,0,0,187577,212619,11015,2038,0,212885,2100417,0,423,2099994,131072,0,131072,524288,0,524288,65536,65536,0,0,360,2097152,0,2097152,56429,0,2804,213164,0,2099854,0,0,31,222298112,917504,0,0,0,65536,65536,0,7557,2018324,0,2097152,2097152,0,737696,740129,0,23067,0,0,0,0,0,0,0,4194304,0,0,0,0,1236304642,2246843919,0,2097152,0,0,0,0,186211,0,0,0,0,0,131072,384,48,0,0,0,432,0,0,0,0,0,9318,0,0,0,2098560,0,2798,0,917504,914819,63,5120,236106,0,0,0,0,0,0,0,0,0,327680,0,0,219914,273466,65536,64048,48,1440,0,65536,0,0,0,0,0,0,0,65536,0,0,0,1966096,0,2097152,0,0,15985750,0,524288,2100645,0,1087531293,0,12076252095093966,12076278486872656,12076278487011215,12076252096319233
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/prev_analysis/1.csv
index 00f247ff96..bac1bb96cd 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,6052750.0,6052750.0,6052750.0,9.184366079279966
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4525082.0,4525082.0,4525082.0,6.866302032424988
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 256u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,3050855.0,3050855.0,3050855.0,4.629328681145212
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/prev_analysis/1001.csv
index ca08330db0..0e3bf5267e 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,46.862275449101794,Instr per wave
 SMEM,1.8083832335329342,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/prev_analysis/101.csv
index 71ad5b35c0..0d6d1d5853 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx908
 mi100
 48
 1228.8
-SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/prev_analysis/1202.csv
index 2318ae0298..8543be5e0e 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,33664.65327686607,2829.0773391723633,547933.4265136719,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/prev_analysis/1901.csv
index 75d6585672..56fa78281f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,2.0,smem_
 VALU,735.0,valu_
 MFMA,,mfma_
 VMEM,8.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,22.0,br_
 VGPR,24.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,67894.0,wavefronts_
 Workgroups,16973.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,163.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,0.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,44.0,hbm_rd_
 HBM Wr,0.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,70.0,vl1_coales_
 VL1 Stall,31.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,34.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/prev_analysis/2001.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/prev_analysis/201.csv
index 29ef4dea1b..6f9207a0cd 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,59.748748256149796,Pct,100,59.748748256149796
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,63.96810207317344,Threads,64,99.9501594893335
 IPC - Issue,0.8437292413357499,Instr/cycle,5,16.874584826714997
-LDS BW,0.0,Gb/sec,23070.72,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,23070.72,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99343549731832,Pct,100,99.99343549731832
 Instr Cache BW,1411.6772152680899,Gb/s,4614.144,30.594563482806123
 Scalar L1D Cache Hit Rate,99.35620448528866,Pct,100,99.35620448528866
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/prev_analysis/602.csv
index 89a0a7c719..223ef5460b 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,63114.67664670659,0,782608,Simd
 Insufficient SIMD VGPRs,625985.9760479042,0,46596962,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/prev_analysis/701.csv
index d3f1bff5a3..1071413faa 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,23.976047904191617,8,36,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/sysinfo.csv
index d75f0946fd..66b62a708e 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-no_roof_Axes4,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 11:30:24 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+no_roof_Axes4,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 11:30:24 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/timestamps.csv
index 6fc5d78c70..d2a2a6da1d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,919015,919020,33554432,256,0,0,8,32,6464,0x0,0x7fc439e04180,12076278471723574,12076278471768969,12076278472093126,12076278472199017
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,919015,919020,32768,256,0,0,24,24,12480,0x0,0x7fc439e35100,12076278486700448,12076278486804817,12076278486811377,12076278486817205
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,919015,919020,4194304,256,0,0,24,24,12928,0x7fc5459af900,0x7fc439e35140,12076278486860124,12076278486872656,12076278487011215,12076278487014772
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/SQ_IFETCH_LEVEL.csv
index cbfd480dea..30aecc59cc 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/SQ_IFETCH_LEVEL.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,220487,220487,33554432,256,0,0,4,32,4160,0x0,0x7f4da8e04280,385209,385209,524288,4718592,680852,76304292,17569133128943,17568417874333,17569276230400,17569276344470
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,220487,220487,32768,256,0,0,12,24,13888,0x0,0x7f4da8e23f80,33204,33204,512,8192,6039,679268,17569281500468,17569276230400,17569281630572,17569281635005
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,220487,220487,4194304,256,0,0,12,24,14336,0x7f4dabe7e380,0x7f4da8e23fc0,164280,164280,65536,917504,141975,15913340,17569281672504,17569281630572,17569282005613,17569282008345
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/SQ_INST_LEVEL_LDS.csv
index 6ca65ff3da..953d201cec 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/SQ_INST_LEVEL_LDS.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,222335,222335,33554432,256,0,0,4,32,4160,0x0,0x7f0e01c04280,0,0,0,17588485752362,17587770621483,17588638424785,17588638538235
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,222335,222335,32768,256,0,0,12,24,13888,0x0,0x7f0e01c23f80,0,0,0,17588643766532,17588638424785,17588643898389,17588643903018
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,222335,222335,4194304,256,0,0,12,24,14336,0x7f0e04b9b380,0x7f0e01c23fc0,0,0,0,17588643938737,17588643898389,17588644273269,17588644275869
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/SQ_INST_LEVEL_SMEM.csv
index 94806478c5..67a050f9b1 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/SQ_INST_LEVEL_SMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,220265,220265,33554432,256,0,0,4,32,4160,0x0,0x7fbbe6404280,3670016,3111402,348523136,17568192656973,17539868996228,17568336933259,17568337047099
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,220265,220265,32768,256,0,0,12,24,13888,0x0,0x7fbbe6423f80,512,97428,10934832,17568342229867,17568336933259,17568342370712,17568342375203
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,220265,220265,4194304,256,0,0,12,24,14336,0x7fbbe938e380,0x7fbbe6423fc0,65536,651168,72983248,17568342409382,17568342370712,17568342743833,17568342746454
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/SQ_INST_LEVEL_VMEM.csv
index bc1c5126b4..df3004c7ef 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/SQ_INST_LEVEL_VMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,222113,222113,33554432,256,0,0,4,32,4160,0x0,0x7ff188604280,524288,5458158,611312952,17587542533964,17585268287516,17587690915765,17587691028265
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,222113,222113,32768,256,0,0,12,24,13888,0x0,0x7ff188623f80,4096,41745,4680188,17587696208333,17587690915765,17587696338655,17587696343210
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,222113,222113,4194304,256,0,0,12,24,14336,0x7ff196e7c380,0x7ff188623fc0,524288,11007151,1232726872,17587696377139,17587696338655,17587696703776,17587696706131
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/SQ_LEVEL_WAVES.csv
index fd54b71a2f..b435fabd18 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/SQ_LEVEL_WAVES.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,220709,220709,33554432,256,0,0,4,32,4160,0x0,0x7fed49604280,384963,384963,8694,3079712,524288,242654629,2993552,0,986873364,17570058961759,17569358224037,17570205681045,17570205795175
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,220709,220709,32768,256,0,0,12,24,13888,0x0,0x7fed49623f80,34766,34766,31261,278136,512,1744560,170381,0,6991616,17570210968303,17570205681045,17570211100894,17570211105849
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,220709,220709,4194304,256,0,0,12,24,14336,0x7fed4c609380,0x7fed49623fc0,164911,164911,14555,1319296,65536,83101426,1210576,0,334135836,17570211149618,17570211100894,17570211492415,17570211494899
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/pmc_perf.csv
index 353976cf73..4470905a2a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDI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],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBufferAligned.kd,0,0,0,221475,221475,33554432,256,0,0,4,32,4160,0x0,0x7f4e84e04280,3100272,3015227,524288,39140375,244883254,392,224,0,387533,387533,39439743.0,38438663.0,1.0,4155985.0,31548908.0,31183143.0,38412373.0,37850538.0,3098561,3021637,387533,0,387533,0,12401056.0,9495849.0,0.0,0.0,0,0,616,0,4718592,4714900,112,3580,375482,0.0,0.0,0.0,524288.0,28546386.0,27823532.0,7789.0,524288.0,131072,524288,302,384733,2248,0,56.0,302.0,0.0,4194696.0,0,0,0,0,0,7340032,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,19985557.0,524288.0,0,382970,0,0,0,382970,0,0,0,382970,0,0,0,382970,0,0,0,382970,0,0,0,382970,0,0,0,382970,0,0,0,382970,0,0,0,382970,0,0,0,382970,0,0,0,382970,0,0,0,382970,0,0,0,382970,0,0,0,382970,0,0,0,382970,0,0,0,382970,0,0,0,382970,0,0,0,382970,0,0,0,382970,0,0,0,382970,0,0,0,382970,0,0,0,382970,0,0,0,382970,0,0,0,382970,0,0,0,382970,0,0,0,382970,0,0,0,382970,0,0,0,382970,0,0,0,382970,0,0,0,382970,0,0,0,382970,0,0,0,382970,0,0,0,0,0,0.0,21118620.0,0,0,0,0,0,0,0,0,0,0,0,0,33,0,0,0,2,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,56,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,0,0,0,0,0,0,0,0,0,0,2,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,34,0,0,0,5,0,0,0,0,0,0,0,112,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,0,0,1,0,0,0,524288.0,0.0,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,44386,129024,129024,0,330,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,905,129024,129024,0,537610,129024,129024,0,0,129024,129024,0,0,129024,129024,0,315298,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,164,129024,129024,0,0,129024,129024,0,0,129024,129024,0,163,129024,129024,0,24153,129024,129024,0,871,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,157,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,44852,129024,129024,0,185,129024,129024,524288.0,0.0,42420,0,0,49761589,45463,0,0,50308752,43907,0,0,49411276,46279,0,0,51545949,44303,0,0,50545490,46985,0,0,51197920,44281,0,0,50005225,46211,0,0,51853497,44877,0,0,50359163,44527,0,0,50356220,44105,0,0,49819114,46105,0,0,51202293,45073,0,0,50901313,47200,0,0,51201281,45981,0,0,50614953,46655,0,0,51882525,42779,0,0,49428572,44854,0,0,49972074,41973,0,0,49274269,47014,0,0,51545785,43766,0,0,50474614,43732,0,0,50378773,43813,0,0,49846125,47843,0,0,52130355,45577,0,0,50391035,45050,0,0,50023489,44144,0,0,49729108,47779,0,0,51739499,45463,0,0,51001138,47779,0,0,51586137,45581,0,0,50638989,47839,0,0,52179703,0.0,65536,65568,32,131104,65591,65537,56,131128,65536,65536,0,131072,65536,65536,0,131072,65646,65538,112,131184,65536,65538,2,131074,65536,65536,0,131072,65536,65536,0,131072,65536,65648,112,131184,65536,65568,32,131104,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65572,36,131108,65536,65537,1,131073,65536,65537,1,131073,65536,65536,0,131072,65758,65594,280,131352,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65568,32,131104,65536,65537,1,131073,65536,65536,0,131072,65536,65536,0,131072,65591,65537,56,131128,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131184,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131296,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131128,0,131072,1074935,0,524288,3670016,3663384,224,6408,1048576,33554432.0,33554432.0,0.0,33554432.0,30442240.0,28798394.0,0.0,524288.0,222546,538459,8640,921,0,386302,4195055.0,0.0,2097594.0,2097461.0,1048576,1048576,0,524288,0,524288,7340032,0,0.0,0.0,104.0,8388608.0,29435318.0,2097152.0,0.0,201052,0,1219,382090,0,753.0,4194304.0,0.0,2064387.0,25690112,9437184,0,0,0,0,0,0,13312.0,8242176.0,0.0,8388608.0,2097152.0,4194304.0,10230695,0,0,8960,4128768.0,4128768.0,0.0,1497381.0,0,0,0,0,0,0,5767168,1048576,315031620.0,0.0,1469968589.0,0.0,40.0,0.0,0,0,372891,0.0,0.0,1483727.0,0.0,3670016,524288,0,0,0,2621440,524288,177530351,4194304.0,0.0,0.0,0.0,0.0,1208381.0,0,0,0.0,313.0,0.0,610.0,43218060,24117248,0,0,9437184,11010048,0,3145728,0.0,0.0,0.0,0.0,0.0,0.0,0,1572864,0.0,0.0,0.0,201483.0,524288,524288,0,3670016,7340032,603979776,4718592,0,0.0,0.0,0.0,0.0,0.0,0.0,524288,0,2064384.0,0.0,2031623.0,0.0,0,0,524288,0,0,0,0,33554432,0.0,4194304.0,0.0,18985928.0,0.0,0.0,144.0,4128768.0,964095.0,1655144513.0,17571492174271,17589313263708,17589313504348,17571636189029
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,221475,221475,32768,256,0,0,12,24,13888,0x0,0x7f4e84e23f80,264264,164781,512,1400548,1672124,504,56,0,33032,33032,2373176.0,161954.0,158.0,0.0,35363.0,32306.0,155688.0,136928.0,264256,171584,33032,0,33032,0,1057024.0,387103.0,0.0,0.0,0,0,560,0,8192,6222,56,1914,23572,0.0,0.0,0.0,4096.0,29503.0,27903.0,0.0,4096.0,128,512,302,32990,2278,0,0.0,59.0,0.0,4600.0,0,0,0,0,0,1024,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,11652.0,4096.0,0,32905,0,0,0,32905,0,0,0,32905,0,0,0,32905,0,0,0,32905,0,0,0,32905,0,0,0,32905,0,0,0,32905,0,0,0,32905,0,0,0,32905,0,0,0,32905,0,0,0,32905,0,0,0,32905,0,0,0,32905,0,0,0,32905,0,0,0,32905,0,0,0,32905,0,0,0,32905,0,0,0,32905,0,0,0,32905,0,0,0,32905,0,0,0,32905,0,0,0,32905,0,0,0,32905,0,0,0,32905,0,0,0,32905,0,0,0,32905,0,0,0,32905,0,0,0,32905,0,0,0,32905,0,0,0,32905,0,0,0,32905,0,0,0,0,0,0.0,0.0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,260,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,258,0,0,0,257,0,0,0,257,0,0,0,312,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,4096.0,4096.0,0,73664,0,0,0,76437,0,0,0,77908,0,0,0,79823,0,0,0,88527,0,0,0,78032,0,0,0,80177,0,0,0,83608,0,0,0,76350,0,0,0,655676,0,0,0,78893,0,0,0,110326,0,0,0,76751,0,0,0,94976,0,0,0,81096,0,0,0,87840,0,0,0,77779,0,0,0,80742,0,0,0,74805,0,0,0,79678,0,0,0,85879,0,0,0,79311,0,0,0,78193,0,0,0,85424,0,0,0,77889,0,0,0,79269,0,0,0,74409,0,0,0,85514,0,0,0,75171,0,0,0,83683,0,0,0,124787,0,0,0,82566,0,0,0.0,0.0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4096.0,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,222,131,353,353,0,128,128,128,0,128,128,128,0,184,184,184,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,222,130,352,352,0,128,128,128,0,128,128,128,0,128,128,128,0,129,129,129,0,128,128,128,0,129,129,129,0,128,128,128,0,128,128,128,55,129,184,184,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,129,129,129,0,128,128,128,0,128,128,128,0,128,128,128,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,352,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,352,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,184,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,672,0,0,512,0,56,456,0,65536.0,65536.0,65536.0,0.0,0.0,0.0,0.0,0.0,6,518,11692,1047,0,31195,4662.0,0.0,499.0,4163.0,512,0,0,0,4096,4096,512,0,0.0,0.0,104.0,16384.0,0.0,16384.0,4096.0,0,0,1618,31367,0,4660.0,0.0,0.0,31.0,35328,26112,0,0,0,0,0,0,104.0,15240.0,0.0,16384.0,16384.0,0.0,0,0,0,29815,0.0,0.0,0.0,0.0,0,0,0,0,0,0,10752,3584,3825469.0,5485111.0,0.0,8192.0,2.0,0.0,0,0,497,0.0,0.0,0.0,0.0,512,4096,0,0,0,512,512,1618263,0.0,0.0,0.0,0.0,0.0,1314.0,0,0,0.0,8262.0,0.0,122.0,18872,32256,0,0,26112,1024,0,1024,0.0,0.0,0.0,0.0,0.0,0.0,0,1024,0.0,0.0,0.0,52794.0,4096,0,4096,512,512,1671168,8192,0,0.0,0.0,0.0,0.0,0.0,0.0,512,0,0.0,0.0,0.0,0.0,0,0,512,0,0,0,0,32768,8192.0,0.0,0.0,106848.0,0.0,4096.0,8206.0,0.0,3275698.0,0.0,17571642401690,17589318300033,17589318313633,17571642884768
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,221475,221475,4194304,256,0,0,12,24,14336,0x7f4e87d62380,0x7f4e84e23fc0,1311536,1207302,65536,15623836,77694881,392,56,0,163941,163941,15926352.0,14470259.0,24121.0,550603.0,13077667.0,12701896.0,14463964.0,12327412.0,1311528,1214284,163941,0,163941,0,5246112.0,4730006.0,0.0,0.0,0,0,448,0,917504,913646,0,3858,153459,0.0,0.0,0.0,524288.0,13757328.0,13742687.0,2233.0,524288.0,16384,65536,302,165109,2270,0,0.0,181.0,0.0,1048968.0,0,0,0,0,0,131072,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,11642256.0,524288.0,0,164446,0,0,0,164446,0,0,0,164446,0,0,0,164446,0,0,0,164446,0,0,0,164446,0,0,0,164446,0,0,0,164446,0,0,0,164446,0,0,0,164446,0,0,0,164446,0,0,0,164446,0,0,0,164446,0,0,0,164446,0,0,0,164446,0,0,0,164446,0,0,0,164446,0,0,0,164446,0,0,0,164446,0,0,0,164446,0,0,0,164446,0,0,0,164446,0,0,0,164446,0,0,0,164446,0,0,0,164446,0,0,0,164446,0,0,0,164446,0,0,0,164446,0,0,0,164446,0,0,0,164446,0,0,0,164446,0,0,0,164446,0,0,0,0,0,0.0,0.0,65536,0,23904,0,65537,0,19004,0,65536,0,20742,0,65537,0,15027,0,65536,0,21893,0,65536,0,25151,0,65537,0,19889,0,65536,0,24128,0,65536,0,20370,0,65536,0,21586,0,65536,0,12371,0,65536,0,26646,0,65536,0,19867,0,65536,0,31375,0,65536,0,27021,0,65538,0,25076,0,65536,0,14794,0,65536,0,24629,0,65536,0,24098,0,65536,0,11770,0,65538,0,19786,0,65592,0,19200,0,65537,0,22009,0,65539,0,22360,0,65596,0,19957,0,65537,0,13891,0,65536,0,12389,0,65536,0,24511,0,65536,0,27092,0,65537,0,14525,0,65594,0,19895,0,65536,0,16042,0,524288.0,524288.0,0,41531926,0,0,0,41984751,0,0,0,45012719,0,0,0,41620872,0,0,0,40629870,0,0,0,44225031,0,0,0,46461619,0,0,0,46087217,0,0,0,41261553,0,0,0,41380468,0,0,0,38808435,0,0,0,41636585,0,0,0,40662074,0,0,0,43338525,0,0,0,40829335,0,0,0,46475240,0,0,0,44099660,0,0,0,43983067,0,0,0,44962563,0,0,0,49747705,0,0,0,40432189,0,0,0,40295135,0,0,0,49220346,0,0,0,40473363,0,0,0,40299382,0,0,0,41733315,0,0,0,39736873,0,0,0,39895200,0,0,0,40780472,0,0,0,45424103,0,0,0,42157429,0,0,0,46453795,0,0,0.0,0.0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,524288.0,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32769,32769,32769,0,32768,32768,32768,0,32768,32768,32768,0,32824,32824,32824,0,32769,32769,32769,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32830,32830,32830,0,32770,32770,32770,0,32769,32769,32769,0,32768,32768,32768,0,32768,32768,32768,166,32770,32936,32936,222,32770,32992,32992,0,32768,32768,32768,0,32768,32768,32768,0,32832,32832,32832,0,32769,32769,32769,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32936,0,0,32992,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,934393,0,0,65536,63800,56,1680,0,8388608.0,8388608.0,8388608.0,0.0,0.0,0.0,0.0,0.0,126357,146845,9639,3282,0,163229,1049150.0,0.0,388.0,1048762.0,65536,0,0,0,524288,524288,131072,0,0.0,0.0,104.0,2097152.0,0.0,2097152.0,524288.0,42596,0,2848,162671,0,1049150.0,0.0,0.0,31.0,4063232,2883584,0,0,0,0,0,0,6608.0,2027262.0,0.0,2097152.0,2097152.0,0.0,1331507,0,0,13770,0.0,0.0,0.0,0.0,262144,0,0,0,0,0,1507328,458752,874530412.0,2278427046.0,0.0,2097152.0,8.0,0.0,0,0,151297,0.0,0.0,0.0,0.0,65536,524288,0,0,0,65536,65536,47082607,0.0,0.0,0.0,0.0,0.0,26086.0,0,0,0.0,2097339.0,0.0,360.0,25808782,3735552,0,0,2883584,196608,0,131072,0.0,0.0,0.0,0.0,0.0,0.0,0,131072,0.0,0.0,594776.0,1719901.0,524288,0,524288,65536,131072,184549376,917504,0,0.0,0.0,0.0,0.0,0.0,0.0,65536,0,0.0,0.0,983046.0,0.0,0,0,65536,0,0,0,0,4194304,2097152.0,0.0,0.0,12402936.0,0.0,524288.0,2097286.0,0.0,1388633377.0,0.0,17571643981060,17589318384193,17589318476193,17571644736091
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/prev_analysis/1.csv
index e95e9a8f01..47c0cc7e4c 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,3357764.0,3357764.0,3357764.0,7.843504225044691
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,1725602.0,1725602.0,1725602.0,4.030886797805197
 "void benchmark_func<double, 256, 8u, 512u>(double, double*) [clone .kd]",1,1716162.0,1716162.0,1716162.0,4.008835611395305
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/prev_analysis/1001.csv
index f475f954a6..fb5988001a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,494.8622754491018,Instr per wave
 VMEM,7.958083832335329,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,0.0,Instr per wave
 SALU,24.520958083832337,Instr per wave
 SMEM,1.8023952095808384,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/prev_analysis/101.csv
index b4d2c2d2f8..40f518e31b 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx90a
 mi200
 56
 1638.4
-SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/prev_analysis/1202.csv
index da443b2558..d8ea5e5efc 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,18318.37779107922,1868.3109588623047,257481.04174804688,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/prev_analysis/1901.csv
index ea6f7e11fd..87a0a70fae 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,2.0,smem_
 VALU,495.0,valu_
 MFMA,0.0,mfma_
 VMEM,8.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,10.0,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,67894.0,wavefronts_
 Workgroups,16973.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,128.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,0.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,44.0,hbm_rd_
 HBM Wr,0.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,70.0,vl1_coales_
 VL1 Stall,2.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,26.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/prev_analysis/201.csv
index 5970f4d40e..2e0ee7f6d6 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,58.35028353667187,Pct,100,58.35028353667187
 MFMA Util,0.0,Pct,100,0.0
 VALU Active Threads/Wave,64.0,Threads,64,100.0
 IPC - Issue,1.0,Instr/cycle,5,20.0
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.9926236331748,Pct,100,99.9926236331748
 Instr Cache BW,1673.857241502793,Gb/s,6092.8,27.472709452186074
 Scalar L1D Cache Hit Rate,99.34855886134334,Pct,100,99.34855886134334
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/prev_analysis/602.csv
index acf870f9f5..123e7c9d8c 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,12167494.700598802,0,387091151,Simd
 Insufficient SIMD VGPRs,0.0,0,0,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/prev_analysis/701.csv
index 12250d77c0..db0925a109 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/sysinfo.csv
index 3754d725ce..161dceb51d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-no_roof_Axes4,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:46:08 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+no_roof_Axes4,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:46:08 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/timestamps.csv
index 4fa8b7e149..9f67fdd60c 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Axes4/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,222418,222418,33554432,256,0,0,4,32,4160,0x0,0x7f66d0e04280,17589313238708,17589313263708,17589313504348,17589313614998
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,222418,222418,32768,256,0,0,12,24,13888,0x0,0x7f66d0e23f80,17589318283979,17589318300033,17589318313633,17589318330788
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,222418,222418,4194304,256,0,0,12,24,14336,0x7f66d3e02380,0x7f66d0e23fc0,17589318336618,17589318384193,17589318476193,17589318478204
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_CMD_INV/mi100/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_CMD_INV/mi100/SQ_IFETCH_LEVEL.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_CMD_INV/mi100/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_CMD_INV/mi100/SQ_IFETCH_LEVEL.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_CMD_INV/mi100/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_CMD_INV/mi100/SQ_INST_LEVEL_LDS.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_CMD_INV/mi100/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_CMD_INV/mi100/SQ_INST_LEVEL_LDS.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_CMD_INV/mi100/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_CMD_INV/mi100/SQ_INST_LEVEL_SMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_CMD_INV/mi100/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_CMD_INV/mi100/SQ_INST_LEVEL_SMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_CMD_INV/mi100/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_CMD_INV/mi100/SQ_INST_LEVEL_VMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_CMD_INV/mi100/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_CMD_INV/mi100/SQ_INST_LEVEL_VMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_CMD_INV/mi100/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_CMD_INV/mi100/SQ_LEVEL_WAVES.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_CMD_INV/mi100/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_CMD_INV/mi100/SQ_LEVEL_WAVES.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_CMD_INV/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_CMD_INV/mi100/pmc_perf.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_CMD_INV/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_CMD_INV/mi100/pmc_perf.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_CMD_INV/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_CMD_INV/mi100/timestamps.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_CMD_INV/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_CMD_INV/mi100/timestamps.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi100/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi100/pmc_dispatch_info.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi100/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi100/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi100/pmc_perf.csv
index 688c8281c7..5b6d2fdcc3 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,CPC_ME1_DC0_SPI_BUSY,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,CPC_ME1_DC0_SPI_BUSY,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBuffer.kd,0,0,0,868852,868857,33554432,256,0,0,8,32,6464,0x0,0x7fe0c3a04180,4029584,3826331,524288,503697,503697,503697,0,730,502466,11423,2560,2851,506751,0,17018,476693,12075292247429918,12075298394918942,12075298395241339,12075292494715737
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,868852,868857,32768,256,0,0,24,24,12480,0x0,0x7fe0c3a35100,224040,75644,512,28004,28004,28004,0,650,28192,12267,2716,2440,24402,0,20912,695,12075292509297973,12075298410199883,12075298410206763,12075292509625201
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,868852,868857,4194304,256,0,0,24,24,12928,0x7fe1f39f1900,0x7fe0c3a35140,1824800,1659275,65536,228099,228099,228099,0,732,217693,11599,2614,2438,213008,0,19759,199686,12075292509682647,12075298410323561,12075298410454600,12075292510053456
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi100/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi100/prev_analysis/1.csv
index 40bf3ff331..51a0593e4c 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi100/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi100/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,6057874.0,6057874.0,6057874.0,9.177472312180896
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4526046.0,4526046.0,4526046.0,6.856805184237423
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 256u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,3050217.0,3050217.0,3050217.0,4.620974629654475
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi100/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi100/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi100/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi100/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi100/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi100/prev_analysis/1202.csv
index d92c0479fa..2d4898d1f7 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi100/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi100/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,,,,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi100/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi100/prev_analysis/1901.csv
index 13c557f6ef..85c7cb0291 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi100/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi100/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,24.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,,il1_fetch_
 IL1 Hit,,il1_hit_
 IL1_L2 Rd,,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi100/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi100/prev_analysis/2001.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi100/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi100/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi100/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi100/prev_analysis/201.csv
index 52e9f5bf0c..91625c4b2e 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi100/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi100/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,,Gb/sec,23070.72,
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,,Gb/sec,23070.72,
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,,Pct,100,
 Instr Cache BW,,Gb/s,4614.144,
 Scalar L1D Cache Hit Rate,,Pct,100,
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi100/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi100/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi100/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi100/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi100/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi100/prev_analysis/701.csv
index 8fb0971b0c..b6e142aea6 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi100/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi100/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,23.976047904191617,8,36,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi100/timestamps.csv
index 3697d11953..a4b9e56da7 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,869055,869060,33554432,256,0,0,8,32,6464,0x0,0x7fe209804180,12075298394874174,12075298394918942,12075298395241339,12075298395319412
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,869055,869060,32768,256,0,0,24,24,12480,0x0,0x7fe209835100,12075298410086942,12075298410199883,12075298410206763,12075298410212375
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,869055,869060,4194304,256,0,0,24,24,12928,0x7fe3153ab900,0x7fe209835140,12075298410303855,12075298410323561,12075298410454600,12075298410457851
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi200/pmc_perf.csv
index 7a0de2d843..77c48c4ad1 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,CPC_ME1_DC0_SPI_BUSY,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,CPC_ME1_DC0_SPI_BUSY,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBufferAligned.kd,0,0,0,161282,161282,33554432,256,0,0,4,32,4160,0x0,0x7f1ced404280,3060256,2974809,524288,382531,382531,382531,0,302,380887,8361,520,1214,381328,0,8876,371799,16487431042244,16491695721721,16491695960599,16487579249208
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,161282,161282,32768,256,0,0,12,24,13888,0x0,0x7f1ced423f80,271576,168769,512,33946,33946,33946,0,302,34055,11324,515,1345,31962,0,29658,496,16487584392605,16491700778153,16491700791273,16487584528580
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,161282,161282,4194304,256,0,0,12,24,14336,0x7f1cf0358380,0x7f1ced423fc0,1312960,1206142,65536,164119,164119,164119,0,302,164001,9947,1980,2871,162636,0,14203,148167,16487584563968,16491700861193,16491700953512,16487584903746
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi200/prev_analysis/1.csv
index d48e3c55cc..2844bea5de 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,3357729.0,3357729.0,3357729.0,7.83928394992091
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,1726385.0,1726385.0,1726385.0,4.030588002153899
 "void benchmark_func<double, 256, 8u, 512u>(double, double*) [clone .kd]",1,1715824.0,1715824.0,1715824.0,4.0059312541569305
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi200/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi200/prev_analysis/1202.csv
index d92c0479fa..2d4898d1f7 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,,,,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi200/prev_analysis/1901.csv
index bf48a8d6b0..fea0ee3201 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,,il1_fetch_
 IL1 Hit,,il1_hit_
 IL1_L2 Rd,,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi200/prev_analysis/201.csv
index b4d9ea9d64..2086c73dba 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,,Gb/sec,22630.4,
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,,Gb/sec,22630.4,
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,,Pct,100,
 Instr Cache BW,,Gb/s,6092.8,
 Scalar L1D Cache Hit Rate,,Pct,100,
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi200/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi200/prev_analysis/701.csv
index d28098ed25..9d9e3a3dab 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi200/timestamps.csv
index ff92a7e566..db577ac297 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_CPC/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,161495,161495,33554432,256,0,0,4,32,4160,0x0,0x7fac9be04280,16491695695851,16491695721721,16491695960599,16491696073827
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,161495,161495,32768,256,0,0,12,24,13888,0x0,0x7fac9be23f80,16491700762811,16491700778153,16491700791273,16491700809859
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,161495,161495,4194304,256,0,0,12,24,14336,0x7facba5de380,0x7fac9be23fc0,16491700814069,16491700861193,16491700953512,16491700955214
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi100/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi100/pmc_dispatch_info.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi100/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi100/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi100/pmc_perf.csv
index aac6f6a58a..a08f47843b 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,GRBM_COUNT,GRBM_GUI_ACTIVE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,GRBM_COUNT,GRBM_GUI_ACTIVE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBuffer.kd,0,0,0,870326,870331,33554432,256,0,0,8,32,6464,0x0,0x7faa94c04180,4036816,3832483,524288,504601,504601,504601,0,4193,0,0,503524,0,12075333171398844,12075337326712913,12075337327035950,12075333417182692
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,870326,870331,32768,256,0,0,24,24,12480,0x0,0x7faa94c35100,222952,77688,512,27868,27868,27868,0,2274,0,0,24307,0,12075333431726747,12075337341910373,12075337341917253,12075333432073060
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,870326,870331,4194304,256,0,0,24,24,12928,0x7faba08f5900,0x7faa94c35140,1734176,1571525,65536,216771,216771,216771,0,2258,0,0,222232,0,12075333432135907,12075337341978052,12075337342114851,12075333432497238
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi100/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi100/prev_analysis/1.csv
index 31b6826161..9dffeb9d4b 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi100/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi100/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,6054671.0,6054671.0,6054671.0,9.178119260095158
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4525404.0,4525404.0,4525404.0,6.859942945225541
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 256u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,3051016.0,3051016.0,3051016.0,4.624956287874021
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi100/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi100/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi100/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi100/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi100/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi100/prev_analysis/1202.csv
index d92c0479fa..2d4898d1f7 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi100/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi100/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,,,,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi100/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi100/prev_analysis/1901.csv
index 13c557f6ef..85c7cb0291 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi100/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi100/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,24.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,,il1_fetch_
 IL1 Hit,,il1_hit_
 IL1_L2 Rd,,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi100/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi100/prev_analysis/2001.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi100/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi100/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi100/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi100/prev_analysis/201.csv
index 52e9f5bf0c..91625c4b2e 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi100/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi100/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,,Gb/sec,23070.72,
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,,Gb/sec,23070.72,
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,,Pct,100,
 Instr Cache BW,,Gb/s,4614.144,
 Scalar L1D Cache Hit Rate,,Pct,100,
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi100/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi100/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi100/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi100/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi100/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi100/prev_analysis/701.csv
index 8fb0971b0c..b6e142aea6 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi100/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi100/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,23.976047904191617,8,36,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi100/timestamps.csv
index 7bd8580771..48eaf2e2bb 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,870469,870474,33554432,256,0,0,8,32,6464,0x0,0x7fda00804180,12075337326665086,12075337326712913,12075337327035950,12075337327141892
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,870469,870474,32768,256,0,0,24,24,12480,0x0,0x7fda00835100,12075337341805278,12075337341910373,12075337341917253,12075337341922797
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,870469,870474,4194304,256,0,0,24,24,12928,0x7fdb0c52f900,0x7fda00835140,12075337341964654,12075337341978052,12075337342114851,12075337342118360
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi200/pmc_perf.csv
index 8ee71c2662..b523fff7e3 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,GRBM_COUNT,GRBM_GUI_ACTIVE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,GRBM_COUNT,GRBM_GUI_ACTIVE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBufferAligned.kd,0,0,0,163645,163645,33554432,256,0,0,4,32,4160,0x0,0x7fdfc4204280,3024400,2936159,524288,378049,378049,378049,0,2943,0,0,378914,0,16557764036566,16560615162516,16560615404114,16557911817657
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,163645,163645,32768,256,0,0,12,24,13888,0x0,0x7fdfc4223f80,277736,167364,512,34716,34716,34716,0,1848,0,0,30542,0,16557916956253,16560620237679,16560620251119,16557917095318
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,163645,163645,4194304,256,0,0,12,24,14336,0x7fdfc71dc380,0x7fdfc4223fc0,1313832,1208091,65536,164228,164228,164228,0,1900,0,0,165602,0,16557917131416,16560620321359,16560620413838,16557917470644
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi200/prev_analysis/1.csv
index 1bf4984716..a5573f7923 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,3358697.0,3358697.0,3358697.0,7.840119862180714
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,1726228.0,1726228.0,1726228.0,4.029489539977107
 "void benchmark_func<double, 256, 8u, 512u>(double, double*) [clone .kd]",1,1716628.0,1716628.0,1716628.0,4.0070805073442335
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi200/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi200/prev_analysis/1202.csv
index d92c0479fa..2d4898d1f7 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,,,,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi200/prev_analysis/1901.csv
index bf48a8d6b0..fea0ee3201 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,,il1_fetch_
 IL1 Hit,,il1_hit_
 IL1_L2 Rd,,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi200/prev_analysis/201.csv
index b4d9ea9d64..2086c73dba 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,,Gb/sec,22630.4,
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,,Gb/sec,22630.4,
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,,Pct,100,
 Instr Cache BW,,Gb/s,6092.8,
 Scalar L1D Cache Hit Rate,,Pct,100,
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi200/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi200/prev_analysis/701.csv
index d28098ed25..9d9e3a3dab 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi200/timestamps.csv
index c24b0b3dcb..b2e7c981da 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_CPF/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,163806,163806,33554432,256,0,0,4,32,4160,0x0,0x7f6951404280,16560615136465,16560615162516,16560615404114,16560615491373
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,163806,163806,32768,256,0,0,12,24,13888,0x0,0x7f6951423f80,16560620221963,16560620237679,16560620251119,16560620269262
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,163806,163806,4194304,256,0,0,12,24,14336,0x7f6954367380,0x7f6951423fc0,16560620274852,16560620321359,16560620413838,16560620415986
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv1/mi100/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv1/mi100/SQ_IFETCH_LEVEL.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv1/mi100/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv1/mi100/SQ_IFETCH_LEVEL.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv1/mi100/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv1/mi100/SQ_INST_LEVEL_LDS.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv1/mi100/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv1/mi100/SQ_INST_LEVEL_LDS.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv1/mi100/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv1/mi100/SQ_INST_LEVEL_SMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv1/mi100/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv1/mi100/SQ_INST_LEVEL_SMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv1/mi100/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv1/mi100/SQ_INST_LEVEL_VMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv1/mi100/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv1/mi100/SQ_INST_LEVEL_VMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv1/mi100/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv1/mi100/SQ_LEVEL_WAVES.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv1/mi100/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv1/mi100/SQ_LEVEL_WAVES.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv1/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv1/mi100/pmc_perf.csv
index 680dcd454a..b9dc37a92b 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv1/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv1/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,BeginNs,EndNs
+Dispatch_ID,Kernel_Name,Start_Timestamp,End_Timestamp
 ,,12074349642855155,12074349643181232
 ,,12074349657727546,12074349657734905
 ,,12074349657795385,12074349657927704
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv1/mi100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv1/mi100/sysinfo.csv
index 6b91041035..146d1cd0d7 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv1/mi100/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv1/mi100/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-no_roof_D_int_inv1,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 10:58:15 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+no_roof_D_int_inv1,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 10:58:15 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv1/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv1/mi100/timestamps.csv
index 1eaeb7cd84..9c2a7a207d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv1/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv1/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,823089,823094,33554432,256,0,0,8,32,6464,0x0,0x7f7049c04180,12074349642809189,12074349642855155,12074349643181232,12074349643291395
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,823089,823094,32768,256,0,0,24,24,12480,0x0,0x7f7049c35100,12074349657629236,12074349657727546,12074349657734905,12074349657740663
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,823089,823094,4194304,256,0,0,24,24,12928,0x7f71558e2900,0x7f7049c35140,12074349657781619,12074349657795385,12074349657927704,12074349657930987
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv1/mi200/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv1/mi200/SQ_IFETCH_LEVEL.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv1/mi200/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv1/mi200/SQ_IFETCH_LEVEL.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv1/mi200/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv1/mi200/SQ_INST_LEVEL_LDS.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv1/mi200/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv1/mi200/SQ_INST_LEVEL_LDS.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv1/mi200/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv1/mi200/SQ_INST_LEVEL_SMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv1/mi200/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv1/mi200/SQ_INST_LEVEL_SMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv1/mi200/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv1/mi200/SQ_INST_LEVEL_VMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv1/mi200/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv1/mi200/SQ_INST_LEVEL_VMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv1/mi200/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv1/mi200/SQ_LEVEL_WAVES.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv1/mi200/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv1/mi200/SQ_LEVEL_WAVES.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv1/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv1/mi200/pmc_perf.csv
index d43ba90a46..2e61025e39 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv1/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv1/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,BeginNs,EndNs
+Dispatch_ID,Kernel_Name,Start_Timestamp,End_Timestamp
 ,,15301661411416,15301661650617
 ,,15301666499277,15301666512717
 ,,15301666583597,15301666675757
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv1/mi200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv1/mi200/sysinfo.csv
index 6df95fe6bf..9306ae4aab 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv1/mi200/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv1/mi200/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-no_roof_D_int_inv1,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:08:00 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+no_roof_D_int_inv1,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:08:00 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv1/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv1/mi200/timestamps.csv
index 31e55a4818..1cd75b8057 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv1/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv1/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,101603,101603,33554432,256,0,0,4,32,4160,0x0,0x7fb1d8604280,15301661384906,15301661411416,15301661650617,15301661763837
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,101603,101603,32768,256,0,0,12,24,13888,0x0,0x7fb1d8623f80,15301666483378,15301666499277,15301666512717,15301666530877
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,101603,101603,4194304,256,0,0,12,24,14336,0x7fb1f7009380,0x7fb1d8623fc0,15301666536847,15301666583597,15301666675757,15301666677913
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv2/mi100/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv2/mi100/SQ_IFETCH_LEVEL.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv2/mi100/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv2/mi100/SQ_IFETCH_LEVEL.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv2/mi100/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv2/mi100/SQ_INST_LEVEL_LDS.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv2/mi100/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv2/mi100/SQ_INST_LEVEL_LDS.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv2/mi100/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv2/mi100/SQ_INST_LEVEL_SMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv2/mi100/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv2/mi100/SQ_INST_LEVEL_SMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv2/mi100/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv2/mi100/SQ_INST_LEVEL_VMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv2/mi100/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv2/mi100/SQ_INST_LEVEL_VMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv2/mi100/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv2/mi100/SQ_LEVEL_WAVES.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv2/mi100/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv2/mi100/SQ_LEVEL_WAVES.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv2/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv2/mi100/pmc_perf.csv
index 310cfc9628..ebca1dde78 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv2/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv2/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,BeginNs,EndNs
+Dispatch_ID,Kernel_Name,Start_Timestamp,End_Timestamp
 ,,12074419883392957,12074419883718874
 ,,12074419898888305,12074419898895345
 ,,12074419898966064,12074419899104303
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv2/mi100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv2/mi100/sysinfo.csv
index bef5fac9d9..1d28695b2c 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv2/mi100/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv2/mi100/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-no_roof_D_int_inv2,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 10:59:26 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+no_roof_D_int_inv2,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 10:59:26 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv2/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv2/mi100/timestamps.csv
index 9f800a690a..cd734cc1ab 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv2/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv2/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,828088,828093,33554432,256,0,0,8,32,6464,0x0,0x7f82b5204180,12074419883346336,12074419883392957,12074419883718874,12074419883803997
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,828088,828093,32768,256,0,0,24,24,12480,0x0,0x7f82b5235100,12074419898783434,12074419898888305,12074419898895345,12074419898901403
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,828088,828093,4194304,256,0,0,24,24,12928,0x7f83c0ea4900,0x7f82b5235140,12074419898953149,12074419898966064,12074419899104303,12074419899107857
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv2/mi200/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv2/mi200/SQ_IFETCH_LEVEL.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv2/mi200/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv2/mi200/SQ_IFETCH_LEVEL.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv2/mi200/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv2/mi200/SQ_INST_LEVEL_LDS.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv2/mi200/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv2/mi200/SQ_INST_LEVEL_LDS.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv2/mi200/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv2/mi200/SQ_INST_LEVEL_SMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv2/mi200/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv2/mi200/SQ_INST_LEVEL_SMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv2/mi200/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv2/mi200/SQ_INST_LEVEL_VMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv2/mi200/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv2/mi200/SQ_INST_LEVEL_VMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv2/mi200/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv2/mi200/SQ_LEVEL_WAVES.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv2/mi200/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv2/mi200/SQ_LEVEL_WAVES.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv2/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv2/mi200/pmc_perf.csv
index 3b220fbc9f..68a16a4552 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv2/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv2/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,BeginNs,EndNs
+Dispatch_ID,Kernel_Name,Start_Timestamp,End_Timestamp
 ,,15391480043136,15391480282977
 ,,15391485040121,15391485053241
 ,,15391485121881,15391485214042
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv2/mi200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv2/mi200/sysinfo.csv
index a138596c6b..f98c86e8fc 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv2/mi200/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv2/mi200/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-no_roof_D_int_inv2,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:09:30 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+no_roof_D_int_inv2,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:09:30 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv2/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv2/mi200/timestamps.csv
index 7c3fd4ab13..8b32b1dc00 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv2/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_int_inv2/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,107705,107705,33554432,256,0,0,4,32,4160,0x0,0x7f26a9c04280,15391480017656,15391480043136,15391480282977,15391480393467
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,107705,107705,32768,256,0,0,12,24,13888,0x0,0x7f26a9c23f80,15391485025091,15391485040121,15391485053241,15391485069680
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,107705,107705,4194304,256,0,0,12,24,14336,0x7f26acbac380,0x7f26a9c23fc0,15391485076169,15391485121881,15391485214042,15391485215896
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/SQ_IFETCH_LEVEL.csv
index a292ccd349..7bf2583964 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/SQ_IFETCH_LEVEL.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,831089,831094,33554432,256,0,0,8,32,6464,0x0,0x7f6cfe404180,501857,501857,524288,6291456,793461,101522844,12074478004723959,12074478252819418,12074478253141976,12074478253258858
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/SQ_INST_LEVEL_LDS.csv
index 1e893e3988..a685f2d8ae 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/SQ_INST_LEVEL_LDS.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,832883,832890,33554432,256,0,0,8,32,6464,0x0,0x7fc0f2204180,0,0,0,12074499581939808,12074499826559611,12074499826883930,12074499826996392
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/SQ_INST_LEVEL_SMEM.csv
index 8737bfd7a5..5bbb6b6797 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/SQ_INST_LEVEL_SMEM.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,832505,832510,33554432,256,0,0,8,32,6464,0x0,0x7efb75a04180,4194304,3056682,391583536,12074497121455497,12074497362888210,12074497363209808,12074497363325850
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/SQ_INST_LEVEL_VMEM.csv
index 65f75ec794..ccdda35773 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/SQ_INST_LEVEL_VMEM.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,832694,832699,33554432,256,0,0,8,32,6464,0x0,0x7f6d86a04180,1048576,11211604,1436793168,12074498349234410,12074498593235664,12074498593558383,12074498593672405
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/SQ_LEVEL_WAVES.csv
index 420c4f3d38..6fbb9869e5 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/SQ_LEVEL_WAVES.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,833074,833079,33554432,256,0,0,8,32,6464,0x0,0x7fe60e804180,506729,506729,16107,4053840,524288,371049637,3844998,0,1499006244,12074500806457299,12074501054609354,12074501054935593,12074501055050096
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/pmc_dispatch_info.csv
index 90cd5504cd..5794a6cd05 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/pmc_dispatch_info.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/pmc_perf.csv
index ea032cdc5f..0862faa38f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/pmc_perf.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBuffer.kd,0,0,0,831824,831829,33554432,256,0,0,8,32,6464,0x0,0x7fe49f204180,1048576,0,1048576,9437184,0,4194304,1048576,0,503513,503513,57795219,55423516,177,12456924,54627508,54532786,55380876,54206807,4028104,3837470,503513,0,503513,0,16112416,15259810,0,0,0,0,0,17356934,1048576,0,498785,0,0,0,498785,0,0,0,498785,0,0,0,498785,0,0,0,498785,0,0,0,498785,0,0,0,498785,0,0,0,498785,0,0,0,498785,0,0,0,498785,0,0,0,498785,0,0,0,498785,0,0,0,498785,0,0,0,498785,0,0,0,498785,0,0,0,498785,0,0,0,498785,0,0,0,498785,0,0,0,498785,0,0,0,498785,0,0,0,498785,0,0,0,498785,0,0,0,498785,0,0,0,498785,0,0,0,498785,0,0,0,498785,0,0,0,498785,0,0,0,498785,0,0,0,498785,0,0,0,498785,0,0,0,498785,0,0,0,498785,0,0,0,37282523,0,0,0,0,52,0,0,0,0,0,0,0,2551,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,36,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,48,0,0,0,0,0,0,0,2567,0,0,0,0,0,0,0,3,0,0,0,5,0,0,0,2626,0,0,0,0,0,0,0,48,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,2487,0,0,0,1048576,0,0,7189,131080,131080,0,15477,131076,131076,0,0,131072,131072,0,486207,131080,131080,0,3109955,131076,131076,0,1362,131072,131072,0,0,131076,131076,0,0,131076,131076,0,3078689,131076,131076,0,0,131072,131072,0,0,131072,131072,0,0,131088,131088,0,0,131072,131072,0,0,131072,131072,0,0,131080,131080,0,0,131072,131072,0,744,131072,131072,0,783,131076,131076,0,0,131072,131072,0,0,131076,131076,0,3344751,131072,131072,0,0,131072,131072,0,0,131072,131072,0,0,131076,131076,0,3011209,131080,131080,0,1716,131072,131072,0,0,131072,131072,0,47483,131080,131080,0,0,131072,131072,0,0,131072,131072,0,0,131072,131072,0,0,131073,131073,1048576,0,751,0,0,17333171,1448,0,0,17510024,828,0,0,17174562,709,0,0,17038456,1100,0,0,17611077,750,0,0,17445933,1262,0,0,18110527,805,0,0,18503637,2035,0,0,17682913,928,0,0,17394119,740,0,0,17053423,4470,0,0,18158655,709,0,0,17629466,46091,0,0,30432580,1181,0,0,17927025,847,0,0,18392686,699,0,0,16985373,50214,0,0,30397305,805,0,0,16868964,670,0,0,16892812,1006,0,0,17583389,843,0,0,17296275,839,0,0,18020451,47069,0,0,31282040,1375,0,0,17121926,1527,0,0,16861099,667,0,0,16801257,1691,0,0,17080785,794,0,0,17487161,38337,0,0,27788253,891,0,0,17877520,740,0,0,18366918,1048576,131072,131072,0,262144,131260,131124,240,262384,131072,131073,1,262145,131072,131073,1,262145,131119,131073,48,262192,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131073,1,262145,131072,131073,1,262145,131072,133654,2582,264726,131072,131072,0,262144,131072,133663,2591,264735,131072,131072,0,262144,131072,131120,48,262192,131072,131072,0,262144,131072,133701,2629,264773,131213,131075,144,262288,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,133759,2687,264831,131072,131072,0,262144,131072,131072,0,262144,131072,131075,3,262147,131072,131089,17,262161,131072,131072,0,262144,131072,131073,1,262145,131119,131073,48,262192,131072,131072,0,262144,131072,131072,0,262144,262144,0,262144,262336,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262288,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,0,0,3145728,524288,32505856,368661443,218845790,117309797,478138,0,0,0,1048576,52546153,52330145,1048576,1048576,131072,524288,741,500492,4191,0,96,10506,0,8388944,32505856,3997264,3794672,56682115,11534336,0,0,14155776,67108864,67108864,0,67108864,54140219,53851200,0,1048576,236876,761164,11254,2411,0,495570,8399464,0,4194727,4204737,13631488,0,3670016,1048576,1048576,0,4194304,9437184,0,0,360,33554432,54418030,4194304,0,0,2409,505328,0,11270,8388608,0,4194350,905969664,6291456,0,0,0,524288,524288,0,15339,16608567,0,16777216,4194304,4194304,0,0,0,16061,4194376,4194376,0,221047,0,0,0,33554432,0,0,0,0,634635762,0,2772837781,0,0,0,0,0,475096,0,0,220998,0,0,8388608,336,144,0,0,0,480,8388608,0,0,0,0,373839,0,0,0,10831,0,21644,0,6291456,6289211,96,2346,1931207,0,0,0,0,0,0,0,0,0,3145728,0,0,0,158070,4194304,4189847,144,4313,2097152,524288,1572864,0,0,0,0,0,0,524288,0,4128808,65536,4063243,0,0,8388608,0,42008243,0,1048576,10377,4194348,12830213,608157887,12074480154042800,12074501904232604,12074501904556121,12074480399536037
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/prev_analysis/1.csv
index 4595d9d690..bf815d78df 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/prev_analysis/1.csv
@@ -1,2 +1,2 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 __amd_rocclr_fillBuffer.kd,1,323517.0,323517.0,323517.0,100.0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/prev_analysis/1001.csv
index 2923ed58d3..25f1221e3b 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,18.0,Instr per wave
 SMEM,8.0,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/prev_analysis/101.csv
index efda4839c7..fdf92ffadd 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx908
 mi100
 48
 1228.8
-SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/prev_analysis/1202.csv
index 9720d51a5d..cd63e1d7b6 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,2812.6635971069336,2812.6635971069336,2812.6635971069336,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/prev_analysis/1901.csv
index 28c0b8854c..0204200f22 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,8.0,smem_
 VALU,22.0,valu_
 MFMA,,mfma_
 VMEM,2.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,6.0,br_
 VGPR,8.0,vgpr_
 SGPR,32.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,524288.0,wavefronts_
 Workgroups,131072.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,12.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,8.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,0.0,hbm_rd_
 HBM Wr,8.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,25.0,vl1_coales_
 VL1 Stall,22.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,30.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/prev_analysis/2001.csv
index 90cd5504cd..5794a6cd05 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/prev_analysis/2001.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/prev_analysis/201.csv
index 6a2c8d4334..0cdbfb6f0f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,23.428352396065247,Pct,100,23.428352396065247
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,64.0,Threads,64,100.0
 IPC - Issue,0.9193548387096774,Instr/cycle,5,18.387096774193548
-LDS BW,0.0,Gb/sec,23070.72,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,23070.72,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99847359971456,Pct,100,99.99847359971456
 Instr Cache BW,1244.6121347564424,Gb/s,4614.144,26.973846823082294
 Scalar L1D Cache Hit Rate,99.99656323844133,Pct,100,99.99656323844133
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/prev_analysis/602.csv
index 80613e002e..be2a19a264 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,0.0,0,0,Simd
 Insufficient SIMD VGPRs,0.0,0,0,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/prev_analysis/701.csv
index ebf5f22ba4..1d3a71c87a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,8.0,8,8,Registers
 SGPRs,32.0,32,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/sysinfo.csv
index 6d3703697b..1e46606adb 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-no_roof_D_str_inv1,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 11:00:48 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+no_roof_D_str_inv1,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 11:00:48 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/timestamps.csv
index 047d1de89e..525feec4df 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,833124,833129,33554432,256,0,0,8,32,6464,0x0,0x7f6af9204180,12074501904188145,12074501904232604,12074501904556121,12074501904665823
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,833124,833129,32768,256,0,0,24,24,12480,0x0,0x7f6af9235100,12074501919186438,12074501919289837,12074501919296557,12074501919301271
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,833124,833129,4194304,256,0,0,24,24,12928,0x7f6c04df4900,0x7f6af9235140,12074501919337989,12074501919350957,12074501919482476,12074501919485554
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/SQ_IFETCH_LEVEL.csv
index 2789566c15..5a81a44518 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/SQ_IFETCH_LEVEL.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,111872,111872,33554432,256,0,0,4,32,4160,0x0,0x7f561f004280,383912,383912,524288,4718592,682010,76299724,15472655986987,15471895495088,15472803281514,15472803371623
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/SQ_INST_LEVEL_LDS.csv
index a499116808..5481cdc386 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/SQ_INST_LEVEL_LDS.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,113724,113724,33554432,256,0,0,4,32,4160,0x0,0x7f8ad0404280,0,0,0,15487215730710,15486456030394,15487363899060,15487364012110
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/SQ_INST_LEVEL_SMEM.csv
index 33af5396ae..e94ac69e05 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/SQ_INST_LEVEL_SMEM.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,111649,111649,33554432,256,0,0,4,32,4160,0x0,0x7fcb9a804280,3670016,3105196,347293264,15471745122876,15443560431362,15471895495301,15471895609831
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/SQ_INST_LEVEL_VMEM.csv
index 7af92a894e..31c4cfb380 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/SQ_INST_LEVEL_VMEM.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,113501,113501,33554432,256,0,0,4,32,4160,0x0,0x7ff540604280,524288,5374562,601979508,15486308202059,15485298324457,15486456030516,15486456145166
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/SQ_LEVEL_WAVES.csv
index 054e6788cc..6a46ab973f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/SQ_LEVEL_WAVES.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,112095,112095,33554432,256,0,0,4,32,4160,0x0,0x7f66b5c04280,379606,379606,8617,3036856,524288,238488074,2951682,0,970166308,15473567035656,15472803281932,15473711110566,15473711201406
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/pmc_dispatch_info.csv
index 8226fe9c0f..63bb17b9f9 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/pmc_dispatch_info.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/pmc_perf.csv
index ca1b7f83ad..efa69be9e3 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/pmc_perf.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDI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],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBufferAligned.kd,0,0,0,112862,112862,33554432,256,0,0,4,32,4160,0x0,0x7f54e8204280,3094096,3008078,524288,39081560,245112148,392,224,0,386761,386761,39347170.0,38291997.0,2.0,4152726.0,31430513.0,31069019.0,38269333.0,37708934.0,3092385,3014483,386761,0,386761,0,12376352.0,9485635.0,0.0,0.0,0,0,616,0,4718592,4715066,112,3414,379738,0.0,0.0,0.0,524288.0,28728309.0,28006378.0,7964.0,524288.0,131072,524288,302,388680,2283,0,56.0,300.0,0.0,4194696.0,0,0,0,0,0,7340032,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,20357029.0,524288.0,0,386571,0,0,0,386571,0,0,0,386571,0,0,0,386571,0,0,0,386571,0,0,0,386571,0,0,0,386571,0,0,0,386571,0,0,0,386571,0,0,0,386571,0,0,0,386571,0,0,0,386571,0,0,0,386571,0,0,0,386571,0,0,0,386571,0,0,0,386571,0,0,0,386571,0,0,0,386571,0,0,0,386571,0,0,0,386571,0,0,0,386571,0,0,0,386571,0,0,0,386571,0,0,0,386571,0,0,0,386571,0,0,0,386571,0,0,0,386571,0,0,0,386571,0,0,0,386571,0,0,0,386571,0,0,0,386571,0,0,0,386571,0,0,0,0,0,0.0,21250464.0,32,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,2,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,112,0,0,0,32,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,35,0,0,0,1,0,0,0,1,0,0,0,0,0,0,0,4,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,0,0,0,0,0,0,56,0,0,0,0,0,0,0,2,0,0,0,524288.0,0.0,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,312997,129024,129024,0,1195,129024,129024,0,0,129024,129024,0,195,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,43936,129024,129024,0,539662,129024,129024,0,0,129024,129024,0,0,129024,129024,0,196,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,27663,129024,129024,0,1029,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,45161,129024,129024,0,186,129024,129024,524288.0,0.0,45361,0,0,50871569,46564,0,0,50989794,44702,0,0,50054588,46534,0,0,51625945,44480,0,0,51000068,46494,0,0,51468068,44170,0,0,50802794,47618,0,0,52731183,45326,0,0,50932397,46962,0,0,51244867,45636,0,0,50345127,48000,0,0,52172549,46349,0,0,51495675,46422,0,0,51388900,46167,0,0,51270366,47834,0,0,52862746,44549,0,0,50510285,45942,0,0,50777509,44524,0,0,50378305,47664,0,0,52157997,44286,0,0,50793828,45506,0,0,51317148,44152,0,0,50497118,48193,0,0,52669966,44584,0,0,50543595,46974,0,0,51282532,45745,0,0,50472073,48352,0,0,52295315,46944,0,0,51861704,47016,0,0,51686907,45546,0,0,50923964,48580,0,0,52949319,0.0,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65569,33,131105,65646,65538,112,131184,65536,65536,0,131072,65536,65536,0,131072,65591,65537,56,131128,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65568,32,131104,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65571,35,131107,65758,65538,224,131296,65536,65537,1,131073,65536,65592,56,131128,65536,65536,0,131072,65536,65536,0,131072,65536,65538,2,131074,65536,65536,0,131072,65536,65536,0,131072,65536,65680,144,131216,65591,65537,56,131128,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131184,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131296,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131128,0,131072,1053430,0,524288,3670016,3663361,224,6431,1048576,33554432.0,33554432.0,0.0,33554432.0,30143066.0,28501914.0,0.0,524288.0,217808,536585,8655,917,0,384192,4195054.0,0.0,2097594.0,2097460.0,1048576,1048576,0,524288,0,524288,7340032,0,0.0,0.0,104.0,8388608.0,29721924.0,2097152.0,0.0,206691,0,1287,387116,0,749.0,4194304.0,0.0,2064387.0,25690112,9437184,0,0,0,0,0,0,13277.0,8242561.0,0.0,8388608.0,2097152.0,4194304.0,9996398,0,0,8785,4128768.0,4128768.0,0.0,1474193.0,0,0,0,0,0,0,5767168,1048576,315605901.0,0.0,1472008782.0,0.0,48.0,0.0,0,0,371260,0.0,0.0,1488680.0,0.0,3670016,524288,0,0,0,2621440,524288,177669161,4194304.0,0.0,0.0,0.0,0.0,1207174.0,0,0,0.0,312.0,0.0,608.0,42094224,24117248,0,0,9437184,11010048,0,3145728,0.0,0.0,0.0,0.0,0.0,0.0,0,1572864,0.0,0.0,0.0,194468.0,524288,524288,0,3670016,7340032,603979776,4718592,0,0.0,0.0,0.0,0.0,0.0,0.0,524288,0,2064384.0,0.0,2031623.0,0.0,0,0,524288,0,0,0,0,33554432,0.0,4194304.0,0.0,19107899.0,0.0,0.0,141.0,4128768.0,927545.0,1654071594.0,15474959102479,15487994649686,15487994888727,15475103975593
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/prev_analysis/1.csv
index c4e758688f..2ff93d5db0 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/prev_analysis/1.csv
@@ -1,2 +1,2 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 __amd_rocclr_fillBufferAligned.kd,1,239041.0,239041.0,239041.0,100.0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/prev_analysis/1001.csv
index e34ed0c6f6..0850fc4acd 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,18.0,Instr per wave
 VMEM,1.0,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,0.0,Instr per wave
 SALU,14.0,Instr per wave
 SMEM,7.0,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/prev_analysis/101.csv
index f587502c95..4e1b5625d7 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx90a
 mi200
 56
 1638.4
-SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/prev_analysis/1202.csv
index 01235f9483..900538f983 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,1870.0572814941406,1870.0572814941406,1870.0572814941406,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/prev_analysis/1901.csv
index 61ac968e48..72fb1a6caf 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,7.0,smem_
 VALU,18.0,valu_
 MFMA,0.0,mfma_
 VMEM,1.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,5.0,br_
 VGPR,4.0,vgpr_
 SGPR,32.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,524288.0,wavefronts_
 Workgroups,131072.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,9.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,8.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,0.0,hbm_rd_
 HBM Wr,8.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,25.0,vl1_coales_
 VL1 Stall,11.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,25.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/prev_analysis/2001.csv
index 8226fe9c0f..63bb17b9f9 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/prev_analysis/2001.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/prev_analysis/201.csv
index 8ad2c32ee7..12fd9f8881 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,23.462074471354104,Pct,100,23.462074471354104
 MFMA Util,0.0,Pct,100,0.0
 VALU Active Threads/Wave,64.0,Threads,64,100.0
 IPC - Issue,1.0,Instr/cycle,5,20.0
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99762469200526,Pct,100,99.99762469200526
 Instr Cache BW,1263.3392932593154,Gb/s,6092.8,20.734954261740338
 Scalar L1D Cache Hit Rate,99.99388577035882,Pct,100,99.99388577035882
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/prev_analysis/602.csv
index 2927abdec9..8d4034a189 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,9996398.0,9996398,9996398,Simd
 Insufficient SIMD VGPRs,0.0,0,0,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/prev_analysis/701.csv
index c47e77a25f..f8ed8cd0d3 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,4.0,4,4,Registers
 SGPRs,32.0,32,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/sysinfo.csv
index 1fe96f9751..c763e67690 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-no_roof_D_str_inv1,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:11:07 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+no_roof_D_str_inv1,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:11:07 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/timestamps.csv
index 2697d647aa..1f4b92462e 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv1/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,113807,113807,33554432,256,0,0,4,32,4160,0x0,0x7fa59d004280,15487994624215,15487994649686,15487994888727,15487994974087
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,113807,113807,32768,256,0,0,12,24,13888,0x0,0x7fa59d023f80,15487999653070,15487999668109,15487999681229,15487999699569
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,113807,113807,4194304,256,0,0,12,24,14336,0x7fa5a000a380,0x7fa59d023fc0,15487999702759,15487999753390,15487999845550,15487999847736
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/SQ_IFETCH_LEVEL.csv
index edd9155644..57f7f1345e 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/SQ_IFETCH_LEVEL.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,836110,836115,33554432,256,0,0,8,32,6464,0x0,0x7f257e804180,508593,508593,524288,6291456,793907,101401160,12074560959920442,12074561205877467,12074561206204025,12074561206317338
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/SQ_INST_LEVEL_LDS.csv
index ce16ce7d7e..bb569b7a8a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/SQ_INST_LEVEL_LDS.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,837907,837914,33554432,256,0,0,8,32,6464,0x0,0x7fb526e04180,0,0,0,12074582556772061,12074582802990040,12074582803317879,12074582803429801
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/SQ_INST_LEVEL_SMEM.csv
index 35975ac49e..56821d6631 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/SQ_INST_LEVEL_SMEM.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,837529,837534,33554432,256,0,0,8,32,6464,0x0,0x7fbb01404180,4194304,3104058,397078200,12074580117588415,12074580362613785,12074580362938264,12074580363057546
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/SQ_INST_LEVEL_VMEM.csv
index 5daf970bb7..491565ee70 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/SQ_INST_LEVEL_VMEM.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,837718,837723,33554432,256,0,0,8,32,6464,0x0,0x7f5639004180,1048576,10948783,1400242312,12074581340250198,12074581582137043,12074581582457681,12074581582546683
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/SQ_LEVEL_WAVES.csv
index 0ac04f0021..5634846fd4 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/SQ_LEVEL_WAVES.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,838098,838103,33554432,256,0,0,8,32,6464,0x0,0x7f9aa9404180,501353,501353,16169,4010832,524288,368853276,3811635,0,1490177728,12074583775566167,12074584022991699,12074584023314417,12074584023425530
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/pmc_dispatch_info.csv
index 90cd5504cd..5794a6cd05 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/pmc_dispatch_info.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/pmc_perf.csv
index 9ec211403f..cbd8f9a744 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/pmc_perf.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBuffer.kd,0,0,0,836845,836850,33554432,256,0,0,8,32,6464,0x0,0x7f99a5604180,1048576,0,1048576,9437184,0,4194304,1048576,0,503585,503585,57787629,55487857,174,11300420,54593046,54489005,55437515,54266351,4028680,3836964,503585,0,503585,0,16114720,15241798,0,0,0,0,0,16848806,1048576,0,503505,0,0,0,503505,0,0,0,503505,0,0,0,503505,0,0,0,503505,0,0,0,503505,0,0,0,503505,0,0,0,503505,0,0,0,503505,0,0,0,503505,0,0,0,503505,0,0,0,503505,0,0,0,503505,0,0,0,503505,0,0,0,503505,0,0,0,503505,0,0,0,503505,0,0,0,503505,0,0,0,503505,0,0,0,503505,0,0,0,503505,0,0,0,503505,0,0,0,503505,0,0,0,503505,0,0,0,503505,0,0,0,503505,0,0,0,503505,0,0,0,503505,0,0,0,503505,0,0,0,503505,0,0,0,503505,0,0,0,503505,0,0,0,37824349,2630,0,0,0,7,0,0,0,0,0,0,0,0,0,0,0,2565,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,22,0,0,0,0,0,0,0,48,0,0,0,0,0,0,0,0,0,0,0,3,0,0,0,1,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,48,0,0,0,0,0,0,0,2626,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,2751,0,0,0,0,0,0,0,1,0,0,0,49,0,0,0,1048576,0,0,3063854,131076,131076,0,3085,131072,131072,0,0,131072,131072,0,0,131072,131072,0,0,131072,131072,0,0,131072,131072,0,542384,131072,131072,0,0,131076,131076,0,0,131080,131080,0,1676,131072,131072,0,0,131076,131076,0,0,131072,131072,0,3043254,131072,131072,0,0,131076,131076,0,272,131072,131072,0,0,131072,131072,0,3037722,131076,131076,0,783,131076,131076,0,0,131072,131072,0,26498,131072,131072,0,0,131072,131072,0,0,131072,131072,0,7334,131072,131072,0,1728,131072,131072,0,0,131072,131072,0,0,131072,131072,0,0,131080,131080,0,0,131076,131076,0,3110786,131076,131076,0,0,131076,131076,0,267,131076,131076,0,0,131072,131072,1048576,0,45341,0,0,30171107,1172,0,0,17340347,889,0,0,17446057,1053,0,0,17305373,45946,0,0,29605465,1111,0,0,17736120,1068,0,0,18281803,898,0,0,18793427,1018,0,0,17292642,801,0,0,17536965,812,0,0,17227490,1707,0,0,17146101,1623,0,0,17492585,1482,0,0,17774623,2027,0,0,18371095,820,0,0,18748122,1354,0,0,16791880,1558,0,0,17123420,1268,0,0,17508399,954,0,0,17178209,960,0,0,17447711,1586,0,0,17864359,807,0,0,18166773,1775,0,0,18780835,49244,0,0,30235794,747,0,0,17055349,836,0,0,17149586,1759,0,0,17091116,45886,0,0,29915192,836,0,0,17699505,825,0,0,18228844,818,0,0,18581618,1048576,131072,133711,2639,264783,131260,131124,240,262384,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131075,3,262147,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,133695,2623,264767,131072,131072,0,262144,131072,131072,0,262144,131072,131120,48,262192,131072,133656,2584,264728,131260,131076,192,262336,131072,131072,0,262144,131072,131121,49,262193,131072,131072,0,262144,131072,131072,0,262144,131072,131093,21,262165,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131119,133808,2783,264927,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,262144,0,262144,262336,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262288,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,0,0,3145728,524288,32505856,373954869,219052027,122396986,481595,0,0,0,1048576,52685473,52469787,1048576,1048576,131072,524288,709,503468,4156,0,96,10680,0,8388944,32505856,4071952,3862200,57684274,11534336,0,0,14155776,67108864,67108864,0,67108864,54735111,54369943,0,1048576,246514,770802,11636,2505,0,504394,8399933,0,4194727,4205206,13631488,0,3670016,1048576,1048576,0,4194304,9437184,0,0,360,33554432,54173951,4194304,0,0,3700,499293,0,10998,8388608,0,4194444,905969664,6291456,0,0,0,524288,524288,0,15346,16608540,0,16777216,4194304,4194304,0,0,0,15782,4194352,4194352,0,214035,0,0,0,33554432,0,0,0,0,645621943,0,2812159422,0,0,0,0,0,476947,0,0,222271,0,0,8388608,336,144,0,0,0,480,8388608,0,0,0,0,308368,0,0,0,10665,0,21312,0,6291456,6289289,96,2277,1910731,0,0,0,0,0,0,0,0,0,3145728,0,0,0,146954,4194304,4189861,144,4299,2097152,524288,1572864,0,0,0,0,0,0,524288,0,4128883,65534,4063247,0,0,8388608,0,42241080,0,1048576,10682,4194403,13113532,602536699,12074563090728874,12074584862623647,12074584862949244,12074563338241323
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/prev_analysis/1.csv
index b42b74c8ee..41ac2a8d08 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/prev_analysis/1.csv
@@ -1,2 +1,2 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 __amd_rocclr_fillBuffer.kd,1,325597.0,325597.0,325597.0,100.0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/prev_analysis/1001.csv
index 2923ed58d3..25f1221e3b 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,18.0,Instr per wave
 SMEM,8.0,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/prev_analysis/101.csv
index c96b008533..ec98bce8c9 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx908
 mi100
 48
 1228.8
-SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/prev_analysis/1202.csv
index 079f042c15..a2eead173f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,2853.04923248291,2853.04923248291,2853.04923248291,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/prev_analysis/1901.csv
index 81a6880f18..30d2eeecf8 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,8.0,smem_
 VALU,22.0,valu_
 MFMA,,mfma_
 VMEM,2.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,6.0,br_
 VGPR,8.0,vgpr_
 SGPR,32.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,524288.0,wavefronts_
 Workgroups,131072.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,12.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,8.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,0.0,hbm_rd_
 HBM Wr,8.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,25.0,vl1_coales_
 VL1 Stall,20.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,30.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/prev_analysis/2001.csv
index 90cd5504cd..5794a6cd05 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/prev_analysis/2001.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/prev_analysis/201.csv
index 448e20fe32..387853f381 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,23.425002730422868,Pct,100,23.425002730422868
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,64.0,Threads,64,100.0
 IPC - Issue,0.9193548387096774,Instr/cycle,5,18.387096774193548
-LDS BW,0.0,Gb/sec,23070.72,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,23070.72,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99847361864475,Pct,100,99.99847361864475
 Instr Cache BW,1236.6612223085594,Gb/s,4614.144,26.80153073481364
 Scalar L1D Cache Hit Rate,99.99656324992452,Pct,100,99.99656324992452
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/prev_analysis/602.csv
index daff0b97d8..fb6af59a5c 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,0.0,0,0,Simd
 Insufficient SIMD VGPRs,0.0,0,0,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/prev_analysis/701.csv
index ebf5f22ba4..1d3a71c87a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,8.0,8,8,Registers
 SGPRs,32.0,32,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/sysinfo.csv
index 04aa6536f4..1b82b50701 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-no_roof_D_str_inv2,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 11:02:11 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+no_roof_D_str_inv2,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 11:02:11 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/timestamps.csv
index 1673d63069..7151313733 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,838147,838152,33554432,256,0,0,8,32,6464,0x0,0x7fe25f004180,12074584862574226,12074584862623647,12074584862949244,12074584863058606
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,838147,838152,32768,256,0,0,24,24,12480,0x0,0x7fe25f035100,12074584877471661,12074584877570440,12074584877577000,12074584877582767
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,838147,838152,4194304,256,0,0,24,24,12928,0x7fe38f13c900,0x7fe25f035140,12074584877625156,12074584877638759,12074584877774918,12074584877778521
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/SQ_IFETCH_LEVEL.csv
index 955df099ef..284bb9e108 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/SQ_IFETCH_LEVEL.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,117974,117974,33554432,256,0,0,4,32,4160,0x0,0x7fa268604280,381858,381858,524288,4718592,682598,76484688,15569291493406,15568534047603,15569439606996,15569439723646
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/SQ_INST_LEVEL_LDS.csv
index bc5c2c0f8d..644124743a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/SQ_INST_LEVEL_LDS.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,119826,119826,33554432,256,0,0,4,32,4160,0x0,0x7fb903c04280,0,0,0,15583840547909,15583087315176,15583988465177,15583988582797
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/SQ_INST_LEVEL_SMEM.csv
index caa579c3e9..32021d7588 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/SQ_INST_LEVEL_SMEM.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,117751,117751,33554432,256,0,0,4,32,4160,0x0,0x7f3585404280,3670016,2896652,324586744,15568386281491,15540020081908,15568534048020,15568534168599
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/SQ_INST_LEVEL_VMEM.csv
index c176d0f97d..ee8daf36b5 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/SQ_INST_LEVEL_VMEM.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,119603,119603,33554432,256,0,0,4,32,4160,0x0,0x7f417f204280,524288,5344073,598481048,15582944168155,15581948933495,15583087314671,15583087428681
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/SQ_LEVEL_WAVES.csv
index c05e8ee42b..62bb2584c1 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/SQ_LEVEL_WAVES.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,118197,118197,33554432,256,0,0,4,32,4160,0x0,0x7f0750204280,386423,386423,8631,3091392,524288,244479707,3006040,0,994217784,15570193355118,15569439606725,15570343849755,15570343964285
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/pmc_dispatch_info.csv
index 8226fe9c0f..63bb17b9f9 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/pmc_dispatch_info.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/pmc_perf.csv
index a14ba85eb2..bd7558b121 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/pmc_perf.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDI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],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBufferAligned.kd,0,0,0,118964,118964,33554432,256,0,0,4,32,4160,0x0,0x7f6ed6804280,3095008,3004660,524288,39036182,244653402,392,224,0,386875,386875,39302060.0,38285005.0,8.0,4173445.0,31416063.0,31054830.0,38262497.0,37702165.0,3093297,3011065,386875,0,386875,0,12380000.0,9475886.0,0.0,0.0,0,0,616,0,4718592,4714812,112,3668,377050,0.0,0.0,0.0,524288.0,28664314.0,27932468.0,7570.0,524288.0,131072,524288,302,386366,2279,0,56.0,303.0,0.0,4194696.0,0,0,0,0,0,7340032,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,20130582.0,524288.0,0,383954,0,0,0,383954,0,0,0,383954,0,0,0,383954,0,0,0,383954,0,0,0,383954,0,0,0,383954,0,0,0,383954,0,0,0,383954,0,0,0,383954,0,0,0,383954,0,0,0,383954,0,0,0,383954,0,0,0,383954,0,0,0,383954,0,0,0,383954,0,0,0,383954,0,0,0,383954,0,0,0,383954,0,0,0,383954,0,0,0,383954,0,0,0,383954,0,0,0,383954,0,0,0,383954,0,0,0,383954,0,0,0,383954,0,0,0,383954,0,0,0,383954,0,0,0,383954,0,0,0,383954,0,0,0,383954,0,0,0,383954,0,0,0,0,0,0.0,21081059.0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,0,0,3,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,112,0,0,0,0,0,0,0,0,0,0,0,32,0,0,0,0,0,0,0,2,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,56,0,0,0,0,0,0,0,0,0,0,0,34,0,0,0,4,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,0,0,1,0,0,0,524288.0,0.0,0,44487,129024,129024,0,0,129024,129024,0,0,129024,129024,0,294174,129024,129024,0,331,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,43415,129024,129024,0,847,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,28698,129024,129024,0,0,129024,129024,0,0,129024,129024,0,209407,129024,129024,0,1045,129024,129024,0,371,129024,129024,0,0,129024,129024,0,166,129024,129024,0,0,129024,129024,0,45982,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,187,129024,129024,524288.0,0.0,44038,0,0,50585246,45450,0,0,50720976,44699,0,0,50160564,46934,0,0,51919651,44565,0,0,51130541,46123,0,0,51501762,45337,0,0,51058479,47388,0,0,52678350,46096,0,0,51130475,46151,0,0,50965806,45551,0,0,50446796,46128,0,0,51864523,45282,0,0,51445688,46706,0,0,51565186,46918,0,0,51510551,48679,0,0,53052952,44178,0,0,50419218,45667,0,0,50687204,42853,0,0,49996632,46019,0,0,51706875,44518,0,0,51033483,46389,0,0,51641394,44463,0,0,50724191,48121,0,0,52774633,45231,0,0,50810891,46216,0,0,51019321,45619,0,0,50477765,48200,0,0,52336280,45731,0,0,51646464,46348,0,0,51414422,45829,0,0,51247600,48859,0,0,53127858,0.0,65536,65569,33,131105,65536,65536,0,131072,65536,65536,0,131072,65536,65537,1,131073,65646,65538,112,131184,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65648,112,131184,65536,65568,32,131104,65536,65536,0,131072,65591,65537,56,131128,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65571,35,131107,65536,65536,0,131072,65536,65536,0,131072,65536,65592,56,131128,65758,65539,225,131297,65536,65538,2,131074,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65568,32,131104,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65591,65537,56,131128,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131184,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131296,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131128,0,131072,1144706,0,524288,3670016,3663157,224,6635,1048576,33554432.0,33554432.0,0.0,33554432.0,30223744.0,28594062.0,0.0,524288.0,219602,538198,9051,915,0,385210,4195054.0,0.0,2097594.0,2097460.0,1048576,1048576,0,524288,0,524288,7340032,0,0.0,0.0,104.0,8388608.0,29671151.0,2097152.0,0.0,206496,0,1190,385447,0,750.0,4194304.0,0.0,2064387.0,25690112,9437184,0,0,0,0,0,0,13292.0,8242396.0,0.0,8388608.0,2097152.0,4194304.0,9939487,0,0,8876,4128768.0,4128768.0,0.0,1492689.0,0,0,0,0,0,0,5767168,1048576,315733572.0,0.0,1471658173.0,0.0,59.0,0.0,0,0,373987,0.0,0.0,1477559.0,0.0,3670016,524288,0,0,0,2621440,524288,176607668,4194304.0,0.0,0.0,0.0,0.0,1214545.0,0,0,0.0,314.0,0.0,612.0,41516224,24117248,0,0,9437184,11010048,0,3145728,0.0,0.0,0.0,0.0,0.0,0.0,0,1572864,0.0,0.0,0.0,198691.0,524288,524288,0,3670016,7340032,603979776,4718592,0,0.0,0.0,0.0,0.0,0.0,0.0,524288,0,2064384.0,0.0,2031624.0,0.0,0,0,524288,0,0,0,0,33554432,0.0,4194304.0,0.0,19067954.0,0.0,0.0,142.0,4128768.0,657305.0,1651822898.0,15571590464768,15584613356102,15584613594183,15571737864299
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/prev_analysis/1.csv
index 1aae887b79..575df6e896 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/prev_analysis/1.csv
@@ -1,2 +1,2 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 __amd_rocclr_fillBufferAligned.kd,1,238081.0,238081.0,238081.0,100.0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/prev_analysis/1001.csv
index e34ed0c6f6..0850fc4acd 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,18.0,Instr per wave
 VMEM,1.0,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,0.0,Instr per wave
 SALU,14.0,Instr per wave
 SMEM,7.0,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/prev_analysis/101.csv
index 7d23fbdd5f..09e42fbef8 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx90a
 mi200
 56
 1638.4
-SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/prev_analysis/1202.csv
index 6e33a55012..7fdbbe2e0b 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,1866.5573272705078,1866.5573272705078,1866.5573272705078,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/prev_analysis/1901.csv
index e379cf4e1d..4a945781ce 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,7.0,smem_
 VALU,18.0,valu_
 MFMA,0.0,mfma_
 VMEM,1.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,5.0,br_
 VGPR,4.0,vgpr_
 SGPR,32.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,524288.0,wavefronts_
 Workgroups,131072.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,9.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,8.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,0.0,hbm_rd_
 HBM Wr,8.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,25.0,vl1_coales_
 VL1 Stall,11.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,25.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/prev_analysis/2001.csv
index 8226fe9c0f..63bb17b9f9 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/prev_analysis/2001.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/prev_analysis/201.csv
index 20b7d95da4..a95bac07ca 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,23.45516092953896,Pct,100,23.45516092953896
 MFMA Util,0.0,Pct,100,0.0
 VALU Active Threads/Wave,64.0,Threads,64,100.0
 IPC - Issue,1.0,Instr/cycle,5,20.0
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99762456404387,Pct,100,99.99762456404387
 Instr Cache BW,1268.4333819162387,Gb/s,6092.8,20.818562597102133
 Scalar L1D Cache Hit Rate,99.99388542988021,Pct,100,99.99388542988021
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/prev_analysis/602.csv
index 248a6896b6..22dab17e79 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,9939487.0,9939487,9939487,Simd
 Insufficient SIMD VGPRs,0.0,0,0,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/prev_analysis/701.csv
index c47e77a25f..f8ed8cd0d3 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,4.0,4,4,Registers
 SGPRs,32.0,32,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/sysinfo.csv
index 6859fc20ba..0fc9d3fda5 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-no_roof_D_str_inv2,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:12:43 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+no_roof_D_str_inv2,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:12:43 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/timestamps.csv
index 4b92bb5db4..29d3ac03de 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv2/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,119909,119909,33554432,256,0,0,4,32,4160,0x0,0x7efd1d404280,15584613330662,15584613356102,15584613594183,15584613701863
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,119909,119909,32768,256,0,0,12,24,13888,0x0,0x7efd1d423f80,15584618411597,15584618427482,15584618440922,15584618459956
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,119909,119909,4194304,256,0,0,12,24,14336,0x7efd20416380,0x7efd1d423fc0,15584618462356,15584618514683,15584618607003,15584618609303
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/SQ_IFETCH_LEVEL.csv
index 3278d46320..8993c6c798 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/SQ_IFETCH_LEVEL.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,841123,841128,33554432,256,0,0,8,32,6464,0x0,0x7f95a8204180,501857,501857,524288,6291456,792751,101548704,12074645000943659,12074645246692457,12074645247014695,12074645247127018
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/SQ_INST_LEVEL_LDS.csv
index 8645b635e2..7b006b6609 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/SQ_INST_LEVEL_LDS.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,842919,842924,33554432,256,0,0,8,32,6464,0x0,0x7f9972c04180,0,0,0,12074666469935818,12074666711948468,12074666712272146,12074666712385508
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/SQ_INST_LEVEL_SMEM.csv
index 6ea5cbb03c..9f6d5d6ca8 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/SQ_INST_LEVEL_SMEM.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,842541,842546,33554432,256,0,0,8,32,6464,0x0,0x7fe21ba04180,4194304,3180526,406957064,12074664009756113,12074664257031347,12074664257355666,12074664257470888
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/SQ_INST_LEVEL_VMEM.csv
index b185190acf..a5fc0209c8 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/SQ_INST_LEVEL_VMEM.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,842730,842735,33554432,256,0,0,8,32,6464,0x0,0x7fcfdba04180,1048576,11242213,1438325168,12074665239681515,12074665484097143,12074665484423061,12074665484535513
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/SQ_LEVEL_WAVES.csv
index 6bf4eb077e..2965ae9bd4 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/SQ_LEVEL_WAVES.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,843110,843115,33554432,256,0,0,8,32,6464,0x0,0x7fdb7a204180,504073,504073,17265,4032592,524288,371528471,3821989,0,1500910784,12074667696996596,12074667943045634,12074667943369633,12074667943481435
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/pmc_dispatch_info.csv
index 90cd5504cd..5794a6cd05 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/pmc_dispatch_info.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/pmc_perf.csv
index 896e1fddaa..35bc8f8245 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/pmc_perf.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBuffer.kd,0,0,0,841858,841863,33554432,256,0,0,8,32,6464,0x0,0x7f56e4604180,1048576,0,1048576,9437184,0,4194304,1048576,0,504257,504257,57857521,55646138,136,12262557,54810031,54719986,55609232,54441331,4034056,3841624,504257,0,504257,0,16136224,15270592,0,0,0,0,0,17593164,1048576,0,504273,0,0,0,504273,0,0,0,504273,0,0,0,504273,0,0,0,504273,0,0,0,504273,0,0,0,504273,0,0,0,504273,0,0,0,504273,0,0,0,504273,0,0,0,504273,0,0,0,504273,0,0,0,504273,0,0,0,504273,0,0,0,504273,0,0,0,504273,0,0,0,504273,0,0,0,504273,0,0,0,504273,0,0,0,504273,0,0,0,504273,0,0,0,504273,0,0,0,504273,0,0,0,504273,0,0,0,504273,0,0,0,504273,0,0,0,504273,0,0,0,504273,0,0,0,504273,0,0,0,504273,0,0,0,504273,0,0,0,504273,0,0,0,37455980,0,0,0,0,52,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,4,0,0,0,0,0,0,0,21,0,0,0,0,0,0,0,2662,0,0,0,0,0,0,0,0,0,0,0,49,0,0,0,2667,0,0,0,3,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,2666,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2579,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1048576,0,0,20441,131080,131080,0,1683,131072,131072,0,261,131076,131076,0,3120501,131072,131072,0,0,131080,131080,0,0,131076,131076,0,0,131072,131072,0,0,131072,131072,0,2777079,131072,131072,0,0,131072,131072,0,259,131072,131072,0,0,131072,131072,0,0,131072,131072,0,0,131072,131072,0,265,131072,131072,0,2958851,131076,131076,0,0,131076,131076,0,1040,131076,131076,0,0,131076,131076,0,3257902,131080,131080,0,8339,131080,131080,0,565831,131080,131080,0,0,131076,131076,0,0,131072,131072,0,0,131072,131072,0,0,131072,131072,0,0,131076,131076,0,0,131072,131072,0,0,131072,131072,0,2500,131076,131076,0,0,131080,131080,0,0,131076,131076,1048576,0,1992,0,0,17613753,1165,0,0,17448086,1696,0,0,17739331,1735,0,0,17087195,822,0,0,17322904,1229,0,0,17537840,1659,0,0,18649875,49793,0,0,31552493,834,0,0,17113696,2087,0,0,17449897,719,0,0,17585151,46446,0,0,29502763,954,0,0,17350027,868,0,0,17375480,955,0,0,18413226,880,0,0,18322943,1808,0,0,16872550,1626,0,0,17082666,882,0,0,17256004,1688,0,0,16699517,1719,0,0,17458624,1865,0,0,17664637,782,0,0,18415628,1618,0,0,18437965,1146,0,0,16968823,1359,0,0,16908955,844,0,0,17265561,50243,0,0,30078154,1327,0,0,17347348,831,0,0,17476674,848,0,0,18258987,47969,0,0,31066629,1048576,131072,131120,48,262192,131260,133684,2800,264944,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131073,1,262145,131072,131072,0,262144,131119,131074,49,262193,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,133727,2655,264799,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131213,133704,2773,264917,131072,131074,2,262146,131072,131072,0,262144,131072,131072,0,262144,131119,131073,48,262192,131072,131121,49,262193,131072,131093,21,262165,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,133717,2645,264789,131072,131072,0,262144,131072,131072,0,262144,262144,0,262144,262336,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262288,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,0,0,3145728,524288,32505856,371643590,218014685,121123049,481596,0,0,0,1048576,52551886,52337712,1048576,1048576,131072,524288,739,504222,4096,0,96,10711,0,8388944,32505856,4016528,3817083,57009500,11534336,0,0,14155776,67108864,67108864,0,67108864,54077996,53721655,0,1048576,235955,760243,11368,2120,0,497876,8399697,0,4194727,4204970,13631488,0,3670016,1048576,1048576,0,4194304,9437184,0,0,360,33554432,54039901,4194304,0,0,2825,500536,0,11002,8388608,0,4194422,905969664,6291456,0,0,0,524288,524288,0,15320,16608791,0,16777216,4194304,4194304,0,0,0,16106,4194360,4194360,0,219815,0,0,0,33554432,0,0,0,0,637703001,0,2788099291,0,0,0,0,0,477638,0,0,223602,0,0,8388608,336,144,0,0,0,480,8388608,0,0,0,0,331617,0,0,0,10492,0,20966,0,6291456,6289639,96,1941,1865065,0,0,0,0,0,0,0,0,0,3145728,0,0,0,149552,4194304,4189879,144,4281,2097152,524288,1572864,0,0,0,0,0,0,524288,0,4128850,65532,4063248,0,0,8388608,0,42075134,0,1048576,10656,4194392,13040960,608763216,12074647128149195,12074668786317400,12074668786640277,12074647373657680
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/prev_analysis/1.csv
index 05b962f2a0..fdb6ee365a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/prev_analysis/1.csv
@@ -1,2 +1,2 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 __amd_rocclr_fillBuffer.kd,1,322877.0,322877.0,322877.0,100.0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/prev_analysis/1001.csv
index 2923ed58d3..25f1221e3b 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,18.0,Instr per wave
 SMEM,8.0,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/prev_analysis/101.csv
index 7ab170785d..2615baecca 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx908
 mi100
 48
 1228.8
-SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/prev_analysis/1202.csv
index 2fa464a322..12016f7fc1 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,2835.415573120117,2835.415573120117,2835.415573120117,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/prev_analysis/1901.csv
index f3caa26796..5a608fa75a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,8.0,smem_
 VALU,22.0,valu_
 MFMA,,mfma_
 VMEM,2.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,6.0,br_
 VGPR,8.0,vgpr_
 SGPR,32.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,524288.0,wavefronts_
 Workgroups,131072.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,12.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,8.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,0.0,hbm_rd_
 HBM Wr,8.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,25.0,vl1_coales_
 VL1 Stall,21.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,30.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/prev_analysis/2001.csv
index 90cd5504cd..5794a6cd05 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/prev_analysis/2001.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/prev_analysis/201.csv
index 4fedf21b75..655733a170 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,23.393785311854867,Pct,100,23.393785311854867
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,64.0,Threads,64,100.0
 IPC - Issue,0.9193548387096774,Instr/cycle,5,18.387096774193548
-LDS BW,0.0,Gb/sec,23070.72,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,23070.72,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.9984737035821,Pct,100,99.9984737035821
 Instr Cache BW,1247.0791787584747,Gb/s,4614.144,27.027313815053766
 Scalar L1D Cache Hit Rate,99.99656326468852,Pct,100,99.99656326468852
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/prev_analysis/602.csv
index c52ed6727f..82297ab74a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,0.0,0,0,Simd
 Insufficient SIMD VGPRs,0.0,0,0,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/prev_analysis/701.csv
index ebf5f22ba4..1d3a71c87a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,8.0,8,8,Registers
 SGPRs,32.0,32,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/sysinfo.csv
index 89fe74b230..ba6e5145c4 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-no_roof_D_str_inv3,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 11:03:35 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+no_roof_D_str_inv3,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 11:03:35 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/timestamps.csv
index b201d20c33..878e86439b 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,843159,843164,33554432,256,0,0,8,32,6464,0x0,0x7f16da404180,12074668786274283,12074668786317400,12074668786640277,12074668786751229
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,843159,843164,32768,256,0,0,24,24,12480,0x0,0x7f16da435100,12074668802608288,12074668802712508,12074668802719388,12074668802725095
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,843159,843164,4194304,256,0,0,24,24,12928,0x7f17e6059900,0x7f16da435140,12074668802782782,12074668802798748,12074668802934907,12074668802937970
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/SQ_IFETCH_LEVEL.csv
index 3dc62c2f31..0b8fca3b6e 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/SQ_IFETCH_LEVEL.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,124076,124076,33554432,256,0,0,4,32,4160,0x0,0x7f98c6a04280,382005,382005,524288,4718592,685920,76912268,15665903733096,15665145891379,15666048758526,15666048871376
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/SQ_INST_LEVEL_LDS.csv
index 8c286ac2d0..30e7066100 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/SQ_INST_LEVEL_LDS.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,125928,125928,33554432,256,0,0,4,32,4160,0x0,0x7f2051404280,0,0,0,15680420622046,15679691353495,15680564081663,15680564195043
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/SQ_INST_LEVEL_SMEM.csv
index 5e2e277d02..43dff8a7ba 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/SQ_INST_LEVEL_SMEM.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,123853,123853,33554432,256,0,0,4,32,4160,0x0,0x7f0a08004280,3670016,3073402,344393840,15665003335004,15636733317106,15665145891400,15665146005079
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/SQ_INST_LEVEL_VMEM.csv
index fe0508b8b1..9f16e61256 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/SQ_INST_LEVEL_VMEM.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,125705,125705,33554432,256,0,0,4,32,4160,0x0,0x7ff7c4204280,524288,5353402,599545692,15679545727493,15678544147099,15679691353922,15679691466212
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/SQ_LEVEL_WAVES.csv
index 43c52533b0..0d6982a745 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/SQ_LEVEL_WAVES.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,124299,124299,33554432,256,0,0,4,32,4160,0x0,0x7f247c204280,381258,381258,8624,3050072,524288,239521297,2964239,0,974333192,15666807410537,15666048758059,15666950611738,15666950726128
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/pmc_dispatch_info.csv
index 8226fe9c0f..63bb17b9f9 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/pmc_dispatch_info.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/pmc_perf.csv
index f300ffa1ac..8e63b8008c 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/pmc_perf.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDI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],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBufferAligned.kd,0,0,0,125066,125066,33554432,256,0,0,4,32,4160,0x0,0x7f77b7c04280,3085616,2998782,524288,38959963,244265871,392,224,0,385701,385701,39227024.0,38202474.0,3.0,4150831.0,31374620.0,31011008.0,38181394.0,37623706.0,3083905,3005173,385701,0,385701,0,12342432.0,9468924.0,0.0,0.0,0,0,616,0,4718592,4714675,112,3805,374586,0.0,0.0,0.0,524288.0,28458588.0,27725724.0,7657.0,524288.0,131072,524288,301,383730,2335,0,56.0,306.0,0.0,4194696.0,0,0,0,0,0,7340032,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,20225689.0,524288.0,0,385068,0,0,0,385068,0,0,0,385068,0,0,0,385068,0,0,0,385068,0,0,0,385068,0,0,0,385068,0,0,0,385068,0,0,0,385068,0,0,0,385068,0,0,0,385068,0,0,0,385068,0,0,0,385068,0,0,0,385068,0,0,0,385068,0,0,0,385068,0,0,0,385068,0,0,0,385068,0,0,0,385068,0,0,0,385068,0,0,0,385068,0,0,0,385068,0,0,0,385068,0,0,0,385068,0,0,0,385068,0,0,0,385068,0,0,0,385068,0,0,0,385068,0,0,0,385068,0,0,0,385068,0,0,0,385068,0,0,0,385068,0,0,0,0,0,0.0,21162534.0,88,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,32,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,36,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,4,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,112,0,0,0,32,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,524288.0,0.0,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,45016,129024,129024,0,331,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,239985,129024,129024,0,0,129024,129024,0,0,129024,129024,0,282664,129024,129024,0,0,129024,129024,0,843,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,28363,129024,129024,0,1037,129024,129024,0,0,129024,129024,0,0,129024,129024,0,164,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,44898,129024,129024,0,185,129024,129024,524288.0,0.0,45284,0,0,51012816,45068,0,0,50752938,45229,0,0,50746782,46985,0,0,52330857,45209,0,0,51462825,45913,0,0,51405620,44860,0,0,51032615,46171,0,0,52553960,45029,0,0,51027555,46289,0,0,51285888,46182,0,0,50844367,46928,0,0,52517226,43719,0,0,51226255,47535,0,0,52020415,45955,0,0,51292742,47170,0,0,53085895,43093,0,0,50430269,45396,0,0,51031075,44288,0,0,50355392,47599,0,0,52399916,43906,0,0,51102241,46748,0,0,51771751,45489,0,0,51159568,48078,0,0,52972163,44983,0,0,50854915,44966,0,0,50846738,44321,0,0,50557958,47833,0,0,52414796,45049,0,0,51576704,45768,0,0,51585333,45957,0,0,51421032,49047,0,0,53248394,0.0,65536,65536,0,131072,65536,65648,112,131184,65536,65536,0,131072,65536,65568,32,131104,65646,65538,112,131184,65536,65537,1,131073,65536,65536,0,131072,65591,65537,56,131128,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65568,32,131104,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65537,1,131073,65536,65571,35,131107,65758,65538,224,131296,65536,65536,0,131072,65536,65592,56,131128,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65568,32,131104,65591,65537,56,131128,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131184,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131296,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131128,0,131072,1131889,0,524288,3670016,3663187,224,6605,1048576,33554432.0,33554432.0,0.0,33554432.0,29917737.0,28267207.0,0.0,524288.0,214136,535540,8641,883,0,381524,4195055.0,0.0,2097594.0,2097461.0,1048576,1048576,0,524288,0,524288,7340032,0,0.0,0.0,104.0,8388608.0,29697943.0,2097152.0,0.0,205844,0,1208,384010,0,750.0,4194304.0,0.0,2064387.0,25690112,9437184,0,0,0,0,0,0,13285.0,8242473.0,0.0,8388608.0,2097152.0,4194304.0,9800915,0,0,8575,4128768.0,4128768.0,0.0,1488736.0,0,0,0,0,0,0,5767168,1048576,315501606.0,0.0,1471486059.0,0.0,31.0,0.0,0,0,373735,0.0,0.0,1479691.0,0.0,3670016,524288,0,0,0,2621440,524288,177821665,4194304.0,0.0,0.0,0.0,0.0,1209966.0,0,0,0.0,310.0,0.0,604.0,41792561,24117248,0,0,9437184,11010048,0,3145728,0.0,0.0,0.0,0.0,0.0,0.0,0,1572864,0.0,0.0,0.0,186024.0,524288,524288,0,3670016,7340032,603979776,4718592,0,0.0,0.0,0.0,0.0,0.0,0.0,524288,0,2064384.0,0.0,2031623.0,0.0,0,0,524288,0,0,0,0,33554432,0.0,4194304.0,0.0,19030141.0,0.0,0.0,140.0,4128768.0,952491.0,1657705906.0,15668201467349,15681196692115,15681196933076,15668349342438
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/prev_analysis/1.csv
index d8c0cec183..44bef41197 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/prev_analysis/1.csv
@@ -1,2 +1,2 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 __amd_rocclr_fillBufferAligned.kd,1,240961.0,240961.0,240961.0,100.0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/prev_analysis/1001.csv
index e34ed0c6f6..0850fc4acd 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,18.0,Instr per wave
 VMEM,1.0,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,0.0,Instr per wave
 SALU,14.0,Instr per wave
 SMEM,7.0,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/prev_analysis/101.csv
index 500aeb299d..48148677e1 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx90a
 mi200
 56
 1638.4
-SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/prev_analysis/1202.csv
index e552609754..111f587e0a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,1863.600700378418,1863.600700378418,1863.600700378418,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/prev_analysis/1901.csv
index f8b25b1603..a44878351d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,7.0,smem_
 VALU,18.0,valu_
 MFMA,0.0,mfma_
 VMEM,1.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,5.0,br_
 VGPR,4.0,vgpr_
 SGPR,32.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,524288.0,wavefronts_
 Workgroups,131072.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,9.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,8.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,0.0,hbm_rd_
 HBM Wr,8.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,25.0,vl1_coales_
 VL1 Stall,11.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,25.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/prev_analysis/2001.csv
index 8226fe9c0f..63bb17b9f9 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/prev_analysis/2001.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/prev_analysis/201.csv
index afd94ad240..64ca405d1d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,23.52655394882405,Pct,100,23.52655394882405
 MFMA Util,0.0,Pct,100,0.0
 VALU Active Threads/Wave,64.0,Threads,64,100.0
 IPC - Issue,1.0,Instr/cycle,5,20.0
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99762449501961,Pct,100,99.99762449501961
 Instr Cache BW,1253.2728864837047,Gb/s,6092.8,20.56973618834862
 Scalar L1D Cache Hit Rate,99.99388547995298,Pct,100,99.99388547995298
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/prev_analysis/602.csv
index ed593112d0..f4df3614d0 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,9800915.0,9800915,9800915,Simd
 Insufficient SIMD VGPRs,0.0,0,0,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/prev_analysis/701.csv
index c47e77a25f..f8ed8cd0d3 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,4.0,4,4,Registers
 SGPRs,32.0,32,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/sysinfo.csv
index 174184c6f7..e1e848ab8f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-no_roof_D_str_inv3,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:14:20 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+no_roof_D_str_inv3,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:14:20 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/timestamps.csv
index cdbd9eb629..0d168f995f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv3/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,126011,126011,33554432,256,0,0,4,32,4160,0x0,0x7f54fd204280,15681196667545,15681196692115,15681196933076,15681197043526
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,126011,126011,32768,256,0,0,12,24,13888,0x0,0x7f54fd223f80,15681201746081,15681201762217,15681201775497,15681201793759
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,126011,126011,4194304,256,0,0,12,24,14336,0x7f55002e7380,0x7f54fd223fc0,15681201797829,15681201842857,15681201935338,15681201937486
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/SQ_IFETCH_LEVEL.csv
index 6b4cbdc500..86ba429f13 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/SQ_IFETCH_LEVEL.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,846143,846148,33554432,256,0,0,8,32,6464,0x0,0x7f9f2c604180,504585,504585,524288,6291456,792028,101489556,12074727566646360,12074727808682422,12074727809006740,12074727809118622
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/SQ_INST_LEVEL_LDS.csv
index 12a355007b..580712d30c 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/SQ_INST_LEVEL_LDS.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,847938,847943,33554432,256,0,0,8,32,6464,0x0,0x7fcd8b204180,0,0,0,12074748966631649,12074749210726566,12074749211051205,12074749211162427
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/SQ_INST_LEVEL_SMEM.csv
index 5a1f63d8c6..00e09feb0b 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/SQ_INST_LEVEL_SMEM.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,847560,847565,33554432,256,0,0,8,32,6464,0x0,0x7f3470204180,4194304,3126890,400001408,12074746522754560,12074746766141450,12074746766465448,12074746766576130
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/SQ_INST_LEVEL_VMEM.csv
index abc31d534b..0d598e8945 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/SQ_INST_LEVEL_VMEM.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,847749,847754,33554432,256,0,0,8,32,6464,0x0,0x7fe06da04180,1048576,11143199,1427282816,12074747739696755,12074747985411099,12074747985736857,12074747985846000
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/SQ_LEVEL_WAVES.csv
index 0da23809fa..d489644e45 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/SQ_LEVEL_WAVES.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,848130,848135,33554432,256,0,0,8,32,6464,0x0,0x7fbebd004180,505161,505161,17640,4041296,524288,371544769,3830257,0,1500998288,12074750189267584,12074750434631927,12074750434956085,12074750435066258
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/pmc_dispatch_info.csv
index 90cd5504cd..5794a6cd05 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/pmc_dispatch_info.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/pmc_perf.csv
index 7ad37c9fa1..ac1b6c9ac7 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/pmc_perf.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBuffer.kd,0,0,0,846879,846884,33554432,256,0,0,8,32,6464,0x0,0x7fb9aba04180,1048576,0,1048576,9437184,0,4194304,1048576,0,505953,505953,57977514,55606492,135,11998404,54826411,54728559,55567419,54386929,4047624,3849622,505953,0,505953,0,16190496,15304803,0,0,0,0,0,17657764,1048576,0,505273,0,0,0,505273,0,0,0,505273,0,0,0,505273,0,0,0,505273,0,0,0,505273,0,0,0,505273,0,0,0,505273,0,0,0,505273,0,0,0,505273,0,0,0,505273,0,0,0,505273,0,0,0,505273,0,0,0,505273,0,0,0,505273,0,0,0,505273,0,0,0,505273,0,0,0,505273,0,0,0,505273,0,0,0,505273,0,0,0,505273,0,0,0,505273,0,0,0,505273,0,0,0,505273,0,0,0,505273,0,0,0,505273,0,0,0,505273,0,0,0,505273,0,0,0,505273,0,0,0,505273,0,0,0,505273,0,0,0,505273,0,0,0,37759949,0,0,0,0,52,0,0,0,0,0,0,0,20,0,0,0,0,0,0,0,0,0,0,0,3,0,0,0,2715,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2642,0,0,0,2,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,3,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,49,0,0,0,1,0,0,0,2695,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2599,0,0,0,1048576,0,0,15809,131080,131080,0,530560,131076,131076,0,710,131072,131072,0,0,131072,131072,0,7338,131072,131072,0,0,131080,131080,0,0,131072,131072,0,0,131076,131076,0,3066549,131076,131076,0,0,131072,131072,0,264,131072,131072,0,0,131072,131072,0,0,131072,131072,0,1587,131072,131072,0,0,131072,131072,0,3129424,131072,131072,0,258,131072,131072,0,785,131076,131076,0,0,131072,131072,0,3168471,131072,131072,0,2951705,131076,131076,0,0,131072,131072,0,0,131072,131072,0,21994,131072,131072,0,0,131076,131076,0,0,131076,131076,0,0,131080,131080,0,0,131072,131072,0,262,131076,131076,0,0,131076,131076,0,0,131076,131076,0,0,131072,131072,1048576,0,928,0,0,17588687,1155,0,0,17448024,1716,0,0,17134307,50123,0,0,30674730,1878,0,0,17802787,1407,0,0,17586765,1912,0,0,18221197,1636,0,0,18383608,1104,0,0,17394059,818,0,0,17419431,1140,0,0,17009792,1044,0,0,16792166,880,0,0,17460604,976,0,0,17779855,1026,0,0,18086682,47935,0,0,30922425,907,0,0,16951183,1051,0,0,17135746,874,0,0,16947644,48278,0,0,29967317,1748,0,0,17572242,919,0,0,17585164,1456,0,0,17876744,773,0,0,18306672,938,0,0,17253578,917,0,0,16971467,724,0,0,16923096,781,0,0,16687209,1155,0,0,17453510,1104,0,0,17631288,1128,0,0,18006380,50694,0,0,31265775,1048576,131072,131072,0,262144,131260,131124,240,262384,131072,131072,0,262144,131072,131093,21,262165,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,133695,2623,264767,131072,131073,1,262145,131119,131073,48,262192,131072,131072,0,262144,131072,133743,2671,264815,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131119,131073,48,262192,131213,131075,144,262288,131072,131072,0,262144,131072,131072,0,262144,131072,131073,1,262145,131072,131072,0,262144,131072,131076,4,262148,131072,131072,0,262144,131072,131073,1,262145,131072,131073,1,262145,131072,131072,0,262144,131072,133876,2804,264948,131072,131072,0,262144,131072,131072,0,262144,131072,131120,48,262192,131072,133516,2444,264588,262144,0,262144,262336,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262288,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,0,0,3145728,524288,32505856,368426134,217395428,118524850,482617,0,0,0,1048576,52333042,52099722,1048576,1048576,131072,524288,712,505209,4350,0,96,10804,0,8388944,32505856,4009872,3807579,56970453,11534336,0,0,14155776,67108864,67108864,0,67108864,54123118,53792569,0,1048576,244349,768637,11613,2001,0,496946,8399462,0,4194727,4204735,13631488,0,3670016,1048576,1048576,0,4194304,9437184,0,0,360,33554432,54310722,4194304,0,0,2849,503200,0,11273,8388608,0,4194426,905969664,6291456,0,0,0,524288,524288,0,15323,16608772,0,16777216,4194304,4194304,0,0,0,16743,4194388,4194388,0,213982,0,0,0,33554432,0,0,0,0,640470617,0,2808470705,0,0,0,0,0,477003,0,0,223699,0,0,8388608,336,144,0,0,0,480,8388608,0,0,0,0,333407,0,0,0,10578,0,21138,0,6291456,6289398,96,2512,1903869,0,0,0,0,0,0,0,0,0,3145728,0,0,0,153078,4194304,4189866,144,4294,2097152,524288,1572864,0,0,0,0,0,0,524288,0,4128814,65536,4063244,0,0,8388608,0,42528876,0,1048576,10753,4194374,13150298,609218065,12074729647348336,12074751277573152,12074751277900030,12074729895276678
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/prev_analysis/1.csv
index 738227a0b2..eb0ae033aa 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/prev_analysis/1.csv
@@ -1,2 +1,2 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 __amd_rocclr_fillBuffer.kd,1,326878.0,326878.0,326878.0,100.0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/prev_analysis/1001.csv
index 2923ed58d3..25f1221e3b 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,18.0,Instr per wave
 SMEM,8.0,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/prev_analysis/101.csv
index 0e392c06bd..08a7ad1cac 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx908
 mi100
 48
 1228.8
-SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/prev_analysis/1202.csv
index 6dcd4a4e31..67989e6c36 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,2810.8683319091797,2810.8683319091797,2810.8683319091797,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/prev_analysis/1901.csv
index 3bb0cf28d7..780e5b268d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,8.0,smem_
 VALU,22.0,valu_
 MFMA,,mfma_
 VMEM,2.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,6.0,br_
 VGPR,8.0,vgpr_
 SGPR,32.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,524288.0,wavefronts_
 Workgroups,131072.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,12.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,8.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,0.0,hbm_rd_
 HBM Wr,8.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,25.0,vl1_coales_
 VL1 Stall,21.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,30.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/prev_analysis/2001.csv
index 90cd5504cd..5794a6cd05 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/prev_analysis/2001.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/prev_analysis/201.csv
index be2ce5f3f1..e0b8dcd74a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,23.315367237668323,Pct,100,23.315367237668323
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,64.0,Threads,64,100.0
 IPC - Issue,0.9193548387096774,Instr/cycle,5,18.387096774193548
-LDS BW,0.0,Gb/sec,23070.72,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,23070.72,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99847364509768,Pct,100,99.99847364509768
 Instr Cache BW,1231.8148789456616,Gb/s,4614.144,26.696498395924824
 Scalar L1D Cache Hit Rate,99.99656325402565,Pct,100,99.99656325402565
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/prev_analysis/602.csv
index 2c31813584..fb3b3c8fe6 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,0.0,0,0,Simd
 Insufficient SIMD VGPRs,0.0,0,0,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/prev_analysis/701.csv
index ebf5f22ba4..1d3a71c87a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,8.0,8,8,Registers
 SGPRs,32.0,32,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/sysinfo.csv
index 32c8ef4676..430d8a9a5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-no_roof_D_str_inv4,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 11:04:57 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+no_roof_D_str_inv4,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 11:04:57 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/timestamps.csv
index b6cb15af3c..1cf6f4e87a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,848179,848184,33554432,256,0,0,8,32,6464,0x0,0x7ffa95804180,12074751277525897,12074751277573152,12074751277900030,12074751278018352
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,848179,848184,32768,256,0,0,24,24,12480,0x0,0x7ffa95835100,12074751292900118,12074751293012458,12074751293019498,12074751293025441
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,848179,848184,4194304,256,0,0,24,24,12928,0x7ffba147b900,0x7ffa95835140,12074751293072999,12074751293087337,12074751293220776,12074751293224410
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/SQ_IFETCH_LEVEL.csv
index 0504837653..97da754439 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/SQ_IFETCH_LEVEL.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,130178,130178,33554432,256,0,0,4,32,4160,0x0,0x7f9279004280,381573,381573,524288,4718592,681695,76443516,15762571747283,15761812678592,15762719269983,15762719380773
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/SQ_INST_LEVEL_LDS.csv
index aa11dcebb3..39db5a851f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/SQ_INST_LEVEL_LDS.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,132030,132030,33554432,256,0,0,4,32,4160,0x0,0x7f0e68c04280,0,0,0,15777135929656,15776378933036,15777285877764,15777285990534
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/SQ_INST_LEVEL_SMEM.csv
index 0dada68c62..fa0010a147 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/SQ_INST_LEVEL_SMEM.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,129955,129955,33554432,256,0,0,4,32,4160,0x0,0x7f1271a04280,3670016,2932198,328594568,15761663996147,15733239854191,15761812678391,15761812791951
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/SQ_INST_LEVEL_VMEM.csv
index af287da55e..118ecf4848 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/SQ_INST_LEVEL_VMEM.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,131807,131807,33554432,256,0,0,4,32,4160,0x0,0x7f6863c04280,524288,5349982,599157692,15776231942063,15775234134975,15776378933316,15776379046866
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/SQ_LEVEL_WAVES.csv
index 3e6799e071..231bdaf407 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/SQ_LEVEL_WAVES.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,130401,130401,33554432,256,0,0,4,32,4160,0x0,0x7fdcfd804280,377305,377305,8638,3018448,524288,234282039,2933032,0,953365084,15763473597683,15762719269701,15763621644021,15763621755131
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/pmc_dispatch_info.csv
index 8226fe9c0f..63bb17b9f9 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/pmc_dispatch_info.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/pmc_perf.csv
index 27497231e9..2a8faeeea6 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/pmc_perf.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDI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],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBufferAligned.kd,0,0,0,131168,131168,33554432,256,0,0,4,32,4160,0x0,0x7f9529e04280,3114320,3027538,524288,39336224,247344076,392,224,0,389289,389289,39600592.0,38331325.0,4.0,4223610.0,31479256.0,31119243.0,38318688.0,37763463.0,3112609,3033937,389289,0,389289,0,12457248.0,9446836.0,0.0,0.0,0,0,616,0,4718592,4715011,112,3469,376266,0.0,0.0,0.0,524288.0,28638685.0,27910909.0,7846.0,524288.0,131072,524288,301,386246,2669,0,56.0,302.0,0.0,4194696.0,0,0,0,0,0,7340032,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,19764636.0,524288.0,0,379962,0,0,0,379962,0,0,0,379962,0,0,0,379962,0,0,0,379962,0,0,0,379962,0,0,0,379962,0,0,0,379962,0,0,0,379962,0,0,0,379962,0,0,0,379962,0,0,0,379962,0,0,0,379962,0,0,0,379962,0,0,0,379962,0,0,0,379962,0,0,0,379962,0,0,0,379962,0,0,0,379962,0,0,0,379962,0,0,0,379962,0,0,0,379962,0,0,0,379962,0,0,0,379962,0,0,0,379962,0,0,0,379962,0,0,0,379962,0,0,0,379962,0,0,0,379962,0,0,0,379962,0,0,0,379962,0,0,0,379962,0,0,0,0,0,0.0,21084231.0,32,0,0,0,56,0,0,0,0,0,0,0,0,0,0,0,2,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,36,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,4,0,0,0,1,0,0,0,1,0,0,0,0,0,0,0,1,0,0,0,32,0,0,0,0,0,0,0,113,0,0,0,0,0,0,0,1,0,0,0,524288.0,0.0,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,44767,129024,129024,0,999,129024,129024,0,199,129024,129024,0,162723,129024,129024,0,217,129024,129024,0,0,129024,129024,0,340838,129024,129024,0,0,129024,129024,0,0,129024,129024,0,44258,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,27651,129024,129024,0,873,129024,129024,0,1005,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,45057,129024,129024,0,188,129024,129024,524288.0,0.0,42947,0,0,50212081,44633,0,0,50413748,44535,0,0,50268667,46918,0,0,52028743,44276,0,0,51022824,47410,0,0,51960370,44202,0,0,50827631,48393,0,0,53080700,45042,0,0,50803032,45324,0,0,50776767,45669,0,0,50377356,48417,0,0,52583302,45474,0,0,51360863,46020,0,0,51325838,45523,0,0,51079941,47317,0,0,52673898,43725,0,0,50608949,45904,0,0,50775946,44019,0,0,50209750,46885,0,0,52045430,45002,0,0,51385734,44931,0,0,51276473,44735,0,0,50868694,47975,0,0,52762102,45384,0,0,50881333,46041,0,0,51080782,44964,0,0,50412200,47871,0,0,52296634,44959,0,0,51339812,47420,0,0,51924220,45746,0,0,51071016,49155,0,0,53232381,0.0,65536,65592,56,131128,65536,65536,0,131072,65536,65570,34,131106,65536,65536,0,131072,65646,65538,112,131184,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65648,112,131184,65536,65536,0,131072,65536,65568,32,131104,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65537,1,131073,65536,65536,0,131072,65536,65568,32,131104,65536,65536,0,131072,65758,65538,224,131296,65536,65536,0,131072,65536,65536,0,131072,65536,65537,1,131073,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65568,32,131104,65536,65536,0,131072,65646,65538,112,131184,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131184,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131296,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131128,0,131072,1065523,0,524288,3670016,3663354,224,6438,1048576,33554432.0,33554432.0,0.0,33554432.0,30025650.0,28384787.0,0.0,524288.0,214388,536498,8654,922,0,382142,4195052.0,0.0,2097594.0,2097458.0,1048576,1048576,0,524288,0,524288,7340032,0,0.0,0.0,104.0,8388608.0,29763375.0,2097152.0,0.0,206890,0,1219,385811,0,753.0,4194304.0,0.0,2064387.0,25690112,9437184,0,0,0,0,0,0,13289.0,8242429.0,0.0,8388608.0,2097152.0,4194304.0,9890073,0,0,8988,4128768.0,4128768.0,0.0,1497821.0,0,0,0,0,0,0,5767168,1048576,315196278.0,0.0,1469469043.0,0.0,68.0,0.0,0,0,372511,0.0,0.0,1470642.0,0.0,3670016,524288,0,0,0,2621440,524288,176048719,4194304.0,0.0,0.0,0.0,0.0,1214775.0,0,0,0.0,310.0,0.0,604.0,43048033,24117248,0,0,9437184,11010048,0,3145728,0.0,0.0,0.0,0.0,0.0,0.0,0,1572864,0.0,0.0,0.0,205651.0,524288,524288,0,3670016,7340032,603979776,4718592,0,0.0,0.0,0.0,0.0,0.0,0.0,524288,0,2064384.0,0.0,2031624.0,0.0,0,0,524288,0,0,0,0,33554432,0.0,4194304.0,0.0,19033531.0,0.0,0.0,144.0,4128768.0,1005538.0,1660544392.0,15764871113240,15777913720200,15777913958281,15765014098904
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/prev_analysis/1.csv
index 1aae887b79..575df6e896 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/prev_analysis/1.csv
@@ -1,2 +1,2 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 __amd_rocclr_fillBufferAligned.kd,1,238081.0,238081.0,238081.0,100.0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/prev_analysis/1001.csv
index e34ed0c6f6..0850fc4acd 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,18.0,Instr per wave
 VMEM,1.0,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,0.0,Instr per wave
 SALU,14.0,Instr per wave
 SMEM,7.0,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/prev_analysis/101.csv
index f2eb54cc82..e243a8be75 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx90a
 mi200
 56
 1638.4
-SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/prev_analysis/1202.csv
index 9e6bc4a5f8..ad0786cbcb 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,1887.0855407714844,1887.0855407714844,1887.0855407714844,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/prev_analysis/1901.csv
index f1e50360e1..c2c9897a3c 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,7.0,smem_
 VALU,18.0,valu_
 MFMA,0.0,mfma_
 VMEM,1.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,5.0,br_
 VGPR,4.0,vgpr_
 SGPR,32.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,524288.0,wavefronts_
 Workgroups,131072.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,9.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,8.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,0.0,hbm_rd_
 HBM Wr,8.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,25.0,vl1_coales_
 VL1 Stall,11.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,24.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/prev_analysis/2001.csv
index 8226fe9c0f..63bb17b9f9 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/prev_analysis/2001.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/prev_analysis/201.csv
index 89a6e9bf45..964505d262 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,23.309714337202912,Pct,100,23.309714337202912
 MFMA Util,0.0,Pct,100,0.0
 VALU Active Threads/Wave,64.0,Threads,64,100.0
 IPC - Issue,1.0,Instr/cycle,5,20.0
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99762466429826,Pct,100,99.99762466429826
 Instr Cache BW,1268.4333819162387,Gb/s,6092.8,20.818562597102133
 Scalar L1D Cache Hit Rate,99.99388575867636,Pct,100,99.99388575867636
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/prev_analysis/602.csv
index fd68248063..ed10256f33 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,9890073.0,9890073,9890073,Simd
 Insufficient SIMD VGPRs,0.0,0,0,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/prev_analysis/701.csv
index c47e77a25f..f8ed8cd0d3 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,4.0,4,4,Registers
 SGPRs,32.0,32,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/sysinfo.csv
index e7c91d9022..0c74b960d8 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-no_roof_D_str_inv4,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:15:57 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+no_roof_D_str_inv4,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:15:57 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/timestamps.csv
index 9ba608700a..6a62464558 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_str_inv4/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,132113,132113,33554432,256,0,0,4,32,4160,0x0,0x7ffb57004280,15777913694499,15777913720200,15777913958281,15777914067731
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,132113,132113,32768,256,0,0,12,24,13888,0x0,0x7ffb57023f80,15777918723337,15777918739107,15777918752067,15777918771456
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,132113,132113,4194304,256,0,0,12,24,14336,0x7ffb5a03a380,0x7ffb57023fc0,15777918773616,15777918833347,15777918925828,15777918927982
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/SQ_IFETCH_LEVEL.csv
index b778775f7d..e6af42bf6c 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/SQ_IFETCH_LEVEL.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,811046,811051,33554432,256,0,0,8,32,6464,0x0,0x7f2ca6c04180,510121,510121,524288,6291456,798606,102250048,12074177449081248,12074177695741410,12074177696068768,12074177696178810
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/SQ_INST_LEVEL_LDS.csv
index 560ab836af..a668f65997 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/SQ_INST_LEVEL_LDS.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,812842,812847,33554432,256,0,0,8,32,6464,0x0,0x7f51c8804180,0,0,0,12074198866430462,12074199109967051,12074199110292649,12074199110404852
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/SQ_INST_LEVEL_SMEM.csv
index 9381b3538c..26afa83bcd 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/SQ_INST_LEVEL_SMEM.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,812464,812469,33554432,256,0,0,8,32,6464,0x0,0x7fe5a9604180,4194304,3131958,400664368,12074196426731494,12074196668216405,12074196668539443,12074196668651435
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/SQ_INST_LEVEL_VMEM.csv
index 8d61befbd3..6cacdfead4 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/SQ_INST_LEVEL_VMEM.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,812653,812658,33554432,256,0,0,8,32,6464,0x0,0x7f5055e04180,1048576,11117293,1422476032,12074197644587905,12074197887201538,12074197887524416,12074197887633338
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/SQ_LEVEL_WAVES.csv
index 78120b097b..11637ae17d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/SQ_LEVEL_WAVES.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,813033,813038,33554432,256,0,0,8,32,6464,0x0,0x7fd047a04180,501625,501625,18127,4013008,524288,370208999,3805450,0,1495680832,12074200085123368,12074200330985419,12074200331308137,12074200331418369
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/pmc_dispatch_info.csv
index 90cd5504cd..5794a6cd05 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/pmc_dispatch_info.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/pmc_perf.csv
index 1188fc7476..f818842114 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/pmc_perf.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBuffer.kd,0,0,0,811781,811786,33554432,256,0,0,8,32,6464,0x0,0x7f7996a04180,1048576,0,1048576,9437184,0,4194304,1048576,0,505209,505209,57912856,55436605,120,12936101,54652400,54561867,55393568,54214100,4041672,3845310,505209,0,505209,0,16166688,15310017,0,0,0,0,0,17084068,1048576,0,507537,0,0,0,507537,0,0,0,507537,0,0,0,507537,0,0,0,507537,0,0,0,507537,0,0,0,507537,0,0,0,507537,0,0,0,507537,0,0,0,507537,0,0,0,507537,0,0,0,507537,0,0,0,507537,0,0,0,507537,0,0,0,507537,0,0,0,507537,0,0,0,507537,0,0,0,507537,0,0,0,507537,0,0,0,507537,0,0,0,507537,0,0,0,507537,0,0,0,507537,0,0,0,507537,0,0,0,507537,0,0,0,507537,0,0,0,507537,0,0,0,507537,0,0,0,507537,0,0,0,507537,0,0,0,507537,0,0,0,507537,0,0,0,37667314,2619,0,0,0,52,0,0,0,0,0,0,0,0,0,0,0,2742,0,0,0,0,0,0,0,0,0,0,0,48,0,0,0,0,0,0,0,1,0,0,0,2,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,3,0,0,0,0,0,0,0,0,0,0,0,2525,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2621,0,0,0,49,0,0,0,0,0,0,0,0,0,0,0,95,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1048576,0,0,261,131076,131076,0,21452,131076,131076,0,0,131072,131072,0,2980599,131080,131080,0,262,131072,131072,0,0,131072,131072,0,0,131080,131080,0,608158,131084,131084,0,2788081,131076,131076,0,0,131072,131072,0,0,131072,131072,0,0,131072,131072,0,0,131072,131072,0,0,131080,131080,0,0,131076,131076,0,3377225,131076,131076,0,0,131072,131072,0,1041,131072,131072,0,0,131072,131072,0,3340617,131072,131072,0,7137,131080,131080,0,0,131072,131072,0,774,131072,131072,0,0,131076,131076,0,1498,131072,131072,0,0,131072,131072,0,0,131076,131076,0,0,131072,131072,0,0,131072,131072,0,0,131072,131072,0,0,131072,131072,0,0,131072,131072,1048576,0,851,0,0,16847973,1131,0,0,16928687,1082,0,0,17599157,982,0,0,16782030,1253,0,0,17158840,1165,0,0,17222499,749,0,0,18396511,49016,0,0,31467849,795,0,0,17033632,1142,0,0,17047545,1022,0,0,17394216,49349,0,0,29570572,1086,0,0,17082904,1233,0,0,17327517,1099,0,0,18386890,730,0,0,18469332,792,0,0,16458760,936,0,0,16638031,875,0,0,17285923,911,0,0,16653858,797,0,0,17031845,1663,0,0,17401003,1039,0,0,18271634,920,0,0,18056611,1040,0,0,16470977,775,0,0,16806356,1021,0,0,17147183,46227,0,0,29680783,1104,0,0,16935407,845,0,0,17181435,938,0,0,18474652,46882,0,0,30733710,1048576,131072,131072,0,262144,131307,131077,240,262384,131072,131072,0,262144,131072,131072,0,262144,131072,131073,1,262145,131072,131072,0,262144,131072,131072,0,262144,131072,131142,70,262214,131072,131073,1,262145,131072,131072,0,262144,131072,131072,0,262144,131072,133698,2626,264770,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131120,48,262192,131213,133543,2612,264756,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131120,48,262192,131072,131072,0,262144,131072,133843,2771,264915,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,133673,2601,264745,131072,131075,3,262147,131072,131072,0,262144,131119,131073,48,262192,131072,131072,0,262144,262144,0,262144,262336,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262288,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,0,0,3145728,524288,32505856,367469389,217868762,117094771,479292,0,0,0,1048576,52493338,52270847,1048576,1048576,131072,524288,757,502196,4181,0,96,10635,0,8388944,32505856,4011984,3807531,56958719,11534336,0,0,14155776,67108864,67108864,0,67108864,54064921,53671749,0,1048576,225625,749913,11715,2027,0,497150,8399660,0,4194727,4204933,13631488,0,3670016,1048576,1048576,0,4194304,9437184,0,0,360,33554432,54451352,4194304,0,0,2465,505304,0,11159,8388608,0,4194398,905969664,6291456,0,0,0,524288,524288,0,15319,16608820,0,16777216,4194304,4194304,0,0,0,15847,4194424,4194424,0,213282,0,0,0,33554432,0,0,0,0,635590519,0,2791561097,0,0,0,0,0,473130,0,0,215446,0,0,8388608,336,144,0,0,0,480,8388608,0,0,0,0,334349,0,0,0,10587,0,21156,0,6291456,6289149,96,2418,2701095,0,0,0,0,0,0,0,0,0,3145728,0,0,0,151340,4194304,4189857,144,4303,2097152,524288,1572864,0,0,0,0,0,0,524288,0,4128801,65535,4063246,0,0,8388608,0,42438911,0,1048576,10958,4194348,13279405,608840180,12074179532587154,12074201171268642,12074201171594079,12074179774650783
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/prev_analysis/1.csv
index b9c3bd2c7f..24a8331611 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/prev_analysis/1.csv
@@ -1,2 +1,2 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 __amd_rocclr_fillBuffer.kd,1,325437.0,325437.0,325437.0,100.0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/prev_analysis/1001.csv
index 2923ed58d3..25f1221e3b 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,18.0,Instr per wave
 SMEM,8.0,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/prev_analysis/101.csv
index 1b60b24861..35d808e016 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx908
 mi100
 48
 1228.8
-SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/prev_analysis/1202.csv
index 7975a33b7f..4a86a4d967 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,2803.568946838379,2803.568946838379,2803.568946838379,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/prev_analysis/1901.csv
index ce3ebe4817..c5ff210938 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,8.0,smem_
 VALU,22.0,valu_
 MFMA,,mfma_
 VMEM,2.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,6.0,br_
 VGPR,8.0,vgpr_
 SGPR,32.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,524288.0,wavefronts_
 Workgroups,131072.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,12.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,8.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,0.0,hbm_rd_
 HBM Wr,8.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,25.0,vl1_coales_
 VL1 Stall,22.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,30.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/prev_analysis/2001.csv
index 90cd5504cd..5794a6cd05 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/prev_analysis/2001.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/prev_analysis/201.csv
index 0d68862ad9..c188d917e1 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,23.349702796268474,Pct,100,23.349702796268474
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,64.0,Threads,64,100.0
 IPC - Issue,0.9193548387096774,Instr/cycle,5,18.387096774193548
-LDS BW,0.0,Gb/sec,23070.72,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,23070.72,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99847358466715,Pct,100,99.99847358466715
 Instr Cache BW,1237.2692226145152,Gb/s,4614.144,26.81470761672187
 Scalar L1D Cache Hit Rate,99.99656324664362,Pct,100,99.99656324664362
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/prev_analysis/602.csv
index 36627e8083..5ec6f8faa1 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,0.0,0,0,Simd
 Insufficient SIMD VGPRs,0.0,0,0,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/prev_analysis/701.csv
index ebf5f22ba4..1d3a71c87a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,8.0,8,8,Registers
 SGPRs,32.0,32,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/sysinfo.csv
index 64327da12a..c921232d09 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-no_roof_D_val_int,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 10:55:47 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+no_roof_D_val_int,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 10:55:47 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/timestamps.csv
index 6d77f44a2b..5629d45021 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,813082,813087,33554432,256,0,0,8,32,6464,0x0,0x7f8056804180,12074201171219545,12074201171268642,12074201171594079,12074201171679780
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,813082,813087,32768,256,0,0,24,24,12480,0x0,0x7f8056835100,12074201186479149,12074201186579536,12074201186586256,12074201186589494
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,813082,813087,4194304,256,0,0,24,24,12928,0x7f8186940900,0x7f8056835140,12074201186623207,12074201186636816,12074201186767374,12074201186770220
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/SQ_IFETCH_LEVEL.csv
index 2c167f0036..435343114d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/SQ_IFETCH_LEVEL.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,87465,87465,33554432,256,0,0,4,32,4160,0x0,0x7f0c96c04280,383190,383190,524288,4718592,681166,76280988,15101578670562,15100821223585,15101731636498,15101731725798
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/SQ_INST_LEVEL_LDS.csv
index bb17655812..873df7613e 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/SQ_INST_LEVEL_LDS.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,89317,89317,33554432,256,0,0,4,32,4160,0x0,0x7f8ee9804280,0,0,0,15116103381438,15115346785094,15116254071116,15116254162375
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/SQ_INST_LEVEL_SMEM.csv
index be8aa39a24..d710a10ced 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/SQ_INST_LEVEL_SMEM.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,87242,87242,33554432,256,0,0,4,32,4160,0x0,0x7fa127004280,3670016,2777554,310942112,15100672539128,15072624448104,15100821223166,15100821302056
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/SQ_INST_LEVEL_VMEM.csv
index f7bf6c3bbc..c7178751c6 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/SQ_INST_LEVEL_VMEM.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,89094,89094,33554432,256,0,0,4,32,4160,0x0,0x7f5bfc204280,524288,5328751,596775548,15115198877346,15114199144494,15115346784689,15115346899639
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/SQ_LEVEL_WAVES.csv
index ed037eba32..e1d054cb1e 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/SQ_LEVEL_WAVES.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,87688,87688,33554432,256,0,0,4,32,4160,0x0,0x7fc0f5004280,382484,382484,8932,3059880,524288,241272021,2971889,0,981319076,15102485596401,15101731636256,15102640493551,15102640607760
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/pmc_dispatch_info.csv
index 8226fe9c0f..63bb17b9f9 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/pmc_dispatch_info.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/pmc_perf.csv
index 5914f34546..df9f3dca76 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/pmc_perf.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDI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],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBufferAligned.kd,0,0,0,88455,88455,33554432,256,0,0,4,32,4160,0x0,0x7fe304604280,3122752,3036808,524288,39455836,248386473,392,224,0,390343,390343,39720829.0,38533317.0,8.0,4218837.0,31679834.0,31319613.0,38520620.0,37964235.0,3121041,3043213,390343,0,390343,0,12490976.0,9432327.0,0.0,0.0,0,0,616,0,4718592,4714382,112,4098,375699,0.0,0.0,0.0,524288.0,28623006.0,27890953.0,7784.0,524288.0,131072,524288,302,384763,2312,0,56.0,304.0,0.0,4194696.0,0,0,0,0,0,7340032,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,20144401.0,524288.0,0,384052,0,0,0,384052,0,0,0,384052,0,0,0,384052,0,0,0,384052,0,0,0,384052,0,0,0,384052,0,0,0,384052,0,0,0,384052,0,0,0,384052,0,0,0,384052,0,0,0,384052,0,0,0,384052,0,0,0,384052,0,0,0,384052,0,0,0,384052,0,0,0,384052,0,0,0,384052,0,0,0,384052,0,0,0,384052,0,0,0,384052,0,0,0,384052,0,0,0,384052,0,0,0,384052,0,0,0,384052,0,0,0,384052,0,0,0,384052,0,0,0,384052,0,0,0,384052,0,0,0,384052,0,0,0,384052,0,0,0,384052,0,0,0,0,0,0.0,21070354.0,1,0,0,0,0,0,0,0,33,0,0,0,0,0,0,0,2,0,0,0,0,0,0,0,0,0,0,0,56,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,32,0,0,0,1,0,0,0,4,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,144,0,0,0,0,0,0,0,1,0,0,0,524288.0,0.0,0,43491,129024,129024,0,0,129024,129024,0,0,129024,129024,0,217850,129024,129024,0,331,129024,129024,0,281061,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,44451,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,27455,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,883,129024,129024,0,506,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,45673,129024,129024,0,0,129024,129024,0,0,129024,129024,0,840,129024,129024,0,186,129024,129024,524288.0,0.0,43653,0,0,50263291,45424,0,0,50571954,44110,0,0,49892018,46828,0,0,51708108,44719,0,0,51125836,45422,0,0,51032570,44064,0,0,50404342,47484,0,0,52592542,44983,0,0,50669674,46145,0,0,50624141,46067,0,0,50576775,48302,0,0,52304887,45760,0,0,51392147,47325,0,0,51547478,44972,0,0,50678608,49139,0,0,52997970,44161,0,0,50301193,44909,0,0,50422266,43577,0,0,49964263,48023,0,0,52160825,44432,0,0,50884789,44508,0,0,50826296,44092,0,0,50527496,47756,0,0,52725157,45943,0,0,50836864,46307,0,0,50831761,45759,0,0,50318733,47529,0,0,51995077,45938,0,0,51334930,46707,0,0,51492994,45431,0,0,51049302,49629,0,0,53140826,0.0,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65571,35,131107,65646,65594,168,131240,65536,65536,0,131072,65536,65536,0,131072,65536,65537,1,131073,65536,65536,0,131072,65536,65648,112,131184,65536,65536,0,131072,65536,65536,0,131072,65536,65568,32,131104,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65591,65537,56,131128,65536,65537,1,131073,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65570,34,131106,65758,65538,224,131296,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65568,32,131104,65591,65537,56,131128,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131184,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131296,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131128,0,131072,1056842,0,524288,3670016,3663358,224,6434,1048576,33554432.0,33554432.0,0.0,33554432.0,29979935.0,28336900.0,0.0,524288.0,213246,536861,8676,887,0,381444,4195053.0,0.0,2097594.0,2097459.0,1048576,1048576,0,524288,0,524288,7340032,0,0.0,0.0,104.0,8388608.0,29690665.0,2097152.0,0.0,206899,0,1215,384651,0,751.0,4194304.0,0.0,2064387.0,25690112,9437184,0,0,0,0,0,0,13312.0,8242176.0,0.0,8388608.0,2097152.0,4194304.0,9868150,0,0,8841,4128768.0,4128768.0,0.0,1477311.0,0,0,0,0,0,0,5767168,1048576,316115512.0,0.0,1473479243.0,0.0,47.0,0.0,0,0,372821,0.0,0.0,1496967.0,0.0,3670016,524288,0,0,0,2621440,524288,177996540,4194304.0,0.0,0.0,0.0,0.0,1224823.0,0,0,0.0,311.0,0.0,606.0,41708399,24117248,0,0,9437184,11010048,0,3145728,0.0,0.0,0.0,0.0,0.0,0.0,0,1572864,0.0,0.0,0.0,188056.0,524288,524288,0,3670016,7340032,603979776,4718592,0,0.0,0.0,0.0,0.0,0.0,0.0,524288,0,2064384.0,0.0,2031624.0,0.0,0,0,524288,0,0,0,0,33554432,0.0,4194304.0,0.0,19013889.0,0.0,0.0,143.0,4128768.0,963951.0,1658661139.0,15103879661841,15116856248425,15116856489226,15104032257649
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/prev_analysis/1.csv
index 955a3d9ff2..13d3d96a4b 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/prev_analysis/1.csv
@@ -1,2 +1,2 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 __amd_rocclr_fillBufferAligned.kd,1,240801.0,240801.0,240801.0,100.0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/prev_analysis/1001.csv
index e34ed0c6f6..0850fc4acd 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,18.0,Instr per wave
 VMEM,1.0,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,0.0,Instr per wave
 SALU,14.0,Instr per wave
 SMEM,7.0,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/prev_analysis/101.csv
index bdf2853073..aa01d34466 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx90a
 mi200
 56
 1638.4
-SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/prev_analysis/1202.csv
index 560db02faa..3130fa453b 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,1895.0383987426758,1895.0383987426758,1895.0383987426758,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/prev_analysis/1901.csv
index 351b8e2350..9d34b59229 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,7.0,smem_
 VALU,18.0,valu_
 MFMA,0.0,mfma_
 VMEM,1.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,5.0,br_
 VGPR,4.0,vgpr_
 SGPR,32.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,524288.0,wavefronts_
 Workgroups,131072.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,9.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,8.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,0.0,hbm_rd_
 HBM Wr,8.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,25.0,vl1_coales_
 VL1 Stall,11.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,25.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/prev_analysis/2001.csv
index 8226fe9c0f..63bb17b9f9 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/prev_analysis/2001.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/prev_analysis/201.csv
index 23646660aa..98b34bfe81 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,23.246773695481625,Pct,100,23.246773695481625
 MFMA Util,0.0,Pct,100,0.0
 VALU Active Threads/Wave,64.0,Threads,64,100.0
 IPC - Issue,1.0,Instr/cycle,5,20.0
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.9976243473849,Pct,100,99.9976243473849
 Instr Cache BW,1254.1056224849565,Gb/s,6092.8,20.58340373038597
 Scalar L1D Cache Hit Rate,99.99388576535205,Pct,100,99.99388576535205
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/prev_analysis/602.csv
index 8961b9a879..854ade6003 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,9868150.0,9868150,9868150,Simd
 Insufficient SIMD VGPRs,0.0,0,0,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/prev_analysis/701.csv
index c47e77a25f..f8ed8cd0d3 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,4.0,4,4,Registers
 SGPRs,32.0,32,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/sysinfo.csv
index 2090b35f70..574540ab64 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-no_roof_D_val_int,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:04:56 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+no_roof_D_val_int,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:04:56 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/timestamps.csv
index 69aeec1626..298f99dc78 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,89400,89400,33554432,256,0,0,4,32,4160,0x0,0x7f07c3004280,15116856221575,15116856248425,15116856489226,15116856600766
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,89400,89400,32768,256,0,0,12,24,13888,0x0,0x7f07c3023f80,15116861274745,15116861290681,15116861304121,15116861320974
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,89400,89400,4194304,256,0,0,12,24,14336,0x7f07c60f9380,0x7f07c3023fc0,15116861328084,15116861370842,15116861463322,15116861465261
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/SQ_IFETCH_LEVEL.csv
index 4191407f66..9c4c44f13e 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/SQ_IFETCH_LEVEL.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,816052,816057,33554432,256,0,0,8,32,6464,0x0,0x7f78ad804180,504665,504665,524288,6291456,793331,101462592,12074257930609228,12074258174563838,12074258174888636,12074258174998619
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/SQ_INST_LEVEL_LDS.csv
index 4c2cc49c45..71777a147e 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/SQ_INST_LEVEL_LDS.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,817849,817854,33554432,256,0,0,8,32,6464,0x0,0x7f83cac04180,0,0,0,12074279377145415,12074279620165558,12074279620490517,12074279620600419
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/SQ_INST_LEVEL_SMEM.csv
index 650287d8e1..a8c5c46e5b 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/SQ_INST_LEVEL_SMEM.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,817470,817475,33554432,256,0,0,8,32,6464,0x0,0x7fb56f004180,4194304,3220464,412218072,12074276930286482,12074277173712598,12074277174038996,12074277174145868
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/SQ_INST_LEVEL_VMEM.csv
index f1be33cff9..05e28bfe66 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/SQ_INST_LEVEL_VMEM.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,817660,817665,33554432,256,0,0,8,32,6464,0x0,0x7f8428204180,1048576,11066119,1416775368,12074278154459019,12074278399375875,12074278399699554,12074278399793937
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/SQ_LEVEL_WAVES.csv
index 189205c802..a9b36ec9a6 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/SQ_LEVEL_WAVES.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,818040,818045,33554432,256,0,0,8,32,6464,0x0,0x7f5078204180,501785,501785,17172,4014288,524288,371058089,3806462,0,1499049932,12074280593792599,12074280841115955,12074280841438833,12074280841548816
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/pmc_dispatch_info.csv
index 90cd5504cd..5794a6cd05 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/pmc_dispatch_info.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/pmc_perf.csv
index 02db01be8b..14ed235b32 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/pmc_perf.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBuffer.kd,0,0,0,816787,816792,33554432,256,0,0,8,32,6464,0x0,0x7f4866804180,1048576,0,1048576,9437184,0,4194304,1048576,0,500385,500385,57416655,55215804,118,12520089,54480343,54385234,55188480,54020859,4003080,3812234,500385,0,500385,0,16012320,15155452,0,0,0,0,0,17451314,1048576,0,505537,0,0,0,505537,0,0,0,505537,0,0,0,505537,0,0,0,505537,0,0,0,505537,0,0,0,505537,0,0,0,505537,0,0,0,505537,0,0,0,505537,0,0,0,505537,0,0,0,505537,0,0,0,505537,0,0,0,505537,0,0,0,505537,0,0,0,505537,0,0,0,505537,0,0,0,505537,0,0,0,505537,0,0,0,505537,0,0,0,505537,0,0,0,505537,0,0,0,505537,0,0,0,505537,0,0,0,505537,0,0,0,505537,0,0,0,505537,0,0,0,505537,0,0,0,505537,0,0,0,505537,0,0,0,505537,0,0,0,505537,0,0,0,37509850,1,0,0,0,52,0,0,0,0,0,0,0,2516,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2528,0,0,0,0,0,0,0,3,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,2687,0,0,0,0,0,0,0,4,0,0,0,0,0,0,0,2768,0,0,0,69,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1048576,0,0,13782,131076,131076,0,2984479,131076,131076,0,0,131076,131076,0,0,131076,131076,0,0,131076,131076,0,0,131072,131072,0,0,131076,131076,0,0,131072,131072,0,0,131072,131072,0,0,131073,131073,0,1441,131072,131072,0,0,131072,131072,0,0,131072,131072,0,3056390,131076,131076,0,0,131072,131072,0,0,131072,131072,0,0,131072,131072,0,3037137,131076,131076,0,26577,131072,131072,0,0,131072,131072,0,0,131072,131072,0,260,131076,131076,0,0,131076,131076,0,6975,131072,131072,0,0,131072,131072,0,0,131072,131072,0,558898,131080,131080,0,0,131072,131072,0,0,131072,131072,0,3331843,131072,131072,0,0,131076,131076,0,0,131072,131072,1048576,0,1146,0,0,16797581,1562,0,0,17176758,1162,0,0,17637684,42875,0,0,29080042,1128,0,0,17172467,1129,0,0,17419106,1022,0,0,18412396,48833,0,0,31673739,762,0,0,16828875,1721,0,0,17370865,1100,0,0,17123486,907,0,0,16849502,1740,0,0,17157875,947,0,0,17428075,1123,0,0,18320462,825,0,0,18466130,1635,0,0,16665158,910,0,0,16796146,1608,0,0,17277545,1665,0,0,16977137,1580,0,0,17164993,1123,0,0,17474497,808,0,0,18278017,1346,0,0,18454309,1762,0,0,16698275,777,0,0,16681856,847,0,0,17175661,46194,0,0,29473228,1621,0,0,16886015,1856,0,0,17465349,792,0,0,18128021,46251,0,0,31222761,1048576,131072,131072,0,262144,131260,131076,192,262336,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131120,48,262192,131072,131072,0,262144,131072,131270,198,262342,131072,131072,0,262144,131072,131072,0,262144,131072,131073,1,262145,131119,133812,2787,264931,131072,131072,0,262144,131072,131072,0,262144,131072,131075,3,262147,131072,131072,0,262144,131072,131072,0,262144,131213,133367,2436,264580,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131120,48,262192,131072,133745,2673,264817,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,133793,2721,264865,131072,131072,0,262144,131072,131072,0,262144,131119,131074,49,262193,131072,131072,0,262144,262144,0,262144,262336,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262288,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,0,0,3145728,524288,32505856,365413943,218109099,114798988,481468,0,0,0,1048576,52176389,51920569,1048576,1048576,131072,524288,705,504072,4396,0,96,10528,0,8388944,32505856,4024912,3816995,57092017,11534336,0,0,14155776,67108864,67108864,0,67108864,54184165,53842468,0,1048576,233761,758049,11765,2425,0,498844,8399652,0,4194727,4204925,13631488,0,3670016,1048576,1048576,0,4194304,9437184,0,0,360,33554432,54045652,4194304,0,0,3178,500103,0,11080,8388608,0,4194374,905969664,6291456,0,0,0,524288,524288,0,15326,16608730,0,16777216,4194304,4194304,0,0,0,16732,4194404,4194404,0,213537,0,0,0,33554432,0,0,0,0,627759198,0,2758352724,0,0,0,0,0,473232,0,0,214556,0,0,8388608,336,144,0,0,0,480,8388608,0,0,0,0,357708,0,0,0,10575,0,21132,0,6291456,6289172,96,2836,1782607,0,0,0,0,0,0,0,0,0,3145728,0,0,0,159766,4194304,4189931,144,4229,2097152,524288,1572864,0,0,0,0,0,0,524288,0,4128824,65528,4063254,0,0,8388608,0,42156251,0,1048576,10785,4194392,13360230,609331320,12074260021265170,12074281682254472,12074281682577189,12074260268779868
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/prev_analysis/1.csv
index d363351d8e..89e8a86dea 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/prev_analysis/1.csv
@@ -1,2 +1,2 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 __amd_rocclr_fillBuffer.kd,1,322717.0,322717.0,322717.0,100.0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/prev_analysis/1001.csv
index 2923ed58d3..25f1221e3b 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,18.0,Instr per wave
 SMEM,8.0,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/prev_analysis/101.csv
index 82a43c33f2..53b6971c6f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx908
 mi100
 48
 1228.8
-SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/prev_analysis/1202.csv
index b527f67690..9d1d6b0479 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,2787.887138366699,2787.887138366699,2787.887138366699,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/prev_analysis/1901.csv
index eb629b067c..48fa1fe486 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,8.0,smem_
 VALU,22.0,valu_
 MFMA,,mfma_
 VMEM,2.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,6.0,br_
 VGPR,8.0,vgpr_
 SGPR,32.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,524288.0,wavefronts_
 Workgroups,131072.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,12.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,8.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,0.0,hbm_rd_
 HBM Wr,8.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,25.0,vl1_coales_
 VL1 Stall,22.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,30.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/prev_analysis/2001.csv
index 90cd5504cd..5794a6cd05 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/prev_analysis/2001.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/prev_analysis/201.csv
index 0217aab2e5..3adceb5d2b 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,23.574807398303307,Pct,100,23.574807398303307
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,64.0,Threads,64,100.0
 IPC - Issue,0.9193548387096774,Instr/cycle,5,18.387096774193548
-LDS BW,0.0,Gb/sec,23070.72,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,23070.72,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99847359024929,Pct,100,99.99847359024929
 Instr Cache BW,1247.697468679989,Gb/s,4614.144,27.04071369857527
 Scalar L1D Cache Hit Rate,99.99656330733937,Pct,100,99.99656330733937
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/prev_analysis/602.csv
index 21593424dc..7e088c1cb9 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,0.0,0,0,Simd
 Insufficient SIMD VGPRs,0.0,0,0,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/prev_analysis/701.csv
index ebf5f22ba4..1d3a71c87a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,8.0,8,8,Registers
 SGPRs,32.0,32,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/sysinfo.csv
index ae065138a9..a0645a5414 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-no_roof_D_val_int2,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 10:57:07 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+no_roof_D_val_int2,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 10:57:07 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/timestamps.csv
index 9e1f4e61bd..d517840510 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,818089,818094,33554432,256,0,0,8,32,6464,0x0,0x7f0ff9604180,12074281682207124,12074281682254472,12074281682577189,12074281682684501
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,818089,818094,32768,256,0,0,24,24,12480,0x0,0x7f0ff9635100,12074281697596990,12074281697709013,12074281697715413,12074281697720760
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,818089,818094,4194304,256,0,0,24,24,12928,0x7f1105234900,0x7f0ff9635140,12074281697766375,12074281697779573,12074281697911732,12074281697915312
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/SQ_IFETCH_LEVEL.csv
index 675527af98..f43a4e6dee 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/SQ_IFETCH_LEVEL.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,93567,93567,33554432,256,0,0,4,32,4160,0x0,0x7fed94604280,380464,380464,524288,4718592,682161,76483404,15197290724316,15196535725945,15197439505579,15197439622389
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/SQ_INST_LEVEL_LDS.csv
index 85fdeaf7ae..2612f08591 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/SQ_INST_LEVEL_LDS.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,95419,95419,33554432,256,0,0,4,32,4160,0x0,0x7f6a44604280,0,0,0,15211782451385,15211058540663,15211933102951,15211933215221
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/SQ_INST_LEVEL_SMEM.csv
index 1a7d565f52..29a87c1cbc 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/SQ_INST_LEVEL_SMEM.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,93344,93344,33554432,256,0,0,4,32,4160,0x0,0x7f25c8e04280,3670016,2905684,325597368,15196387174775,15168358636089,15196535725943,15196535842233
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/SQ_INST_LEVEL_VMEM.csv
index 6b87b5ac7e..a8fe86912d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/SQ_INST_LEVEL_VMEM.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,95196,95196,33554432,256,0,0,4,32,4160,0x0,0x7f12a0804280,524288,5513780,617513264,15210909416378,15209907886533,15211058541100,15211058655220
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/SQ_LEVEL_WAVES.csv
index dbaee2e012..559fe08be0 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/SQ_LEVEL_WAVES.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,93790,93790,33554432,256,0,0,4,32,4160,0x0,0x7f3703004280,380685,380685,8904,3045488,524288,238849213,2957524,0,971651960,15198196980356,15197439505504,15198347905050,15198348017380
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/pmc_dispatch_info.csv
index 8226fe9c0f..63bb17b9f9 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/pmc_dispatch_info.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/pmc_perf.csv
index 7cdcc378f6..cc8244c0d8 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/pmc_perf.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDI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],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBufferAligned.kd,0,0,0,94557,94557,33554432,256,0,0,4,32,4160,0x0,0x7f79d9204280,3078800,2991257,524288,38864259,243322824,392,224,0,384849,384849,39128419.0,38189671.0,1.0,4123723.0,31359650.0,30995990.0,38168525.0,37608926.0,3077089,2997659,384849,0,384849,0,12315168.0,9422582.0,0.0,0.0,0,0,616,0,4718592,4714903,112,3577,374810,0.0,0.0,0.0,524288.0,28510422.0,27780998.0,7830.0,524288.0,131072,524288,302,384301,2613,0,56.0,300.0,0.0,4194696.0,0,0,0,0,0,7340032,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,20034939.0,524288.0,0,382879,0,0,0,382879,0,0,0,382879,0,0,0,382879,0,0,0,382879,0,0,0,382879,0,0,0,382879,0,0,0,382879,0,0,0,382879,0,0,0,382879,0,0,0,382879,0,0,0,382879,0,0,0,382879,0,0,0,382879,0,0,0,382879,0,0,0,382879,0,0,0,382879,0,0,0,382879,0,0,0,382879,0,0,0,382879,0,0,0,382879,0,0,0,382879,0,0,0,382879,0,0,0,382879,0,0,0,382879,0,0,0,382879,0,0,0,382879,0,0,0,382879,0,0,0,382879,0,0,0,382879,0,0,0,382879,0,0,0,382879,0,0,0,0,0,0.0,21191258.0,32,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,112,0,0,0,32,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,91,0,0,0,2,0,0,0,0,0,0,0,0,0,0,0,4,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,32,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,524288.0,0.0,0,43558,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,327,129024,129024,0,168,129024,129024,0,0,129024,129024,0,0,129024,129024,0,544578,129024,129024,0,44392,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,273188,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,165,129024,129024,0,29302,129024,129024,0,0,129024,129024,0,363,129024,129024,0,169,129024,129024,0,881,129024,129024,0,0,129024,129024,0,0,129024,129024,0,861,129024,129024,0,0,129024,129024,0,45338,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,185,129024,129024,524288.0,0.0,44030,0,0,50332510,44727,0,0,50227226,44944,0,0,50147500,47029,0,0,51706316,45135,0,0,51267951,45171,0,0,51388322,45319,0,0,50724308,47360,0,0,52488650,45407,0,0,50690081,47479,0,0,51403331,45079,0,0,50137604,48137,0,0,52252069,45742,0,0,51318460,46913,0,0,51662345,45938,0,0,51045171,48240,0,0,52913727,43103,0,0,50052876,45269,0,0,50479423,43905,0,0,50008329,47948,0,0,52257848,43992,0,0,50890028,46539,0,0,51512847,44661,0,0,50637845,49073,0,0,53067383,45447,0,0,50832348,46551,0,0,51074235,45651,0,0,50358102,48629,0,0,52146208,47447,0,0,52103387,48430,0,0,52187000,47067,0,0,51292734,48584,0,0,53002912,0.0,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65568,32,131104,65646,65538,112,131184,65536,65537,1,131073,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65648,112,131184,65536,65568,32,131104,65536,65536,0,131072,65536,65536,0,131072,65591,65537,56,131128,65536,65536,0,131072,65536,65536,0,131072,65536,65537,1,131073,65536,65536,0,131072,65536,65593,57,131129,65536,65572,36,131108,65758,65538,224,131296,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65568,32,131104,65591,65537,56,131128,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131184,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131296,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131128,0,131072,1141815,0,524288,3670016,3663230,224,6562,1048576,33554432.0,33554432.0,0.0,33554432.0,30087665.0,28446601.0,0.0,524288.0,217718,537240,8348,1024,0,383104,4195056.0,0.0,2097594.0,2097462.0,1048576,1048576,0,524288,0,524288,7340032,0,0.0,0.0,104.0,8388608.0,29444797.0,2097152.0,0.0,200541,0,1223,382025,0,750.0,4194304.0,0.0,2064387.0,25690112,9437184,0,0,0,0,0,0,13276.0,8242572.0,0.0,8388608.0,2097152.0,4194304.0,9682030,0,0,9261,4128768.0,4128768.0,0.0,1480074.0,0,0,0,0,0,0,5767168,1048576,315908019.0,0.0,1471958497.0,0.0,56.0,0.0,0,0,374208,0.0,0.0,1484073.0,0.0,3670016,524288,0,0,0,2621440,524288,176710561,4194304.0,0.0,0.0,0.0,0.0,1212921.0,0,0,0.0,310.0,0.0,604.0,42322090,24117248,0,0,9437184,11010048,0,3145728,0.0,0.0,0.0,0.0,0.0,0.0,0,1572864,0.0,0.0,0.0,193239.0,524288,524288,0,3670016,7340032,603979776,4718592,0,0.0,0.0,0.0,0.0,0.0,0.0,524288,0,2064384.0,0.0,2031623.0,0.0,0,0,524288,0,0,0,0,33554432,0.0,4194304.0,0.0,19111406.0,0.0,0.0,141.0,4128768.0,1000404.0,1644890571.0,15199592145131,15212563457302,15212563696663,15199739506521
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/prev_analysis/1.csv
index 68e829eeff..94da4b5565 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/prev_analysis/1.csv
@@ -1,2 +1,2 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 __amd_rocclr_fillBufferAligned.kd,1,239361.0,239361.0,239361.0,100.0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/prev_analysis/1001.csv
index e34ed0c6f6..0850fc4acd 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,18.0,Instr per wave
 VMEM,1.0,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,0.0,Instr per wave
 SALU,14.0,Instr per wave
 SMEM,7.0,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/prev_analysis/101.csv
index 52e8f8bf3d..fcbadf3e12 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx90a
 mi200
 56
 1638.4
-SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/prev_analysis/1202.csv
index eb6ad47dd5..9485a4e0ec 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,1856.4058227539062,1856.4058227539062,1856.4058227539062,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/prev_analysis/1901.csv
index 9eeda1c1e0..9c02b5b654 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,7.0,smem_
 VALU,18.0,valu_
 MFMA,0.0,mfma_
 VMEM,1.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,5.0,br_
 VGPR,4.0,vgpr_
 SGPR,32.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,524288.0,wavefronts_
 Workgroups,131072.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,9.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,8.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,0.0,hbm_rd_
 HBM Wr,8.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,25.0,vl1_coales_
 VL1 Stall,11.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,25.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/prev_analysis/2001.csv
index 8226fe9c0f..63bb17b9f9 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/prev_analysis/2001.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/prev_analysis/201.csv
index 77975de9b6..f2fc8af2e8 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,23.578638335075276,Pct,100,23.578638335075276
 MFMA Util,0.0,Pct,100,0.0
 VALU Active Threads/Wave,64.0,Threads,64,100.0
 IPC - Issue,1.0,Instr/cycle,5,20.0
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.9976246098899,Pct,100,99.9976246098899
 Instr Cache BW,1261.6503440410092,Gb/s,6092.8,20.70723385046299
 Scalar L1D Cache Hit Rate,99.9938855517225,Pct,100,99.9938855517225
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/prev_analysis/602.csv
index e8774db230..3ace87bdf0 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,9682030.0,9682030,9682030,Simd
 Insufficient SIMD VGPRs,0.0,0,0,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/prev_analysis/701.csv
index c47e77a25f..f8ed8cd0d3 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,4.0,4,4,Registers
 SGPRs,32.0,32,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/sysinfo.csv
index 7c510b271e..84046d4715 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-no_roof_D_val_int2,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:06:31 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+no_roof_D_val_int2,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:06:31 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/timestamps.csv
index 344d2ace5b..182d4e4b1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_D_val_int2/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,95502,95502,33554432,256,0,0,4,32,4160,0x0,0x7f75bb004280,15212563431061,15212563457302,15212563696663,15212563783953
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,95502,95502,32768,256,0,0,12,24,13888,0x0,0x7f75bb023f80,15212568497522,15212568513158,15212568526598,15212568544131
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,95502,95502,4194304,256,0,0,12,24,14336,0x7f75be0eb380,0x7f75bb023fc0,15212568549181,15212568597318,15212568689958,15212568691937
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/SQ_IFETCH_LEVEL.csv
index 70899b8395..208046503c 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/SQ_IFETCH_LEVEL.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,755932,755937,33554432,256,0,0,8,32,6464,0x0,0x7f6350a04180,501385,501385,524288,6291456,792776,101387900,12073296106305438,12073296353748903,12073296354070661,12073296354180763
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,755932,755937,32768,256,0,0,24,24,12480,0x0,0x7f6350a35100,28418,28418,512,8192,8704,1113164,12073296368774149,12073296369105020,12073296369111420,12073296369120523
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,755932,755937,4194304,256,0,0,24,24,12928,0x7f645c6d3900,0x7f6350a35140,224043,224043,65536,917504,140299,17957892,12073296369180594,12073296369413339,12073296369550778,12073296369554990
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/SQ_INST_LEVEL_LDS.csv
index 6f309818ad..7e937c986f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/SQ_INST_LEVEL_LDS.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,757728,757733,33554432,256,0,0,8,32,6464,0x0,0x7f5f1e804180,0,0,0,12073322403671812,12073322648150746,12073322648474265,12073322648565718
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,757728,757733,32768,256,0,0,24,24,12480,0x0,0x7f5f1e835100,0,0,0,12073322662967688,12073322663283395,12073322663289475,12073322663294936
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,757728,757733,4194304,256,0,0,24,24,12928,0x7f602a408900,0x7f5f1e835140,0,0,0,12073322663363423,12073322663572834,12073322663711073,12073322663714957
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/SQ_INST_LEVEL_SMEM.csv
index 3927a2f6f2..4db9ba63fc 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/SQ_INST_LEVEL_SMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,757350,757355,33554432,256,0,0,8,32,6464,0x0,0x7f1bcd404180,4194304,3146572,402506232,12073319881536439,12073320129458315,12073320129781033,12073320129902446
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,757350,757355,32768,256,0,0,24,24,12480,0x0,0x7f1bcd435100,512,22220,2845384,12073320144256057,12073320144558077,12073320144564797,12073320144570330
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,757350,757355,4194304,256,0,0,24,24,12928,0x7f1cd8fae900,0x7f1bcd435140,65536,172804,22106112,12073320144634440,12073320144849115,12073320144981755,12073320144986293
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/SQ_INST_LEVEL_VMEM.csv
index 34f79b5808..6584b94133 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/SQ_INST_LEVEL_VMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,757540,757545,33554432,256,0,0,8,32,6464,0x0,0x7fbc36004180,1048576,11130298,1424579952,12073321140149730,12073321386458195,12073321386781073,12073321386889055
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,757540,757545,32768,256,0,0,24,24,12480,0x0,0x7fbc36035100,4096,105724,13510384,12073321401287929,12073321401580399,12073321401586959,12073321401592666
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,757540,757545,4194304,256,0,0,24,24,12928,0x7fbd41d40900,0x7fbc36035140,524288,10368054,1327167128,12073321401655021,12073321401871117,12073321402009836,12073321402014089
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/SQ_LEVEL_WAVES.csv
index 934dee6a5a..2c20db709d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/SQ_LEVEL_WAVES.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,757917,757924,33554432,256,0,0,8,32,6464,0x0,0x7f4356004180,506807,506807,15879,4054464,524288,370859234,3851936,0,1498228064,12073323655347483,12073323902796259,12073323903122497,12073323903234730
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,757917,757924,32768,256,0,0,24,24,12480,0x0,0x7f4356035100,27237,27237,19908,217904,512,1128290,75411,0,4527404,12073323917579825,12073323917905060,12073323917911140,12073323917920027
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,757917,757924,4194304,256,0,0,24,24,12928,0x7f4461b92900,0x7f4356035140,216604,216604,21170,1732840,65536,145951834,1566234,0,585622068,12073323917984507,12073323918234659,12073323918366498,12073323918370534
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/pmc_dispatch_info.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/pmc_perf.csv
index ace73702c3..3355cd813e 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBuffer.kd,0,0,0,756666,756671,33554432,256,0,0,8,32,6464,0x0,0x7f6864e04180,1048576,0,1048576,9437184,0,4194304,1048576,0,504524,504524,57917379,55512046,171,11879439,54587228,54474309,55459192,54284818,4036192,3845614,504524,0,504524,0,16144768,15287721,0,0,0,0,0,17065508,1048576,0,500966,0,0,0,500966,0,0,0,500966,0,0,0,500966,0,0,0,500966,0,0,0,500966,0,0,0,500966,0,0,0,500966,0,0,0,500966,0,0,0,500966,0,0,0,500966,0,0,0,500966,0,0,0,500966,0,0,0,500966,0,0,0,500966,0,0,0,500966,0,0,0,500966,0,0,0,500966,0,0,0,500966,0,0,0,500966,0,0,0,500966,0,0,0,500966,0,0,0,500966,0,0,0,500966,0,0,0,500966,0,0,0,500966,0,0,0,500966,0,0,0,500966,0,0,0,500966,0,0,0,500966,0,0,0,500966,0,0,0,500966,0,0,0,37545346,1,0,0,0,52,0,0,0,0,0,0,0,0,0,0,0,2723,0,0,0,48,0,0,0,1,0,0,0,1,0,0,0,2688,0,0,0,0,0,0,0,0,0,0,0,48,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,2400,0,0,0,0,0,0,0,3,0,0,0,0,0,0,0,0,0,0,0,2722,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,57,0,0,0,0,0,0,0,2,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1048576,0,0,0,131072,131072,0,21452,131076,131076,0,0,131072,131072,0,0,131072,131072,0,3005306,131072,131072,0,0,131072,131072,0,0,131076,131076,0,0,131072,131072,0,3195546,131083,131083,0,0,131072,131072,0,2264,131072,131072,0,259,131072,131072,0,0,131072,131072,0,0,131072,131072,0,0,131076,131076,0,3350998,131076,131076,0,0,131072,131072,0,794,131072,131072,0,0,131076,131076,0,0,131076,131076,0,3111638,131072,131072,0,0,131072,131072,0,0,131072,131072,0,0,131072,131072,0,6100,131072,131072,0,0,131076,131076,0,538369,131072,131072,0,0,131076,131076,0,0,131072,131072,0,0,131072,131072,0,0,131072,131072,0,0,131076,131076,1048576,0,1704,0,0,17297061,999,0,0,17330933,1054,0,0,17125212,852,0,0,17249793,45138,0,0,30060112,876,0,0,17356383,1175,0,0,17990912,1857,0,0,18844237,45378,0,0,29893746,1472,0,0,17429145,890,0,0,17107001,1465,0,0,17236587,1167,0,0,17208870,1179,0,0,17532750,947,0,0,17807845,1199,0,0,18709517,1206,0,0,16608194,936,0,0,17092000,795,0,0,16833680,642,0,0,17109217,49168,0,0,30198520,1139,0,0,17360468,941,0,0,17959176,764,0,0,18415237,45100,0,0,28841374,1207,0,0,17027968,1652,0,0,16968875,1349,0,0,17100852,770,0,0,17288244,1464,0,0,17411248,802,0,0,18018992,1726,0,0,18809888,1048576,131072,131072,0,262144,131260,131076,192,262336,131119,131073,48,262192,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131090,18,262162,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,133795,2723,264867,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131122,50,262194,131213,133507,2576,264720,131072,131072,0,262144,131072,131072,0,262144,131072,131073,1,262145,131072,131168,96,262240,131072,131073,1,262145,131072,133805,2733,264877,131072,131073,1,262145,131072,131072,0,262144,131072,131072,0,262144,131072,133640,2568,264712,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131119,131073,48,262192,262144,0,262144,262336,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262288,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,0,0,3145728,524288,32505856,371405931,219881276,119018799,484657,0,0,0,1048576,52841613,52630731,1048576,1048576,131072,524288,685,507356,4543,0,96,10760,0,8388944,32505856,4004304,3798117,56793948,11534336,0,0,14155776,67108864,67108864,0,67108864,53904055,53558330,0,1048576,241990,766278,11560,2112,0,496187,8399613,0,4194727,4204886,13631488,0,3670016,1048576,1048576,0,4194304,9437184,0,0,360,33554432,54116940,4194304,0,0,2890,500107,0,11096,8388608,0,4194338,905969664,6291456,0,0,0,524288,524288,0,15329,16608739,0,16777216,4194304,4194304,0,0,0,17565,4194372,4194372,0,224426,0,0,0,33554432,0,0,0,0,644962107,0,2817938095,0,0,0,0,0,474587,0,0,217273,0,0,8388608,336,144,0,0,0,480,8388608,0,0,0,0,325944,0,0,0,10690,0,21362,0,6291456,6289466,96,2139,1981762,0,0,0,0,0,0,0,0,0,3145728,0,0,0,154412,4194304,4189860,144,4300,2097152,524288,1572864,0,0,0,0,0,0,524288,0,4128844,65536,4063243,0,0,8388608,0,42420953,0,1048576,10658,4194348,12998571,608537759,12073298230302122,12073324787088525,12073324787413161,12073298477214528
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,756666,756671,32768,256,0,0,24,24,12480,0x0,0x7f6864e35100,0,4096,4096,512,0,512,4096,0,27585,27585,1449587,565978,213,117935,85303,69478,557868,537342,220680,82467,27585,0,27585,0,882720,194242,0,0,0,0,0,100906,4096,0,27731,0,0,0,27731,0,0,0,27731,0,0,0,27731,0,0,0,27731,0,0,0,27731,0,0,0,27731,0,0,0,27731,0,0,0,27731,0,0,0,27731,0,0,0,27731,0,0,0,27731,0,0,0,27731,0,0,0,27731,0,0,0,27731,0,0,0,27731,0,0,0,27731,0,0,0,27731,0,0,0,27731,0,0,0,27731,0,0,0,27731,0,0,0,27731,0,0,0,27731,0,0,0,27731,0,0,0,27731,0,0,0,27731,0,0,0,27731,0,0,0,27731,0,0,0,27731,0,0,0,27731,0,0,0,27731,0,0,0,27731,0,0,0,0,257,0,0,0,304,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,304,0,0,0,256,0,0,0,256,0,0,0,261,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,377,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,4096,4096,0,117951,0,0,0,129709,0,0,0,81420,0,0,0,87378,0,0,0,83307,0,0,0,75150,0,0,0,92639,0,0,0,83702,0,0,0,79547,0,0,0,73230,0,0,0,79057,0,0,0,81249,0,0,0,83027,0,0,0,83041,0,0,0,70506,0,0,0,73865,0,0,0,123833,0,0,0,132786,0,0,0,71811,0,0,0,101115,0,0,0,90753,0,0,0,110363,0,0,0,85300,0,0,0,82713,0,0,0,176043,0,0,0,90735,0,0,0,101437,0,0,0,100535,0,0,0,249402,0,0,0,120102,0,0,0,90494,0,0,0,98282,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4096,0,256,256,256,0,256,256,256,47,257,304,304,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,377,377,377,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,188,260,448,448,0,256,256,256,0,304,304,304,0,256,256,256,188,260,448,448,0,256,256,256,0,257,257,257,0,304,304,304,0,257,257,257,0,256,256,256,0,257,257,257,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,47,257,304,304,0,256,256,256,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,304,0,0,256,0,0,0,0,512,512,35328,1133021,1081309,15360,11567,0,0,0,4096,65573,62553,4096,4096,128,512,611,27510,4430,0,48,220,0,8624,36352,223856,76484,1052966,26624,0,0,30208,65536,65536,65536,0,0,0,0,0,114,626,11860,2063,0,23736,8891,0,470,8421,1024,0,1024,4096,0,4096,512,512,0,0,360,16384,0,16384,0,0,2879,25713,0,8892,0,0,31,1933312,8192,0,0,0,512,512,0,120,15064,0,16384,16384,0,0,0,0,21254,0,0,0,0,0,0,0,32768,0,0,0,0,13060592,17708093,0,8192,0,0,0,0,695,0,0,0,0,0,1024,432,48,0,0,0,480,0,0,0,0,0,3258,0,0,0,8374,0,344,0,8192,6577,48,1567,1090,0,0,0,0,0,0,0,0,0,2560,0,0,0,49668,512,0,48,464,0,512,0,0,0,0,0,0,0,512,0,0,0,0,0,8192,0,0,419749,0,4096,8421,0,2995436,0,12073298492022533,12073324801993664,12073324802001184,12073298492997404
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,756666,756671,4194304,256,0,0,24,24,12928,0x7f69709ba900,0x7f6864e35140,0,524288,524288,65536,0,65536,524288,0,218250,218250,24153707,22931575,31182,10743769,21983902,21840847,22919508,20753215,1746000,1594261,218250,0,218250,0,6984000,6270459,0,0,0,0,0,20231594,524288,0,226276,0,0,0,226276,0,0,0,226276,0,0,0,226276,0,0,0,226276,0,0,0,226276,0,0,0,226276,0,0,0,226276,0,0,0,226276,0,0,0,226276,0,0,0,226276,0,0,0,226276,0,0,0,226276,0,0,0,226276,0,0,0,226276,0,0,0,226276,0,0,0,226276,0,0,0,226276,0,0,0,226276,0,0,0,226276,0,0,0,226276,0,0,0,226276,0,0,0,226276,0,0,0,226276,0,0,0,226276,0,0,0,226276,0,0,0,226276,0,0,0,226276,0,0,0,226276,0,0,0,226276,0,0,0,226276,0,0,0,226276,0,0,0,0,65537,0,12895,0,65584,0,6582,0,65540,0,21788,0,65536,0,30654,0,66586,0,71086,0,65536,0,11092,0,65537,0,7370,0,65536,0,28242,0,65536,0,4783,0,65536,0,4109,0,65536,0,27024,0,65584,0,18012,0,65536,0,4142,0,65536,0,1453,0,65537,0,9037,0,65536,0,20406,0,65536,0,6323,0,65536,0,1636,0,65536,0,4622,0,65536,0,42338,0,66296,0,30135,0,65536,0,49213,0,65536,0,2801,0,65536,0,28390,0,65812,0,31324,0,65536,0,4147,0,65536,0,888,0,65536,0,2192,0,65536,0,4349,0,65536,0,6030,0,65540,0,14657,0,65536,0,6573,0,524288,524288,0,45416510,0,0,0,37994144,0,0,0,41177977,0,0,0,41027547,0,0,0,45978735,0,0,0,37049923,0,0,0,37333432,0,0,0,37599053,0,0,0,33738830,0,0,0,33778119,0,0,0,31689046,0,0,0,38176047,0,0,0,33097710,0,0,0,34045692,0,0,0,34423478,0,0,0,36025280,0,0,0,39722286,0,0,0,35200470,0,0,0,36054038,0,0,0,34862787,0,0,0,48235839,0,0,0,32286861,0,0,0,35956851,0,0,0,41594830,0,0,0,41954091,0,0,0,40309824,0,0,0,33804805,0,0,0,35946078,0,0,0,35353220,0,0,0,37885558,0,0,0,37546818,0,0,0,34104355,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,524288,0,65536,65536,65536,0,65536,65536,65536,235,65541,65776,65776,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65657,65657,65657,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,67804,67804,67804,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65584,65584,65584,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65537,65537,65537,0,65584,65584,65584,0,65537,65537,65537,0,65536,65536,65536,0,65537,65537,65537,0,65536,65536,65536,0,65536,65536,65536,0,67888,67888,67888,0,65536,65536,65536,0,65536,65536,65536,188,65540,65728,65728,0,65536,65536,65536,65536,0,0,65536,0,0,65728,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65728,0,0,65536,0,0,0,0,65536,65536,4128768,154029160,52386240,97383080,199395,0,0,0,524288,22265777,22261449,524288,524288,16384,65536,734,217457,4490,0,48,2600,0,2097536,4259840,1802360,1609147,23794232,3014656,0,0,3473408,8388608,8388608,8388608,0,0,0,0,0,179633,209647,11224,2404,0,221112,2101542,0,423,2101119,131072,0,131072,524288,0,524288,65536,65536,0,0,360,2097152,0,2097152,40353,0,3156,217092,0,2100883,0,0,31,222298112,917504,0,0,0,65536,65536,0,7555,2019541,0,2097152,2097152,0,788772,791553,0,24020,0,0,0,0,0,0,0,4194304,0,0,0,0,951768802,1489429148,0,2097152,0,0,0,0,199138,0,0,0,0,0,131072,384,48,0,0,0,432,0,0,0,0,0,12831,0,0,0,2101606,0,8890,0,917504,914675,48,7479,201923,0,0,0,0,0,0,0,0,0,327680,0,0,709203,762667,65536,64048,48,1440,0,65536,0,0,0,0,0,0,0,65536,0,0,0,1966098,0,2097152,0,0,16586681,0,524288,2100233,0,992250065,0,12073298493632885,12073324802063264,12073324802195582,12073298494890582
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/prev_analysis/1.csv
index 2d1c570d81..f6921b17ea 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,6056273.0,6056273.0,6056273.0,9.187209783876687
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4525565.0,4525565.0,4525565.0,6.865165266752325
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 256u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,3051657.0,3051657.0,3051657.0,4.629284883200572
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/prev_analysis/1001.csv
index ca08330db0..0e3bf5267e 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,46.862275449101794,Instr per wave
 SMEM,1.8083832335329342,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/prev_analysis/101.csv
index 399904d972..acc7bac57e 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx908
 mi100
 48
 1228.8
-SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/prev_analysis/1202.csv
index 0fcaf6682e..65b27e21ba 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,33868.78030171651,2833.602378845215,547935.7421264648,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/prev_analysis/1901.csv
index ba66aaa675..af07e9b44a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,2.0,smem_
 VALU,735.0,valu_
 MFMA,,mfma_
 VMEM,8.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,22.0,br_
 VGPR,24.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,67894.0,wavefronts_
 Workgroups,16973.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,163.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,0.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,44.0,hbm_rd_
 HBM Wr,0.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,70.0,vl1_coales_
 VL1 Stall,30.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,36.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/prev_analysis/2001.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/prev_analysis/201.csv
index 88d9c6d94a..a3685fd8f5 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,59.48172189329084,Pct,100,59.48172189329084
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,63.966769045863586,Threads,64,99.94807663416185
 IPC - Issue,0.8437171046876727,Instr/cycle,5,16.874342093753455
-LDS BW,0.0,Gb/sec,23070.72,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,23070.72,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99344867258755,Pct,100,99.99344867258755
 Instr Cache BW,1411.2246532670722,Gb/s,4614.144,30.58475533635431
 Scalar L1D Cache Hit Rate,99.35620448525918,Pct,100,99.35620448525918
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/prev_analysis/602.csv
index f588e4fa08..77d374389b 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,65224.73652694611,0,796058,Simd
 Insufficient SIMD VGPRs,587650.6706586826,0,30107228,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/prev_analysis/701.csv
index d3f1bff5a3..1071413faa 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,23.976047904191617,8,36,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/sysinfo.csv
index e0071a975a..178338d372 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-no_roof_Double_N_flag,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 10:41:11 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+no_roof_Double_N_flag,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 10:41:11 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/timestamps.csv
index 1facd86af2..b9f0357a8c 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,757968,757973,33554432,256,0,0,8,32,6464,0x0,0x7f0482e04180,12073324787041015,12073324787088525,12073324787413161,12073324787519474
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,757968,757973,32768,256,0,0,24,24,12480,0x0,0x7f0482e35100,12073324801889625,12073324801993664,12073324802001184,12073324802013495
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,757968,757973,4194304,256,0,0,24,24,12928,0x7f05b2e12900,0x7f0482e35140,12073324802049502,12073324802063264,12073324802195582,12073324802199130
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi200/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi200/SQ_IFETCH_LEVEL.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi200/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi200/SQ_IFETCH_LEVEL.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi200/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi200/SQ_INST_LEVEL_LDS.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi200/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi200/SQ_INST_LEVEL_LDS.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi200/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi200/SQ_INST_LEVEL_SMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi200/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi200/SQ_INST_LEVEL_SMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi200/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi200/SQ_INST_LEVEL_VMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi200/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi200/SQ_INST_LEVEL_VMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi200/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi200/SQ_LEVEL_WAVES.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi200/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi200/SQ_LEVEL_WAVES.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi200/pmc_perf.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi200/pmc_perf.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi200/timestamps.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_Double_N_flag/mi200/timestamps.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/SQ_IFETCH_LEVEL.csv
index 1055e8c358..ce81947862 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/SQ_IFETCH_LEVEL.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,876410,876415,33554432,256,0,0,8,32,6464,0x0,0x7f86b0804180,502417,502417,524288,6291456,792074,101468424,12075464706636657,12075464952814066,12075464953137104,12075464953244526
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,876410,876415,32768,256,0,0,24,24,12480,0x0,0x7f86b0835100,27900,27900,512,8192,9142,1172576,12075464967863184,12075464968173098,12075464968179658,12075464968189791
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,876410,876415,4194304,256,0,0,24,24,12928,0x7f87bc457900,0x7f86b0835140,214220,214220,65536,917504,141065,18113532,12075464968248541,12075464968474536,12075464968605415,12075464968609782
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/SQ_INST_LEVEL_LDS.csv
index 09bf071d7d..861a66cf6f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/SQ_INST_LEVEL_LDS.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,878205,878210,33554432,256,0,0,8,32,6464,0x0,0x7fda9e804180,0,0,0,12075490913337740,12075491157373530,12075491157700728,12075491157810061
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,878205,878210,32768,256,0,0,24,24,12480,0x0,0x7fda9e835100,0,0,0,12075491172372645,12075491172674565,12075491172680805,12075491172686408
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,878205,878210,4194304,256,0,0,24,24,12928,0x7fdbaa4f8900,0x7fda9e835140,0,0,0,12075491172750597,12075491172956963,12075491173095523,12075491173099846
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/SQ_INST_LEVEL_SMEM.csv
index 726cab3a9a..ec7f03c1b0 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/SQ_INST_LEVEL_SMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,877827,877832,33554432,256,0,0,8,32,6464,0x0,0x7f4ad9c04180,4194304,3135726,401294704,12075488413680327,12075488657100185,12075488657423864,12075488657516476
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,877827,877832,32768,256,0,0,24,24,12480,0x0,0x7f4ad9c35100,512,23040,2946360,12075488672123943,12075488672422873,12075488672428793,12075488672434250
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,877827,877832,4194304,256,0,0,24,24,12928,0x7f4be5955900,0x7f4ad9c35140,65536,170538,21864680,12075488672497187,12075488672709591,12075488672839671,12075488672843561
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/SQ_INST_LEVEL_VMEM.csv
index 05c4753ca7..4fadb944ea 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/SQ_INST_LEVEL_VMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,878017,878022,33554432,256,0,0,8,32,6464,0x0,0x7fe7e0804180,1048576,11129705,1423944200,12075489662502027,12075489905133127,12075489905456965,12075489905564478
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,878017,878022,32768,256,0,0,24,24,12480,0x0,0x7fe7e0835100,4096,106110,13581472,12075489920015244,12075489920316975,12075489920323535,12075489920329017
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,878017,878022,4194304,256,0,0,24,24,12928,0x7fe8ec374900,0x7fe7e0835140,524288,12171095,1557839408,12075489920389199,12075489920605133,12075489920737773,12075489920741814
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/SQ_LEVEL_WAVES.csv
index d488579f5a..e50bc52b18 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/SQ_LEVEL_WAVES.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,878393,878398,33554432,256,0,0,8,32,6464,0x0,0x7ff88c604180,500997,500997,15800,4007984,524288,366527727,3809352,0,1480896796,12075492161888947,12075492407544938,12075492407867176,12075492407976019
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,878393,878398,32768,256,0,0,24,24,12480,0x0,0x7ff88c635100,28335,28335,21087,226688,512,1171242,80732,0,4699144,12075492422255036,12075492422579781,12075492422586341,12075492422594627
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,878393,878398,4194304,256,0,0,24,24,12928,0x7ff9981c6900,0x7ff88c635140,215316,215316,22602,1722536,65536,146273927,1556140,0,586912116,12075492422666941,12075492422900579,12075492423031618,12075492423036148
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/pmc_dispatch_info.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/pmc_perf.csv
index c576d8edea..45eaed6d09 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBuffer.kd,0,0,0,877144,877149,33554432,256,0,0,8,32,6464,0x0,0x7f335a004180,1048576,0,1048576,9437184,0,4194304,1048576,0,499366,499366,57291809,55030297,92,12500212,54244596,54155688,54986663,53805364,3994928,3803912,499366,0,499366,0,15979712,15139873,0,0,0,0,0,17569587,1048576,0,503183,0,0,0,503183,0,0,0,503183,0,0,0,503183,0,0,0,503183,0,0,0,503183,0,0,0,503183,0,0,0,503183,0,0,0,503183,0,0,0,503183,0,0,0,503183,0,0,0,503183,0,0,0,503183,0,0,0,503183,0,0,0,503183,0,0,0,503183,0,0,0,503183,0,0,0,503183,0,0,0,503183,0,0,0,503183,0,0,0,503183,0,0,0,503183,0,0,0,503183,0,0,0,503183,0,0,0,503183,0,0,0,503183,0,0,0,503183,0,0,0,503183,0,0,0,503183,0,0,0,503183,0,0,0,503183,0,0,0,503183,0,0,0,37412684,2542,0,0,0,52,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,48,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2648,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2586,0,0,0,3,0,0,0,4,0,0,0,48,0,0,0,0,0,0,0,0,0,0,0,24,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,1,0,0,0,0,0,0,0,2661,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1048576,0,0,0,131076,131076,0,587789,131072,131072,0,0,131076,131076,0,0,131072,131072,0,2952654,131072,131072,0,0,131076,131076,0,0,131076,131076,0,0,131076,131076,0,3172056,131072,131072,0,0,131072,131072,0,257,131072,131072,0,20013,131076,131076,0,0,131076,131076,0,0,131076,131076,0,816,131076,131076,0,3063820,131074,131074,0,1894,131072,131072,0,791,131072,131072,0,0,131080,131080,0,0,131076,131076,0,2914428,131072,131072,0,0,131080,131080,0,0,131088,131088,0,0,131072,131072,0,8778,131076,131076,0,0,131076,131076,0,0,131080,131080,0,0,131084,131084,0,0,131080,131080,0,0,131072,131072,0,0,131076,131076,0,0,131076,131076,1048576,0,1139,0,0,17256227,1087,0,0,17027725,766,0,0,16961121,1055,0,0,17253347,905,0,0,17419290,46932,0,0,30373473,1138,0,0,17749018,872,0,0,18794200,1698,0,0,17400789,43804,0,0,29497958,878,0,0,16822367,1676,0,0,17228560,1142,0,0,17302953,1826,0,0,17598979,1480,0,0,18159617,1825,0,0,18783945,832,0,0,16868722,1177,0,0,16810310,943,0,0,16740834,851,0,0,16901808,837,0,0,17390727,46618,0,0,30376028,974,0,0,17895639,935,0,0,18804049,927,0,0,16839670,42614,0,0,28628710,1841,0,0,16932693,1727,0,0,17080647,1560,0,0,17515511,698,0,0,17366446,1435,0,0,18058870,1661,0,0,18845795,1048576,131072,131072,0,262144,131260,131124,240,262384,131072,131072,0,262144,131072,133677,2605,264749,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131142,70,262214,131072,131072,0,262144,131072,131073,1,262145,131072,131072,0,262144,131072,131072,0,262144,131072,131121,49,262193,131072,131075,3,262147,131072,133635,2563,264707,131072,131073,1,262145,131213,131075,144,262288,131072,131072,0,262144,131072,133813,2741,264885,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131119,131073,48,262192,131072,131072,0,262144,131119,131073,48,262192,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,133553,2481,264625,262144,0,262144,262336,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262288,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,0,0,3145728,524288,32505856,370549340,219354833,118688651,480188,0,0,0,1048576,52877957,52669909,1048576,1048576,131072,524288,677,502185,4276,0,96,10617,0,8388944,32505856,4033656,3829305,57254094,11534336,0,0,14155776,67108864,67108864,0,67108864,54403446,54050891,0,1048576,243528,767816,11917,2409,0,499778,8399776,0,4194727,4205049,13631488,0,3670016,1048576,1048576,0,4194304,9437184,0,0,360,33554432,54407148,4194304,0,0,2407,501227,0,11106,8388608,0,4194362,905969664,6291456,0,0,0,524288,524288,0,15312,16608945,0,16777216,4194304,4194304,0,0,0,17258,4194380,4194380,0,217864,0,0,0,33554432,0,0,0,0,643059154,0,2807689104,0,0,0,0,0,475373,0,0,222272,0,0,8388608,336,144,0,0,0,480,8388608,0,0,0,0,332564,0,0,0,10671,0,21324,0,6291456,6289386,96,2318,2470534,0,0,0,0,0,0,0,0,0,3145728,0,0,0,143612,4194304,4189852,144,4308,2097152,524288,1572864,0,0,0,0,0,0,524288,0,4128826,65535,4063244,0,0,8388608,0,42141494,0,1048576,10649,4194384,13041986,614373167,12075466817500283,12075493288191172,12075493288515649,12075467061856218
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,877144,877149,32768,256,0,0,24,24,12480,0x0,0x7f335a035100,0,4096,4096,512,0,512,4096,0,28258,28258,1454927,587636,240,134950,89424,66146,579552,559104,226064,82817,28258,0,28258,0,904256,197374,0,0,0,0,0,57504,4096,0,27432,0,0,0,27432,0,0,0,27432,0,0,0,27432,0,0,0,27432,0,0,0,27432,0,0,0,27432,0,0,0,27432,0,0,0,27432,0,0,0,27432,0,0,0,27432,0,0,0,27432,0,0,0,27432,0,0,0,27432,0,0,0,27432,0,0,0,27432,0,0,0,27432,0,0,0,27432,0,0,0,27432,0,0,0,27432,0,0,0,27432,0,0,0,27432,0,0,0,27432,0,0,0,27432,0,0,0,27432,0,0,0,27432,0,0,0,27432,0,0,0,27432,0,0,0,27432,0,0,0,27432,0,0,0,27432,0,0,0,27432,0,0,0,0,256,0,0,0,304,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,260,0,0,0,304,0,0,0,256,0,0,0,256,0,0,0,378,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,4096,4096,0,122936,0,0,0,120674,0,0,0,68734,0,0,0,99904,0,0,0,139767,0,0,0,159278,0,0,0,75260,0,0,0,114680,0,0,0,96501,0,0,0,84794,0,0,0,82543,0,0,0,110266,0,0,0,160873,0,0,0,79784,0,0,0,73878,0,0,0,65309,0,0,0,124005,0,0,0,165784,0,0,0,96478,0,0,0,175954,0,0,0,103478,0,0,0,168970,0,0,0,96774,0,0,0,108963,0,0,0,169737,0,0,0,75508,0,0,0,86735,0,0,0,79056,0,0,0,84770,0,0,0,89528,0,0,0,78347,0,0,0,90627,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4096,0,256,256,256,0,304,304,304,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,376,376,376,0,256,256,256,0,257,257,257,0,256,256,256,0,256,256,256,0,305,305,305,188,260,448,448,0,256,256,256,0,257,257,257,0,256,256,256,188,260,448,448,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,47,257,304,304,0,256,256,256,0,256,256,256,0,256,256,256,47,257,304,304,0,256,256,256,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,304,0,0,256,0,0,0,0,512,512,35328,1067860,1018109,13399,11182,0,0,0,4096,34484,32327,4096,4096,128,512,594,27444,4358,0,48,171,0,8624,36352,225648,74369,1035631,26624,0,0,30208,65536,65536,65536,0,0,0,0,0,115,627,11817,2416,0,23858,8892,0,470,8422,1024,0,1024,4096,0,4096,512,512,0,0,360,16384,0,16384,0,0,2460,24485,0,8891,0,0,31,1933312,8192,0,0,0,512,512,0,120,15064,0,16384,16384,0,0,0,0,20979,0,0,0,0,0,0,0,32768,0,0,0,0,12301745,17480125,0,8192,0,0,0,0,696,0,0,0,0,0,1024,432,48,0,0,0,480,0,0,0,0,0,3181,0,0,0,8422,0,440,0,8192,6563,48,1581,1092,0,0,0,0,0,0,0,0,0,2560,0,0,0,49272,512,0,48,464,0,512,0,0,0,0,0,0,0,512,0,0,0,0,0,8192,0,0,434667,0,4096,8420,0,3357756,0,12075467076886621,12075493302909906,12075493302916626,12075467077876982
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,877144,877149,4194304,256,0,0,24,24,12928,0x7f3465d39900,0x7f335a035140,0,524288,524288,65536,0,65536,524288,0,218919,218919,24340397,23116959,32190,9419321,22733951,22649693,23108640,20943706,1751352,1606707,218919,0,218919,0,7005408,6277317,0,0,0,0,0,21124216,524288,0,225927,0,0,0,225927,0,0,0,225927,0,0,0,225927,0,0,0,225927,0,0,0,225927,0,0,0,225927,0,0,0,225927,0,0,0,225927,0,0,0,225927,0,0,0,225927,0,0,0,225927,0,0,0,225927,0,0,0,225927,0,0,0,225927,0,0,0,225927,0,0,0,225927,0,0,0,225927,0,0,0,225927,0,0,0,225927,0,0,0,225927,0,0,0,225927,0,0,0,225927,0,0,0,225927,0,0,0,225927,0,0,0,225927,0,0,0,225927,0,0,0,225927,0,0,0,225927,0,0,0,225927,0,0,0,225927,0,0,0,225927,0,0,0,0,65536,0,1528,0,65584,0,10414,0,65540,0,8009,0,65536,0,6094,0,65536,0,8899,0,65536,0,474,0,65536,0,4254,0,65536,0,3095,0,65536,0,5962,0,65536,0,6781,0,65536,0,1448,0,65536,0,4926,0,67043,0,51001,0,65536,0,2646,0,65536,0,2780,0,65536,0,0,0,68117,0,92798,0,65536,0,0,0,65536,0,4735,0,65584,0,220,0,65536,0,6268,0,65536,0,1331,0,65659,0,7587,0,65536,0,9040,0,65536,0,1167,0,65537,0,1237,0,65536,0,3045,0,65536,0,2903,0,65537,0,7453,0,65536,0,6192,0,65540,0,1170,0,65536,0,10635,0,524288,524288,0,37831710,0,0,0,41565309,0,0,0,34844227,0,0,0,34709317,0,0,0,53458390,0,0,0,37407657,0,0,0,39972223,0,0,0,35584692,0,0,0,35334667,0,0,0,37361324,0,0,0,39261439,0,0,0,36204947,0,0,0,32796089,0,0,0,42074519,0,0,0,40674156,0,0,0,37491149,0,0,0,34559805,0,0,0,40751997,0,0,0,33347579,0,0,0,36814026,0,0,0,42203010,0,0,0,45872030,0,0,0,39333649,0,0,0,33025237,0,0,0,35154559,0,0,0,42976756,0,0,0,33233973,0,0,0,37583691,0,0,0,43348965,0,0,0,44132952,0,0,0,38550460,0,0,0,41921599,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,524288,0,65536,65536,65536,0,65584,65584,65584,188,65540,65728,65728,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65656,65656,65656,0,65536,65536,65536,0,65537,65537,65537,0,65536,65536,65536,0,65536,65536,65536,0,65585,65585,65585,0,65536,65536,65536,0,65977,65977,65977,0,65537,65537,65537,0,65536,65536,65536,0,65536,65536,65536,0,68119,68119,68119,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,47,65537,65584,65584,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,188,65540,65728,65728,0,65536,65536,65536,65536,0,0,65536,0,0,65728,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65728,0,0,65536,0,0,0,0,65536,65536,4128768,120702721,43785187,72657694,209894,0,0,0,524288,22555299,22541619,524288,524288,16384,65536,726,226791,4247,0,48,5161,0,2097536,4259840,1704656,1529264,22699361,3014656,0,0,3473408,8388608,8388608,8388608,0,0,0,0,0,181167,206909,11834,2457,0,208859,2099016,0,423,2098593,131072,0,131072,524288,0,524288,65536,65536,0,0,360,2097152,0,2097152,40614,0,2514,214979,0,2100381,0,0,31,222298112,917504,0,0,0,65536,65536,0,7601,2014803,0,2097152,2097152,0,576464,578234,0,21759,0,0,0,0,0,0,0,4194304,0,0,0,0,904243125,1408737440,0,2097152,0,0,0,0,202253,0,0,0,0,0,131072,384,48,0,0,0,432,0,0,0,0,0,10058,0,0,0,2099645,0,4968,0,917504,914661,48,7655,174261,0,0,0,0,0,0,0,0,0,327680,0,0,167874,220490,65536,64048,48,1440,0,65536,0,0,0,0,0,0,0,65536,0,0,0,1966101,0,2097152,0,0,16278778,0,524288,2100415,0,1083045400,0,12075467078509657,12075493302977585,12075493303109584,12075467079768878
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/prev_analysis/1.csv
index 038a0e3e36..77f12d14c1 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,6058989.0,6058989.0,6058989.0,9.18914860131471
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4527802.0,4527802.0,4527802.0,6.866928693108693
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 256u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,3055814.0,3055814.0,3055814.0,4.634490827426474
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/prev_analysis/1001.csv
index ca08330db0..0e3bf5267e 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,46.862275449101794,Instr per wave
 SMEM,1.8083832335329342,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/prev_analysis/101.csv
index d1dbc91027..15a7ab1e52 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx908
 mi100
 48
 1228.8
-SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/prev_analysis/1202.csv
index 8a84c5efb2..12cd5f8db6 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,33444.03549267432,2827.067108154297,547939.0354614258,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/prev_analysis/1901.csv
index 3a7d291e09..5125ae54f8 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,2.0,smem_
 VALU,735.0,valu_
 MFMA,,mfma_
 VMEM,8.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,22.0,br_
 VGPR,24.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,67894.0,wavefronts_
 Workgroups,16973.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,163.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,0.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,44.0,hbm_rd_
 HBM Wr,0.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,70.0,vl1_coales_
 VL1 Stall,34.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,36.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/prev_analysis/2001.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/prev_analysis/201.csv
index 0af8c658c6..c5a5ee6251 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,59.91374930114081,Pct,100,59.91374930114081
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,63.96784434657877,Threads,64,99.94975679152932
 IPC - Issue,0.8437264174127108,Instr/cycle,5,16.874528348254216
-LDS BW,0.0,Gb/sec,23070.72,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,23070.72,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99341386727856,Pct,100,99.99341386727856
 Instr Cache BW,1410.800013434607,Gb/s,4614.144,30.57555233288356
 Scalar L1D Cache Hit Rate,99.3562044852199,Pct,100,99.3562044852199
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/prev_analysis/602.csv
index 67294eea1d..ee2b10e27c 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,56313.658682634734,0,608377,Simd
 Insufficient SIMD VGPRs,661930.3473053892,0,35304948,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/prev_analysis/701.csv
index d3f1bff5a3..1071413faa 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,23.976047904191617,8,36,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/sysinfo.csv
index 57359c0436..6e5838f9ea 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-no_roof_HBM,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 11:17:19 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+no_roof_HBM,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 11:17:19 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/timestamps.csv
index 21c8f73995..37902995e8 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,878445,878450,33554432,256,0,0,8,32,6464,0x0,0x7f1ad1004180,12075493288149052,12075493288191172,12075493288515649,12075493288621740
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,878445,878450,32768,256,0,0,24,24,12480,0x0,0x7f1ad1035100,12075493302808305,12075493302909906,12075493302916626,12075493302922527
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,878445,878450,4194304,256,0,0,24,24,12928,0x7f1bdcd26900,0x7f1ad1035140,12075493302964405,12075493302977585,12075493303109584,12075493303113051
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/SQ_IFETCH_LEVEL.csv
index e2fbafad1d..1cc1063541 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/SQ_IFETCH_LEVEL.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,171715,171715,33554432,256,0,0,4,32,4160,0x0,0x7f2308604280,391956,391956,524288,4718592,681055,76330204,16734539745714,16733827730523,16734686763127,16734686870866
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,171715,171715,32768,256,0,0,12,24,13888,0x0,0x7f2308623f80,34061,34061,512,8192,5692,637356,16734691984230,16734686763127,16734692126944,16734692131466
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,171715,171715,4194304,256,0,0,12,24,14336,0x7f2326f55380,0x7f2308623fc0,165116,165116,65536,917504,140374,15732588,16734692170164,16734692126944,16734692511422,16734692514033
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/SQ_INST_LEVEL_LDS.csv
index 8f83d1589c..21d14ed82c 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/SQ_INST_LEVEL_LDS.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,173563,173563,33554432,256,0,0,4,32,4160,0x0,0x7f141c404280,0,0,0,16753923405123,16753219775231,16754068759944,16754068872133
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,173563,173563,32768,256,0,0,12,24,13888,0x0,0x7f141c423f80,0,0,0,16754074035127,16754068759944,16754074177997,16754074183093
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,173563,173563,4194304,256,0,0,12,24,14336,0x7f143acea380,0x7f141c423fc0,0,0,0,16754074217311,16754074177997,16754074545515,16754074548261
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/SQ_INST_LEVEL_SMEM.csv
index 3fb1ccd0c8..7a28b39dc1 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/SQ_INST_LEVEL_SMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,171493,171493,33554432,256,0,0,4,32,4160,0x0,0x7ff97ce04280,3670016,2921456,327299160,16733599949439,16705688806276,16733747324957,16733747438606
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,171493,171493,32768,256,0,0,12,24,13888,0x0,0x7ff97ce23f80,512,101584,11373816,16733752604709,16733747324957,16733752742369,16733752747084
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,171493,171493,4194304,256,0,0,12,24,14336,0x7ff97fed7380,0x7ff97ce23fc0,65536,637696,71461512,16733752780713,16733752742369,16733753110368,16733753113152
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/SQ_INST_LEVEL_VMEM.csv
index 81de606887..8d3242de45 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/SQ_INST_LEVEL_VMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,173341,173341,33554432,256,0,0,4,32,4160,0x0,0x7f6ae2604280,524288,5492355,615139540,16752993786704,16750705824713,16753138534982,16753138649231
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,173341,173341,32768,256,0,0,12,24,13888,0x0,0x7f6ae2623f80,4096,46104,5155712,16753143817485,16753138534982,16753143946796,16753143951501
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,173341,173341,4194304,256,0,0,12,24,14336,0x7f6ae5516380,0x7f6ae2623fc0,524288,10934570,1224677772,16753143985840,16753143946796,16753144319114,16753144321749
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/SQ_LEVEL_WAVES.csv
index 7d87b424b2..0afb1ffb7f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/SQ_LEVEL_WAVES.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,171937,171937,33554432,256,0,0,4,32,4160,0x0,0x7f77b5404280,381400,381400,8624,3051208,524288,238786957,2962821,0,971386520,16735474065011,16734768942885,16735622697763,16735622807212
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,171937,171937,32768,256,0,0,12,24,13888,0x0,0x7f77b5423f80,33755,33755,30273,270048,512,1744911,162249,0,6993368,16735627947686,16735622697763,16735628093100,16735628097541
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,171937,171937,4194304,256,0,0,12,24,14336,0x7f77b84d4380,0x7f77b5423fc0,165721,165721,14790,1325776,65536,82001424,1212050,0,329733740,16735628140580,16735628093100,16735628481578,16735628483868
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/pmc_perf.csv
index a17e341d1f..74748eea7c 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDI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],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBufferAligned.kd,0,0,0,172703,172703,33554432,256,0,0,4,32,4160,0x0,0x7f5d1a404280,3085904,3000143,524288,38978969,243889526,392,224,0,385737,385737,39244184.0,38312182.0,6.0,4166268.0,31428769.0,31064626.0,38287244.0,37725259.0,3084193,3006539,385737,0,385737,0,12343584.0,9478852.0,0.0,0.0,0,0,616,0,4718592,4714947,112,3533,378058,0.0,0.0,0.0,524288.0,28710692.0,27992397.0,7817.0,524288.0,131072,524288,302,387241,2253,0,56.0,304.0,0.0,4194696.0,0,0,0,0,0,7340032,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,20338987.0,524288.0,0,390150,0,0,0,390150,0,0,0,390150,0,0,0,390150,0,0,0,390150,0,0,0,390150,0,0,0,390150,0,0,0,390150,0,0,0,390150,0,0,0,390150,0,0,0,390150,0,0,0,390150,0,0,0,390150,0,0,0,390150,0,0,0,390150,0,0,0,390150,0,0,0,390150,0,0,0,390150,0,0,0,390150,0,0,0,390150,0,0,0,390150,0,0,0,390150,0,0,0,390150,0,0,0,390150,0,0,0,390150,0,0,0,390150,0,0,0,390150,0,0,0,390150,0,0,0,390150,0,0,0,390150,0,0,0,390150,0,0,0,390150,0,0,0,0,0,0.0,21004764.0,0,0,0,0,0,0,0,0,0,0,0,0,35,0,0,0,2,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,112,0,0,0,56,0,0,0,32,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,37,0,0,0,4,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,0,0,1,0,0,0,524288.0,0.0,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,44452,129024,129024,0,329,129024,129024,0,339,129024,129024,0,885,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,44152,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,211081,129024,129024,0,303312,129024,129024,0,884,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,178,129024,129024,0,0,129024,129024,0,0,129024,129024,0,44876,129024,129024,0,187,129024,129024,524288.0,0.0,45392,0,0,50920711,44940,0,0,50736903,44894,0,0,50314812,46828,0,0,51877235,44666,0,0,51201753,47618,0,0,51989988,43461,0,0,50530675,47221,0,0,52721774,44349,0,0,50651923,46125,0,0,50959568,45499,0,0,50453458,47405,0,0,52096124,45827,0,0,51613471,46972,0,0,51589818,46107,0,0,51351476,48388,0,0,53189316,43201,0,0,50339736,45604,0,0,50871223,43883,0,0,49986395,47969,0,0,52252951,45279,0,0,51363249,46208,0,0,51423265,44582,0,0,50644151,47182,0,0,52664630,45082,0,0,50666661,45372,0,0,50891313,46246,0,0,50799737,48379,0,0,52351648,45746,0,0,51482147,46734,0,0,51643683,46263,0,0,51456480,49518,0,0,53314077,0.0,65536,65536,0,131072,65536,65592,56,131128,65536,65536,0,131072,65536,65568,32,131104,65646,65538,112,131184,65536,65537,1,131073,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65568,32,131104,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65591,65537,56,131128,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65537,1,131073,65536,65572,36,131108,65758,65538,224,131296,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65648,112,131184,65536,65536,0,131072,65536,65536,0,131072,65536,65569,33,131105,65591,65537,56,131128,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131184,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131296,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131128,0,131072,1155083,0,524288,3670016,3663206,224,6586,1048576,33554432.0,33554432.0,0.0,33554432.0,30325100.0,28689062.0,0.0,524288.0,222229,538138,8627,948,0,385311,4195054.0,0.0,2097594.0,2097460.0,1048576,1048576,0,524288,0,524288,7340032,0,0.0,0.0,104.0,8388608.0,29707618.0,2097152.0,0.0,206019,0,1259,384623,0,751.0,4194304.0,0.0,2064387.0,25690112,9437184,0,0,0,0,0,0,13282.0,8242506.0,0.0,8388608.0,2097152.0,4194304.0,9711160,0,0,8687,4128768.0,4128768.0,0.0,1483151.0,0,0,0,0,0,0,5767168,1048576,314836462.0,0.0,1469928070.0,0.0,32.0,0.0,0,0,371121,0.0,0.0,1478391.0,0.0,3670016,524288,0,0,0,2621440,524288,177615057,4194304.0,0.0,0.0,0.0,0.0,1210862.0,0,0,0.0,311.0,0.0,606.0,43076468,24117248,0,0,9437184,11010048,0,3145728,0.0,0.0,0.0,0.0,0.0,0.0,0,1572864,0.0,0.0,0.0,203468.0,524288,524288,0,3670016,7340032,603979776,4718592,0,0.0,0.0,0.0,0.0,0.0,0.0,524288,0,2064384.0,0.0,2031623.0,0.0,0,0,524288,0,0,0,0,33554432,0.0,4194304.0,0.0,18996638.0,0.0,0.0,141.0,4128768.0,989153.0,1659769822.0,16736914282106,16754707803636,16754708043475,16737062791768
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,172703,172703,32768,256,0,0,12,24,13888,0x0,0x7f5d1a423f80,261592,159631,512,1394689,1754061,504,56,0,32698,32698,2310893.0,195728.0,179.0,0.0,45833.0,42977.0,189400.0,170602.0,261584,167336,32698,0,32698,0,1046336.0,357499.0,0.0,0.0,0,0,560,0,8192,6151,56,1985,23347,0.0,0.0,0.0,4096.0,32813.0,31417.0,0.0,4096.0,128,512,302,32684,2258,0,0.0,62.0,0.0,4600.0,0,0,0,0,0,1024,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,11782.0,4096.0,0,33256,0,0,0,33256,0,0,0,33256,0,0,0,33256,0,0,0,33256,0,0,0,33256,0,0,0,33256,0,0,0,33256,0,0,0,33256,0,0,0,33256,0,0,0,33256,0,0,0,33256,0,0,0,33256,0,0,0,33256,0,0,0,33256,0,0,0,33256,0,0,0,33256,0,0,0,33256,0,0,0,33256,0,0,0,33256,0,0,0,33256,0,0,0,33256,0,0,0,33256,0,0,0,33256,0,0,0,33256,0,0,0,33256,0,0,0,33256,0,0,0,33256,0,0,0,33256,0,0,0,33256,0,0,0,33256,0,0,0,33256,0,0,0,0,0,0.0,0.0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,312,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,261,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,4096.0,4096.0,0,78963,0,0,0,88414,0,0,0,86844,0,0,0,99753,0,0,0,81119,0,0,0,78685,0,0,0,82654,0,0,0,113057,0,0,0,77110,0,0,0,103135,0,0,0,89782,0,0,0,89614,0,0,0,102749,0,0,0,79951,0,0,0,78883,0,0,0,82809,0,0,0,75353,0,0,0,84859,0,0,0,77551,0,0,0,86044,0,0,0,644812,0,0,0,89368,0,0,0,79841,0,0,0,89585,0,0,0,78933,0,0,0,82921,0,0,0,73008,0,0,0,81896,0,0,0,75171,0,0,0,83995,0,0,0,87907,0,0,0,86064,0,0,0.0,0.0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4096.0,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,222,131,353,353,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,222,130,352,352,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,129,129,129,0,129,129,129,0,128,128,128,55,129,184,184,0,128,128,128,0,128,128,128,0,128,128,128,0,184,184,184,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,352,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,352,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,184,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,662,0,0,512,0,56,456,0,65536.0,65536.0,65536.0,0.0,0.0,0.0,0.0,0.0,4,516,11409,1422,0,32052,4660.0,0.0,499.0,4161.0,512,0,0,0,4096,4096,512,0,0.0,0.0,104.0,16384.0,0.0,16384.0,4096.0,0,0,1349,31588,0,4662.0,0.0,0.0,31.0,35328,26112,0,0,0,0,0,0,104.0,15240.0,0.0,16384.0,16384.0,0.0,0,0,0,29567,0.0,0.0,0.0,0.0,0,0,0,0,0,0,10752,3584,3946445.0,5410269.0,0.0,8192.0,0.0,0.0,0,0,497,0.0,0.0,0.0,0.0,512,4096,0,0,0,512,512,1752200,0.0,0.0,0.0,0.0,0.0,1392.0,0,0,0.0,8261.0,0.0,120.0,18860,32256,0,0,26112,1024,0,1024,0.0,0.0,0.0,0.0,0.0,0.0,0,1024,0.0,0.0,0.0,30426.0,4096,0,4096,512,512,1671168,8192,0,0.0,0.0,0.0,0.0,0.0,0.0,512,0,0.0,0.0,0.0,0.0,0,0,512,0,0,0,0,32768,8192.0,0.0,0.0,127880.0,0.0,4096.0,8206.0,0.0,3290223.0,0.0,16737069022357,16754712857214,16754712870174,16737069514971
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,172703,172703,4194304,256,0,0,12,24,14336,0x7f5d1d500380,0x7f5d1a423fc0,1315512,1205893,65536,15602121,74897619,392,56,0,164438,164438,15907970.0,14474845.0,24597.0,627797.0,13150350.0,12805905.0,14468142.0,12331203.0,1315504,1212670,164438,0,164438,0,5262016.0,4731470.0,0.0,0.0,0,0,448,0,917504,914016,0,3488,153715,0.0,0.0,0.0,524288.0,13960582.0,13948234.0,2206.0,524288.0,16384,65536,302,164593,2329,0,0.0,184.0,0.0,1048968.0,0,0,0,0,0,131072,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,11060227.0,524288.0,0,164696,0,0,0,164696,0,0,0,164696,0,0,0,164696,0,0,0,164696,0,0,0,164696,0,0,0,164696,0,0,0,164696,0,0,0,164696,0,0,0,164696,0,0,0,164696,0,0,0,164696,0,0,0,164696,0,0,0,164696,0,0,0,164696,0,0,0,164696,0,0,0,164696,0,0,0,164696,0,0,0,164696,0,0,0,164696,0,0,0,164696,0,0,0,164696,0,0,0,164696,0,0,0,164696,0,0,0,164696,0,0,0,164696,0,0,0,164696,0,0,0,164696,0,0,0,164696,0,0,0,164696,0,0,0,164696,0,0,0,164696,0,0,0,0,0,0.0,0.0,65536,0,9323,0,65537,0,12613,0,65537,0,12471,0,65538,0,4929,0,65536,0,25794,0,65536,0,35484,0,65536,0,26072,0,65536,0,17943,0,65536,0,10968,0,65536,0,8468,0,65593,0,10618,0,65536,0,12553,0,65536,0,21699,0,65536,0,20547,0,65538,0,24365,0,65536,0,10480,0,65536,0,11138,0,65537,0,31304,0,65536,0,10143,0,65536,0,34191,0,65536,0,13638,0,65593,0,13675,0,65536,0,14485,0,65539,0,15351,0,65540,0,16431,0,65537,0,14657,0,65536,0,9552,0,65536,0,6941,0,65536,0,14488,0,65536,0,18893,0,65599,0,13725,0,65536,0,6664,0,524288.0,524288.0,0,39704829,0,0,0,41724569,0,0,0,41298423,0,0,0,46713841,0,0,0,49213222,0,0,0,43877309,0,0,0,43347217,0,0,0,51425620,0,0,0,49124788,0,0,0,41029886,0,0,0,41378331,0,0,0,40649053,0,0,0,44900245,0,0,0,51661189,0,0,0,47325037,0,0,0,50367012,0,0,0,51576373,0,0,0,45567745,0,0,0,52727869,0,0,0,40569199,0,0,0,47673733,0,0,0,41267249,0,0,0,46740426,0,0,0,40647780,0,0,0,40797082,0,0,0,49919499,0,0,0,41280173,0,0,0,46080948,0,0,0,47901917,0,0,0,42784034,0,0,0,44500315,0,0,0,50290273,0,0,0.0,0.0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,524288.0,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32769,32769,32769,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32769,32769,32769,0,32768,32768,32768,0,32769,32769,32769,0,32826,32826,32826,0,32768,32768,32768,166,32770,32936,32936,222,32770,32992,32992,0,32768,32768,32768,0,32768,32768,32768,0,32824,32824,32824,0,32768,32768,32768,0,32768,32768,32768,0,32834,32834,32834,0,32768,32768,32768,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32936,0,0,32992,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,892403,0,0,65536,63800,56,1680,0,8388608.0,8388608.0,8388608.0,0.0,0.0,0.0,0.0,0.0,125405,147937,10073,2750,0,162759,1049153.0,0.0,388.0,1048765.0,65536,0,0,0,524288,524288,131072,0,0.0,0.0,104.0,2097152.0,0.0,2097152.0,524288.0,43669,0,2805,163591,0,1049153.0,0.0,0.0,31.0,4063232,2883584,0,0,0,0,0,0,6595.0,2027284.0,0.0,2097152.0,2097152.0,0.0,1255397,0,0,13797,0.0,0.0,0.0,0.0,262144,0,0,0,0,0,1507328,458752,905390463.0,2295596349.0,0.0,2097152.0,18.0,0.0,0,0,151795,0.0,0.0,0.0,0.0,65536,524288,0,0,0,65536,65536,47991729,0.0,0.0,0.0,0.0,0.0,39017.0,0,0,0.0,2097342.0,0.0,366.0,21627123,3735552,0,0,2883584,196608,0,131072,0.0,0.0,0.0,0.0,0.0,0.0,0,131072,0.0,0.0,604988.0,1856873.0,524288,0,524288,65536,131072,184549376,917504,0,0.0,0.0,0.0,0.0,0.0,0.0,65536,0,0.0,0.0,983048.0,0.0,0,0,65536,0,0,0,0,4194304,2097152.0,0.0,0.0,12362013.0,0.0,524288.0,2097288.0,0.0,1410678067.0,0.0,16737070611845,16754712937053,16754713029533,16737071412059
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/prev_analysis/1.csv
index 42e563aca3..d7ed8805fa 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,3358386.0,3358386.0,3358386.0,7.84359217840379
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,1725753.0,1725753.0,1725753.0,4.030538101533557
 "void benchmark_func<double, 256, 8u, 512u>(double, double*) [clone .kd]",1,1715993.0,1715993.0,1715993.0,4.007743384171937
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/prev_analysis/1001.csv
index f475f954a6..fb5988001a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,494.8622754491018,Instr per wave
 VMEM,7.958083832335329,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,0.0,Instr per wave
 SALU,24.520958083832337,Instr per wave
 SMEM,1.8023952095808384,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/prev_analysis/101.csv
index b5783342c4..7d62f09a37 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx90a
 mi200
 56
 1638.4
-SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/prev_analysis/1202.csv
index 56ad3f6b07..5ec7ca2638 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,18378.054618698396,1860.7294158935547,258461.89099121094,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/prev_analysis/1901.csv
index 3b46d09b91..5b7622a10c 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,2.0,smem_
 VALU,495.0,valu_
 MFMA,0.0,mfma_
 VMEM,8.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,10.0,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,67894.0,wavefronts_
 Workgroups,16973.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,128.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,0.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,44.0,hbm_rd_
 HBM Wr,0.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,70.0,vl1_coales_
 VL1 Stall,2.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,25.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/prev_analysis/201.csv
index c22feb0ccf..79410fabc3 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,58.3122735945208,Pct,100,58.3122735945208
 MFMA Util,0.0,Pct,100,0.0
 VALU Active Threads/Wave,64.0,Threads,64,100.0
 IPC - Issue,1.0,Instr/cycle,5,20.0
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99256299659508,Pct,100,99.99256299659508
 Instr Cache BW,1673.7149422199436,Gb/s,6092.8,27.470373920364096
 Scalar L1D Cache Hit Rate,99.3485588595644,Pct,100,99.3485588595644
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/prev_analysis/602.csv
index 167c141c34..ffa81e2bef 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,11973584.934131736,0,380232439,Simd
 Insufficient SIMD VGPRs,0.0,0,0,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/prev_analysis/701.csv
index 12250d77c0..db0925a109 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/sysinfo.csv
index a49fae7508..fb24f372ed 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-no_roof_HBM,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:32:14 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+no_roof_HBM,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:32:14 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/timestamps.csv
index a5c082fee6..6e3bfb9794 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_HBM/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,173646,173646,33554432,256,0,0,4,32,4160,0x0,0x7f6e09c04280,16754707778416,16754707803636,16754708043475,16754708156254
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,173646,173646,32768,256,0,0,12,24,13888,0x0,0x7f6e09c23f80,16754712841564,16754712857214,16754712870174,16754712888122
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,173646,173646,4194304,256,0,0,12,24,14336,0x7f6e0ccf7380,0x7f6e09c23fc0,16754712891302,16754712937053,16754713029533,16754713031628
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv1/mi100/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv1/mi100/SQ_IFETCH_LEVEL.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv1/mi100/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv1/mi100/SQ_IFETCH_LEVEL.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv1/mi100/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv1/mi100/SQ_INST_LEVEL_LDS.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv1/mi100/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv1/mi100/SQ_INST_LEVEL_LDS.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv1/mi100/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv1/mi100/SQ_INST_LEVEL_SMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv1/mi100/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv1/mi100/SQ_INST_LEVEL_SMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv1/mi100/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv1/mi100/SQ_INST_LEVEL_VMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv1/mi100/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv1/mi100/SQ_INST_LEVEL_VMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv1/mi100/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv1/mi100/SQ_LEVEL_WAVES.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv1/mi100/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv1/mi100/SQ_LEVEL_WAVES.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv1/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv1/mi100/pmc_perf.csv
index 5431ca9138..5a94591c8b 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv1/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv1/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,BeginNs,EndNs
+Dispatch_ID,Kernel_Name,Start_Timestamp,End_Timestamp
 ,,12073844215991070,12073844216315707
 ,,12073844230982223,12073844230988943
 ,,12073844231051502,12073844231190221
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv1/mi100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv1/mi100/sysinfo.csv
index eb7d835152..7ec6457070 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv1/mi100/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv1/mi100/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-no_roof_K_int_inv1,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 10:49:50 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+no_roof_K_int_inv1,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 10:49:50 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv1/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv1/mi100/timestamps.csv
index 7476d1edb3..c377ced75e 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv1/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv1/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,788020,788025,33554432,256,0,0,8,32,6464,0x0,0x7f8ff5c04180,12073844215944908,12073844215991070,12073844216315707,12073844216424659
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,788020,788025,32768,256,0,0,24,24,12480,0x0,0x7f8ff5c35100,12073844230881636,12073844230982223,12073844230988943,12073844230994525
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,788020,788025,4194304,256,0,0,24,24,12928,0x7f9101782900,0x7f8ff5c35140,12073844231038267,12073844231051502,12073844231190221,12073844231193645
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv1/mi200/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv1/mi200/SQ_IFETCH_LEVEL.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv1/mi200/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv1/mi200/SQ_IFETCH_LEVEL.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv1/mi200/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv1/mi200/SQ_INST_LEVEL_LDS.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv1/mi200/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv1/mi200/SQ_INST_LEVEL_LDS.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv1/mi200/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv1/mi200/SQ_INST_LEVEL_SMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv1/mi200/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv1/mi200/SQ_INST_LEVEL_SMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv1/mi200/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv1/mi200/SQ_INST_LEVEL_VMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv1/mi200/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv1/mi200/SQ_INST_LEVEL_VMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv1/mi200/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv1/mi200/SQ_LEVEL_WAVES.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv1/mi200/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv1/mi200/SQ_LEVEL_WAVES.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv1/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv1/mi200/pmc_perf.csv
index 03b2635dcf..9bc1ec3a54 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv1/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv1/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,BeginNs,EndNs
+Dispatch_ID,Kernel_Name,Start_Timestamp,End_Timestamp
 ,,14662813835085,14662814075085
 ,,14662818921813,14662818935573
 ,,14662818989013,14662819081493
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv1/mi200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv1/mi200/sysinfo.csv
index 42924af45a..4b7d4d6f84 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv1/mi200/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv1/mi200/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-no_roof_K_int_inv1,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 19:57:22 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+no_roof_K_int_inv1,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 19:57:22 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv1/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv1/mi200/timestamps.csv
index 3f6efbd600..527bbce0f0 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv1/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv1/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,58889,58889,33554432,256,0,0,4,32,4160,0x0,0x7fdca2a04280,14662813809575,14662813835085,14662814075085,14662814187635
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,58889,58889,32768,256,0,0,12,24,13888,0x0,0x7fdca2a23f80,14662818905860,14662818921813,14662818935573,14662818944289
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,58889,58889,4194304,256,0,0,12,24,14336,0x7fdca5aa8380,0x7fdca2a23fc0,14662818959018,14662818989013,14662819081493,14662819083445
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv2/mi100/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv2/mi100/SQ_IFETCH_LEVEL.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv2/mi100/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv2/mi100/SQ_IFETCH_LEVEL.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv2/mi100/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv2/mi100/SQ_INST_LEVEL_LDS.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv2/mi100/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv2/mi100/SQ_INST_LEVEL_LDS.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv2/mi100/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv2/mi100/SQ_INST_LEVEL_SMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv2/mi100/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv2/mi100/SQ_INST_LEVEL_SMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv2/mi100/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv2/mi100/SQ_INST_LEVEL_VMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv2/mi100/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv2/mi100/SQ_INST_LEVEL_VMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv2/mi100/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv2/mi100/SQ_LEVEL_WAVES.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv2/mi100/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv2/mi100/SQ_LEVEL_WAVES.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv2/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv2/mi100/pmc_perf.csv
index eec571116b..fa8f0dd984 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv2/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv2/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,BeginNs,EndNs
+Dispatch_ID,Kernel_Name,Start_Timestamp,End_Timestamp
 ,,12073911975000599,12073911975324436
 ,,12073911991058234,12073911991064634
 ,,12073911991139993,12073911991274712
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv2/mi100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv2/mi100/sysinfo.csv
index 6bc9556295..903b08745f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv2/mi100/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv2/mi100/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-no_roof_K_int_inv2,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 10:50:58 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+no_roof_K_int_inv2,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 10:50:58 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv2/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv2/mi100/timestamps.csv
index 4bb623ffa9..47ee1173e0 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv2/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv2/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,793045,793050,33554432,256,0,0,8,32,6464,0x0,0x7f4e4e404180,12073911974958433,12073911975000599,12073911975324436,12073911975434588
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,793045,793050,32768,256,0,0,24,24,12480,0x0,0x7f4e4e435100,12073911990951875,12073911991058234,12073911991064634,12073911991070395
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,793045,793050,4194304,256,0,0,24,24,12928,0x7f4f5a135900,0x7f4e4e435140,12073911991125818,12073911991139993,12073911991274712,12073911991277620
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv2/mi200/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv2/mi200/SQ_IFETCH_LEVEL.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv2/mi200/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv2/mi200/SQ_IFETCH_LEVEL.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv2/mi200/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv2/mi200/SQ_INST_LEVEL_LDS.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv2/mi200/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv2/mi200/SQ_INST_LEVEL_LDS.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv2/mi200/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv2/mi200/SQ_INST_LEVEL_SMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv2/mi200/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv2/mi200/SQ_INST_LEVEL_SMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv2/mi200/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv2/mi200/SQ_INST_LEVEL_VMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv2/mi200/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv2/mi200/SQ_INST_LEVEL_VMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv2/mi200/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv2/mi200/SQ_LEVEL_WAVES.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv2/mi200/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv2/mi200/SQ_LEVEL_WAVES.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv2/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv2/mi200/pmc_perf.csv
index c4bfc96692..ac62f12508 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv2/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv2/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,BeginNs,EndNs
+Dispatch_ID,Kernel_Name,Start_Timestamp,End_Timestamp
 ,,14752285842401,14752286082241
 ,,14752290940971,14752290954571
 ,,14752291030091,14752291122731
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv2/mi200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv2/mi200/sysinfo.csv
index 632a069b07..51775bbe27 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv2/mi200/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv2/mi200/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-no_roof_K_int_inv2,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 19:58:51 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+no_roof_K_int_inv2,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 19:58:51 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv2/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv2/mi200/timestamps.csv
index 2c4b75ba3f..5705ff8586 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv2/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_int_inv2/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,64991,64991,33554432,256,0,0,4,32,4160,0x0,0x7fd7cb004280,14752285816700,14752285842401,14752286082241,14752286146881
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,64991,64991,32768,256,0,0,12,24,13888,0x0,0x7fd7cb023f80,14752290924768,14752290940971,14752290954571,14752290972477
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,64991,64991,4194304,256,0,0,12,24,14336,0x7fd7ce004380,0x7fd7cb023fc0,14752290978417,14752291030091,14752291122731,14752291124893
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv1/mi100/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv1/mi100/SQ_IFETCH_LEVEL.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv1/mi100/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv1/mi100/SQ_IFETCH_LEVEL.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv1/mi100/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv1/mi100/SQ_INST_LEVEL_LDS.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv1/mi100/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv1/mi100/SQ_INST_LEVEL_LDS.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv1/mi100/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv1/mi100/SQ_INST_LEVEL_SMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv1/mi100/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv1/mi100/SQ_INST_LEVEL_SMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv1/mi100/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv1/mi100/SQ_INST_LEVEL_VMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv1/mi100/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv1/mi100/SQ_INST_LEVEL_VMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv1/mi100/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv1/mi100/SQ_LEVEL_WAVES.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv1/mi100/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv1/mi100/SQ_LEVEL_WAVES.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv1/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv1/mi100/pmc_perf.csv
index 9959090e4a..d0c3f9f6b4 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv1/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv1/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,BeginNs,EndNs
+Dispatch_ID,Kernel_Name,Start_Timestamp,End_Timestamp
 ,,12073980798057932,12073980798383529
 ,,12073980813133369,12073980813140729
 ,,12073980813202008,12073980813333207
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv1/mi100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv1/mi100/sysinfo.csv
index a1638ca20c..44258b9e87 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv1/mi100/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv1/mi100/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-no_roof_K_str_inv1,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 10:52:07 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+no_roof_K_str_inv1,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 10:52:07 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv1/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv1/mi100/timestamps.csv
index 3c3b3eca58..fb14cc4709 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv1/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv1/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,798053,798058,33554432,256,0,0,8,32,6464,0x0,0x7f79d9004180,12073980798009607,12073980798057932,12073980798383529,12073980798490902
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,798053,798058,32768,256,0,0,24,24,12480,0x0,0x7f79d9035100,12073980813032255,12073980813133369,12073980813140729,12073980813146097
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,798053,798058,4194304,256,0,0,24,24,12928,0x7f7ae4d1a900,0x7f79d9035140,12073980813188265,12073980813202008,12073980813333207,12073980813336521
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv1/mi200/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv1/mi200/SQ_IFETCH_LEVEL.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv1/mi200/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv1/mi200/SQ_IFETCH_LEVEL.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv1/mi200/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv1/mi200/SQ_INST_LEVEL_LDS.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv1/mi200/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv1/mi200/SQ_INST_LEVEL_LDS.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv1/mi200/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv1/mi200/SQ_INST_LEVEL_SMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv1/mi200/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv1/mi200/SQ_INST_LEVEL_SMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv1/mi200/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv1/mi200/SQ_INST_LEVEL_VMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv1/mi200/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv1/mi200/SQ_INST_LEVEL_VMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv1/mi200/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv1/mi200/SQ_LEVEL_WAVES.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv1/mi200/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv1/mi200/SQ_LEVEL_WAVES.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv1/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv1/mi200/pmc_perf.csv
index a744458b23..ad4778fe41 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv1/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv1/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,BeginNs,EndNs
+Dispatch_ID,Kernel_Name,Start_Timestamp,End_Timestamp
 ,,14841685400295,14841685640615
 ,,14841690471665,14841690485425
 ,,14841690555665,14841690648306
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv1/mi200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv1/mi200/sysinfo.csv
index f491d32ce5..25a7e27796 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv1/mi200/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv1/mi200/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-no_roof_K_str_inv1,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:00:20 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+no_roof_K_str_inv1,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:00:20 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv1/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv1/mi200/timestamps.csv
index adbab5f303..eeca880ca2 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv1/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv1/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,71093,71093,33554432,256,0,0,4,32,4160,0x0,0x7f5429804280,14841685374494,14841685400295,14841685640615,14841685726625
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,71093,71093,32768,256,0,0,12,24,13888,0x0,0x7f5429823f80,14841690456186,14841690471665,14841690485425,14841690502545
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,71093,71093,4194304,256,0,0,12,24,14336,0x7f542c75a380,0x7f5429823fc0,14841690508615,14841690555665,14841690648306,14841690650592
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv2/mi100/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv2/mi100/SQ_IFETCH_LEVEL.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv2/mi100/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv2/mi100/SQ_IFETCH_LEVEL.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv2/mi100/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv2/mi100/SQ_INST_LEVEL_LDS.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv2/mi100/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv2/mi100/SQ_INST_LEVEL_LDS.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv2/mi100/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv2/mi100/SQ_INST_LEVEL_SMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv2/mi100/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv2/mi100/SQ_INST_LEVEL_SMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv2/mi100/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv2/mi100/SQ_INST_LEVEL_VMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv2/mi100/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv2/mi100/SQ_INST_LEVEL_VMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv2/mi100/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv2/mi100/SQ_LEVEL_WAVES.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv2/mi100/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv2/mi100/SQ_LEVEL_WAVES.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv2/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv2/mi100/pmc_perf.csv
index 645b494693..eb00c9f3f9 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv2/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv2/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,BeginNs,EndNs
+Dispatch_ID,Kernel_Name,Start_Timestamp,End_Timestamp
 ,,12074048574703185,12074048575031342
 ,,12074048589878969,12074048589885849
 ,,12074048589947289,12074048590085208
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv2/mi100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv2/mi100/sysinfo.csv
index fc7ec5fed4..c9394fbbfd 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv2/mi100/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv2/mi100/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-no_roof_K_str_inv2,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 10:53:14 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+no_roof_K_str_inv2,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 10:53:14 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv2/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv2/mi100/timestamps.csv
index de9744e76d..683796f25e 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv2/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv2/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,803058,803063,33554432,256,0,0,8,32,6464,0x0,0x7f8929004180,12074048574655407,12074048574703185,12074048575031342,12074048575137994
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,803058,803063,32768,256,0,0,24,24,12480,0x0,0x7f8929035100,12074048589774560,12074048589878969,12074048589885849,12074048589891387
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,803058,803063,4194304,256,0,0,24,24,12928,0x7f8a34c6f900,0x7f8929035140,12074048589933676,12074048589947289,12074048590085208,12074048590088634
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv2/mi200/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv2/mi200/SQ_IFETCH_LEVEL.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv2/mi200/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv2/mi200/SQ_IFETCH_LEVEL.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv2/mi200/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv2/mi200/SQ_INST_LEVEL_LDS.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv2/mi200/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv2/mi200/SQ_INST_LEVEL_LDS.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv2/mi200/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv2/mi200/SQ_INST_LEVEL_SMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv2/mi200/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv2/mi200/SQ_INST_LEVEL_SMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv2/mi200/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv2/mi200/SQ_INST_LEVEL_VMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv2/mi200/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv2/mi200/SQ_INST_LEVEL_VMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv2/mi200/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv2/mi200/SQ_LEVEL_WAVES.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv2/mi200/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv2/mi200/SQ_LEVEL_WAVES.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv2/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv2/mi200/pmc_perf.csv
index 52c7e1517f..570adb2dcb 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv2/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv2/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,BeginNs,EndNs
+Dispatch_ID,Kernel_Name,Start_Timestamp,End_Timestamp
 ,,14931181662002,14931181900563
 ,,14931186752258,14931186766178
 ,,14931186839938,14931186932258
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv2/mi200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv2/mi200/sysinfo.csv
index 601449a0a8..7d0bec3a37 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv2/mi200/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv2/mi200/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-no_roof_K_str_inv2,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:01:50 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+no_roof_K_str_inv2,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:01:50 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv2/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv2/mi200/timestamps.csv
index e04a03ca85..c5512d35f9 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv2/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv2/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,77195,77195,33554432,256,0,0,4,32,4160,0x0,0x7faeada04280,14931181635852,14931181662002,14931181900563,14931182011543
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,77195,77195,32768,256,0,0,12,24,13888,0x0,0x7faeada23f80,14931186736697,14931186752258,14931186766178,14931186782826
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,77195,77195,4194304,256,0,0,12,24,14336,0x7faeb09a5380,0x7faeada23fc0,14931186790625,14931186839938,14931186932258,14931186934502
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv3/mi100/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv3/mi100/SQ_IFETCH_LEVEL.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv3/mi100/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv3/mi100/SQ_IFETCH_LEVEL.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv3/mi100/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv3/mi100/SQ_INST_LEVEL_LDS.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv3/mi100/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv3/mi100/SQ_INST_LEVEL_LDS.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv3/mi100/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv3/mi100/SQ_INST_LEVEL_SMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv3/mi100/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv3/mi100/SQ_INST_LEVEL_SMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv3/mi100/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv3/mi100/SQ_INST_LEVEL_VMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv3/mi100/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv3/mi100/SQ_INST_LEVEL_VMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv3/mi100/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv3/mi100/SQ_LEVEL_WAVES.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv3/mi100/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv3/mi100/SQ_LEVEL_WAVES.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv3/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv3/mi100/pmc_perf.csv
index 577b22cb0e..cdf18e01a0 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv3/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv3/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,BeginNs,EndNs
+Dispatch_ID,Kernel_Name,Start_Timestamp,End_Timestamp
 ,,12074120223522971,12074120223846488
 ,,12074120239113834,12074120239121354
 ,,12074120239180874,12074120239316072
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv3/mi100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv3/mi100/sysinfo.csv
index 5abefbf05a..16c42ef113 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv3/mi100/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv3/mi100/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-no_roof_K_str_inv3,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 10:54:26 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+no_roof_K_str_inv3,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 10:54:26 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv3/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv3/mi100/timestamps.csv
index 174144329a..36615eba17 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv3/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv3/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,808065,808070,33554432,256,0,0,8,32,6464,0x0,0x7fa36ea04180,12074120223479845,12074120223522971,12074120223846488,12074120223956240
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,808065,808070,32768,256,0,0,24,24,12480,0x0,0x7fa36ea35100,12074120239008248,12074120239113834,12074120239121354,12074120239126237
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,808065,808070,4194304,256,0,0,24,24,12928,0x7fa49ead7900,0x7fa36ea35140,12074120239167053,12074120239180874,12074120239316072,12074120239319096
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv3/mi200/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv3/mi200/SQ_IFETCH_LEVEL.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv3/mi200/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv3/mi200/SQ_IFETCH_LEVEL.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv3/mi200/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv3/mi200/SQ_INST_LEVEL_LDS.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv3/mi200/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv3/mi200/SQ_INST_LEVEL_LDS.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv3/mi200/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv3/mi200/SQ_INST_LEVEL_SMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv3/mi200/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv3/mi200/SQ_INST_LEVEL_SMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv3/mi200/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv3/mi200/SQ_INST_LEVEL_VMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv3/mi200/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv3/mi200/SQ_INST_LEVEL_VMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv3/mi200/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv3/mi200/SQ_LEVEL_WAVES.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv3/mi200/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv3/mi200/SQ_LEVEL_WAVES.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv3/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv3/mi200/pmc_perf.csv
index 6f4fb03725..bda41ac671 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv3/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv3/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,BeginNs,EndNs
+Dispatch_ID,Kernel_Name,Start_Timestamp,End_Timestamp
 ,,15020762055322,15020762295802
 ,,15020767117893,15020767131333
 ,,15020767202053,15020767294374
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv3/mi200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv3/mi200/sysinfo.csv
index 4e8bc45d87..c4630543b0 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv3/mi200/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv3/mi200/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-no_roof_K_str_inv3,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:03:20 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+no_roof_K_str_inv3,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:03:20 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv3/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv3/mi200/timestamps.csv
index b76fe792f1..810594c2a9 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv3/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_inv3/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,83298,83298,33554432,256,0,0,4,32,4160,0x0,0x7f0920604280,15020762028139,15020762055322,15020762295802,15020762310902
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,83298,83298,32768,256,0,0,12,24,13888,0x0,0x7f0920623f80,15020767101717,15020767117893,15020767131333,15020767148466
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,83298,83298,4194304,256,0,0,12,24,14336,0x7f0923692380,0x7f0920623fc0,15020767154026,15020767202053,15020767294374,15020767296772
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi100/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi100/SQ_IFETCH_LEVEL.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi100/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi100/SQ_IFETCH_LEVEL.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi100/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi100/SQ_INST_LEVEL_LDS.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi100/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi100/SQ_INST_LEVEL_LDS.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi100/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi100/SQ_INST_LEVEL_SMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi100/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi100/SQ_INST_LEVEL_SMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi100/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi100/SQ_INST_LEVEL_VMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi100/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi100/SQ_INST_LEVEL_VMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi100/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi100/SQ_LEVEL_WAVES.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi100/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi100/SQ_LEVEL_WAVES.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi100/pmc_perf.csv
index 5ce452ad39..48a445b6af 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,BeginNs,EndNs
+Dispatch_ID,Kernel_Name,Start_Timestamp,End_Timestamp
 ,,12073588591494210,12073588591817567
 ,,12073588606571402,12073588606578441
 ,,12073588606643241,12073588606777000
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi100/sysinfo.csv
index d6927a5a96..8bd87032b9 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi100/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi100/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-no_roof_K_str_valid_1,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 10:45:34 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+no_roof_K_str_valid_1,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 10:45:34 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi100/timestamps.csv
index c9a14ea519..048a720aac 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,772988,772993,33554432,256,0,0,8,32,6464,0x0,0x7fb674c04180,12073588591446161,12073588591494210,12073588591817567,12073588591923859
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,772988,772993,32768,256,0,0,24,24,12480,0x0,0x7fb674c35100,12073588606470502,12073588606571402,12073588606578441,12073588606584394
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,772988,772993,4194304,256,0,0,24,24,12928,0x7fb780943900,0x7fb674c35140,12073588606630239,12073588606643241,12073588606777000,12073588606780799
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/SQ_IFETCH_LEVEL.csv
index 989a328210..b09a8c70ff 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/SQ_IFETCH_LEVEL.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,44513,44513,33554432,256,0,0,4,32,4160,0x0,0x7fb9c7c04280,376336,376336,524288,4718592,681997,76343864,14448897372628,14448164014392,14449040873709,14449040986798
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/SQ_INST_LEVEL_LDS.csv
index 976b2ce3ef..5a3da53392 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/SQ_INST_LEVEL_LDS.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,46365,46365,33554432,256,0,0,4,32,4160,0x0,0x7f8c29e04280,0,0,0,14463139413387,14462403477330,14463287878525,14463287993104
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/SQ_INST_LEVEL_SMEM.csv
index 86c1f2b5ff..25f2e5126b 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/SQ_INST_LEVEL_SMEM.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,44290,44290,33554432,256,0,0,4,32,4160,0x0,0x7f58ffc04280,3670016,3098192,347303192,14448015163654,14419898526910,14448164014600,14448164128069
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/SQ_INST_LEVEL_VMEM.csv
index 9b4a1eb8ac..c5662c6745 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/SQ_INST_LEVEL_VMEM.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,46142,46142,33554432,256,0,0,4,32,4160,0x0,0x7f4022804280,524288,5226796,585379448,14462253958391,14461269181726,14462403477387,14462403591256
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/SQ_LEVEL_WAVES.csv
index c181a6c6fc..b22624890e 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/SQ_LEVEL_WAVES.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,44736,44736,33554432,256,0,0,4,32,4160,0x0,0x7f4347c04280,380973,380973,8827,3047792,524288,239485259,2961262,0,974188708,14449773045699,14449040873501,14449925047669,14449925160848
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/pmc_dispatch_info.csv
index 8226fe9c0f..63bb17b9f9 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/pmc_dispatch_info.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/pmc_perf.csv
index 0df982629a..4d1852bbb1 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/pmc_perf.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDI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],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBufferAligned.kd,0,0,0,45503,45503,33554432,256,0,0,4,32,4160,0x0,0x7ff046c04280,3080352,2993399,524288,38889002,243827034,392,224,0,385043,385043,39155498.0,38156322.0,0.0,4162775.0,31337961.0,30976633.0,38136073.0,37577553.0,3078641,2999799,385043,0,385043,0,12321376.0,9457102.0,0.0,0.0,0,0,616,0,4718592,4715055,112,3425,375034,0.0,0.0,0.0,524288.0,28447851.0,27724801.0,7663.0,524288.0,131072,524288,302,384159,2277,0,56.0,302.0,0.0,4194696.0,0,0,0,0,0,7340032,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,20088460.0,524288.0,0,384151,0,0,0,384151,0,0,0,384151,0,0,0,384151,0,0,0,384151,0,0,0,384151,0,0,0,384151,0,0,0,384151,0,0,0,384151,0,0,0,384151,0,0,0,384151,0,0,0,384151,0,0,0,384151,0,0,0,384151,0,0,0,384151,0,0,0,384151,0,0,0,384151,0,0,0,384151,0,0,0,384151,0,0,0,384151,0,0,0,384151,0,0,0,384151,0,0,0,384151,0,0,0,384151,0,0,0,384151,0,0,0,384151,0,0,0,384151,0,0,0,384151,0,0,0,384151,0,0,0,384151,0,0,0,384151,0,0,0,384151,0,0,0,0,0,0.0,21442838.0,32,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2,0,0,0,168,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,35,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,4,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,1,0,0,0,524288.0,0.0,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,43896,129024,129024,0,842,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,209055,129024,129024,0,910,129024,129024,0,43525,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,214,129024,129024,0,201,129024,129024,0,28345,129024,129024,0,1002,129024,129024,0,186,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,340468,129024,129024,0,185,129024,129024,524288.0,0.0,43136,0,0,50141013,44406,0,0,50472613,43963,0,0,50078967,47370,0,0,52172033,44554,0,0,51081966,46049,0,0,51445983,43934,0,0,50474332,47563,0,0,52661220,44678,0,0,50647238,45634,0,0,50695463,44312,0,0,50097667,48378,0,0,52314257,45293,0,0,51438662,47063,0,0,51714932,45947,0,0,51009388,48783,0,0,53057415,44472,0,0,50497395,45998,0,0,50865051,44139,0,0,50045342,47651,0,0,52302277,44594,0,0,51098894,45201,0,0,51278726,44558,0,0,50588564,47369,0,0,52353191,45618,0,0,50713710,45431,0,0,50782829,44810,0,0,50170173,48390,0,0,52324680,46932,0,0,51848716,47038,0,0,51562468,45689,0,0,51073583,49807,0,0,53292027,0.0,65536,65568,32,131104,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65646,65538,112,131184,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65568,32,131104,65536,65536,0,131072,65536,65648,112,131184,65536,65536,0,131072,65536,65536,0,131072,65536,65537,1,131073,65536,65536,0,131072,65536,65592,56,131128,65591,65537,56,131128,65536,65571,35,131107,65536,65536,0,131072,65536,65537,1,131073,65536,65536,0,131072,65758,65538,224,131296,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65568,32,131104,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65591,65537,56,131128,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131184,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131296,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131128,0,131072,1140640,0,524288,3670016,3663227,224,6565,1048576,33554432.0,33554432.0,0.0,33554432.0,30311548.0,28676573.0,0.0,524288.0,220562,535985,8520,922,0,385284,4195052.0,0.0,2097594.0,2097458.0,1048576,1048576,0,524288,0,524288,7340032,0,0.0,0.0,104.0,8388608.0,29317160.0,2097152.0,0.0,198914,0,1209,382194,0,752.0,4194304.0,0.0,2064387.0,25690112,9437184,0,0,0,0,0,0,13296.0,8242352.0,0.0,8388608.0,2097152.0,4194304.0,9783063,0,0,8659,4128768.0,4128768.0,0.0,1493649.0,0,0,0,0,0,0,5767168,1048576,315833810.0,0.0,1473792300.0,0.0,30.0,0.0,0,0,372295,0.0,0.0,1476088.0,0.0,3670016,524288,0,0,0,2621440,524288,176659623,4194304.0,0.0,0.0,0.0,0.0,1216303.0,0,0,0.0,312.0,0.0,608.0,42323832,24117248,0,0,9437184,11010048,0,3145728,0.0,0.0,0.0,0.0,0.0,0.0,0,1572864,0.0,0.0,0.0,187746.0,524288,524288,0,3670016,7340032,603979776,4718592,0,0.0,0.0,0.0,0.0,0.0,0.0,524288,0,2064384.0,0.0,2031624.0,0.0,0,0,524288,0,0,0,0,33554432,0.0,4194304.0,0.0,19071194.0,0.0,0.0,140.0,4128768.0,653521.0,1649874973.0,14451158716902,14463900844097,14463901083617,14451305823418
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/prev_analysis/1.csv
index 961f4d1540..2d79d1e736 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/prev_analysis/1.csv
@@ -1,2 +1,2 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 __amd_rocclr_fillBufferAligned.kd,1,239520.0,239520.0,239520.0,100.0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/prev_analysis/1001.csv
index e34ed0c6f6..0850fc4acd 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,18.0,Instr per wave
 VMEM,1.0,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,0.0,Instr per wave
 SALU,14.0,Instr per wave
 SMEM,7.0,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/prev_analysis/101.csv
index 61d48bffb0..e9df61908b 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx90a
 mi200
 56
 1638.4
-SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/prev_analysis/1202.csv
index bc32bc20b9..9552a52f47 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,1860.2526397705078,1860.2526397705078,1860.2526397705078,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/prev_analysis/1901.csv
index 162ee9a5d2..6a2fa2660f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,7.0,smem_
 VALU,18.0,valu_
 MFMA,0.0,mfma_
 VMEM,1.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,5.0,br_
 VGPR,4.0,vgpr_
 SGPR,32.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,524288.0,wavefronts_
 Workgroups,131072.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,9.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,8.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,0.0,hbm_rd_
 HBM Wr,8.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,25.0,vl1_coales_
 VL1 Stall,11.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,25.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/prev_analysis/2001.csv
index 8226fe9c0f..63bb17b9f9 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/prev_analysis/2001.csv
@@ -1,2 +1,2 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/prev_analysis/201.csv
index 575a9d7068..864b2cf214 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,23.566758477924242,Pct,100,23.566758477924242
 MFMA Util,0.0,Pct,100,0.0
 VALU Active Threads/Wave,64.0,Threads,64,100.0
 IPC - Issue,1.0,Instr/cycle,5,20.0
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99762468646392,Pct,100,99.99762468646392
 Instr Cache BW,1260.8128256513025,Gb/s,6092.8,20.69348781596807
 Scalar L1D Cache Hit Rate,99.99388554671538,Pct,100,99.99388554671538
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/prev_analysis/602.csv
index eecbd2bd9f..817776642a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,9783063.0,9783063,9783063,Simd
 Insufficient SIMD VGPRs,0.0,0,0,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/prev_analysis/701.csv
index c47e77a25f..f8ed8cd0d3 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,4.0,4,4,Registers
 SGPRs,32.0,32,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/sysinfo.csv
index bedb81206f..af9aecb450 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-no_roof_K_str_valid_1,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 19:54:03 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+no_roof_K_str_valid_1,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 19:54:03 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/timestamps.csv
index e83c34f9d5..eefa9fd488 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_1/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,46448,46448,33554432,256,0,0,4,32,4160,0x0,0x7f8e84604280,14463900819187,14463900844097,14463901083617,14463901175016
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,46448,46448,32768,256,0,0,12,24,13888,0x0,0x7f8e84623f80,14463905847103,14463905862813,14463905876413,14463905894372
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,46448,46448,4194304,256,0,0,12,24,14336,0x7f8ea2e13380,0x7f8e84623fc0,14463905898542,14463905944893,14463906036893,14463906039168
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/SQ_IFETCH_LEVEL.csv
index dae6f8b73f..a36de17f1b 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/SQ_IFETCH_LEVEL.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,775962,775967,32768,256,0,0,24,24,12480,0x0,0x7fe812a35100,28095,28095,512,8192,8964,1155984,12073651922092234,12073652162626612,12073652162633172,12073652162650563
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,775962,775967,4194304,256,0,0,24,24,12928,0x7fe91e57b900,0x7fe812a35140,215683,215683,65536,917504,146713,18785300,12073652162709753,12073652166086314,12073652166217513,12073652166223122
 3,"void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 0u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",0,0,6,775962,775967,4194304,256,0,0,36,24,13632,0x7fe91e57b800,0x7fe812a35180,384329,384329,65536,1245184,180380,23109400,12073652166285989,12073652166502952,12073652166748071,12073652166817627
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/SQ_INST_LEVEL_LDS.csv
index 6395f9f3b4..7f24b7585f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/SQ_INST_LEVEL_LDS.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,777768,777773,32768,256,0,0,24,24,12480,0x0,0x7f36e6235100,0,0,0,12073678195944575,12073678440445034,12073678440450954,12073678440469336
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,777768,777773,4194304,256,0,0,24,24,12928,0x7f37f1f4d900,0x7f36e6235140,0,0,0,12073678440522845,12073678443951858,12073678444084817,12073678444088843
 3,"void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 0u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",0,0,6,777768,777773,4194304,256,0,0,36,24,13632,0x7f37f1f4d800,0x7f36e6235180,0,0,0,12073678444155757,12073678444332816,12073678444583695,12073678444651989
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/SQ_INST_LEVEL_SMEM.csv
index 2f9faea324..5a9a4a854c 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/SQ_INST_LEVEL_SMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,777387,777392,32768,256,0,0,24,24,12480,0x0,0x7f9cc7235100,512,22346,2851448,12073675650850447,12073675896937872,12073675896944112,12073675896960904
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,777387,777392,4194304,256,0,0,24,24,12928,0x7f9df753f900,0x7f9cc7235140,65536,170396,21833240,12073675897031595,12073675900372735,12073675900512574,12073675900516371
 3,"void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 0u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",0,0,6,777387,777392,4194304,256,0,0,36,24,13632,0x7f9df753f800,0x7f9cc7235180,65536,161112,20599968,12073675900583927,12073675900762173,12073675901023132,12073675901091019
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/SQ_INST_LEVEL_VMEM.csv
index 2424175af6..9a77481274 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/SQ_INST_LEVEL_VMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,777578,777583,32768,256,0,0,24,24,12480,0x0,0x7fe2b4835100,4096,119293,15255336,12073676921659065,12073677171755972,12073677171763012,12073677171779354
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,777578,777583,4194304,256,0,0,24,24,12928,0x7fe3c04af900,0x7fe2b4835140,524288,10373638,1327819836,12073677171850156,12073677175172037,12073677175312677,12073677175316418
 3,"void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 0u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",0,0,6,777578,777583,4194304,256,0,0,36,24,13632,0x7fe3c04af800,0x7fe2b4835180,524288,13288805,1700886432,12073677175374666,12073677175547236,12073677175803715,12073677175871249
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/SQ_LEVEL_WAVES.csv
index 898803965f..88514f0d0d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/SQ_LEVEL_WAVES.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,777957,777962,32768,256,0,0,24,24,12480,0x0,0x7f8860435100,27953,27953,20673,223632,512,1081504,74149,0,4340216,12073679457248310,12073679705398428,12073679705404988,12073679705420780
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,777957,777962,4194304,256,0,0,24,24,12928,0x7f896c0e2900,0x7f8860435140,216892,216892,19309,1735144,65536,144549520,1566090,0,580016492,12073679705487454,12073679708915491,12073679709047971,12073679709052138
 3,"void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 0u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",0,0,6,777957,777962,4194304,256,0,0,36,24,13632,0x7f896c0e2800,0x7f8860435180,397468,397468,32768,3179752,65536,242406065,2982773,0,971441212,12073679709124383,12073679709326210,12073679709576609,12073679709641894
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/pmc_dispatch_info.csv
index 4544bf0858..8f3ca42ca4 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
 3,"void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 0u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/pmc_perf.csv
index 4abc1f4ae4..a12199b087 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,776699,776704,32768,256,0,0,24,24,12480,0x0,0x7f9842635100,0,4096,4096,512,0,512,4096,0,28383,28383,1522605,599324,192,127745,75124,54888,591240,570745,227064,85954,28383,0,28383,0,908256,195684,0,0,0,0,0,52221,4096,0,29070,0,0,0,29070,0,0,0,29070,0,0,0,29070,0,0,0,29070,0,0,0,29070,0,0,0,29070,0,0,0,29070,0,0,0,29070,0,0,0,29070,0,0,0,29070,0,0,0,29070,0,0,0,29070,0,0,0,29070,0,0,0,29070,0,0,0,29070,0,0,0,29070,0,0,0,29070,0,0,0,29070,0,0,0,29070,0,0,0,29070,0,0,0,29070,0,0,0,29070,0,0,0,29070,0,0,0,29070,0,0,0,29070,0,0,0,29070,0,0,0,29070,0,0,0,29070,0,0,0,29070,0,0,0,29070,0,0,0,29070,0,0,0,0,257,0,0,0,304,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,257,0,0,0,376,0,0,0,4096,4096,0,103277,0,0,0,85021,0,0,0,78040,0,0,0,83250,0,0,0,96529,0,0,0,120356,0,0,0,85621,0,0,0,104205,0,0,0,145551,0,0,0,110862,0,0,0,113562,0,0,0,85687,0,0,0,120851,0,0,0,87876,0,0,0,69568,0,0,0,66767,0,0,0,102553,0,0,0,124280,0,0,0,94785,0,0,0,167194,0,0,0,133961,0,0,0,188631,0,0,0,100056,0,0,0,90095,0,0,0,98822,0,0,0,93794,0,0,0,95050,0,0,0,83311,0,0,0,169088,0,0,0,80524,0,0,0,79402,0,0,0,80610,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4096,0,256,256,256,0,256,256,256,0,257,257,257,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,376,376,376,0,256,256,256,0,256,256,256,0,256,256,256,188,260,448,448,0,305,305,305,0,256,256,256,0,256,256,256,235,261,496,496,0,256,256,256,0,256,256,256,0,256,256,256,0,304,304,304,0,256,256,256,0,256,256,256,0,256,256,256,0,257,257,257,0,256,256,256,0,256,256,256,0,256,256,256,47,258,305,305,0,256,256,256,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,304,0,0,256,0,0,0,0,512,512,35328,1089193,1034321,18520,11308,0,0,0,4096,44081,41976,4096,4096,128,512,586,26800,4253,0,48,219,0,8624,36352,225792,79764,1100173,26624,0,0,30208,65536,65536,65536,0,0,0,0,0,113,625,11198,2496,0,24159,8892,0,470,8422,1024,0,1024,4096,0,4096,512,512,0,0,360,16384,0,16384,0,0,2882,25601,0,8892,0,0,31,1933312,8192,0,0,0,512,512,0,120,15064,0,16384,16384,0,0,0,0,20824,0,0,0,0,0,0,0,32768,0,0,0,0,12528952,17665468,0,8192,0,0,0,0,694,0,0,0,0,0,1024,432,48,0,0,0,480,0,0,0,0,0,3206,0,0,0,8374,0,344,0,8192,6710,48,1434,1102,0,0,0,0,0,0,0,0,0,2560,0,0,0,46076,512,0,48,464,0,512,0,0,0,0,0,0,0,512,0,0,0,0,0,8192,0,0,438187,0,4096,8421,0,3105040,0,12073654023556749,12073680578843076,12073680579165793,12073654266377052
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,776699,776704,4194304,256,0,0,24,24,12928,0x7f994e22c900,0x7f9842635140,0,524288,524288,65536,0,65536,524288,0,224905,224905,24996297,23811740,30425,5984101,23439359,23377600,23800980,21643213,1799240,1650023,224905,0,224905,0,7196960,6486962,0,0,0,0,0,20325195,524288,0,218806,0,0,0,218806,0,0,0,218806,0,0,0,218806,0,0,0,218806,0,0,0,218806,0,0,0,218806,0,0,0,218806,0,0,0,218806,0,0,0,218806,0,0,0,218806,0,0,0,218806,0,0,0,218806,0,0,0,218806,0,0,0,218806,0,0,0,218806,0,0,0,218806,0,0,0,218806,0,0,0,218806,0,0,0,218806,0,0,0,218806,0,0,0,218806,0,0,0,218806,0,0,0,218806,0,0,0,218806,0,0,0,218806,0,0,0,218806,0,0,0,218806,0,0,0,218806,0,0,0,218806,0,0,0,218806,0,0,0,218806,0,0,0,0,65537,0,8935,0,65584,0,2714,0,65540,0,4713,0,65536,0,9184,0,65537,0,11784,0,65537,0,2038,0,65536,0,12523,0,68335,0,102253,0,65536,0,2910,0,65536,0,8613,0,65536,0,1186,0,65536,0,11824,0,65537,0,5030,0,65536,0,1704,0,65536,0,0,0,65536,0,4356,0,65536,0,0,0,65536,0,8371,0,65536,0,1395,0,65536,0,18581,0,65536,0,2213,0,65536,0,6289,0,65536,0,2795,0,65536,0,4313,0,65536,0,0,0,65536,0,5645,0,65536,0,2141,0,66654,0,47669,0,65536,0,5449,0,65537,0,4045,0,65540,0,6396,0,65656,0,5173,0,524288,524288,0,53123495,0,0,0,26994482,0,0,0,28970619,0,0,0,28450300,0,0,0,28311872,0,0,0,28131314,0,0,0,27105742,0,0,0,30094103,0,0,0,23660153,0,0,0,27709379,0,0,0,26424633,0,0,0,27950085,0,0,0,27181504,0,0,0,28298733,0,0,0,26754952,0,0,0,29107386,0,0,0,29820923,0,0,0,29084861,0,0,0,27615800,0,0,0,29310005,0,0,0,28207078,0,0,0,29105674,0,0,0,27377408,0,0,0,27116500,0,0,0,43831147,0,0,0,27628061,0,0,0,26575344,0,0,0,28569797,0,0,0,26958947,0,0,0,28420904,0,0,0,28350266,0,0,0,24064998,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,524288,0,65536,65536,65536,0,65536,65536,65536,188,65541,65729,65729,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65656,65656,65656,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65585,65585,65585,0,66316,66316,66316,0,65536,65536,65536,47,65537,65584,65584,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,66488,66488,66488,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65537,65537,65537,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,188,65541,65729,65729,0,65536,65536,65536,65536,0,0,65536,0,0,65728,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65728,0,0,65536,0,0,0,0,65536,65536,4128768,141636224,51815247,85561137,200549,0,0,0,524288,22533025,22528211,524288,524288,16384,65536,726,217798,4178,0,48,2908,0,2097536,4259840,1791160,1619170,23983978,3014656,0,0,3473408,8388608,8388608,8388608,0,0,0,0,0,151777,186652,11220,2428,0,219893,2101696,0,423,2101273,131072,0,131072,524288,0,524288,65536,65536,0,0,360,2097152,0,2097152,30078,0,2879,227562,0,2102996,0,0,31,222298112,917504,0,0,0,65536,65536,0,7608,2014358,0,2097152,2097152,0,601844,603509,0,20374,0,0,0,0,0,0,0,4194304,0,0,0,0,861742369,1335345662,0,2097152,0,0,0,0,200236,0,0,0,0,0,131072,384,48,0,0,0,432,0,0,0,0,0,6855,0,0,0,2100761,0,7200,0,917504,914826,48,7478,193179,0,0,0,0,0,0,0,0,0,327680,0,0,192287,245468,65536,64048,48,1440,0,65536,0,0,0,0,0,0,0,65536,0,0,0,1966105,0,2097152,0,0,14611816,0,524288,2101749,0,871890466,0,12073654266997154,12073680593660944,12073680593667504,12073654271343782
 3,"void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 0u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",0,0,6,776699,776704,4194304,256,0,0,36,24,13632,0x7f994e22c800,0x7f9842635180,0,524288,524288,917504,0,65536,524288,0,394837,394837,45414407,44201687,0,22279911,42742961,42457875,44192928,35800109,3158696,3011129,394837,0,394837,0,12634784,11920478,0,0,0,0,0,34604803,524288,0,386502,0,0,0,386502,0,0,0,386502,0,0,0,386502,0,0,0,386502,0,0,0,386502,0,0,0,386502,0,0,0,386502,0,0,0,386502,0,0,0,386502,0,0,0,386502,0,0,0,386502,0,0,0,386502,0,0,0,386502,0,0,0,386502,0,0,0,386502,0,0,0,386502,0,0,0,386502,0,0,0,386502,0,0,0,386502,0,0,0,386502,0,0,0,386502,0,0,0,386502,0,0,0,386502,0,0,0,386502,0,0,0,386502,0,0,0,386502,0,0,0,386502,0,0,0,386502,0,0,0,386502,0,0,0,386502,0,0,0,386502,0,0,0,0,131073,0,7068,0,131120,0,21801,0,131072,0,8399,0,131072,0,5912,0,131073,0,13968,0,131073,0,11081,0,131076,0,35583,0,132446,0,165707,0,131072,0,2752,0,131072,0,5190,0,131072,0,16820,0,131714,0,90760,0,131073,0,42421,0,131072,0,46568,0,131072,0,8461,0,131072,0,0,0,131072,0,21584,0,131072,0,52734,0,131072,0,11686,0,131072,0,36251,0,131072,0,5963,0,131072,0,12504,0,131074,0,12449,0,131570,0,32291,0,131072,0,24697,0,131072,0,35438,0,131076,0,6578,0,131137,0,10855,0,131072,0,2504,0,131073,0,7751,0,131072,0,8164,0,131192,0,28053,0,524288,524288,0,93403849,0,0,0,66093476,0,0,0,67302871,0,0,0,66531398,0,0,0,89815180,0,0,0,68940514,0,0,0,67078600,0,0,0,61187281,0,0,0,62765856,0,0,0,60577504,0,0,0,58503200,0,0,0,68063801,0,0,0,68479444,0,0,0,77608355,0,0,0,71021259,0,0,0,67247510,0,0,0,67417326,0,0,0,66394157,0,0,0,69892920,0,0,0,71235696,0,0,0,72608484,0,0,0,62938651,0,0,0,59659948,0,0,0,61118228,0,0,0,82718263,0,0,0,64637768,0,0,0,56878961,0,0,0,65268030,0,0,0,66833150,0,0,0,65325436,0,0,0,69089955,0,0,0,65602370,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,131072,131072,131072,0,131072,131072,131072,0,131073,131073,131073,0,131072,131072,131072,0,131072,131072,131072,0,131072,131072,131072,188,131076,131264,131264,0,131072,131072,131072,0,131072,131072,131072,0,131072,131072,131072,0,131192,131192,131192,0,131072,131072,131072,0,132512,132512,132512,0,131072,131072,131072,0,131072,131072,131072,0,131121,131121,131121,0,131227,131227,131227,0,131072,131072,131072,47,131073,131120,131120,0,131072,131072,131072,0,131072,131072,131072,0,131072,131072,131072,94,132328,132422,132422,0,131072,131072,131072,0,131072,131072,131072,0,131072,131072,131072,188,131077,131265,131265,0,131072,131072,131072,0,131137,131137,131137,0,131072,131072,131072,0,131073,131073,131073,0,131072,131072,131072,131072,0,0,131072,0,0,131072,0,0,131072,0,0,131072,0,0,131072,0,0,131264,0,0,131072,0,0,131072,0,0,131072,0,0,131072,0,0,131072,0,0,131072,0,0,131072,0,0,131072,0,0,131072,0,0,131072,0,0,131072,0,0,131072,0,0,131072,0,0,131072,0,0,131072,0,0,131168,0,0,131072,0,0,131072,0,0,131072,0,0,131264,0,0,131072,0,0,131072,0,0,131072,0,0,131072,0,0,131072,0,0,0,0,131072,65536,6291456,223071589,55420450,161228611,376034,0,0,0,524288,43308473,43301311,0,524288,16384,65536,704,393145,4128,0,48,3205,0,4194784,6422528,3139256,2974545,44402188,4259840,0,0,4718592,33554432,33554432,33554432,0,0,0,0,0,448884,371800,11517,2411,0,388436,4196224,0,517,4195707,983040,0,196608,524288,0,524288,65536,917504,0,0,360,8388608,0,2097152,125500,0,2874,399951,0,4198067,0,0,31,301989888,1245184,0,0,0,65536,65536,0,14559,8231781,0,8388608,2097152,0,0,5799086,0,24280,0,0,0,0,0,0,0,4194304,0,0,0,0,1025159273,3746835902,0,4194304,0,0,0,0,364293,0,0,0,0,0,131072,480,48,0,0,0,528,0,0,0,0,0,1506,0,0,0,4197464,0,6298,0,1245184,1240614,48,7594,180061,0,0,0,0,0,0,0,0,0,327680,0,0,1003395,1057281,65536,64048,48,1440,0,65536,0,0,0,0,0,0,0,65536,0,0,0,4063263,0,4194304,0,0,32421268,0,0,4196625,0,2366481368,0,12073654271968273,12073680593730224,12073680593861263,12073654273374346
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/prev_analysis/1.csv
index 360e314a29..3de885bbb2 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<double, 256, 8u, 512u>(double, double*) [clone .kd]",1,6055952.0,6055952.0,6055952.0,9.861963818845169
 "void benchmark_func<double, 256, 8u, 256u>(double, double*) [clone .kd]",1,3055016.0,3055016.0,3055016.0,4.975015861749414
 "void benchmark_func<__half2, 256, 8u, 512u>(__half2, __half2*) [clone .kd]",1,3042856.0,3042856.0,3042856.0,4.955213610998887
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/prev_analysis/1001.csv
index 1e8362a8e4..c706f4c2f5 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,47.036144578313255,Instr per wave
 SMEM,1.7710843373493976,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/prev_analysis/101.csv
index c01e4b171b..aac1cab12e 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx908
 mi100
 48
 1228.8
-SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/prev_analysis/1202.csv
index fec416f1ee..1cc354dc41 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,34072.097686399895,8282.283996582031,547943.4234619141,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/prev_analysis/1901.csv
index 89186afd6d..a9f889fb82 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,2.0,smem_
 VALU,739.0,valu_
 MFMA,,mfma_
 VMEM,8.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,22.0,br_
 VGPR,24.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,65144.0,wavefronts_
 Workgroups,16286.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,164.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,0.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,45.0,hbm_rd_
 HBM Wr,0.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,70.0,vl1_coales_
 VL1 Stall,29.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,36.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/prev_analysis/2001.csv
index 4544bf0858..8f3ca42ca4 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
 3,"void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 0u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/prev_analysis/201.csv
index 94d2ff3a90..48e0eeeb69 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,59.66759608770426,Pct,100,59.66759608770426
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,63.967394162016944,Threads,64,99.94905337815148
 IPC - Issue,0.8432685624171746,Instr/cycle,5,16.865371248343493
-LDS BW,0.0,Gb/sec,23070.72,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,23070.72,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99349467178565,Pct,100,99.99349467178565
 Instr Cache BW,1871.8430027726747,Gb/s,4614.144,40.567502938197734
 Scalar L1D Cache Hit Rate,99.35234690234445,Pct,100,99.35234690234445
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/prev_analysis/602.csv
index eeef97530f..0df38cffca 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,53471.53614457831,0,601844,Simd
 Insufficient SIMD VGPRs,607217.8313253012,0,40859796,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/prev_analysis/701.csv
index 878c96c694..aa09824713 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,24.072289156626507,12,36,Registers
 SGPRs,24.0,24,24,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/sysinfo.csv
index 9a4aec0dbe..f8929d2fe6 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-no_roof_K_str_valid_2,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 10:47:06 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+no_roof_K_str_valid_2,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 10:47:06 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/timestamps.csv
index 6539e6c280..3aaa0b6edb 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,778008,778013,33554432,256,0,0,8,32,6464,0x0,0x7f2ed5804180,12073680578796416,12073680578843076,12073680579165793,12073680579274515
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,778008,778013,32768,256,0,0,24,24,12480,0x0,0x7f2ed5835100,12073680593560744,12073680593660944,12073680593667504,12073680593673153
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,778008,778013,4194304,256,0,0,24,24,12928,0x7f2fe13d4900,0x7f2ed5835140,12073680593717145,12073680593730224,12073680593861263,12073680593864739
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/SQ_IFETCH_LEVEL.csv
index e63e22e1ba..c6572ed7b9 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/SQ_IFETCH_LEVEL.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,50615,50615,33554432,256,0,0,4,32,4160,0x0,0x7f106c204280,381662,381662,524288,4718592,682781,76474668,14549135283508,14548430677620,14549278636490,14549278723480
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,50615,50615,32768,256,0,0,12,24,13888,0x0,0x7f106c223f80,33344,33344,512,8192,7667,853584,14549283804850,14549278636490,14549283942091,14549283946636
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,50615,50615,4194304,256,0,0,12,24,14336,0x7f106f1e2380,0x7f106c223fc0,165184,165184,65536,917504,140178,15722936,14549283985335,14549283942091,14549284323372,14549284326005
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/SQ_INST_LEVEL_LDS.csv
index 388374e223..8fe1353a03 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/SQ_INST_LEVEL_LDS.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,52467,52467,33554432,256,0,0,4,32,4160,0x0,0x7f247c604280,0,0,0,14568190565521,14567484194809,14568337405668,14568337516787
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,52467,52467,32768,256,0,0,12,24,13888,0x0,0x7f247c623f80,0,0,0,14568342677176,14568337405668,14568342807746,14568342812342
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,52467,52467,4194304,256,0,0,12,24,14336,0x7f247f5c5380,0x7f247c623fc0,0,0,0,14568342848271,14568342807746,14568343182786,14568343185282
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/SQ_INST_LEVEL_SMEM.csv
index c1f72f7a61..2202a5e196 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/SQ_INST_LEVEL_SMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,50392,50392,33554432,256,0,0,4,32,4160,0x0,0x7ff1c8004280,3670016,3072532,343952688,14548206813282,14520270043680,14548351630982,14548351743681
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,50392,50392,32768,256,0,0,12,24,13888,0x0,0x7ff1c8023f80,512,98024,11004312,14548356892740,14548351630982,14548357021063,14548357025506
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,50392,50392,4194304,256,0,0,12,24,14336,0x7ff1e68b2380,0x7ff1c8023fc0,65536,624754,69900272,14548357059645,14548357021063,14548357375943,14548357378546
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/SQ_INST_LEVEL_VMEM.csv
index f5710abb6d..6664a53ce2 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/SQ_INST_LEVEL_VMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,52244,52244,33554432,256,0,0,4,32,4160,0x0,0x7f3a31204280,524288,5474310,613169220,14567261939029,14564984375285,14567405775876,14567405888595
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,52244,52244,32768,256,0,0,12,24,13888,0x0,0x7f3a31223f80,4096,43125,4828188,14567411038484,14567405775876,14567411178434,14567411183100
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,52244,52244,4194304,256,0,0,12,24,14336,0x7f3a341c6380,0x7f3a31223fc0,524288,10703754,1198787932,14567411217799,14567411178434,14567411543394,14567411546020
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/SQ_LEVEL_WAVES.csv
index f3c625968a..8619c30570 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/SQ_LEVEL_WAVES.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,50838,50838,33554432,256,0,0,4,32,4160,0x0,0x7f8972804280,384122,384122,9114,3072984,524288,240909359,2983329,0,979898464,14550060425166,14549360686396,14550209453811,14550209564501
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,50838,50838,32768,256,0,0,12,24,13888,0x0,0x7f8972823f80,33113,33113,29609,264912,512,1684346,156174,0,6750792,14550214684021,14550209453811,14550214820371,14550214825127
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,50838,50838,4194304,256,0,0,12,24,14336,0x7f89757a8380,0x7f8972823fc0,165182,165182,13559,1321464,65536,74540865,1215222,0,299899252,14550214868916,14550214820371,14550215215411,14550215217776
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/pmc_perf.csv
index 7aea37e112..a0eaf40efb 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDI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],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBufferAligned.kd,0,0,0,51605,51605,33554432,256,0,0,4,32,4160,0x0,0x7fbfc3c04280,3063136,2976354,524288,38669290,240448685,392,224,0,382891,382891,38935460.0,37994768.0,3.0,4056655.0,31087082.0,30710737.0,37972333.0,37413620.0,3061425,2982763,382891,0,382891,0,12252512.0,9400642.0,0.0,0.0,0,0,616,0,4718592,4714902,112,3578,376935,0.0,0.0,0.0,524288.0,28633154.0,27910627.0,7688.0,524288.0,131072,524288,302,386054,2274,0,56.0,306.0,0.0,4194696.0,0,0,0,0,0,7340032,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,20027762.0,524288.0,0,382855,0,0,0,382855,0,0,0,382855,0,0,0,382855,0,0,0,382855,0,0,0,382855,0,0,0,382855,0,0,0,382855,0,0,0,382855,0,0,0,382855,0,0,0,382855,0,0,0,382855,0,0,0,382855,0,0,0,382855,0,0,0,382855,0,0,0,382855,0,0,0,382855,0,0,0,382855,0,0,0,382855,0,0,0,382855,0,0,0,382855,0,0,0,382855,0,0,0,382855,0,0,0,382855,0,0,0,382855,0,0,0,382855,0,0,0,382855,0,0,0,382855,0,0,0,382855,0,0,0,382855,0,0,0,382855,0,0,0,382855,0,0,0,0,0,0.0,21333661.0,32,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,112,0,0,0,32,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,35,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,6,0,0,0,0,0,0,0,0,0,0,0,2,0,0,0,0,0,0,0,32,0,0,0,0,0,0,0,57,0,0,0,0,0,0,0,1,0,0,0,524288.0,0.0,0,43689,129024,129024,0,0,129024,129024,0,0,129024,129024,0,179,129024,129024,0,334,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,43089,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,171,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,27961,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,1043,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,46056,129024,129024,0,279294,129024,129024,0,875,129024,129024,0,0,129024,129024,0,549015,129024,129024,524288.0,0.0,44680,0,0,51038196,45801,0,0,51250544,46297,0,0,50936378,46775,0,0,52208009,44911,0,0,51494939,46044,0,0,51816053,45948,0,0,51481540,48770,0,0,53423789,44974,0,0,51220636,47912,0,0,51816307,45897,0,0,51101957,48570,0,0,52721846,45978,0,0,51790973,48626,0,0,52501465,46907,0,0,51761740,49522,0,0,53682184,44985,0,0,51000027,46106,0,0,51144448,45038,0,0,50634677,47280,0,0,52457936,44808,0,0,51414085,45554,0,0,51451503,45187,0,0,51179331,47884,0,0,53035870,45201,0,0,51161525,45841,0,0,51228773,46635,0,0,51175164,48206,0,0,52681800,47507,0,0,52312771,46993,0,0,51985145,46512,0,0,51530320,49832,0,0,53693014,0.0,65591,65569,88,131160,65536,65536,0,131072,65536,65537,1,131073,65536,65593,57,131129,65646,65538,112,131184,65536,65536,0,131072,65536,65536,0,131072,65536,65537,1,131073,65536,65536,0,131072,65536,65569,33,131105,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65537,1,131073,65536,65572,36,131108,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65758,65650,336,131408,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65568,32,131104,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65591,65537,56,131128,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131184,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131296,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131128,0,131072,1024311,0,524288,3670016,3663297,224,6495,1048576,33554432.0,33554432.0,0.0,33554432.0,29762427.0,28075060.0,0.0,524288.0,209230,535541,8845,924,0,378707,4195054.0,0.0,2097594.0,2097460.0,1048576,1048576,0,524288,0,524288,7340032,0,0.0,0.0,104.0,8388608.0,29665287.0,2097152.0,0.0,204675,0,1223,384297,0,751.0,4194304.0,0.0,2064387.0,25690112,9437184,0,0,0,0,0,0,13280.0,8242528.0,0.0,8388608.0,2097152.0,4194304.0,9962866,0,0,8953,4128768.0,4128768.0,0.0,1496112.0,0,0,0,0,0,0,5767168,1048576,316210007.0,0.0,1474367701.0,0.0,37.0,0.0,0,0,373483,0.0,0.0,1473234.0,0.0,3670016,524288,0,0,0,2621440,524288,176156900,4194304.0,0.0,0.0,0.0,0.0,1215742.0,0,0,0.0,313.0,0.0,610.0,43080273,24117248,0,0,9437184,11010048,0,3145728,0.0,0.0,0.0,0.0,0.0,0.0,0,1572864,0.0,0.0,0.0,196334.0,524288,524288,0,3670016,7340032,603979776,4718592,0,0.0,0.0,0.0,0.0,0.0,0.0,524288,0,2064384.0,0.0,2031624.0,0.0,0,0,524288,0,0,0,0,33554432,0.0,4194304.0,0.0,19088030.0,0.0,0.0,143.0,4128768.0,995027.0,1660403773.0,14551474846705,14568986326615,14568986565655,14551619036250
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,51605,51605,32768,256,0,0,12,24,13888,0x0,0x7fbfc3c23f80,264104,159947,512,1385494,1713023,504,56,0,33012,33012,2313360.0,165753.0,191.0,0.0,37700.0,34589.0,159504.0,140678.0,264096,167146,33012,0,33012,0,1056384.0,358385.0,0.0,0.0,0,0,560,0,8192,6183,56,1953,24243,0.0,0.0,0.0,4096.0,39048.0,37719.0,0.0,4096.0,128,512,302,33615,2282,0,0.0,62.0,0.0,4600.0,0,0,0,0,0,1024,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,11466.0,4096.0,0,33564,0,0,0,33564,0,0,0,33564,0,0,0,33564,0,0,0,33564,0,0,0,33564,0,0,0,33564,0,0,0,33564,0,0,0,33564,0,0,0,33564,0,0,0,33564,0,0,0,33564,0,0,0,33564,0,0,0,33564,0,0,0,33564,0,0,0,33564,0,0,0,33564,0,0,0,33564,0,0,0,33564,0,0,0,33564,0,0,0,33564,0,0,0,33564,0,0,0,33564,0,0,0,33564,0,0,0,33564,0,0,0,33564,0,0,0,33564,0,0,0,33564,0,0,0,33564,0,0,0,33564,0,0,0,33564,0,0,0,33564,0,0,0,0,0,0.0,0.0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,312,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,261,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,258,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,257,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,4096.0,4096.0,0,75508,0,0,0,75116,0,0,0,74404,0,0,0,78402,0,0,0,143833,0,0,0,80722,0,0,0,125691,0,0,0,86316,0,0,0,83267,0,0,0,80361,0,0,0,76252,0,0,0,84777,0,0,0,72214,0,0,0,80386,0,0,0,84163,0,0,0,85384,0,0,0,78190,0,0,0,79665,0,0,0,74862,0,0,0,80904,0,0,0,75847,0,0,0,83143,0,0,0,89738,0,0,0,85987,0,0,0,79312,0,0,0,80590,0,0,0,77037,0,0,0,83743,0,0,0,81491,0,0,0,81688,0,0,0,78207,0,0,0,666828,0,0,0.0,0.0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4096.0,0,128,128,128,0,128,128,128,0,128,128,128,0,129,129,129,0,128,128,128,222,130,352,352,0,128,128,128,0,129,129,129,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,222,130,352,352,0,128,128,128,0,128,128,128,0,129,129,129,0,129,129,129,0,128,128,128,0,128,128,128,0,128,128,128,0,184,184,184,55,129,184,184,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,352,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,352,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,184,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,670,0,0,512,0,56,456,0,65536.0,65536.0,65536.0,0.0,0.0,0.0,0.0,0.0,6,518,11078,1131,0,30378,4660.0,0.0,499.0,4161.0,512,0,0,0,4096,4096,512,0,0.0,0.0,104.0,16384.0,0.0,16384.0,4096.0,0,0,1288,31666,0,4662.0,0.0,0.0,31.0,35328,26112,0,0,0,0,0,0,104.0,15240.0,0.0,16384.0,16384.0,0.0,0,0,0,30844,0.0,0.0,0.0,0.0,0,0,0,0,0,0,10752,3584,4554105.0,5917233.0,0.0,8192.0,2.0,0.0,0,0,499,0.0,0.0,0.0,0.0,512,4096,0,0,0,512,512,1634575,0.0,0.0,0.0,0.0,0.0,1347.0,0,0,0.0,8263.0,0.0,124.0,15214,32256,0,0,26112,1024,0,1024,0.0,0.0,0.0,0.0,0.0,0.0,0,1024,0.0,0.0,0.0,52772.0,4096,0,4096,512,512,1671168,8192,0,0.0,0.0,0.0,0.0,0.0,0.0,512,0,0.0,0.0,0.0,0.0,0,0,512,0,0,0,0,32768,8192.0,0.0,0.0,100839.0,0.0,4096.0,8205.0,0.0,3378801.0,0.0,14551625232040,14568991411250,14568991424690,14551625708537
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,51605,51605,4194304,256,0,0,12,24,14336,0x7fbfe644a380,0x7fbfc3c23fc0,1317120,1213083,65536,15692105,79139744,392,56,0,164639,164639,16001336.0,14517360.0,22691.0,1162156.0,13397680.0,13073161.0,14511032.0,12379951.0,1317112,1220052,164639,0,164639,0,5268448.0,4755305.0,0.0,0.0,0,0,448,0,917504,912439,0,5065,154387,0.0,0.0,0.0,524288.0,12677476.0,12637515.0,2193.0,524288.0,16384,65536,302,165262,2282,0,0.0,186.0,0.0,1048968.0,0,0,0,0,0,131072,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,11994891.0,524288.0,0,185674,0,0,0,185674,0,0,0,185674,0,0,0,185674,0,0,0,185674,0,0,0,185674,0,0,0,185674,0,0,0,185674,0,0,0,185674,0,0,0,185674,0,0,0,185674,0,0,0,185674,0,0,0,185674,0,0,0,185674,0,0,0,185674,0,0,0,185674,0,0,0,185674,0,0,0,185674,0,0,0,185674,0,0,0,185674,0,0,0,185674,0,0,0,185674,0,0,0,185674,0,0,0,185674,0,0,0,185674,0,0,0,185674,0,0,0,185674,0,0,0,185674,0,0,0,185674,0,0,0,185674,0,0,0,185674,0,0,0,185674,0,0,0,0,0,0.0,0.0,65536,0,6886,0,65536,0,24591,0,65536,0,24903,0,65536,0,7479,0,65536,0,43738,0,65536,0,21064,0,65536,0,37161,0,65536,0,23950,0,65592,0,8103,0,65536,0,6673,0,65536,0,5329,0,65536,0,7836,0,65536,0,4300,0,65536,0,17346,0,65537,0,6501,0,65536,0,17339,0,65536,0,18475,0,65536,0,7615,0,65598,0,6549,0,65536,0,6606,0,65536,0,4330,0,65536,0,8867,0,65537,0,32609,0,65539,0,9356,0,65540,0,8227,0,65537,0,5767,0,65536,0,4159,0,65600,0,4436,0,65536,0,7853,0,65539,0,12499,0,65536,0,9637,0,65536,0,21149,0,524288.0,524288.0,0,48201822,0,0,0,42861359,0,0,0,47654367,0,0,0,42610627,0,0,0,45438054,0,0,0,48227316,0,0,0,44957546,0,0,0,47351786,0,0,0,42320822,0,0,0,40772606,0,0,0,40078010,0,0,0,43105859,0,0,0,42426689,0,0,0,42598404,0,0,0,46201974,0,0,0,45173977,0,0,0,45671979,0,0,0,44048732,0,0,0,41682053,0,0,0,50135777,0,0,0,46220043,0,0,0,48781300,0,0,0,48259221,0,0,0,39310930,0,0,0,38647758,0,0,0,44058283,0,0,0,41644383,0,0,0,42695183,0,0,0,42234104,0,0,0,44133520,0,0,0,49254576,0,0,0,43874473,0,0,0.0,0.0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,524288.0,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32769,32769,32769,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32769,32769,32769,0,32768,32768,32768,0,32770,32770,32770,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32769,32769,32769,0,32829,32829,32829,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32824,32824,32824,166,32770,32936,32936,222,32770,32992,32992,0,32768,32768,32768,0,32768,32768,32768,0,32831,32831,32831,0,32768,32768,32768,0,32769,32769,32769,0,32768,32768,32768,0,32768,32768,32768,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32936,0,0,32992,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,867003,0,0,65536,63800,56,1680,0,8388608.0,8388608.0,8388608.0,0.0,0.0,0.0,0.0,0.0,127334,149364,10082,2536,0,161618,1049150.0,0.0,388.0,1048762.0,65536,0,0,0,524288,524288,131072,0,0.0,0.0,104.0,2097152.0,0.0,2097152.0,524288.0,45924,0,2837,162158,0,1049152.0,0.0,0.0,31.0,4063232,2883584,0,0,0,0,0,0,6595.0,2027316.0,0.0,2097152.0,2097152.0,0.0,1291910,0,0,14677,0.0,0.0,0.0,0.0,262144,0,0,0,0,0,1507328,458752,994974674.0,2296287524.0,0.0,2097152.0,98.0,0.0,0,0,147384,0.0,0.0,0.0,0.0,65536,524288,0,0,0,65536,65536,47881684,0.0,0.0,0.0,0.0,0.0,30200.0,0,0,0.0,2097347.0,0.0,376.0,31080177,3735552,0,0,2883584,196608,0,131072,0.0,0.0,0.0,0.0,0.0,0.0,0,131072,0.0,0.0,518468.0,1461897.0,524288,0,524288,65536,131072,184549376,917504,0,0.0,0.0,0.0,0.0,0.0,0.0,65536,0,0.0,0.0,983048.0,0.0,0,0,65536,0,0,0,0,4194304,2097152.0,0.0,0.0,12368881.0,0.0,524288.0,2097279.0,0.0,1452521137.0,0.0,14551626804307,14568991496690,14568991589490,14551627565846
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/prev_analysis/1.csv
index cf0324fac2..b15ad60dcd 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,3357438.0,3357438.0,3357438.0,7.842727689159224
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,1725599.0,1725599.0,1725599.0,4.030872069025687
 "void benchmark_func<double, 256, 8u, 512u>(double, double*) [clone .kd]",1,1715199.0,1715199.0,1715199.0,4.006578435616149
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/prev_analysis/1001.csv
index f475f954a6..fb5988001a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,494.8622754491018,Instr per wave
 VMEM,7.958083832335329,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,0.0,Instr per wave
 SALU,24.520958083832337,Instr per wave
 SMEM,1.8023952095808384,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/prev_analysis/101.csv
index 804c48780d..6e10473c65 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx90a
 mi200
 56
 1638.4
-SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/prev_analysis/1202.csv
index a156d06385..982c81ddb7 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,18392.079291840513,1834.477882385254,258386.62493896484,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/prev_analysis/1901.csv
index 5894f930bc..52941e48e0 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,2.0,smem_
 VALU,495.0,valu_
 MFMA,0.0,mfma_
 VMEM,8.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,10.0,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,67894.0,wavefronts_
 Workgroups,16973.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,128.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,0.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,44.0,hbm_rd_
 HBM Wr,0.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,70.0,vl1_coales_
 VL1 Stall,2.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,25.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/prev_analysis/201.csv
index ef59dcd2d4..992e58b2c1 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,58.35286510582007,Pct,100,58.35286510582007
 MFMA Util,0.0,Pct,100,0.0
 VALU Active Threads/Wave,64.0,Threads,64,100.0
 IPC - Issue,1.0,Instr/cycle,5,20.0
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.9925737309827,Pct,100,99.9925737309827
 Instr Cache BW,1673.8451004169183,Gb/s,6092.8,27.47251018278818
 Scalar L1D Cache Hit Rate,99.34855886047387,Pct,100,99.34855886047387
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/prev_analysis/602.csv
index 9cadca82b2..4e2e72d52b 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,12065411.964071857,0,377390686,Simd
 Insufficient SIMD VGPRs,0.0,0,0,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/prev_analysis/701.csv
index 12250d77c0..db0925a109 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/sysinfo.csv
index b1597e9aba..990415fcf0 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-no_roof_K_str_valid_2,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 19:55:48 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+no_roof_K_str_valid_2,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 19:55:48 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/timestamps.csv
index 1ce077eafe..ad4688f398 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_2/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,52550,52550,33554432,256,0,0,4,32,4160,0x0,0x7fe766404280,14568986303294,14568986326615,14568986565655,14568986676554
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,52550,52550,32768,256,0,0,12,24,13888,0x0,0x7fe766423f80,14568991395945,14568991411250,14568991424690,14568991442994
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,52550,52550,4194304,256,0,0,12,24,14336,0x7fe769317380,0x7fe766423fc0,14568991444864,14568991496690,14568991589490,14568991591490
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/SQ_IFETCH_LEVEL.csv
index 83d1613bb5..65ee0c3de7 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/SQ_IFETCH_LEVEL.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,780972,780977,32768,256,0,0,24,24,12480,0x0,0x7f77d3835100,28063,28063,512,8192,9113,1173384,12073744209856086,12073744456831972,12073744456838532,12073744456854494
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,780972,780977,4194304,256,0,0,24,24,12928,0x7f79037ee900,0x7f77d3835140,225684,225684,65536,917504,141547,18056080,12073744456914435,12073744460284314,12073744460422234,12073744460426211
 3,"void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 0u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",0,0,6,780972,780977,4194304,256,0,0,36,24,13632,0x7f79037ee800,0x7f77d3835180,397169,397169,65536,1245184,184005,23483300,12073744460499818,12073744460682232,12073744460935991,12073744461007582
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/SQ_INST_LEVEL_LDS.csv
index 8c7dc21d51..422b139774 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/SQ_INST_LEVEL_LDS.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,782773,782778,32768,256,0,0,24,24,12480,0x0,0x7f9215a35100,0,0,0,12073770598409366,12073770840001630,12073770840008350,12073770840036231
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,782773,782778,4194304,256,0,0,24,24,12928,0x7f93215c0900,0x7f9215a35140,0,0,0,12073770840082988,12073770843419016,12073770843551495,12073770843555201
 3,"void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 0u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",0,0,6,782773,782778,4194304,256,0,0,36,24,13632,0x7f93215c0800,0x7f9215a35180,0,0,0,12073770843625722,12073770843802694,12073770844054533,12073770844127895
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/SQ_INST_LEVEL_SMEM.csv
index 4f893716d3..c62f47844f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/SQ_INST_LEVEL_SMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,782392,782397,32768,256,0,0,24,24,12480,0x0,0x7ff3cba35100,512,25036,3196320,12073768071308876,12073768312061874,12073768312067954,12073768312082305
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,782392,782397,4194304,256,0,0,24,24,12928,0x7ff4fba6b900,0x7ff3cba35140,65536,180830,23121968,12073768312142718,12073768315519181,12073768315659820,12073768315662829
 3,"void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 0u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",0,0,6,782392,782397,4194304,256,0,0,36,24,13632,0x7ff4fba6b800,0x7ff3cba35180,65536,155512,20002040,12073768315729413,12073768315902220,12073768316154059,12073768316222219
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/SQ_INST_LEVEL_VMEM.csv
index 54b2189deb..0a532ea001 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/SQ_INST_LEVEL_VMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,782584,782589,32768,256,0,0,24,24,12480,0x0,0x7f2c39435100,4096,104486,13391376,12073769337931736,12073769581611424,12073769581617344,12073769581632866
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,782584,782589,4194304,256,0,0,24,24,12928,0x7f2d45047900,0x7f2c39435140,524288,11844146,1516127172,12073769581690433,12073769585039850,12073769585173449,12073769585177393
 3,"void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 0u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",0,0,6,782584,782589,4194304,256,0,0,36,24,13632,0x7f2d45047800,0x7f2c39435180,524288,13125130,1679990092,12073769585246141,12073769585420648,12073769585673447,12073769585740800
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/SQ_LEVEL_WAVES.csv
index 30881a03ae..7a9f527f21 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/SQ_LEVEL_WAVES.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,782962,782969,32768,256,0,0,24,24,12480,0x0,0x7fbc15835100,28702,28702,21267,229624,512,1177439,79275,0,4724064,12073771862594205,12073772106108812,12073772106116172,12073772106133555
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,782962,782969,4194304,256,0,0,24,24,12928,0x7fbd21381900,0x7fbc15835140,219325,219325,21956,1754608,65536,147470725,1584782,0,591688660,12073772106202663,12073772109573557,12073772109708117,12073772109711353
 3,"void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 0u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",0,0,6,782962,782969,4194304,256,0,0,36,24,13632,0x7fbd21381800,0x7fbc15835180,391573,391573,28590,3132592,65536,207106540,2957236,0,830242992,12073772109789418,12073772109979476,12073772110228435,12073772110295810
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/pmc_dispatch_info.csv
index 4544bf0858..8f3ca42ca4 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
 3,"void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 0u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/pmc_perf.csv
index debadb4d20..3ce0313c02 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,781707,781712,32768,256,0,0,24,24,12480,0x0,0x7f8387835100,0,4096,4096,512,0,512,4096,0,29137,29137,1582029,598239,204,128996,87174,66811,590156,569723,233096,89914,29137,0,29137,0,932384,200810,0,0,0,0,0,61303,4096,0,27639,0,0,0,27639,0,0,0,27639,0,0,0,27639,0,0,0,27639,0,0,0,27639,0,0,0,27639,0,0,0,27639,0,0,0,27639,0,0,0,27639,0,0,0,27639,0,0,0,27639,0,0,0,27639,0,0,0,27639,0,0,0,27639,0,0,0,27639,0,0,0,27639,0,0,0,27639,0,0,0,27639,0,0,0,27639,0,0,0,27639,0,0,0,27639,0,0,0,27639,0,0,0,27639,0,0,0,27639,0,0,0,27639,0,0,0,27639,0,0,0,27639,0,0,0,27639,0,0,0,27639,0,0,0,27639,0,0,0,27639,0,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,257,0,0,0,377,0,0,0,256,0,0,0,256,0,0,0,260,0,0,0,304,0,0,0,256,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,304,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,4096,4096,0,103830,0,0,0,105393,0,0,0,77263,0,0,0,102049,0,0,0,134899,0,0,0,99068,0,0,0,80543,0,0,0,90742,0,0,0,165891,0,0,0,123364,0,0,0,108411,0,0,0,83604,0,0,0,96043,0,0,0,102391,0,0,0,73238,0,0,0,88154,0,0,0,82851,0,0,0,101419,0,0,0,63181,0,0,0,86167,0,0,0,77197,0,0,0,251655,0,0,0,127072,0,0,0,91901,0,0,0,93440,0,0,0,109614,0,0,0,86254,0,0,0,96308,0,0,0,192929,0,0,0,102851,0,0,0,201760,0,0,0,89390,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4096,0,256,256,256,0,304,304,304,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,377,377,377,0,256,256,256,188,260,448,448,47,257,304,304,0,256,256,256,0,256,256,256,188,260,448,448,0,256,256,256,0,256,256,256,0,256,256,256,0,257,257,257,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,47,257,304,304,0,305,305,305,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,304,0,0,256,0,0,0,0,512,512,35328,1076872,1024128,16392,11575,0,0,0,4096,66469,63353,4096,4096,128,512,602,28237,4334,0,48,219,0,8624,36352,225736,77070,1087144,26624,0,0,30208,65536,65536,65536,0,0,0,0,0,117,629,11857,2404,0,23997,8892,0,470,8422,1024,0,1024,4096,0,4096,512,512,0,0,360,16384,0,16384,0,0,2810,25510,0,8892,0,0,31,1933312,8192,0,0,0,512,512,0,120,15064,0,16384,16384,0,0,0,0,20673,0,0,0,0,0,0,0,32768,0,0,0,0,12786736,17871297,0,8192,0,0,0,0,696,0,0,0,0,0,1024,432,48,0,0,0,480,0,0,0,0,0,2320,0,0,0,8373,0,342,0,8192,6538,48,1606,1062,0,0,0,0,0,0,0,0,0,2560,0,0,0,49486,512,0,48,464,0,512,0,0,0,0,0,0,0,512,0,0,0,0,0,8192,0,0,421971,0,4096,8372,0,2969896,0,12073746345986414,12073772979361026,12073772979685183,12073746589323718
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,781707,781712,4194304,256,0,0,24,24,12928,0x7f84b7928900,0x7f8387835140,0,524288,524288,65536,0,65536,524288,0,229506,229506,25380167,24103508,30643,4947501,23078088,22951695,24076116,21907303,1836048,1676025,229506,0,229506,0,7344192,6586868,0,0,0,0,0,19684544,524288,0,214230,0,0,0,214230,0,0,0,214230,0,0,0,214230,0,0,0,214230,0,0,0,214230,0,0,0,214230,0,0,0,214230,0,0,0,214230,0,0,0,214230,0,0,0,214230,0,0,0,214230,0,0,0,214230,0,0,0,214230,0,0,0,214230,0,0,0,214230,0,0,0,214230,0,0,0,214230,0,0,0,214230,0,0,0,214230,0,0,0,214230,0,0,0,214230,0,0,0,214230,0,0,0,214230,0,0,0,214230,0,0,0,214230,0,0,0,214230,0,0,0,214230,0,0,0,214230,0,0,0,214230,0,0,0,214230,0,0,0,214230,0,0,0,0,65536,0,0,0,65536,0,13738,0,65540,0,0,0,65536,0,14032,0,65536,0,5139,0,65536,0,0,0,65537,0,15326,0,65536,0,260,0,65537,0,0,0,65536,0,0,0,65537,0,0,0,65962,0,18015,0,65536,0,1276,0,65536,0,0,0,65536,0,1953,0,65584,0,1680,0,65536,0,4832,0,67767,0,52264,0,65536,0,642,0,65536,0,68,0,65536,0,5080,0,65536,0,0,0,65536,0,0,0,67677,0,55995,0,65536,0,10174,0,65537,0,1156,0,65536,0,2049,0,65536,0,2632,0,65536,0,732,0,65536,0,6969,0,65540,0,0,0,65536,0,16142,0,524288,524288,0,27221994,0,0,0,26580307,0,0,0,26665693,0,0,0,27332507,0,0,0,26216379,0,0,0,28439835,0,0,0,31562334,0,0,0,29397517,0,0,0,26104639,0,0,0,48908904,0,0,0,27188851,0,0,0,27301488,0,0,0,32863353,0,0,0,29029632,0,0,0,30535641,0,0,0,33902687,0,0,0,28215760,0,0,0,29073081,0,0,0,29015563,0,0,0,29140334,0,0,0,26887538,0,0,0,46966402,0,0,0,27772429,0,0,0,27995312,0,0,0,29787853,0,0,0,30005290,0,0,0,28129860,0,0,0,28965679,0,0,0,27800146,0,0,0,32344702,0,0,0,28239156,0,0,0,30189838,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,524288,0,67372,67372,67372,0,65584,65584,65584,188,65540,65728,65728,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65658,65658,65658,0,65536,65536,65536,0,65536,65536,65536,47,65537,65584,65584,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65537,65537,65537,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,66197,66197,66197,0,65536,65536,65536,188,65540,65728,65728,0,65585,65585,65585,65536,0,0,65536,0,0,65728,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65728,0,0,65536,0,0,0,0,65536,65536,4128768,146328072,56470865,85597367,193511,0,0,0,524288,21390423,21383163,524288,524288,16384,65536,787,211422,4235,0,48,1418,0,2097536,4259840,1797136,1632872,24230513,3014656,0,0,3473408,8388608,8388608,8388608,0,0,0,0,0,149475,184710,11447,2501,0,220674,2102189,0,423,2101766,131072,0,131072,524288,0,524288,65536,65536,0,0,360,2097152,0,2097152,34514,0,3300,221524,0,2102108,0,0,31,222298112,917504,0,0,0,65536,65536,0,7537,2015775,0,2097152,2097152,0,540051,541615,0,24033,0,0,0,0,0,0,0,4194304,0,0,0,0,1179309330,2076771001,0,2097152,0,0,0,0,190613,0,0,0,0,0,131072,384,48,0,0,0,432,0,0,0,0,0,8484,0,0,0,2099143,0,3964,0,917504,914683,48,7550,229382,0,0,0,0,0,0,0,0,0,327680,0,0,308335,361688,65536,64048,48,1440,0,65536,0,0,0,0,0,0,0,65536,0,0,0,1966092,0,2097152,0,0,17856135,0,524288,2099423,0,1144501308,0,12073746589945042,12073772994919010,12073772994926210,12073746594327326
 3,"void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 0u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",0,0,6,781707,781712,4194304,256,0,0,36,24,13632,0x7f84b7928800,0x7f8387835180,0,524288,524288,917504,0,65536,524288,0,403143,403143,46271417,45145948,0,20326684,44853009,44830998,45135816,36742168,3225144,3068775,403143,0,403143,0,12900576,12135194,0,0,0,0,0,35582690,524288,0,395957,0,0,0,395957,0,0,0,395957,0,0,0,395957,0,0,0,395957,0,0,0,395957,0,0,0,395957,0,0,0,395957,0,0,0,395957,0,0,0,395957,0,0,0,395957,0,0,0,395957,0,0,0,395957,0,0,0,395957,0,0,0,395957,0,0,0,395957,0,0,0,395957,0,0,0,395957,0,0,0,395957,0,0,0,395957,0,0,0,395957,0,0,0,395957,0,0,0,395957,0,0,0,395957,0,0,0,395957,0,0,0,395957,0,0,0,395957,0,0,0,395957,0,0,0,395957,0,0,0,395957,0,0,0,395957,0,0,0,395957,0,0,0,0,131072,0,27331,0,131072,0,27514,0,131072,0,19702,0,131072,0,19463,0,131072,0,38736,0,131072,0,3100,0,131077,0,40606,0,131072,0,21520,0,131073,0,10759,0,131072,0,3960,0,131073,0,14345,0,131480,0,46744,0,131072,0,32226,0,132461,0,136391,0,131072,0,9151,0,131120,0,12739,0,131072,0,36471,0,131242,0,17723,0,131072,0,13773,0,131072,0,21650,0,131072,0,36239,0,131072,0,3703,0,131074,0,34980,0,131951,0,96335,0,131072,0,15318,0,131073,0,4265,0,131076,0,58688,0,131072,0,28588,0,131072,0,5644,0,131236,0,39590,0,131072,0,7545,0,131072,0,20992,0,524288,524288,0,76942266,0,0,0,74205358,0,0,0,77447517,0,0,0,69809461,0,0,0,76173725,0,0,0,73569343,0,0,0,72686737,0,0,0,69643956,0,0,0,78088165,0,0,0,82050102,0,0,0,73095471,0,0,0,68077469,0,0,0,75343717,0,0,0,81582086,0,0,0,80182685,0,0,0,78996811,0,0,0,72001840,0,0,0,69049676,0,0,0,81825489,0,0,0,73950732,0,0,0,82140729,0,0,0,112771330,0,0,0,71793644,0,0,0,61548642,0,0,0,69196262,0,0,0,74342236,0,0,0,78685393,0,0,0,73841689,0,0,0,67370089,0,0,0,73905056,0,0,0,68475165,0,0,0,69617953,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,131421,131421,131421,0,131120,131120,131120,0,131072,131072,131072,0,131072,131072,131072,0,131515,131515,131515,0,131072,131072,131072,188,131076,131264,131264,0,131072,131072,131072,0,131072,131072,131072,0,131072,131072,131072,0,131072,131072,131072,0,131072,131072,131072,0,131193,131193,131193,0,131072,131072,131072,0,131072,131072,131072,47,131073,131120,131120,0,131072,131072,131072,0,131072,131072,131072,0,131072,131072,131072,0,131072,131072,131072,0,131072,131072,131072,0,131072,131072,131072,94,131075,131169,131169,0,131072,131072,131072,0,132541,132541,132541,0,131072,131072,131072,188,131076,131264,131264,0,131072,131072,131072,0,131671,131671,131671,0,131072,131072,131072,0,131072,131072,131072,0,131121,131121,131121,131072,0,0,131072,0,0,131072,0,0,131072,0,0,131072,0,0,131072,0,0,131264,0,0,131072,0,0,131072,0,0,131072,0,0,131072,0,0,131072,0,0,131072,0,0,131072,0,0,131072,0,0,131072,0,0,131072,0,0,131072,0,0,131072,0,0,131072,0,0,131072,0,0,131072,0,0,131168,0,0,131072,0,0,131072,0,0,131072,0,0,131264,0,0,131072,0,0,131072,0,0,131072,0,0,131072,0,0,131072,0,0,0,0,131072,65536,6291456,269232592,58137684,204672380,372080,0,0,0,524288,43407001,43405530,0,524288,16384,65536,771,389983,4476,0,48,1722,0,4194784,6422528,3147216,2987410,44533080,4259840,0,0,4718592,33554432,33554432,33554432,0,0,0,0,0,397783,343762,11661,2442,0,389531,4196548,0,517,4196031,983040,0,196608,524288,0,524288,65536,917504,0,0,360,8388608,0,2097152,129704,0,3229,398632,0,4196412,0,0,31,301989888,1245184,0,0,0,65536,65536,0,14490,8232897,0,8388608,2097152,0,0,6721762,0,29242,0,0,0,0,0,0,0,4194304,0,0,0,0,1147292440,4445755755,0,4194304,0,0,0,0,358658,0,0,0,0,0,131072,480,48,0,0,0,528,0,0,0,0,0,1036,0,0,0,4196753,0,4876,0,1245184,1242954,56,4867,246818,0,0,0,0,0,0,0,0,0,327680,0,0,762297,815517,65536,64048,48,1440,0,65536,0,0,0,0,0,0,0,65536,0,0,0,4063245,0,4194304,0,0,32743883,0,0,4197309,0,2115672161,0,12073746594950835,12073772994991810,12073772995121089,12073746596364472
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/prev_analysis/1.csv
index ca8c00cb52..aa558d1f14 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<double, 256, 8u, 512u>(double, double*) [clone .kd]",1,6056914.0,6056914.0,6056914.0,9.853670829198093
 "void benchmark_func<double, 256, 8u, 256u>(double, double*) [clone .kd]",1,3049417.0,3049417.0,3049417.0,4.960934122386542
 "void benchmark_func<__half2, 256, 8u, 512u>(__half2, __half2*) [clone .kd]",1,3042377.0,3042377.0,3042377.0,4.949481121297612
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/prev_analysis/1001.csv
index 1e8362a8e4..c706f4c2f5 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,47.036144578313255,Instr per wave
 SMEM,1.7710843373493976,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/prev_analysis/101.csv
index 5b014e080f..07950ad96e 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx908
 mi100
 48
 1228.8
-SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/prev_analysis/1202.csv
index df06d8cc83..2738cae0e5 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,34014.50963215656,8413.0625,547856.8496704102,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/prev_analysis/1901.csv
index 0c9c87a82e..b7727b8a35 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,2.0,smem_
 VALU,739.0,valu_
 MFMA,,mfma_
 VMEM,8.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,22.0,br_
 VGPR,24.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,65144.0,wavefronts_
 Workgroups,16286.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,164.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,0.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,45.0,hbm_rd_
 HBM Wr,0.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,70.0,vl1_coales_
 VL1 Stall,29.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,37.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/prev_analysis/2001.csv
index 4544bf0858..8f3ca42ca4 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
 3,"void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 0u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/prev_analysis/201.csv
index 65b45c89fd..bce056bc94 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,59.420327515928456,Pct,100,59.420327515928456
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,63.96669244299845,Threads,64,99.94795694218507
 IPC - Issue,0.8432626707642372,Instr/cycle,5,16.865253415284744
-LDS BW,0.0,Gb/sec,23070.72,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,23070.72,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99335174164285,Pct,100,99.99335174164285
 Instr Cache BW,1869.6539339623155,Gb/s,4614.144,40.520060361408646
 Scalar L1D Cache Hit Rate,99.35234690234445,Pct,100,99.35234690234445
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/prev_analysis/602.csv
index 879eebea2e..779212e479 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,70269.06626506025,0,687275,Simd
 Insufficient SIMD VGPRs,606700.6445783132,0,30353536,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/prev_analysis/701.csv
index 878c96c694..aa09824713 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,24.072289156626507,12,36,Registers
 SGPRs,24.0,24,24,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/sysinfo.csv
index de2458689b..799caf46da 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-no_roof_K_str_valid_3,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 10:48:39 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+no_roof_K_str_valid_3,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 10:48:39 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/timestamps.csv
index 76740f5e1b..62fbf3dd8a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_K_str_valid_3/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,783013,783018,33554432,256,0,0,8,32,6464,0x0,0x7fba2d204180,12073772979314599,12073772979361026,12073772979685183,12073772979786416
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,783013,783018,32768,256,0,0,24,24,12480,0x0,0x7fba2d235100,12073772994812250,12073772994919010,12073772994926210,12073772994931631
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,783013,783018,4194304,256,0,0,24,24,12928,0x7fbb38ece900,0x7fba2d235140,12073772994978458,12073772994991810,12073772995121089,12073772995124360
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/SQ_IFETCH_LEVEL.csv
index 084081be3e..5aacf9df99 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/SQ_IFETCH_LEVEL.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,881406,881411,33554432,256,0,0,8,32,6464,0x0,0x7f83cf004180,506353,506353,524288,6291456,794764,101493964,12075558005611663,12075558251967055,12075558252292333,12075558252409266
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,881406,881411,32768,256,0,0,24,24,12480,0x0,0x7f83cf035100,27923,27923,512,8192,9102,1160500,12075558267218307,12075558267541132,12075558267547692,12075558267557047
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,881406,881411,4194304,256,0,0,24,24,12928,0x7f84fef7d900,0x7f83cf035140,225403,225403,65536,917504,140100,17951384,12075558267623290,12075558267846570,12075558267984809,12075558267988449
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/SQ_INST_LEVEL_LDS.csv
index 5bbf7a2bb2..d58b6cf14b 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/SQ_INST_LEVEL_LDS.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,883201,883206,33554432,256,0,0,8,32,6464,0x0,0x7fd771604180,0,0,0,12075584365029624,12075584613841975,12075584614166773,12075584614280556
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,883201,883206,32768,256,0,0,24,24,12480,0x0,0x7fd771635100,0,0,0,12075584628944648,12075584629261691,12075584629267451,12075584629277647
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,883201,883206,4194304,256,0,0,24,24,12928,0x7fd87d1ae900,0x7fd771635140,0,0,0,12075584629330024,12075584629558809,12075584629690008,12075584629693460
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/SQ_INST_LEVEL_SMEM.csv
index dc270961b8..eaf9d6f328 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/SQ_INST_LEVEL_SMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,882823,882828,33554432,256,0,0,8,32,6464,0x0,0x7fb7a5204180,4194304,3067606,392800944,12075581843866604,12075582096226298,12075582096550136,12075582096665119
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,882823,882828,32768,256,0,0,24,24,12480,0x0,0x7fb7a5235100,512,20750,2640256,12075582111295519,12075582111607009,12075582111613409,12075582111621855
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,882823,882828,4194304,256,0,0,24,24,12928,0x7fb8b0e36900,0x7fb7a5235140,65536,161028,20675144,12075582111680474,12075582111899328,12075582112032767,12075582112036796
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/SQ_INST_LEVEL_VMEM.csv
index 6a51a11400..798a35d2a0 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/SQ_INST_LEVEL_VMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,883013,883018,33554432,256,0,0,8,32,6464,0x0,0x7f37d5e04180,1048576,11017086,1410404088,12075583113293448,12075583358016024,12075583358339702,12075583358452295
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,883013,883018,32768,256,0,0,24,24,12480,0x0,0x7f37d5e35100,4096,113754,14559752,12075583373237833,12075583373538585,12075583373545305,12075583373549552
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,883013,883018,4194304,256,0,0,24,24,12928,0x7f38e1a27900,0x7f37d5e35140,524288,13292261,1701489292,12075583373608492,12075583373831224,12075583373959543,12075583373962610
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/SQ_LEVEL_WAVES.csv
index 8b7ea6a907..100782b285 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/SQ_LEVEL_WAVES.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,883389,883396,33554432,256,0,0,8,32,6464,0x0,0x7fdac0c04180,503328,503328,16716,4026632,524288,368148079,3821321,0,1487459732,12075585626284420,12075585872918177,12075585873242015,12075585873353507
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,883389,883396,32768,256,0,0,24,24,12480,0x0,0x7fdac0c35100,27627,27627,20613,221024,512,1172834,77934,0,4705472,12075585887772815,12075585888100860,12075585888107900,12075585888116233
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,883389,883396,4194304,256,0,0,24,24,12928,0x7fdbcc918900,0x7fdac0c35140,221309,221309,23106,1770480,65536,146887965,1592256,0,589362288,12075585888182105,12075585888419418,12075585888553497,12075585888556892
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/pmc_dispatch_info.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/pmc_perf.csv
index 6974405fa8..679d3c6458 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBuffer.kd,0,0,0,882141,882146,33554432,256,0,0,8,32,6464,0x0,0x7fc01ca04180,1048576,0,1048576,9437184,0,4194304,1048576,0,500217,500217,57500859,55310877,70,12393777,54404125,54298070,55267429,54084176,4001736,3817846,500217,0,500217,0,16006944,15189616,0,0,0,0,0,17648433,1048576,0,500833,0,0,0,500833,0,0,0,500833,0,0,0,500833,0,0,0,500833,0,0,0,500833,0,0,0,500833,0,0,0,500833,0,0,0,500833,0,0,0,500833,0,0,0,500833,0,0,0,500833,0,0,0,500833,0,0,0,500833,0,0,0,500833,0,0,0,500833,0,0,0,500833,0,0,0,500833,0,0,0,500833,0,0,0,500833,0,0,0,500833,0,0,0,500833,0,0,0,500833,0,0,0,500833,0,0,0,500833,0,0,0,500833,0,0,0,500833,0,0,0,500833,0,0,0,500833,0,0,0,500833,0,0,0,500833,0,0,0,500833,0,0,0,37646567,2563,0,0,0,4,0,0,0,1,0,0,0,0,0,0,0,2824,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,3,0,0,0,0,0,0,0,0,0,0,0,2567,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2700,0,0,0,51,0,0,0,1,0,0,0,0,0,0,0,17,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1048576,0,0,0,131072,131072,0,15374,131072,131072,0,0,131072,131072,0,3059153,131072,131072,0,0,131072,131072,0,0,131072,131072,0,1141,131072,131072,0,2955711,131072,131072,0,0,131072,131072,0,0,131072,131072,0,0,131072,131072,0,0,131072,131072,0,0,131080,131080,0,0,131072,131072,0,0,131072,131072,0,20324,131076,131076,0,0,131080,131080,0,1293,131072,131072,0,1493,131080,131080,0,3174029,131072,131072,0,0,131072,131072,0,0,131080,131080,0,281,131072,131072,0,1853,131084,131084,0,0,131072,131072,0,0,131072,131072,0,0,131072,131072,0,0,131072,131072,0,262,131076,131076,0,23895,131072,131072,0,566257,131072,131072,0,3213756,131072,131072,1048576,0,1608,0,0,17156124,1696,0,0,17269582,1705,0,0,17354275,1105,0,0,17371332,863,0,0,17212467,863,0,0,17313245,853,0,0,18033971,917,0,0,18616921,1114,0,0,17047210,1039,0,0,17295828,666,0,0,17136589,42882,0,0,29024582,1179,0,0,17259797,45177,0,0,30035940,1041,0,0,18253875,784,0,0,18668885,722,0,0,16813741,49381,0,0,30444386,1770,0,0,17246122,806,0,0,16764714,1715,0,0,17401125,1788,0,0,17534355,903,0,0,18067258,48065,0,0,31450342,1175,0,0,16604160,805,0,0,16948742,1083,0,0,16937632,1078,0,0,16904195,1180,0,0,17367148,741,0,0,17557838,837,0,0,17928155,1002,0,0,18832319,1048576,131072,131092,20,262164,131260,131076,192,262336,131072,131073,1,262145,131072,131120,48,262192,131072,133693,2621,264765,131072,131072,0,262144,131072,131073,1,262145,131072,131072,0,262144,131072,133645,2573,264717,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131213,131075,144,262288,131072,131072,0,262144,131072,131072,0,262144,131072,133766,2694,264838,131119,131077,52,262196,131072,131120,48,262192,131072,131072,0,262144,131072,133556,2484,264628,131072,131072,0,262144,131072,131072,0,262144,131072,131121,49,262193,131072,131072,0,262144,131119,131073,48,262192,131072,131072,0,262144,131072,131072,0,262144,262144,0,262144,262336,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262288,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,0,0,3145728,524288,32505856,372953019,220204793,120242370,479031,0,0,0,1048576,52381588,52157252,1048576,1048576,131072,524288,714,500844,4469,0,96,10524,0,8388944,32505856,4072560,3859966,57765230,11534336,0,0,14155776,67108864,67108864,0,67108864,54188960,53759004,0,1048576,233994,758282,11768,2436,0,504758,8399876,0,4194727,4205149,13631488,0,3670016,1048576,1048576,0,4194304,9437184,0,0,360,33554432,54096442,4194304,0,0,2377,504124,0,10977,8388608,0,4194410,905969664,6291456,0,0,0,524288,524288,0,15340,16608636,0,16777216,4194304,4194304,0,0,0,17378,4194388,4194388,0,212995,0,0,0,33554432,0,0,0,0,643981525,0,2814738230,0,0,0,0,0,474075,0,0,225490,0,0,8388608,336,144,0,0,0,480,8388608,0,0,0,0,375953,0,0,0,10743,0,21468,0,6291456,6289397,96,2162,1828467,0,0,0,0,0,0,0,0,0,3145728,0,0,0,156763,4194304,4189858,144,4302,2097152,524288,1572864,0,0,0,0,0,0,524288,0,4128853,65536,4063247,0,0,8388608,0,42059275,0,1048576,10652,4194393,13110248,608083220,12075560165185506,12075586759255753,12075586759580870,12075560412773968
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,882141,882146,32768,256,0,0,24,24,12480,0x0,0x7fc01ca35100,0,4096,4096,512,0,512,4096,0,28172,28172,1455662,585584,254,44185,226033,211468,577520,557061,225376,82869,28172,0,28172,0,901504,201764,0,0,0,0,0,219630,4096,0,28327,0,0,0,28327,0,0,0,28327,0,0,0,28327,0,0,0,28327,0,0,0,28327,0,0,0,28327,0,0,0,28327,0,0,0,28327,0,0,0,28327,0,0,0,28327,0,0,0,28327,0,0,0,28327,0,0,0,28327,0,0,0,28327,0,0,0,28327,0,0,0,28327,0,0,0,28327,0,0,0,28327,0,0,0,28327,0,0,0,28327,0,0,0,28327,0,0,0,28327,0,0,0,28327,0,0,0,28327,0,0,0,28327,0,0,0,28327,0,0,0,28327,0,0,0,28327,0,0,0,28327,0,0,0,28327,0,0,0,28327,0,0,0,0,304,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,261,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,376,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,4096,4096,0,90899,0,0,0,92817,0,0,0,91263,0,0,0,123538,0,0,0,96924,0,0,0,107060,0,0,0,86400,0,0,0,114369,0,0,0,86256,0,0,0,74497,0,0,0,83176,0,0,0,78117,0,0,0,94784,0,0,0,77748,0,0,0,83314,0,0,0,228008,0,0,0,125845,0,0,0,97083,0,0,0,65246,0,0,0,87819,0,0,0,106939,0,0,0,136729,0,0,0,94512,0,0,0,87277,0,0,0,86769,0,0,0,114225,0,0,0,82949,0,0,0,94855,0,0,0,88026,0,0,0,112311,0,0,0,85311,0,0,0,84949,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4096,0,376,376,376,0,256,256,256,0,257,257,257,0,256,256,256,0,257,257,257,0,256,256,256,0,257,257,257,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,188,260,448,448,0,256,256,256,0,256,256,256,0,256,256,256,188,260,448,448,0,256,256,256,0,256,256,256,0,256,256,256,0,304,304,304,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,305,305,305,0,256,256,256,47,257,304,304,47,257,304,304,0,256,256,256,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,304,0,0,256,0,0,0,0,512,512,35328,1124079,1073010,14717,11699,0,0,0,4096,63368,60268,4096,4096,128,512,607,27700,4382,0,48,219,0,8624,36352,232888,73153,1027705,26624,0,0,30208,65536,65536,65536,0,0,0,0,0,116,628,12132,3048,0,24774,8844,0,470,8374,1024,0,1024,4096,0,4096,512,512,0,0,360,16384,0,16384,0,0,2386,25222,0,8843,0,0,31,1933312,8192,0,0,0,512,512,0,120,15064,0,16384,16384,0,0,0,0,20066,0,0,0,0,0,0,0,32768,0,0,0,0,12394911,17422313,0,8192,0,0,0,0,695,0,0,0,0,0,1024,432,48,0,0,0,480,0,0,0,0,0,2860,0,0,0,8422,0,440,0,8192,6532,48,1612,1080,0,0,0,0,0,0,0,0,0,2560,0,0,0,49750,512,0,48,464,0,512,0,0,0,0,0,0,0,512,0,0,0,0,0,8192,0,0,464935,0,4096,8373,0,3269264,0,12075560427786558,12075586774350126,12075586774357486,12075560428751531
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,882141,882146,4194304,256,0,0,24,24,12928,0x7fc12859b900,0x7fc01ca35140,0,524288,524288,65536,0,65536,524288,0,216826,216826,24164327,22973889,32130,10438614,22481284,22400192,22963428,20797003,1734608,1595201,216826,0,216826,0,6938432,6254733,0,0,0,0,0,21292322,524288,0,227345,0,0,0,227345,0,0,0,227345,0,0,0,227345,0,0,0,227345,0,0,0,227345,0,0,0,227345,0,0,0,227345,0,0,0,227345,0,0,0,227345,0,0,0,227345,0,0,0,227345,0,0,0,227345,0,0,0,227345,0,0,0,227345,0,0,0,227345,0,0,0,227345,0,0,0,227345,0,0,0,227345,0,0,0,227345,0,0,0,227345,0,0,0,227345,0,0,0,227345,0,0,0,227345,0,0,0,227345,0,0,0,227345,0,0,0,227345,0,0,0,227345,0,0,0,227345,0,0,0,227345,0,0,0,227345,0,0,0,227345,0,0,0,0,66283,0,40546,0,65536,0,24994,0,65541,0,8161,0,65536,0,27609,0,65536,0,10147,0,65536,0,21781,0,65536,0,11365,0,65537,0,5532,0,65536,0,9180,0,65536,0,5764,0,65536,0,3093,0,65536,0,16093,0,65536,0,9457,0,65536,0,19076,0,65537,0,10392,0,65536,0,13037,0,65536,0,5230,0,65536,0,239,0,65536,0,5200,0,65536,0,17493,0,65536,0,4469,0,65536,0,9683,0,65536,0,433,0,65536,0,3937,0,67499,0,61878,0,65536,0,18074,0,65537,0,16747,0,65536,0,49459,0,65656,0,23412,0,65536,0,18574,0,65540,0,11096,0,65536,0,22650,0,524288,524288,0,29678929,0,0,0,31637694,0,0,0,31132408,0,0,0,51010891,0,0,0,28848134,0,0,0,30549491,0,0,0,28403807,0,0,0,34133545,0,0,0,27557278,0,0,0,26990704,0,0,0,28434750,0,0,0,25898581,0,0,0,27892391,0,0,0,30123439,0,0,0,26331582,0,0,0,30475645,0,0,0,31003191,0,0,0,26548424,0,0,0,27185944,0,0,0,49309441,0,0,0,29303995,0,0,0,32764032,0,0,0,26458984,0,0,0,27882628,0,0,0,28344646,0,0,0,30967387,0,0,0,28536164,0,0,0,30503258,0,0,0,26227595,0,0,0,26413860,0,0,0,28881838,0,0,0,34914616,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,524288,0,65656,65656,65656,0,65536,65536,65536,188,65541,65729,65729,0,65536,65536,65536,0,67523,67523,67523,0,65536,65536,65536,0,65537,65537,65537,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65584,65584,65584,0,65536,65536,65536,0,66698,66698,66698,0,65536,65536,65536,0,65536,65536,65536,0,65585,65585,65585,0,65536,65536,65536,47,65537,65584,65584,188,65540,65728,65728,0,65536,65536,65536,65536,0,0,65536,0,0,65728,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65728,0,0,65536,0,0,0,0,65536,65536,4128768,142512984,50711563,87541581,203497,0,0,0,524288,22935860,22931905,524288,524288,16384,65536,770,221039,4228,0,48,3524,0,2097536,4259840,1758096,1585257,23461277,3014656,0,0,3473408,8388608,8388608,8388608,0,0,0,0,0,172765,202243,12216,2446,0,215604,2100657,0,423,2100234,131072,0,131072,524288,0,524288,65536,65536,0,0,360,2097152,0,2097152,28758,0,2383,223399,0,2102679,0,0,31,222298112,917504,0,0,0,65536,65536,0,7624,2016653,0,2097152,2097152,0,652235,654289,0,18890,0,0,0,0,0,0,0,4194304,0,0,0,0,874182824,1381295508,0,2097152,0,0,0,0,198120,0,0,0,0,0,131072,384,48,0,0,0,432,0,0,0,0,0,5879,0,0,0,2100424,0,6526,0,917504,914734,48,7462,214364,0,0,0,0,0,0,0,0,0,327680,0,0,523798,577228,65536,64048,48,1440,0,65536,0,0,0,0,0,0,0,65536,0,0,0,1966103,0,2097152,0,0,14535209,0,524288,2102184,0,853036787,0,12075560429384177,12075586774416205,12075586774548844,12075560430633399
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/prev_analysis/1.csv
index dc2d831f44..a4a8aa6993 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,6056270.0,6056270.0,6056270.0,9.180321875081429
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4526523.0,4526523.0,4526523.0,6.861473830420245
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 256u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,3054375.0,3054375.0,3054375.0,4.629936516569083
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/prev_analysis/1001.csv
index ca08330db0..0e3bf5267e 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,46.862275449101794,Instr per wave
 SMEM,1.8083832335329342,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/prev_analysis/101.csv
index 25a69ca83d..660e406419 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx908
 mi100
 48
 1228.8
-SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/prev_analysis/1202.csv
index fdb92e5d54..37e3c5d4f6 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,33708.332039793095,2845.4057235717773,547995.8263549805,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/prev_analysis/1901.csv
index 2d17c2e8a9..1c2590ee39 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,2.0,smem_
 VALU,735.0,valu_
 MFMA,,mfma_
 VMEM,8.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,22.0,br_
 VGPR,24.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,67894.0,wavefronts_
 Workgroups,16973.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,163.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,0.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,44.0,hbm_rd_
 HBM Wr,0.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,70.0,vl1_coales_
 VL1 Stall,29.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,35.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/prev_analysis/2001.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/prev_analysis/201.csv
index 1da83d5310..30d3fddd0b 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,59.76438413359071,Pct,100,59.76438413359071
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,63.96829369599436,Threads,64,99.95045889999119
 IPC - Issue,0.843730412291422,Instr/cycle,5,16.87460824582844
-LDS BW,0.0,Gb/sec,23070.72,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,23070.72,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99339422753378,Pct,100,99.99339422753378
 Instr Cache BW,1410.5801853328412,Gb/s,4614.144,30.570788110055545
 Scalar L1D Cache Hit Rate,99.35620448524938,Pct,100,99.35620448524938
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/prev_analysis/602.csv
index d67f29da2c..31574b5a1b 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,57948.05389221557,0,754150,Simd
 Insufficient SIMD VGPRs,552109.8922155688,0,28833928,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/prev_analysis/701.csv
index d3f1bff5a3..1071413faa 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,23.976047904191617,8,36,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/sysinfo.csv
index 0107cbe24d..2a96113078 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-no_roof_L2,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 11:18:53 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+no_roof_L2,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 11:18:53 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/timestamps.csv
index ac77235680..c20f28d154 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,883441,883446,33554432,256,0,0,8,32,6464,0x0,0x7ff824e04180,12075586759212326,12075586759255753,12075586759580870,12075586759688601
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,883441,883446,32768,256,0,0,24,24,12480,0x0,0x7ff824e35100,12075586774242810,12075586774350126,12075586774357486,12075586774362522
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,883441,883446,4194304,256,0,0,24,24,12928,0x7ff930a16900,0x7ff824e35140,12075586774402597,12075586774416205,12075586774548844,12075586774551744
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/SQ_IFETCH_LEVEL.csv
index 70e4d4fd13..e4ad74db96 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/SQ_IFETCH_LEVEL.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,177804,177804,33554432,256,0,0,4,32,4160,0x0,0x7f40b8404280,381919,381919,524288,4718592,685598,76676572,16840284895039,16839606489049,16840427785593,16840427876702
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,177804,177804,32768,256,0,0,12,24,13888,0x0,0x7f40b8423f80,32605,32605,512,8192,6806,758616,16840433038203,16840427785593,16840433175018,16840433179689
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,177804,177804,4194304,256,0,0,12,24,14336,0x7f40bb50a380,0x7f40b8423fc0,164561,164561,65536,917504,146389,16367828,16840433216967,16840433175018,16840433547658,16840433550197
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/SQ_INST_LEVEL_LDS.csv
index 2b75c83a78..7c25e9e6e7 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/SQ_INST_LEVEL_LDS.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,179652,179652,33554432,256,0,0,4,32,4160,0x0,0x7fd9d3c04280,0,0,0,16859713058942,16859009125752,16859861346957,16859861457606
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,179652,179652,32768,256,0,0,12,24,13888,0x0,0x7fd9d3c23f80,0,0,0,16859866633818,16859861346957,16859866765499,16859866770364
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,179652,179652,4194304,256,0,0,12,24,14336,0x7fd9fa375380,0x7fd9d3c23fc0,0,0,0,16859866805353,16859866765499,16859867147898,16859867150612
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/SQ_INST_LEVEL_SMEM.csv
index a262ef10f0..f1ab570b00 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/SQ_INST_LEVEL_SMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,177582,177582,33554432,256,0,0,4,32,4160,0x0,0x7f086e404280,3670016,2914962,326107912,16839383772301,16811381207062,16839527269174,16839527382153
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,177582,177582,32768,256,0,0,12,24,13888,0x0,0x7f086e423f80,512,97024,10871064,16839532544354,16839527269174,16839532670119,16839532674450
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,177582,177582,4194304,256,0,0,12,24,14336,0x7f0871432380,0x7f086e423fc0,65536,635462,71138704,16839532707339,16839532670119,16839533029478,16839533031969
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/SQ_INST_LEVEL_VMEM.csv
index ba309e0af5..d83f3dd2af 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/SQ_INST_LEVEL_VMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,179430,179430,33554432,256,0,0,4,32,4160,0x0,0x7f9443c04280,524288,5466818,612353336,16858782812500,16856487414671,16858929877860,16858929990859
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,179430,179430,32768,256,0,0,12,24,13888,0x0,0x7f9443c23f80,4096,42941,4815172,16858935125832,16858929877860,16858935253682,16858935258218
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,179430,179430,4194304,256,0,0,12,24,14336,0x7f945a354380,0x7f9443c23fc0,524288,11185595,1252764532,16858935292957,16858935253682,16858935621521,16858935623797
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/SQ_LEVEL_WAVES.csv
index 7523ed1663..90ef998440 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/SQ_LEVEL_WAVES.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,178026,178026,33554432,256,0,0,4,32,4160,0x0,0x7f9f83204280,382341,382341,8876,3058736,524288,240679350,2971011,0,978934980,16841218929066,16840509341095,16841361739123,16841361852632
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,178026,178026,32768,256,0,0,12,24,13888,0x0,0x7f9f83223f80,33587,33587,30122,268704,512,1725473,157214,0,6915424,16841367031283,16841361739123,16841367170627,16841367175439
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,178026,178026,4194304,256,0,0,12,24,14336,0x7f9f8a1e2380,0x7f9f83223fc0,164382,164382,13430,1315064,65536,79519952,1211585,0,319812376,16841367220158,16841367170627,16841367564066,16841367566537
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/pmc_perf.csv
index 51dcfe9c5b..df12479b17 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDI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],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBufferAligned.kd,0,0,0,178792,178792,33554432,256,0,0,4,32,4160,0x0,0x7f0729404280,3107952,3020893,524288,39192970,245049426,392,224,0,388493,388493,39514688.0,38385068.0,6.0,4196202.0,31459476.0,31093594.0,38347938.0,37782927.0,3106241,3027301,388493,0,388493,0,12431776.0,9531576.0,0.0,0.0,0,0,616,0,4718592,4714895,112,3585,375594,0.0,0.0,0.0,524288.0,28514448.0,27788232.0,7882.0,524288.0,131072,524288,302,384680,2230,0,56.0,304.0,0.0,4194696.0,0,0,0,0,0,7340032,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,19854204.0,524288.0,0,380989,0,0,0,380989,0,0,0,380989,0,0,0,380989,0,0,0,380989,0,0,0,380989,0,0,0,380989,0,0,0,380989,0,0,0,380989,0,0,0,380989,0,0,0,380989,0,0,0,380989,0,0,0,380989,0,0,0,380989,0,0,0,380989,0,0,0,380989,0,0,0,380989,0,0,0,380989,0,0,0,380989,0,0,0,380989,0,0,0,380989,0,0,0,380989,0,0,0,380989,0,0,0,380989,0,0,0,380989,0,0,0,380989,0,0,0,380989,0,0,0,380989,0,0,0,380989,0,0,0,380989,0,0,0,380989,0,0,0,380989,0,0,0,0,0,0.0,21300826.0,0,0,0,0,0,0,0,0,0,0,0,0,34,0,0,0,3,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,0,0,0,0,0,0,112,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,92,0,0,0,5,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,0,0,1,0,0,0,524288.0,0.0,0,44414,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,328,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,43891,129024,129024,0,0,129024,129024,0,0,129024,129024,0,525760,129024,129024,0,0,129024,129024,0,0,129024,129024,0,185,129024,129024,0,194,129024,129024,0,0,129024,129024,0,28815,129024,129024,0,861,129024,129024,0,279078,129024,129024,0,0,129024,129024,0,870,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,45478,129024,129024,0,306,129024,129024,0,0,129024,129024,0,0,129024,129024,0,274,129024,129024,524288.0,0.0,43746,0,0,50313039,45227,0,0,50782628,43524,0,0,49804632,46647,0,0,51666842,44960,0,0,51283622,46043,0,0,51494901,45354,0,0,51100175,48361,0,0,52952686,46130,0,0,51073679,46195,0,0,50927009,45226,0,0,50397236,48619,0,0,52486019,46691,0,0,51515483,46393,0,0,51598721,46731,0,0,51338614,49287,0,0,53355267,44086,0,0,50636213,46485,0,0,50881661,43377,0,0,49954369,47038,0,0,51967354,45477,0,0,51281111,45941,0,0,51282842,43738,0,0,50478042,47488,0,0,52504685,45601,0,0,50970658,46353,0,0,51041182,45058,0,0,50410430,47816,0,0,52160548,45478,0,0,51277221,47719,0,0,51929184,46012,0,0,51084312,48577,0,0,52965601,0.0,65536,65568,32,131104,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65646,65538,112,131184,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65568,32,131104,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65592,56,131128,65536,65648,112,131184,65536,65536,0,131072,65536,65571,35,131107,65536,65536,0,131072,65536,65536,0,131072,65536,65537,1,131073,65758,65538,224,131296,65536,65536,0,131072,65536,65536,0,131072,65536,65538,2,131074,65536,65536,0,131072,65536,65568,32,131104,65536,65536,0,131072,65591,65538,57,131129,65536,65536,0,131072,65591,65537,56,131128,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131184,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131296,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131128,0,131072,1147845,0,524288,3670016,3663216,224,6576,1048576,33554432.0,33554432.0,0.0,33554432.0,30344352.0,28700871.0,0.0,524288.0,222146,536309,8422,920,0,385118,4195055.0,0.0,2097594.0,2097461.0,1048576,1048576,0,524288,0,524288,7340032,0,0.0,0.0,104.0,8388608.0,29946572.0,2097152.0,0.0,210138,0,1224,388164,0,749.0,4194304.0,0.0,2064387.0,25690112,9437184,0,0,0,0,0,0,13293.0,8242385.0,0.0,8388608.0,2097152.0,4194304.0,9763844,0,0,9240,4128768.0,4128768.0,0.0,1489235.0,0,0,0,0,0,0,5767168,1048576,314971157.0,0.0,1469822122.0,0.0,43.0,0.0,0,0,370405,0.0,0.0,1477010.0,0.0,3670016,524288,0,0,0,2621440,524288,174068746,4194304.0,0.0,0.0,0.0,0.0,1254130.0,0,0,0.0,309.0,0.0,602.0,42757819,24117248,0,0,9437184,11010048,0,3145728,0.0,0.0,0.0,0.0,0.0,0.0,0,1572864,0.0,0.0,0.0,201126.0,524288,524288,0,3670016,7340032,603979776,4718592,0,0.0,0.0,0.0,0.0,0.0,0.0,524288,0,2064384.0,0.0,2031623.0,0.0,0,0,524288,0,0,0,0,33554432,0.0,4194304.0,0.0,19010385.0,0.0,0.0,141.0,4128768.0,658190.0,1650540786.0,16842641898872,16860531261993,16860531499752,16842795667668
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,178792,178792,32768,256,0,0,12,24,13888,0x0,0x7f0729423f80,266928,161311,512,1395082,1701066,504,56,0,33365,33365,2332843.0,171277.0,175.0,0.0,35749.0,32721.0,164984.0,146199.0,266920,169156,33365,0,33365,0,1067680.0,382179.0,0.0,0.0,0,0,560,0,8192,6183,56,1953,24241,0.0,0.0,0.0,4096.0,34221.0,32879.0,0.0,4096.0,128,512,302,33526,2270,0,0.0,60.0,0.0,4600.0,0,0,0,0,0,1024,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,11623.0,4096.0,0,34402,0,0,0,34402,0,0,0,34402,0,0,0,34402,0,0,0,34402,0,0,0,34402,0,0,0,34402,0,0,0,34402,0,0,0,34402,0,0,0,34402,0,0,0,34402,0,0,0,34402,0,0,0,34402,0,0,0,34402,0,0,0,34402,0,0,0,34402,0,0,0,34402,0,0,0,34402,0,0,0,34402,0,0,0,34402,0,0,0,34402,0,0,0,34402,0,0,0,34402,0,0,0,34402,0,0,0,34402,0,0,0,34402,0,0,0,34402,0,0,0,34402,0,0,0,34402,0,0,0,34402,0,0,0,34402,0,0,0,34402,0,0,0,0,0,0.0,0.0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,316,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,257,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,4096.0,4096.0,0,77163,0,0,0,79311,0,0,0,78674,0,0,0,119625,0,0,0,83325,0,0,0,80584,0,0,0,77287,0,0,0,141440,0,0,0,124918,0,0,0,80649,0,0,0,89142,0,0,0,85158,0,0,0,637134,0,0,0,83288,0,0,0,100112,0,0,0,95632,0,0,0,83354,0,0,0,75686,0,0,0,78492,0,0,0,80366,0,0,0,79224,0,0,0,80718,0,0,0,84556,0,0,0,87760,0,0,0,87569,0,0,0,79259,0,0,0,77951,0,0,0,107226,0,0,0,76197,0,0,0,82332,0,0,0,79738,0,0,0,81410,0,0,0.0,0.0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4096.0,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,222,130,352,352,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,222,130,352,352,0,128,128,128,0,184,184,184,0,128,128,128,0,129,129,129,0,128,128,128,0,128,128,128,0,129,129,129,0,128,128,128,55,129,184,184,0,128,128,128,0,129,129,129,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,352,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,352,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,184,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,680,0,0,512,0,56,456,0,65536.0,65536.0,65536.0,0.0,0.0,0.0,0.0,0.0,6,518,11228,1043,0,30567,4661.0,0.0,499.0,4162.0,512,0,0,0,4096,4096,512,0,0.0,0.0,104.0,16384.0,0.0,16384.0,4096.0,0,0,1448,32312,0,4661.0,0.0,0.0,31.0,35328,26112,0,0,0,0,0,0,104.0,15240.0,0.0,16384.0,16384.0,0.0,0,0,0,30146,0.0,0.0,0.0,0.0,0,0,0,0,0,0,10752,3584,4501387.0,5646916.0,0.0,8192.0,2.0,0.0,0,0,498,0.0,0.0,0.0,0.0,512,4096,0,0,0,512,512,1648551,0.0,0.0,0.0,0.0,0.0,1416.0,0,0,0.0,8260.0,0.0,118.0,13457,32256,0,0,26112,1024,0,1024,0.0,0.0,0.0,0.0,0.0,0.0,0,1024,0.0,0.0,0.0,43517.0,4096,0,4096,512,512,1671168,8192,0,0.0,0.0,0.0,0.0,0.0,0.0,512,0,0.0,0.0,0.0,0.0,0,0,512,0,0,0,0,32768,8192.0,0.0,0.0,116679.0,0.0,4096.0,8204.0,0.0,3226089.0,0.0,16842801844658,16860536322773,16860536336053,16842802317084
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,178792,178792,4194304,256,0,0,12,24,14336,0x7f072c42b380,0x7f0729423fc0,1319024,1211062,65536,15650168,83939690,392,56,0,164877,164877,15975024.0,14520472.0,24380.0,589172.0,13968877.0,13853595.0,14513480.0,12376849.0,1319016,1217988,164877,0,164877,0,5276064.0,4725370.0,0.0,0.0,0,0,448,0,917504,913606,0,3898,153160,0.0,0.0,0.0,524288.0,13255016.0,13229070.0,2197.0,524288.0,16384,65536,302,164752,2255,0,0.0,184.0,0.0,1048968.0,0,0,0,0,0,131072,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,10229290.0,524288.0,0,172240,0,0,0,172240,0,0,0,172240,0,0,0,172240,0,0,0,172240,0,0,0,172240,0,0,0,172240,0,0,0,172240,0,0,0,172240,0,0,0,172240,0,0,0,172240,0,0,0,172240,0,0,0,172240,0,0,0,172240,0,0,0,172240,0,0,0,172240,0,0,0,172240,0,0,0,172240,0,0,0,172240,0,0,0,172240,0,0,0,172240,0,0,0,172240,0,0,0,172240,0,0,0,172240,0,0,0,172240,0,0,0,172240,0,0,0,172240,0,0,0,172240,0,0,0,172240,0,0,0,172240,0,0,0,172240,0,0,0,172240,0,0,0,0,0,0.0,0.0,65536,0,5262,0,65536,0,24740,0,65536,0,33932,0,65539,0,12252,0,65536,0,37700,0,65536,0,20288,0,65536,0,14810,0,65536,0,26986,0,65536,0,13509,0,65536,0,6614,0,65536,0,10249,0,65536,0,13256,0,65536,0,8203,0,65536,0,41415,0,65592,0,7656,0,65536,0,31140,0,65536,0,14098,0,65536,0,21711,0,65536,0,6140,0,65536,0,15335,0,65536,0,17072,0,65597,0,8682,0,65537,0,19501,0,65539,0,8096,0,65540,0,3719,0,65536,0,16566,0,65536,0,8544,0,65536,0,5848,0,65536,0,6097,0,65537,0,35222,0,65599,0,10116,0,65536,0,40419,0,524288.0,524288.0,0,47814849,0,0,0,45938061,0,0,0,47641585,0,0,0,48912478,0,0,0,47433790,0,0,0,47717051,0,0,0,47534072,0,0,0,47411211,0,0,0,42598098,0,0,0,48728118,0,0,0,41292475,0,0,0,47596703,0,0,0,49031000,0,0,0,46783951,0,0,0,47348574,0,0,0,46532873,0,0,0,46881511,0,0,0,48554059,0,0,0,43201112,0,0,0,48953559,0,0,0,47428389,0,0,0,47328269,0,0,0,48732025,0,0,0,42270186,0,0,0,39850384,0,0,0,40137255,0,0,0,44311159,0,0,0,41972241,0,0,0,42607893,0,0,0,46191707,0,0,0,47382356,0,0,0,46691299,0,0,0.0,0.0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,524288.0,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32824,32824,32824,0,32768,32768,32768,0,32828,32828,32828,0,32769,32769,32769,0,32769,32769,32769,0,32769,32769,32769,0,32768,32768,32768,166,32770,32936,32936,222,32770,32992,32992,0,32769,32769,32769,0,32768,32768,32768,0,32828,32828,32828,0,32768,32768,32768,0,32769,32769,32769,0,32768,32768,32768,0,32768,32768,32768,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32936,0,0,32992,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,924860,0,0,65536,63800,56,1680,0,8388608.0,8388608.0,8388608.0,0.0,0.0,0.0,0.0,0.0,125678,148834,9829,2550,0,162034,1049152.0,0.0,388.0,1048764.0,65536,0,0,0,524288,524288,131072,0,0.0,0.0,104.0,2097152.0,0.0,2097152.0,524288.0,43497,0,3413,161522,0,1049147.0,0.0,0.0,31.0,4063232,2883584,0,0,0,0,0,0,6598.0,2027337.0,0.0,2097152.0,2097152.0,0.0,1317365,0,0,13470,0.0,0.0,0.0,0.0,262144,0,0,0,0,0,1507328,458752,999226667.0,2300664217.0,0.0,2097152.0,41.0,0.0,0,0,147529,0.0,0.0,0.0,0.0,65536,524288,0,0,0,65536,65536,46961697,0.0,0.0,0.0,0.0,0.0,22885.0,0,0,0.0,2097342.0,0.0,366.0,46510656,3735552,0,0,2883584,196608,0,131072,0.0,0.0,0.0,0.0,0.0,0.0,0,131072,0.0,0.0,663993.0,2081025.0,524288,0,524288,65536,131072,184549376,917504,0,0.0,0.0,0.0,0.0,0.0,0.0,65536,0,0.0,0.0,983047.0,0.0,0,0,65536,0,0,0,0,4194304,2097152.0,0.0,0.0,12387446.0,0.0,524288.0,2097285.0,0.0,1480550677.0,0.0,16842803413080,16860536405493,16860536497973,16842804158817
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/prev_analysis/1.csv
index c871359323..e9694f55fd 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,3356788.0,3356788.0,3356788.0,7.842024139073824
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,1726233.0,1726233.0,1726233.0,4.032772059381118
 "void benchmark_func<double, 256, 8u, 512u>(double, double*) [clone .kd]",1,1715194.0,1715194.0,1715194.0,4.006983089547087
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/prev_analysis/1001.csv
index f475f954a6..fb5988001a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,494.8622754491018,Instr per wave
 VMEM,7.958083832335329,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,0.0,Instr per wave
 SALU,24.520958083832337,Instr per wave
 SMEM,1.8023952095808384,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/prev_analysis/101.csv
index 91732ddff9..e1c61389ba 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx90a
 mi200
 56
 1638.4
-SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/prev_analysis/1202.csv
index ce7690ba4d..e9290e2588 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,18359.682815003536,1869.5787506103516,258019.01513671875,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/prev_analysis/1901.csv
index b94ce35d47..1a087b5154 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,2.0,smem_
 VALU,495.0,valu_
 MFMA,0.0,mfma_
 VMEM,8.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,10.0,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,67894.0,wavefronts_
 Workgroups,16973.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,128.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,0.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,44.0,hbm_rd_
 HBM Wr,0.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,70.0,vl1_coales_
 VL1 Stall,2.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,26.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/prev_analysis/201.csv
index 4742f0578c..6701b61648 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,58.29673236113646,Pct,100,58.29673236113646
 MFMA Util,0.0,Pct,100,0.0
 VALU Active Threads/Wave,64.0,Threads,64,100.0
 IPC - Issue,1.0,Instr/cycle,5,20.0
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99258642521708,Pct,100,99.99258642521708
 Instr Cache BW,1673.8972944706347,Gb/s,6092.8,27.473366834142507
 Scalar L1D Cache Hit Rate,99.34855885966435,Pct,100,99.34855885966435
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/prev_analysis/602.csv
index 1b54f86f5a..631f46a52d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,12161038.125748502,0,383489245,Simd
 Insufficient SIMD VGPRs,0.0,0,0,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/prev_analysis/701.csv
index 12250d77c0..db0925a109 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/sysinfo.csv
index 341ee7a704..8372305d20 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-no_roof_L2,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:33:59 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+no_roof_L2,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:33:59 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/timestamps.csv
index b672dcb254..a7442fe1b5 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_L2/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,179735,179735,33554432,256,0,0,4,32,4160,0x0,0x7f657d204280,16860531235832,16860531261993,16860531499752,16860531588771
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,179735,179735,32768,256,0,0,12,24,13888,0x0,0x7f657d223f80,16860536306988,16860536322773,16860536336053,16860536353576
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,179735,179735,4194304,256,0,0,12,24,14336,0x7f65802d0380,0x7f657d223fc0,16860536359256,16860536405493,16860536497973,16860536500272
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/SQ_IFETCH_LEVEL.csv
index da9739ae5e..1ef5409b49 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/SQ_IFETCH_LEVEL.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,886680,886685,33554432,256,0,0,8,32,6464,0x0,0x7f98d4204180,505193,505193,524288,6291456,791260,101350472,12075665363674578,12075665606759266,12075665607084224,12075665607198306
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,886680,886685,32768,256,0,0,24,24,12480,0x0,0x7f98d4235100,26708,26708,512,8192,9259,1192656,12075665621709475,12075665622024186,12075665622030106,12075665622035671
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,886680,886685,4194304,256,0,0,24,24,12928,0x7f99dfd94900,0x7f98d4235140,218404,218404,65536,917504,132523,17002904,12075665622094921,12075665622329624,12075665622462904,12075665622465891
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/SQ_INST_LEVEL_LDS.csv
index f764b8cb58..9491c4fd56 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/SQ_INST_LEVEL_LDS.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,888478,888483,33554432,256,0,0,8,32,6464,0x0,0x7f6b8fa04180,0,0,0,12075691988771742,12075692235331689,12075692235657127,12075692235743799
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,888478,888483,32768,256,0,0,24,24,12480,0x0,0x7f6b8fa35100,0,0,0,12075692250649060,12075692250949049,12075692250955449,12075692250966700
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,888478,888483,4194304,256,0,0,24,24,12928,0x7f6cbfd3f900,0x7f6b8fa35140,0,0,0,12075692251083307,12075692251279767,12075692251419766,12075692251424521
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/SQ_INST_LEVEL_SMEM.csv
index 218429ab2c..1d9b01dbdd 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/SQ_INST_LEVEL_SMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,888100,888105,33554432,256,0,0,8,32,6464,0x0,0x7f49be204180,4194304,3091928,395511152,12075689455409911,12075689702511295,12075689702834494,12075689702945996
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,888100,888105,32768,256,0,0,24,24,12480,0x0,0x7f49be235100,512,19438,2487784,12075689717521184,12075689717825428,12075689717831668,12075689717843964
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,888100,888105,4194304,256,0,0,24,24,12928,0x7f4ac9dc0900,0x7f49be235140,65536,153344,19642224,12075689717899497,12075689718126387,12075689718259186,12075689718262041
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/SQ_INST_LEVEL_VMEM.csv
index 425fb0edd8..e3d90db469 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/SQ_INST_LEVEL_VMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,888290,888295,33554432,256,0,0,8,32,6464,0x0,0x7ff9c9204180,1048576,11115189,1422752100,12075690716652435,12075690959335080,12075690959657319,12075690959788262
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,888290,888295,32768,256,0,0,24,24,12480,0x0,0x7ff9c9235100,4096,109827,14039984,12075690974519309,12075690974851012,12075690974857572,12075690974872115
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,888290,888295,4194304,256,0,0,24,24,12928,0x7ffad4ef0900,0x7ff9c9235140,524288,11930885,1527102668,12075690974923620,12075690975198850,12075690975333410,12075690975337470
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/SQ_LEVEL_WAVES.csv
index df1436c3c4..f46c6fdaf2 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/SQ_LEVEL_WAVES.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,888668,888673,33554432,256,0,0,8,32,6464,0x0,0x7fd386a04180,503298,503298,16208,4026392,524288,368681213,3823942,0,1489509324,12075693255469203,12075693503558436,12075693503882275,12075693503995028
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,888668,888673,32768,256,0,0,24,24,12480,0x0,0x7fd386a35100,27453,27453,20349,219632,512,1099007,75824,0,4410052,12075693518940393,12075693519276566,12075693519282966,12075693519292367
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,888668,888673,4194304,256,0,0,24,24,12928,0x7fd4925e5900,0x7fd386a35140,225660,225660,21632,1805288,65536,148270238,1641641,0,594887172,12075693519362728,12075693519605845,12075693519743764,12075693519746681
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/pmc_dispatch_info.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/pmc_perf.csv
index c41e413d63..c6a4de4e72 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBuffer.kd,0,0,0,887414,887419,33554432,256,0,0,8,32,6464,0x0,0x7f91f0a04180,1048576,0,1048576,9437184,0,4194304,1048576,0,502081,502081,57679079,55102842,136,13320092,54495715,54421279,55067778,53893629,4016648,3829730,502081,0,502081,0,16066592,15204453,0,0,0,0,0,17455272,1048576,0,503951,0,0,0,503951,0,0,0,503951,0,0,0,503951,0,0,0,503951,0,0,0,503951,0,0,0,503951,0,0,0,503951,0,0,0,503951,0,0,0,503951,0,0,0,503951,0,0,0,503951,0,0,0,503951,0,0,0,503951,0,0,0,503951,0,0,0,503951,0,0,0,503951,0,0,0,503951,0,0,0,503951,0,0,0,503951,0,0,0,503951,0,0,0,503951,0,0,0,503951,0,0,0,503951,0,0,0,503951,0,0,0,503951,0,0,0,503951,0,0,0,503951,0,0,0,503951,0,0,0,503951,0,0,0,503951,0,0,0,503951,0,0,0,37615109,2567,0,0,0,100,0,0,0,1,0,0,0,0,0,0,0,2653,0,0,0,0,0,0,0,0,0,0,0,48,0,0,0,0,0,0,0,0,0,0,0,3,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,3,0,0,0,0,0,0,0,0,0,0,0,2595,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2601,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,15,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,1048576,0,0,0,131080,131080,0,19998,131072,131072,0,0,131072,131072,0,0,131076,131076,0,0,131088,131088,0,0,131072,131072,0,5009,131072,131072,0,0,131072,131072,0,0,131076,131076,0,275,131072,131072,0,3097914,131072,131072,0,0,131072,131072,0,0,131076,131076,0,0,131072,131072,0,0,131076,131076,0,0,131072,131072,0,3295085,131080,131080,0,2226,131076,131076,0,373,131076,131076,0,0,131072,131072,0,378,131072,131072,0,0,131072,131072,0,3228820,131073,131073,0,0,131072,131072,0,0,131072,131072,0,793,131072,131072,0,2914196,131080,131080,0,0,131072,131072,0,1550,131076,131076,0,0,131072,131072,0,0,131072,131072,0,541131,131072,131072,1048576,0,48463,0,0,30127894,834,0,0,17059917,1075,0,0,16960359,908,0,0,17251215,858,0,0,17046695,873,0,0,17329890,781,0,0,17771351,1532,0,0,18961544,942,0,0,16872390,874,0,0,17217954,2027,0,0,17093962,1676,0,0,16892975,50956,0,0,30639987,1589,0,0,17555433,926,0,0,17953665,807,0,0,18434917,1451,0,0,17036012,1035,0,0,16853941,1116,0,0,16920034,758,0,0,16825226,817,0,0,17075461,1330,0,0,17225830,763,0,0,18062481,752,0,0,18575051,43401,0,0,27995382,790,0,0,16860949,1001,0,0,16847397,749,0,0,16758784,50624,0,0,30606176,821,0,0,17426785,1070,0,0,17926672,793,0,0,18620641,1048576,131072,131072,0,262144,131260,131079,195,262339,131072,131072,0,262144,131072,133771,2699,264843,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,133600,2528,264672,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131073,1,262145,131072,131072,0,262144,131072,131120,48,262192,131072,133663,2591,264735,131072,131072,0,262144,131213,131124,193,262337,131072,131073,1,262145,131072,133788,2716,264860,131072,131096,24,262168,131072,131072,0,262144,131072,131120,48,262192,131072,131072,0,262144,131072,131072,0,262144,131119,131073,48,262192,131072,131072,0,262144,131072,131072,0,262144,131119,131073,48,262192,131072,131072,0,262144,131072,131073,1,262145,131072,131072,0,262144,262144,0,262144,262336,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262288,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,0,0,3145728,524288,32505856,370274667,219974565,117794246,480180,0,0,0,1048576,52567256,52359398,1048576,1048576,131072,524288,684,502307,4363,0,96,10449,0,8388944,32505856,4015240,3809852,56938780,11534336,0,0,14155776,67108864,67108864,0,67108864,53950691,53584147,0,1048576,229796,754084,11908,2551,0,497517,8399483,0,4194727,4204756,13631488,0,3670016,1048576,1048576,0,4194304,9437184,0,0,360,33554432,54149615,4194304,0,0,2414,498299,0,10986,8388608,0,4194386,905969664,6291456,0,0,0,524288,524288,0,15335,16608638,0,16777216,4194304,4194304,0,0,0,17103,4194384,4194384,0,222816,0,0,0,33554432,0,0,0,0,631605860,0,2775761797,0,0,0,0,0,479590,0,0,219562,0,0,8388608,336,144,0,0,0,480,8388608,0,0,0,0,346030,0,0,0,10800,0,21582,0,6291456,6289440,96,2207,1921538,0,0,0,0,0,0,0,0,0,3145728,0,0,0,146611,4194304,4189861,144,4299,2097152,524288,1572864,0,0,0,0,0,0,524288,0,4128828,65532,4063249,0,0,8388608,0,42111035,0,1048576,10580,4194348,12932969,609436708,12075667522502114,12075694399805565,12075694400129562,12075667770658622
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,887414,887419,32768,256,0,0,24,24,12480,0x0,0x7f91f0a35100,0,4096,4096,512,0,512,4096,0,28293,28293,1545182,630839,190,115427,83821,61425,622712,602198,226344,88833,28293,0,28293,0,905376,199190,0,0,0,0,0,60715,4096,0,27902,0,0,0,27902,0,0,0,27902,0,0,0,27902,0,0,0,27902,0,0,0,27902,0,0,0,27902,0,0,0,27902,0,0,0,27902,0,0,0,27902,0,0,0,27902,0,0,0,27902,0,0,0,27902,0,0,0,27902,0,0,0,27902,0,0,0,27902,0,0,0,27902,0,0,0,27902,0,0,0,27902,0,0,0,27902,0,0,0,27902,0,0,0,27902,0,0,0,27902,0,0,0,27902,0,0,0,27902,0,0,0,27902,0,0,0,27902,0,0,0,27902,0,0,0,27902,0,0,0,27902,0,0,0,27902,0,0,0,27902,0,0,0,0,256,0,0,0,304,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,304,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,377,0,0,0,256,0,0,0,258,0,0,0,256,0,0,0,4096,4096,0,125523,0,0,0,172668,0,0,0,72166,0,0,0,106582,0,0,0,84552,0,0,0,143082,0,0,0,189913,0,0,0,96304,0,0,0,79739,0,0,0,95703,0,0,0,112265,0,0,0,97149,0,0,0,83794,0,0,0,91619,0,0,0,74799,0,0,0,75389,0,0,0,89437,0,0,0,131118,0,0,0,80220,0,0,0,90698,0,0,0,106504,0,0,0,125374,0,0,0,112658,0,0,0,100065,0,0,0,110239,0,0,0,86254,0,0,0,73968,0,0,0,71161,0,0,0,101044,0,0,0,80056,0,0,0,83282,0,0,0,94611,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4096,0,256,256,256,0,257,257,257,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,257,257,257,0,256,256,256,188,260,448,448,0,256,256,256,0,256,256,256,0,305,305,305,188,261,449,449,0,256,256,256,0,376,376,376,0,256,256,256,0,304,304,304,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,47,257,304,304,0,256,256,256,47,258,305,305,0,256,256,256,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,304,0,0,256,0,0,0,0,512,512,35328,1061515,1008678,16485,11313,0,0,0,4096,70519,67546,4096,4096,128,512,586,27194,4330,0,48,172,0,8624,36352,228688,75740,1058410,26624,0,0,30208,65536,65536,65536,0,0,0,0,0,114,626,12239,2020,0,24282,8891,0,470,8421,1024,0,1024,4096,0,4096,512,512,0,0,360,16384,0,16384,0,0,2443,26474,0,8891,0,0,31,1933312,8192,0,0,0,512,512,0,120,15064,0,16384,16384,0,0,0,0,20313,0,0,0,0,0,0,0,32768,0,0,0,0,11976503,16743821,0,8192,0,0,0,0,694,0,0,0,0,0,1024,432,48,0,0,0,480,0,0,0,0,0,3191,0,0,0,8422,0,440,0,8192,6543,48,1601,1098,0,0,0,0,0,0,0,0,0,2560,0,0,0,47972,512,0,48,464,0,512,0,0,0,0,0,0,0,512,0,0,0,0,0,8192,0,0,459799,0,4096,8420,0,3335420,0,12075667785733067,12075694414846664,12075694414853544,12075667786704983
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,887414,887419,4194304,256,0,0,24,24,12928,0x7f92fc736900,0x7f91f0a35140,0,524288,524288,65536,0,65536,524288,0,225834,225834,25178147,23828700,28706,5002645,22113512,21930842,23799420,21636901,1806672,1662045,225834,0,225834,0,7226688,6526662,0,0,0,0,0,21256271,524288,0,227047,0,0,0,227047,0,0,0,227047,0,0,0,227047,0,0,0,227047,0,0,0,227047,0,0,0,227047,0,0,0,227047,0,0,0,227047,0,0,0,227047,0,0,0,227047,0,0,0,227047,0,0,0,227047,0,0,0,227047,0,0,0,227047,0,0,0,227047,0,0,0,227047,0,0,0,227047,0,0,0,227047,0,0,0,227047,0,0,0,227047,0,0,0,227047,0,0,0,227047,0,0,0,227047,0,0,0,227047,0,0,0,227047,0,0,0,227047,0,0,0,227047,0,0,0,227047,0,0,0,227047,0,0,0,227047,0,0,0,227047,0,0,0,0,68145,0,74321,0,65584,0,3712,0,65540,0,2857,0,65536,0,1148,0,65536,0,12275,0,65536,0,4451,0,65536,0,7853,0,65584,0,7631,0,65536,0,569,0,65536,0,6069,0,65536,0,433,0,65536,0,713,0,65537,0,3295,0,65536,0,636,0,65536,0,5446,0,65536,0,9025,0,65536,0,8748,0,65536,0,9774,0,65536,0,5827,0,65536,0,5431,0,65536,0,598,0,65536,0,1026,0,65536,0,916,0,65536,0,526,0,67693,0,61606,0,65536,0,3887,0,65536,0,4178,0,65536,0,974,0,65657,0,3656,0,65536,0,3710,0,65541,0,0,0,65536,0,185,0,524288,524288,0,42350029,0,0,0,43086675,0,0,0,39346191,0,0,0,39069966,0,0,0,37439585,0,0,0,33441441,0,0,0,38826464,0,0,0,45539175,0,0,0,41906159,0,0,0,41355519,0,0,0,45930707,0,0,0,35702693,0,0,0,38972675,0,0,0,31746600,0,0,0,41928037,0,0,0,45541354,0,0,0,37915614,0,0,0,38293888,0,0,0,31520843,0,0,0,32607243,0,0,0,36396589,0,0,0,40094966,0,0,0,38731729,0,0,0,41163639,0,0,0,39324278,0,0,0,38774854,0,0,0,46507521,0,0,0,42628190,0,0,0,39279605,0,0,0,48489672,0,0,0,37773414,0,0,0,46420150,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,524288,0,65536,65536,65536,0,65537,65537,65537,188,65540,65728,65728,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65804,65804,65804,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65537,65537,65537,0,65536,65536,65536,0,65536,65536,65536,0,67466,67466,67466,0,65536,65536,65536,0,65585,65585,65585,0,65537,65537,65537,0,65536,65536,65536,0,65656,65656,65656,0,65536,65536,65536,0,65584,65584,65584,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,47,65537,65584,65584,0,65536,65536,65536,188,65541,65729,65729,0,65536,65536,65536,65536,0,0,65536,0,0,65728,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65728,0,0,65536,0,0,0,0,65536,65536,4128768,153178110,47604108,101314162,204391,0,0,0,524288,23110876,23107254,524288,524288,16384,65536,750,222230,4185,0,48,3688,0,2097536,4259840,1774544,1605135,23726502,3014656,0,0,3473408,8388608,8388608,8388608,0,0,0,0,0,170036,200048,11406,2066,0,217519,2101336,0,423,2100913,131072,0,131072,524288,0,524288,65536,65536,0,0,360,2097152,0,2097152,34211,0,2407,217250,0,2100818,0,0,31,222298112,917504,0,0,0,65536,65536,0,7544,2018461,0,2097152,2097152,0,675269,677494,0,19586,0,0,0,0,0,0,0,4194304,0,0,0,0,951341516,1545064680,0,2097152,0,0,0,0,196889,0,0,0,0,0,131072,384,48,0,0,0,432,0,0,0,0,0,10473,0,0,0,2100451,0,6580,0,917504,915134,48,6925,207065,0,0,0,0,0,0,0,0,0,327680,0,0,266034,319121,65536,64048,48,1440,0,65536,0,0,0,0,0,0,0,65536,0,0,0,1966099,0,2097152,0,0,17503161,0,524288,2099601,0,1154102293,0,12075667787336066,12075694414912583,12075694415050502,12075667788604483
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/prev_analysis/1.csv
index 0816a365b5..9d6c29332c 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,6055313.0,6055313.0,6055313.0,9.153802447178489
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4526845.0,4526845.0,4526845.0,6.843220959675858
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 256u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,3055177.0,3055177.0,3055177.0,4.618503898834533
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/prev_analysis/1001.csv
index ca08330db0..0e3bf5267e 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,46.862275449101794,Instr per wave
 SMEM,1.8083832335329342,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/prev_analysis/101.csv
index 6858d9483d..d030b043ee 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx908
 mi100
 48
 1228.8
-SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/prev_analysis/1202.csv
index 5de79da3b2..261470ec52 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,33792.64228807095,2824.971519470215,547863.3396606445,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/prev_analysis/1901.csv
index 0dbd881d89..f5f3b597ed 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,2.0,smem_
 VALU,735.0,valu_
 MFMA,,mfma_
 VMEM,8.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,22.0,br_
 VGPR,24.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,67894.0,wavefronts_
 Workgroups,16973.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,163.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,0.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,44.0,hbm_rd_
 HBM Wr,0.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,70.0,vl1_coales_
 VL1 Stall,30.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,36.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/prev_analysis/2001.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/prev_analysis/201.csv
index f2ac2bf694..4998c9b8bd 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,59.498075581463596,Pct,100,59.498075581463596
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,63.967365846180016,Threads,64,99.94900913465628
 IPC - Issue,0.8437219202975509,Instr/cycle,5,16.874438405951018
-LDS BW,0.0,Gb/sec,23070.72,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,23070.72,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99341732931109,Pct,100,99.99341732931109
 Instr Cache BW,1404.5621523461245,Gb/s,4614.144,30.44036233689552
 Scalar L1D Cache Hit Rate,99.3562044852641,Pct,100,99.3562044852641
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/prev_analysis/602.csv
index 6635852b5a..53ea2b1058 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,59333.59281437126,0,675269,Simd
 Insufficient SIMD VGPRs,510077.371257485,0,32159342,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/prev_analysis/701.csv
index d3f1bff5a3..1071413faa 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,23.976047904191617,8,36,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/sysinfo.csv
index 660bdb218e..ed2a9c0590 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-no_roof_LDS,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 11:20:40 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+no_roof_LDS,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 11:20:40 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/timestamps.csv
index 50515c358c..7b31981e10 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,888717,888722,33554432,256,0,0,8,32,6464,0x0,0x7fdfc0a04180,12075694399763814,12075694399805565,12075694400129562,12075694400241953
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,888717,888722,32768,256,0,0,24,24,12480,0x0,0x7fdfc0a35100,12075694414747250,12075694414846664,12075694414853544,12075694414858728
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,888717,888722,4194304,256,0,0,24,24,12928,0x7fe0cc5b8900,0x7fdfc0a35140,12075694414899373,12075694414912583,12075694415050502,12075694415053690
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/SQ_IFETCH_LEVEL.csv
index 9eb4a67d74..8bfc3346e6 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/SQ_IFETCH_LEVEL.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,184236,184236,33554432,256,0,0,4,32,4160,0x0,0x7fee55204280,386516,386516,524288,4718592,685264,76679568,16953847137113,16953138320733,16953997271590,16953997383379
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,184236,184236,32768,256,0,0,12,24,13888,0x0,0x7fee55223f80,34791,34791,512,8192,7523,843944,16954002581675,16953997271590,16954002717340,16954002722171
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,184236,184236,4194304,256,0,0,12,24,14336,0x7fee58218380,0x7fee55223fc0,164259,164259,65536,917504,153577,17134652,16954002759440,16954002717340,16954003100700,16954003103440
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/SQ_INST_LEVEL_LDS.csv
index 49534e1223..ac66b3dd21 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/SQ_INST_LEVEL_LDS.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,186084,186084,33554432,256,0,0,4,32,4160,0x0,0x7f94d7004280,0,0,0,16973195804354,16972484773181,16973344589663,16973344660002
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,186084,186084,32768,256,0,0,12,24,13888,0x0,0x7f94d7023f80,0,0,0,16973349824352,16973344589663,16973349947567,16973349952398
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,186084,186084,4194304,256,0,0,12,24,14336,0x7f94d9f95380,0x7f94d7023fc0,0,0,0,16973349986577,16973349947567,16973350328206,16973350330797
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/SQ_INST_LEVEL_SMEM.csv
index fd946318a0..2ac30aa05c 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/SQ_INST_LEVEL_SMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,184014,184014,33554432,256,0,0,4,32,4160,0x0,0x7f1801604280,3670016,3052198,341830256,16952912946575,16924899554579,16953056898851,16953057010350
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,184014,184014,32768,256,0,0,12,24,13888,0x0,0x7f1801623f80,512,102772,11501280,16953062182138,16953056898851,16953062317723,16953062322224
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,184014,184014,4194304,256,0,0,12,24,14336,0x7f180462e380,0x7f1801623fc0,65536,609332,68242880,16953062356463,16953062317723,16953062699802,16953062702283
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/SQ_INST_LEVEL_VMEM.csv
index 2b764963c5..01f08bf39f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/SQ_INST_LEVEL_VMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,185862,185862,33554432,256,0,0,4,32,4160,0x0,0x7fc67fc04280,524288,5482426,614047600,16972254858152,16969949696979,16972405596631,16972405710940
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,185862,185862,32768,256,0,0,12,24,13888,0x0,0x7fc67fc23f80,4096,36328,4067060,16972410874139,16972405596631,16972411001739,16972411006625
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,185862,185862,4194304,256,0,0,12,24,14336,0x7fc7830d3380,0x7fc67fc23fc0,524288,10881740,1218670928,16972411041434,16972411001739,16972411364618,16972411367235
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/SQ_LEVEL_WAVES.csv
index cfe5efcefd..b76994fd7d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/SQ_LEVEL_WAVES.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,184458,184458,33554432,256,0,0,4,32,4160,0x0,0x7f9b90c04280,380574,380574,9096,3044600,524288,238703669,2955557,0,971055804,16954769013602,16954080008850,16954919879829,16954919993648
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,184458,184458,32768,256,0,0,12,24,13888,0x0,0x7f9b90c23f80,33740,33740,29864,269928,512,1706268,161842,0,6838596,16954925146557,16954919879829,16954925285577,16954925290352
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,184458,184458,4194304,256,0,0,12,24,14336,0x7f9b93ca1380,0x7f9b90c23fc0,164660,164660,13829,1317288,65536,71961423,1210359,0,289583872,16954925333911,16954925285577,16954925673736,16954925676301
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/pmc_perf.csv
index f660ba0705..d5d0355705 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDI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],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBufferAligned.kd,0,0,0,185224,185224,33554432,256,0,0,4,32,4160,0x0,0x7fb835204280,3099240,3009038,524288,39094512,244702847,392,224,0,387404,387404,39360209.0,38330016.0,6.0,4155939.0,31427796.0,31063395.0,38307368.0,37746495.0,3097529,3015439,387404,0,387404,0,12396928.0,9493333.0,0.0,0.0,0,0,616,0,4718592,4714964,112,3516,375706,0.0,0.0,0.0,524288.0,28537242.0,27806849.0,7770.0,524288.0,131072,524288,301,384962,2344,0,56.0,302.0,0.0,4194696.0,0,0,0,0,0,7340032,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,20085629.0,524288.0,0,383206,0,0,0,383206,0,0,0,383206,0,0,0,383206,0,0,0,383206,0,0,0,383206,0,0,0,383206,0,0,0,383206,0,0,0,383206,0,0,0,383206,0,0,0,383206,0,0,0,383206,0,0,0,383206,0,0,0,383206,0,0,0,383206,0,0,0,383206,0,0,0,383206,0,0,0,383206,0,0,0,383206,0,0,0,383206,0,0,0,383206,0,0,0,383206,0,0,0,383206,0,0,0,383206,0,0,0,383206,0,0,0,383206,0,0,0,383206,0,0,0,383206,0,0,0,383206,0,0,0,383206,0,0,0,383206,0,0,0,383206,0,0,0,0,0,0.0,21048071.0,32,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,112,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,90,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,5,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,32,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,524288.0,0.0,0,44285,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,333,129024,129024,0,0,129024,129024,0,560372,129024,129024,0,0,129024,129024,0,867,129024,129024,0,43924,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,167,129024,129024,0,27646,129024,129024,0,178,129024,129024,0,500,129024,129024,0,0,129024,129024,0,279846,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,45595,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,187,129024,129024,524288.0,0.0,43387,0,0,50345087,44785,0,0,50721516,44373,0,0,50277810,47881,0,0,52350539,45036,0,0,51320460,46177,0,0,51299348,44683,0,0,50804829,47673,0,0,52834670,44945,0,0,50837036,46565,0,0,51176779,45625,0,0,50524810,48226,0,0,52248620,46755,0,0,51799559,46891,0,0,51673783,46764,0,0,51353602,48658,0,0,53120637,43934,0,0,50381346,44221,0,0,50266268,43561,0,0,49774462,47188,0,0,52057323,44820,0,0,51235580,45554,0,0,51356799,44345,0,0,50791228,47456,0,0,52631790,45590,0,0,50807303,46365,0,0,51167497,45548,0,0,50602859,47703,0,0,52286979,46017,0,0,51576720,47144,0,0,51726925,47137,0,0,51620964,49406,0,0,53455253,0.0,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65568,32,131104,65701,65539,168,131240,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65568,32,131104,65536,65648,112,131184,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65572,36,131108,65758,65541,227,131299,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65592,56,131128,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65569,33,131105,65591,65537,56,131128,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131184,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131296,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131128,0,131072,1110746,0,524288,3670016,3663122,224,6670,1048576,33554432.0,33554432.0,0.0,33554432.0,30284530.0,28649085.0,0.0,524288.0,219812,539494,8427,897,0,384430,4195054.0,0.0,2097594.0,2097460.0,1048576,1048576,0,524288,0,524288,7340032,0,0.0,0.0,104.0,8388608.0,29676754.0,2097152.0,0.0,206894,0,1260,384797,0,750.0,4194304.0,0.0,2064387.0,25690112,9437184,0,0,0,0,0,0,13271.0,8242627.0,0.0,8388608.0,2097152.0,4194304.0,9871574,0,0,8617,4128768.0,4128768.0,0.0,1482243.0,0,0,0,0,0,0,5767168,1048576,315687122.0,0.0,1472227400.0,0.0,49.0,0.0,0,0,373530,0.0,0.0,1492795.0,0.0,3670016,524288,0,0,0,2621440,524288,175787320,4194304.0,0.0,0.0,0.0,0.0,1217086.0,0,0,0.0,313.0,0.0,610.0,42620540,24117248,0,0,9437184,11010048,0,3145728,0.0,0.0,0.0,0.0,0.0,0.0,0,1572864,0.0,0.0,0.0,189355.0,524288,524288,0,3670016,7340032,603979776,4718592,0,0.0,0.0,0.0,0.0,0.0,0.0,524288,0,2064384.0,0.0,2031624.0,0.0,0,0,524288,0,0,0,0,33554432,0.0,4194304.0,0.0,18994502.0,0.0,0.0,143.0,4128768.0,647601.0,1654623441.0,16956205081194,16974017042861,16974017282380,16956353676933
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,185224,185224,32768,256,0,0,12,24,13888,0x0,0x7fb835223f80,278040,168568,512,1438740,1778926,504,56,0,34754,34754,2422199.0,178331.0,190.0,0.0,40002.0,36926.0,172032.0,153240.0,278032,175166,34754,0,34754,0,1112128.0,387287.0,0.0,0.0,0,0,560,0,8192,6122,56,2014,23459,0.0,0.0,0.0,4096.0,31146.0,29705.0,0.0,4096.0,128,512,302,32966,2614,0,0.0,60.0,0.0,4600.0,0,0,0,0,0,1024,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,11837.0,4096.0,0,33936,0,0,0,33936,0,0,0,33936,0,0,0,33936,0,0,0,33936,0,0,0,33936,0,0,0,33936,0,0,0,33936,0,0,0,33936,0,0,0,33936,0,0,0,33936,0,0,0,33936,0,0,0,33936,0,0,0,33936,0,0,0,33936,0,0,0,33936,0,0,0,33936,0,0,0,33936,0,0,0,33936,0,0,0,33936,0,0,0,33936,0,0,0,33936,0,0,0,33936,0,0,0,33936,0,0,0,33936,0,0,0,33936,0,0,0,33936,0,0,0,33936,0,0,0,33936,0,0,0,33936,0,0,0,33936,0,0,0,33936,0,0,0,0,0,0.0,0.0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,316,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,258,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,257,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,4096.0,4096.0,0,79431,0,0,0,79987,0,0,0,78346,0,0,0,95027,0,0,0,87768,0,0,0,82113,0,0,0,678177,0,0,0,95357,0,0,0,98355,0,0,0,115455,0,0,0,91511,0,0,0,81543,0,0,0,92926,0,0,0,92807,0,0,0,89426,0,0,0,96781,0,0,0,86507,0,0,0,86601,0,0,0,83198,0,0,0,89555,0,0,0,80332,0,0,0,82339,0,0,0,85802,0,0,0,92623,0,0,0,89230,0,0,0,96105,0,0,0,82638,0,0,0,95573,0,0,0,84449,0,0,0,83738,0,0,0,80269,0,0,0,97763,0,0,0.0,0.0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4096.0,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,222,130,352,352,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,184,184,184,222,130,352,352,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,130,130,130,0,129,129,129,55,129,184,184,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,352,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,352,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,184,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,670,0,0,512,0,56,456,0,65536.0,65536.0,65536.0,0.0,0.0,0.0,0.0,0.0,6,518,11203,1018,0,30005,4659.0,0.0,499.0,4160.0,512,0,0,0,4096,4096,512,0,0.0,0.0,104.0,16384.0,0.0,16384.0,4096.0,0,0,1449,32060,0,4661.0,0.0,0.0,31.0,35328,26112,0,0,0,0,0,0,104.0,15240.0,0.0,16384.0,16384.0,0.0,0,0,0,29012,0.0,0.0,0.0,0.0,0,0,0,0,0,0,10752,3584,4053798.0,5488049.0,0.0,8192.0,0.0,0.0,0,0,496,0.0,0.0,0.0,0.0,512,4096,0,0,0,512,512,1758133,0.0,0.0,0.0,0.0,0.0,1322.0,0,0,0.0,8263.0,0.0,124.0,15834,32256,0,0,26112,1024,0,1024,0.0,0.0,0.0,0.0,0.0,0.0,0,1024,0.0,0.0,0.0,43899.0,4096,0,4096,512,512,1671168,8192,0,0.0,0.0,0.0,0.0,0.0,0.0,512,0,0.0,0.0,0.0,0.0,0,0,512,0,0,0,0,32768,8192.0,0.0,0.0,123714.0,0.0,4096.0,8204.0,0.0,3423724.0,0.0,16956359875261,16974022060764,16974022074684,16956360356887
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,185224,185224,4194304,256,0,0,12,24,14336,0x7fb8381d8380,0x7fb835223fc0,1312800,1205883,65536,15587535,81844924,392,56,0,164099,164099,15907554.0,14453631.0,24573.0,771254.0,13844478.0,13607819.0,14447340.0,12311015.0,1312792,1212263,164099,0,164099,0,5251168.0,4711978.0,0.0,0.0,0,0,448,0,917504,913921,0,3583,153603,0.0,0.0,0.0,524288.0,13718809.0,13702009.0,2166.0,524288.0,16384,65536,302,163968,2281,0,0.0,182.0,0.0,1048968.0,0,0,0,0,0,131072,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,11801305.0,524288.0,0,163928,0,0,0,163928,0,0,0,163928,0,0,0,163928,0,0,0,163928,0,0,0,163928,0,0,0,163928,0,0,0,163928,0,0,0,163928,0,0,0,163928,0,0,0,163928,0,0,0,163928,0,0,0,163928,0,0,0,163928,0,0,0,163928,0,0,0,163928,0,0,0,163928,0,0,0,163928,0,0,0,163928,0,0,0,163928,0,0,0,163928,0,0,0,163928,0,0,0,163928,0,0,0,163928,0,0,0,163928,0,0,0,163928,0,0,0,163928,0,0,0,163928,0,0,0,163928,0,0,0,163928,0,0,0,163928,0,0,0,163928,0,0,0,0,0,0.0,0.0,65536,0,13247,0,65538,0,16159,0,65536,0,17590,0,65536,0,8570,0,65536,0,36116,0,65537,0,15681,0,65537,0,36656,0,65536,0,26816,0,65536,0,27314,0,65536,0,13854,0,65536,0,17344,0,65536,0,34988,0,65537,0,16236,0,65536,0,9155,0,65592,0,18892,0,65536,0,15156,0,65536,0,5220,0,65536,0,12810,0,65595,0,11521,0,65536,0,28394,0,65536,0,23747,0,65536,0,16466,0,65537,0,20271,0,65539,0,13554,0,65540,0,27548,0,65538,0,7017,0,65536,0,8519,0,65601,0,17157,0,65536,0,13727,0,65536,0,21841,0,65537,0,32858,0,65536,0,31813,0,524288.0,524288.0,0,47446561,0,0,0,42770545,0,0,0,47029268,0,0,0,49304821,0,0,0,46793798,0,0,0,47485609,0,0,0,48787111,0,0,0,46606022,0,0,0,46773465,0,0,0,48867025,0,0,0,39474875,0,0,0,47949311,0,0,0,49716313,0,0,0,45251503,0,0,0,45314548,0,0,0,43957294,0,0,0,45406626,0,0,0,47289395,0,0,0,41671155,0,0,0,46405620,0,0,0,42226636,0,0,0,47261028,0,0,0,45741649,0,0,0,39316372,0,0,0,43522501,0,0,0,46631797,0,0,0,38542335,0,0,0,41505244,0,0,0,45149012,0,0,0,43517847,0,0,0,46337454,0,0,0,46698222,0,0,0.0,0.0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,524288.0,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32769,32769,32769,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32769,32769,32769,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32824,32824,32824,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32833,32833,32833,0,32769,32769,32769,166,32770,32936,32936,222,32770,32992,32992,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32836,32836,32836,0,32768,32768,32768,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32936,0,0,32992,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,859014,0,0,65536,63800,56,1680,0,8388608.0,8388608.0,8388608.0,0.0,0.0,0.0,0.0,0.0,122216,144775,9762,2602,0,162212,1049152.0,0.0,388.0,1048764.0,65536,0,0,0,524288,524288,131072,0,0.0,0.0,104.0,2097152.0,0.0,2097152.0,524288.0,43563,0,3357,162861,0,1049153.0,0.0,0.0,31.0,4063232,2883584,0,0,0,0,0,0,6609.0,2027361.0,0.0,2097152.0,2097152.0,0.0,1296950,0,0,14292,0.0,0.0,0.0,0.0,262144,0,0,0,0,0,1507328,458752,995813683.0,2227517818.0,0.0,2097152.0,49.0,0.0,0,0,147644,0.0,0.0,0.0,0.0,65536,524288,0,0,0,65536,65536,49341148,0.0,0.0,0.0,0.0,0.0,20166.0,0,0,0.0,2097346.0,0.0,374.0,20045967,3735552,0,0,2883584,196608,0,131072,0.0,0.0,0.0,0.0,0.0,0.0,0,131072,0.0,0.0,404482.0,1187648.0,524288,0,524288,65536,131072,184549376,917504,0,0.0,0.0,0.0,0.0,0.0,0.0,65536,0,0.0,0.0,983047.0,0.0,0,0,65536,0,0,0,0,4194304,2097152.0,0.0,0.0,12292692.0,0.0,524288.0,2097280.0,0.0,1464268816.0,0.0,16956361452585,16974022228923,16974022321243,16956362165664
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/prev_analysis/1.csv
index 5f636702fc..f6c9de4769 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,3357910.0,3357910.0,3357910.0,7.838752126855418
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,1725915.0,1725915.0,1725915.0,4.029000145037142
 "void benchmark_func<double, 256, 8u, 512u>(double, double*) [clone .kd]",1,1715835.0,1715835.0,1715835.0,4.005469251880773
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/prev_analysis/1001.csv
index f475f954a6..fb5988001a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,494.8622754491018,Instr per wave
 VMEM,7.958083832335329,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,0.0,Instr per wave
 SALU,24.520958083832337,Instr per wave
 SMEM,1.8023952095808384,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/prev_analysis/101.csv
index 2de23a99ba..f973a5b515 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx90a
 mi200
 56
 1638.4
-SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/prev_analysis/1202.csv
index 208b965360..a81c7397d1 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,18493.56813163529,1866.9345626831055,257731.92138671875,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/prev_analysis/1901.csv
index 5538e7f887..4cc8ead5b4 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,2.0,smem_
 VALU,495.0,valu_
 MFMA,0.0,mfma_
 VMEM,8.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,10.0,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,67894.0,wavefronts_
 Workgroups,16973.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,128.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,0.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,44.0,hbm_rd_
 HBM Wr,0.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,70.0,vl1_coales_
 VL1 Stall,2.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,25.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/prev_analysis/201.csv
index 9cb28f2395..c593d22119 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,58.30684236262384,Pct,100,58.30684236262384
 MFMA Util,0.0,Pct,100,0.0
 VALU Active Threads/Wave,64.0,Threads,64,100.0
 IPC - Issue,1.0,Instr/cycle,5,20.0
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99252306378494,Pct,100,99.99252306378494
 Instr Cache BW,1671.997276984569,Gb/s,6092.8,27.442182198407448
 Scalar L1D Cache Hit Rate,99.34855885872486,Pct,100,99.34855885872486
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/prev_analysis/602.csv
index c83ccb7dd5..97d5764015 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,12332779.844311377,0,380284366,Simd
 Insufficient SIMD VGPRs,0.0,0,0,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/prev_analysis/701.csv
index 12250d77c0..db0925a109 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/sysinfo.csv
index 8677b59958..5311bff706 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-no_roof_LDS,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:35:53 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+no_roof_LDS,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:35:53 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/timestamps.csv
index c24ac3ecbb..348da83de9 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_LDS/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,186167,186167,33554432,256,0,0,4,32,4160,0x0,0x7f4df6404280,16974017017829,16974017042861,16974017282380,16974017371119
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,186167,186167,32768,256,0,0,12,24,13888,0x0,0x7f4df6423f80,16974022044663,16974022060764,16974022074684,16974022101802
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,186167,186167,4194304,256,0,0,12,24,14336,0x7f4df94f8380,0x7f4df6423fc0,16974022218628,16974022228923,16974022321243,16974022323445
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi100/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi100/pmc_dispatch_info.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi100/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi100/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi100/pmc_perf.csv
index ddd9cf4d9b..ffb47e68be 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,GRBM_COUNT,GRBM_GUI_ACTIVE,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,GRBM_SPI_BUSY,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,GRBM_COUNT,GRBM_GUI_ACTIVE,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,GRBM_SPI_BUSY,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBuffer.kd,0,0,0,867091,867096,33554432,256,0,0,8,32,6464,0x0,0x7f1723204180,4009488,3796892,524288,501185,501185,4009480,3808756,481466,131072,524288,237812,762100,0,0,0,0,0,0,0,0,0,3145728,524288,0,12075245655947833,12075254841595086,12075254841918603,12075245900085460
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,867091,867096,32768,256,0,0,24,24,12480,0x0,0x7f1723235100,227376,78085,512,28421,28421,227368,89705,11822,128,512,116,628,0,0,0,0,0,0,0,0,0,2560,512,0,12075245914782663,12075254857383717,12075254857390437,12075245915123937
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,867091,867096,4194304,256,0,0,24,24,12928,0x7f1853411900,0x7f1723235140,1789856,1625054,65536,223731,223731,1789848,1636787,201193,16384,65536,146267,185422,36101,0,528910,530495,0,0,0,0,0,327680,65536,0,12075245915195861,12075254857456036,12075254857593475,12075245915562362
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi100/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi100/prev_analysis/1.csv
index 9aab09fa8f..20effc135b 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi100/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi100/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,6055640.0,6055640.0,6055640.0,9.171013186720057
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4527010.0,4527010.0,4527010.0,6.855967066472505
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 256u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,3051339.0,3051339.0,3051339.0,4.621125133950034
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi100/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi100/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi100/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi100/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi100/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi100/prev_analysis/1202.csv
index d92c0479fa..2d4898d1f7 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi100/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi100/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,,,,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi100/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi100/prev_analysis/1901.csv
index f1556d6a26..f626057062 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi100/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi100/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,24.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,67894.0,wavefronts_
 Workgroups,16973.0,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,,il1_fetch_
 IL1 Hit,,il1_hit_
 IL1_L2 Rd,,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi100/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi100/prev_analysis/2001.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi100/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi100/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi100/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi100/prev_analysis/201.csv
index 52e9f5bf0c..91625c4b2e 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi100/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi100/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,,Gb/sec,23070.72,
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,,Gb/sec,23070.72,
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,,Pct,100,
 Instr Cache BW,,Gb/s,4614.144,
 Scalar L1D Cache Hit Rate,,Pct,100,
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi100/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi100/prev_analysis/602.csv
index d7b890b5c1..aac53107bd 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi100/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi100/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,52685.389221556885,0,724293,Simd
 Insufficient SIMD VGPRs,637435.3353293414,0,37560409,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi100/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi100/prev_analysis/701.csv
index 251e393e89..b26c791122 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi100/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi100/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,23.976047904191617,8,36,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi100/timestamps.csv
index 876e2acf6f..1cfea23236 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,867387,867392,33554432,256,0,0,8,32,6464,0x0,0x7fe62c404180,12075254841546349,12075254841595086,12075254841918603,12075254842023395
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,867387,867392,32768,256,0,0,24,24,12480,0x0,0x7fe62c435100,12075254857277052,12075254857383717,12075254857390437,12075254857396494
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,867387,867392,4194304,256,0,0,24,24,12928,0x7fe737fe9900,0x7fe62c435140,12075254857442800,12075254857456036,12075254857593475,12075254857597277
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi200/pmc_perf.csv
index c1dc0abe45..9ed6ef5209 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,GRBM_COUNT,GRBM_GUI_ACTIVE,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,GRBM_SPI_BUSY,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,GRBM_COUNT,GRBM_GUI_ACTIVE,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,GRBM_SPI_BUSY,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBufferAligned.kd,0,0,0,158654,158654,33554432,256,0,0,4,32,4160,0x0,0x7fa6dc604280,3092728,3006178,524288,386590,386590,3091017,3012577,369581,131072,524288,206210,533836,200024,0,9758208,0,0,0,0,0,0,1572864,524288,0,16413065555999,16419337860341,16419338099862,16413209395409
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,158654,158654,32768,256,0,0,12,24,13888,0x0,0x7fa6dc623f80,265064,158730,512,33132,33132,265056,166792,24057,128,512,6,518,0,0,0,0,0,0,0,0,0,1024,512,0,16413214566424,16419342871250,16419342884850,16413214708661
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,158654,158654,4194304,256,0,0,12,24,14336,0x7fa6fb036380,0x7fa6dc623fc0,1321432,1217149,65536,165178,165178,1321424,1225218,153082,16384,65536,123905,146734,54346,0,1784508,0,0,0,0,0,0,131072,65536,0,16413214749460,16419342956210,16419343048851,16413215092723
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi200/prev_analysis/1.csv
index c07550b35e..b874cc1dab 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,3358580.0,3358580.0,3358580.0,7.840918201128663
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,1726730.0,1726730.0,1726730.0,4.031212204394386
 "void benchmark_func<double, 256, 8u, 512u>(double, double*) [clone .kd]",1,1717930.0,1717930.0,1717930.0,4.0106677837851015
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi200/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi200/prev_analysis/1202.csv
index d92c0479fa..2d4898d1f7 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,,,,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi200/prev_analysis/1901.csv
index 2fbb314bca..6afc7632e9 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,67894.0,wavefronts_
 Workgroups,16973.0,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,,il1_fetch_
 IL1 Hit,,il1_hit_
 IL1_L2 Rd,,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi200/prev_analysis/201.csv
index b4d9ea9d64..2086c73dba 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,,Gb/sec,22630.4,
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,,Gb/sec,22630.4,
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,,Pct,100,
 Instr Cache BW,,Gb/s,6092.8,
 Scalar L1D Cache Hit Rate,,Pct,100,
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi200/prev_analysis/602.csv
index fb1823e502..46b3c3e505 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,12207266.958083833,0,374174125,Simd
 Insufficient SIMD VGPRs,0.0,0,0,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi200/prev_analysis/701.csv
index 6c1da816d8..e5a0856200 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi200/timestamps.csv
index 0c18523c67..e16e36b499 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SPI/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,158945,158945,33554432,256,0,0,4,32,4160,0x0,0x7f9532004280,16419337834810,16419337860341,16419338099862,16419338190962
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,158945,158945,32768,256,0,0,12,24,13888,0x0,0x7f9532023f80,16419342856499,16419342871250,16419342884850,16419342902458
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,158945,158945,4194304,256,0,0,12,24,14336,0x7f9535013380,0x7f9532023fc0,16419342906708,16419342956210,16419343048851,16419343050865
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi100/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi100/SQ_IFETCH_LEVEL.csv
index ba1279627d..c5ba69927f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi100/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi100/SQ_IFETCH_LEVEL.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,853357,853362,33554432,256,0,0,8,32,6464,0x0,0x7ffa19204180,502929,502929,524288,6291456,798316,102258248,12074917650594883,12074917897672290,12074917897995488,12074917898106350
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,853357,853362,32768,256,0,0,24,24,12480,0x0,0x7ffa19235100,27371,27371,512,8192,9165,1184228,12074917912453813,12074917912761361,12074917912767921,12074917912777615
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,853357,853362,4194304,256,0,0,24,24,12928,0x7ffb24dd6900,0x7ffa19235140,219859,219859,65536,917504,139927,17960496,12074917912834541,12074917913076879,12074917913211438,12074917913215769
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi100/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi100/SQ_INST_LEVEL_LDS.csv
index c7f8b13de5..c88b5f30b7 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi100/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi100/SQ_INST_LEVEL_LDS.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,854631,854636,33554432,256,0,0,8,32,6464,0x0,0x7fcaf4204180,0,0,0,12074931194990761,12074931439076452,12074931439398527,12074931439483969
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,854631,854636,32768,256,0,0,24,24,12480,0x0,0x7fcaf4235100,0,0,0,12074931454090613,12074931454386643,12074931454392883,12074931454398035
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,854631,854636,4194304,256,0,0,24,24,12928,0x7fcbffe0b900,0x7fcaf4235140,0,0,0,12074931454502008,12074931454675279,12074931454805037,12074931454808828
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi100/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi100/SQ_INST_LEVEL_SMEM.csv
index 8ee0304dde..37eb42ce4c 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi100/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi100/SQ_INST_LEVEL_SMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,854253,854258,33554432,256,0,0,8,32,6464,0x0,0x7f437fa04180,4194304,3113484,398058824,12074928673089866,12074928916148327,12074928916469765,12074928916589637
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,854253,854258,32768,256,0,0,24,24,12480,0x0,0x7f437fa35100,512,22802,2912040,12074928931160515,12074928931449325,12074928931455565,12074928931460723
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,854253,854258,4194304,256,0,0,24,24,12928,0x7f44afc5c900,0x7f437fa35140,65536,174688,22360120,12074928931518671,12074928931735243,12074928931867083,12074928931871116
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi100/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi100/SQ_INST_LEVEL_VMEM.csv
index 8d27e78e86..efdef28a88 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi100/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi100/SQ_INST_LEVEL_VMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,854441,854446,33554432,256,0,0,8,32,6464,0x0,0x7fdf0a004180,1048576,11154079,1427869420,12074929933434417,12074930179735700,12074930180056496,12074930180119639
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,854441,854446,32768,256,0,0,24,24,12480,0x0,0x7fdf0a035100,4096,109002,13940580,12074930194737013,12074930195053493,12074930195059733,12074930195068589
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,854441,854446,4194304,256,0,0,24,24,12928,0x7fe015c7f900,0x7fdf0a035140,524288,12009341,1537163048,12074930195132147,12074930195344050,12074930195476688,12074930195481066
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi100/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi100/SQ_LEVEL_WAVES.csv
index c94a97919f..c11f36900b 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi100/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi100/SQ_LEVEL_WAVES.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,854819,854824,33554432,256,0,0,8,32,6464,0x0,0x7f50f0604180,505702,505702,17864,4045624,524288,371738932,3834066,0,1501770576,12074932448944807,12074932692399413,12074932692724531,12074932692834683
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,854819,854824,32768,256,0,0,24,24,12480,0x0,0x7f50f0635100,27648,27648,20304,221192,512,1140601,76481,0,4576612,12074932707374504,12074932707696217,12074932707702937,12074932707711209
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,854819,854824,4194304,256,0,0,24,24,12928,0x7f51fc1c5900,0x7f50f0635140,212645,212645,19764,1701168,65536,143831518,1525047,0,577143784,12074932707777543,12074932708023255,12074932708152855,12074932708157048
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi100/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi100/pmc_dispatch_info.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi100/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi100/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi100/pmc_perf.csv
index f7c6809647..a2a062aea9 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBuffer.kd,0,0,0,853819,853824,33554432,256,0,0,8,32,6464,0x0,0x7f1b60404180,1048576,0,1048576,9437184,0,4194304,1048576,0,506136,506136,0,0,3145728,524288,32505856,372897729,219252809,121139064,32505856,3988240,3782833,56584058,11534336,0,0,14155776,13631488,0,3670016,1048576,1048576,0,4194304,9437184,905969664,6291456,0,0,0,524288,524288,0,0,0,0,33554432,0,0,0,0,0,8388608,336,144,0,0,0,480,0,6291456,6289253,96,2781,1912049,0,0,4194304,4189858,144,4302,2097152,524288,1572864,12074919163373650,12074933586686810,12074933587013047,12074919407253238
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,853819,853824,32768,256,0,0,24,24,12480,0x0,0x7f1b60435100,0,4096,4096,512,0,512,4096,0,28186,28186,0,0,512,512,35328,1129873,1079015,14506,36352,223152,72770,1012626,26624,0,0,30208,1024,0,1024,4096,0,4096,512,512,1933312,8192,0,0,0,512,512,0,0,0,0,32768,0,0,0,0,0,1024,432,48,0,0,0,480,0,8192,6651,48,1493,1094,0,0,512,0,48,464,0,512,0,12074919421505183,12074933601700471,12074933601707191,12074919421845866
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,853819,853824,4194304,256,0,0,24,24,12928,0x7f1c6c05c900,0x7f1b60435140,0,524288,524288,65536,0,65536,524288,0,219929,219929,0,0,65536,65536,4128768,147222780,54345681,88617259,4259840,1833112,1640220,24320186,3014656,0,0,3473408,131072,0,131072,524288,0,524288,65536,65536,222298112,917504,0,0,0,65536,65536,0,0,0,0,4194304,0,0,0,0,0,131072,384,48,0,0,0,432,0,917504,914733,66,5340,221761,0,0,65536,64048,48,1440,0,65536,0,12074919421917469,12074933601773270,12074933601904149,12074919422312564
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi100/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi100/prev_analysis/1.csv
index 2fef24a481..97ab00ef95 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi100/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi100/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,6053232.0,6053232.0,6053232.0,9.15552966823178
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4525564.0,4525564.0,4525564.0,6.84492771258093
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 256u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,3050536.0,3050536.0,3050536.0,4.613943898401565
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi100/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi100/prev_analysis/1001.csv
index ca08330db0..0e3bf5267e 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi100/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi100/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,46.862275449101794,Instr per wave
 SMEM,1.8083832335329342,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi100/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi100/prev_analysis/1202.csv
index 9f68986a2e..8496a8140d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi100/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi100/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,33635.78321961728,2844.9838943481445,547933.1223144531,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi100/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi100/prev_analysis/1901.csv
index 457de90ae6..d403ae8942 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi100/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi100/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,2.0,smem_
 VALU,735.0,valu_
 MFMA,,mfma_
 VMEM,8.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,22.0,br_
 VGPR,24.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,163.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,33.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi100/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi100/prev_analysis/2001.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi100/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi100/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi100/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi100/prev_analysis/201.csv
index bdcea105ea..8845d4ce29 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi100/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi100/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,59.79971446776359,Pct,100,59.79971446776359
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,63.967970405083776,Threads,64,99.9499537579434
 IPC - Issue,0.8437279322064409,Instr/cycle,5,16.87455864412882
-LDS BW,0.0,Gb/sec,23070.72,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,23070.72,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99347917010805,Pct,100,99.99347917010805
 Instr Cache BW,1407.8247714184517,Gb/s,4614.144,30.5110714233984
 Scalar L1D Cache Hit Rate,99.35620448524938,Pct,100,99.35620448524938
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi100/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi100/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi100/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi100/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi100/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi100/prev_analysis/701.csv
index e64851d52b..cdde4fb05f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi100/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi100/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,23.976047904191617,8,36,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi100/timestamps.csv
index cc32be846e..5e9c9ab87b 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,854870,854875,33554432,256,0,0,8,32,6464,0x0,0x7f5cd2204180,12074933586640071,12074933586686810,12074933587013047,12074933587117989
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,854870,854875,32768,256,0,0,24,24,12480,0x0,0x7f5cd2235100,12074933601595213,12074933601700471,12074933601707191,12074933601713273
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,854870,854875,4194304,256,0,0,24,24,12928,0x7f5dddeb8900,0x7f5cd2235140,12074933601758607,12074933601773270,12074933601904149,12074933601907994
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi200/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi200/SQ_IFETCH_LEVEL.csv
index 2e14823f67..15fd996080 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi200/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi200/SQ_IFETCH_LEVEL.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,139452,139452,33554432,256,0,0,4,32,4160,0x0,0x7fd343a04280,382453,382453,524288,4718592,681988,76312884,15935259102191,15934554108230,15935406777810,15935406890870
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,139452,139452,32768,256,0,0,12,24,13888,0x0,0x7fd343a23f80,32830,32830,512,8192,6052,682248,15935412056765,15935406777810,15935412185995,15935412190492
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,139452,139452,4194304,256,0,0,12,24,14336,0x7fd346a49380,0x7fd343a23fc0,163478,163478,65536,917504,145056,16237136,15935412230171,15935412185995,15935412560877,15935412563503
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi200/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi200/SQ_INST_LEVEL_LDS.csv
index 57282aa3a3..d356d2b030 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi200/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi200/SQ_INST_LEVEL_LDS.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,141060,141060,33554432,256,0,0,4,32,4160,0x0,0x7f30bae04280,0,0,0,15947651176630,15946941320324,15947796315367,15947796428017
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,141060,141060,32768,256,0,0,12,24,13888,0x0,0x7f30bae23f80,0,0,0,15947801580212,15947796315367,15947801708832,15947801713329
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,141060,141060,4194304,256,0,0,12,24,14336,0x7f30bde12380,0x7f30bae23fc0,0,0,0,15947801747388,15947801708832,15947802073474,15947802087111
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi200/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi200/SQ_INST_LEVEL_SMEM.csv
index 66bd19eb25..756c3cd2b9 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi200/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi200/SQ_INST_LEVEL_SMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,139230,139230,33554432,256,0,0,4,32,4160,0x0,0x7fb387c04280,3670016,2903386,325116496,15934325738709,15906380722381,15934474519983,15934474610513
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,139230,139230,32768,256,0,0,12,24,13888,0x0,0x7fb387c23f80,512,104398,11697264,15934479744409,15934474519983,15934479871689,15934479876296
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,139230,139230,4194304,256,0,0,12,24,14336,0x7fb39e240380,0x7fb387c23fc0,65536,718900,80475816,15934479911685,15934479871689,15934480234890,15934480237578
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi200/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi200/SQ_INST_LEVEL_VMEM.csv
index c81d72f12b..c6d68e119c 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi200/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi200/SQ_INST_LEVEL_VMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,140838,140838,33554432,256,0,0,4,32,4160,0x0,0x7f5a3e004280,524288,5390543,603702352,15946712130917,15945761114570,15946860850104,15946860941414
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,140838,140838,32768,256,0,0,12,24,13888,0x0,0x7f5a3e023f80,4096,42171,4717444,15946866109959,15946860850104,15946866239250,15946866243926
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,140838,140838,4194304,256,0,0,12,24,14336,0x7f5a410a7380,0x7f5a3e023fc0,524288,10422720,1167281496,15946866278065,15946866239250,15946866610612,15946866613217
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi200/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi200/SQ_LEVEL_WAVES.csv
index 4938503148..410d28b874 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi200/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi200/SQ_LEVEL_WAVES.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,139674,139674,33554432,256,0,0,4,32,4160,0x0,0x7fd5b1204280,384850,384850,8820,3078808,524288,241640859,2989147,0,982799868,15936192338888,15935488832829,15936344993596,15936345106986
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,139674,139674,32768,256,0,0,12,24,13888,0x0,0x7fd5b1223f80,32944,32944,29120,263560,512,1664540,155549,0,6671668,15936350272441,15936344993596,15936350410580,15936350415498
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,139674,139674,4194304,256,0,0,12,24,14336,0x7fd5b419b380,0x7fd5b1223fc0,165488,165488,13630,1323912,65536,72039579,1216170,0,289894760,15936350459957,15936350410580,15936350808502,15936350810989
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi200/pmc_perf.csv
index d16fc70b8a..5c35853dfc 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS,SQ_INSTS_VALU,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS,SQ_INSTS_VALU,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBufferAligned.kd,0,0,0,140304,140304,33554432,256,0,0,4,32,4160,0x0,0x7fa31e804280,0,524288,0,524288,7340032,0,25690112,9437184,387297,387297,0,0,0,0,0,0,0,0,0,0,0,616,0,4718592,4714976,112,3702,1032987,0,524288,3670016,3663316,224,6476,1048576,1048576,1048576,0,0,0,0,5767168,1048576,3670016,524288,0,0,0,2621440,524288,237604043,173545637,39941158,24117248,3074528,2986378,38767640,0,0,9437184,11010048,0,3145728,524288,524288,0,3670016,7340032,603979776,4718592,0,0,0,524288,524288,0,0,0,0,33554432,0,0,0,0,0,7340032,0,0,0,0,0,0,0,0,0,0,0,0,0,392,224,15937487434886,15948461788706,15948462027747,15937635676675
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,140304,140304,32768,256,0,0,12,24,13888,0x0,0x7fa31e823f80,0,0,4096,4096,512,0,35328,26112,33604,33604,0,0,0,0,0,0,0,0,0,0,0,560,0,8192,6117,56,1945,654,0,0,512,0,56,456,0,512,0,0,0,0,0,10752,3584,512,4096,0,0,0,512,512,1711759,1665120,14383,32256,267784,158428,1382345,0,0,26112,1024,0,1024,4096,0,4096,512,512,1671168,8192,0,0,0,512,512,0,0,0,0,32768,0,0,0,0,0,1024,0,0,0,0,0,0,0,0,0,0,0,0,0,504,56,15937640838860,15948466868890,15948466882330,15937640983137
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,140304,140304,4194304,256,0,0,12,24,14336,0x7fa32177c380,0x7fa31e823fc0,0,0,524288,524288,131072,0,4063232,2883584,164986,164986,0,0,0,0,0,0,262144,0,0,0,0,448,0,917504,913647,0,3595,921140,0,0,65536,63800,56,1680,0,65536,0,0,0,0,0,1507328,458752,65536,524288,0,0,0,65536,65536,84801032,48438574,32626906,3735552,1321240,1206472,15607412,0,0,2883584,196608,0,131072,524288,0,524288,65536,131072,184549376,917504,0,0,0,65536,65536,0,0,0,0,4194304,0,0,0,0,0,131072,0,0,0,0,0,0,0,0,0,0,0,0,0,392,56,15937641031606,15948466952090,15948467044891,15937641379878
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi200/prev_analysis/1.csv
index 2faab9e7e3..427dd52c30 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,3356336.0,3356336.0,3356336.0,7.83811714205833
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,1725608.0,1725608.0,1725608.0,4.029846131398344
 "void benchmark_func<double, 256, 8u, 512u>(double, double*) [clone .kd]",1,1716168.0,1716168.0,1716168.0,4.007800714663836
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi200/prev_analysis/1001.csv
index f475f954a6..fb5988001a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,494.8622754491018,Instr per wave
 VMEM,7.958083832335329,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,0.0,Instr per wave
 SALU,24.520958083832337,Instr per wave
 SMEM,1.8023952095808384,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi200/prev_analysis/1202.csv
index 88e2772965..01f59ca08b 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,18351.745494865372,1812.7749862670898,258114.5219116211,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi200/prev_analysis/1901.csv
index 847521b667..e4f723629b 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,2.0,smem_
 VALU,495.0,valu_
 MFMA,0.0,mfma_
 VMEM,8.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,10.0,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,128.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,26.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi200/prev_analysis/201.csv
index 51940ac144..dcdec0c050 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,58.296276331287274,Pct,100,58.296276331287274
 MFMA Util,0.0,Pct,100,0.0
 VALU Active Threads/Wave,64.0,Threads,64,100.0
 IPC - Issue,1.0,Instr/cycle,5,20.0
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.9925069159217,Pct,100,99.9925069159217
 Instr Cache BW,1672.5993938761956,Gb/s,6092.8,27.452064631633984
 Scalar L1D Cache Hit Rate,99.34855886066374,Pct,100,99.34855886066374
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi200/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi200/prev_analysis/701.csv
index 138a2b5ecf..519511494f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi200/timestamps.csv
index 4e8353d065..9876c7010f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SQ/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,141143,141143,33554432,256,0,0,4,32,4160,0x0,0x7f4378404280,15948461762825,15948461788706,15948462027747,15948462150707
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,141143,141143,32768,256,0,0,12,24,13888,0x0,0x7f4378423f80,15948466853362,15948466868890,15948466882330,15948466899001
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,141143,141143,4194304,256,0,0,12,24,14336,0x7f437b4e8380,0x7f4378423fc0,15948466903361,15948466952090,15948467044891,15948467046497
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi100/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi100/pmc_dispatch_info.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi100/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi100/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi100/pmc_perf.csv
index 2e7b417362..05b879d72b 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBuffer.kd,0,0,0,856407,856412,33554432,256,0,0,8,32,6464,0x0,0x7fa1ea204180,4041424,3834729,57369470,524288,363773308,336,144,0,505177,505177,0,0,480,0,6291456,6289306,96,2549,2002436,0,0,4194304,4189867,144,4293,2097152,524288,1572864,12074982604635657,12074986773041058,12074986773364415,12074982846593824
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,856407,856412,32768,256,0,0,24,24,12480,0x0,0x7fa1ea235100,226080,76798,1088889,512,1161151,432,48,0,28259,28259,0,0,480,0,8192,6567,48,1577,1118,0,0,512,0,48,464,0,512,0,12074982860884361,12074986788051185,12074986788058225,12074982861244270
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,856407,856412,4194304,256,0,0,24,24,12928,0x7fa2f5f14900,0x7fa1ea235140,1792800,1624185,24108712,65536,128855123,384,48,0,224099,224099,0,0,432,0,917504,914532,48,7542,235921,0,0,65536,64048,48,1440,0,65536,0,12074982861317877,12074986788122704,12074986788249903,12074982861699696
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi100/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi100/prev_analysis/1.csv
index b97011488d..8691f50ab2 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi100/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi100/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,6054681.0,6054681.0,6054681.0,9.183842532562457
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4525891.0,4525891.0,4525891.0,6.864948006929122
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 256u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,3051820.0,3051820.0,3051820.0,4.629052185858306
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi100/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi100/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi100/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi100/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi100/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi100/prev_analysis/1202.csv
index 7f1b721995..c0a1a286d3 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi100/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi100/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,33557.12503271046,2775.370086669922,547846.4844970703,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi100/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi100/prev_analysis/1901.csv
index 5e01af18f0..69bf75643b 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi100/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi100/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,24.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,163.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi100/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi100/prev_analysis/2001.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi100/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi100/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi100/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi100/prev_analysis/201.csv
index 0cd0801e1c..4da35a2a4d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi100/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi100/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,,Gb/sec,23070.72,
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,,Gb/sec,23070.72,
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.9934279723574,Pct,100,99.9934279723574
 Instr Cache BW,1413.3436343873632,Gb/s,4614.144,30.630678938224797
 Scalar L1D Cache Hit Rate,99.35620448529356,Pct,100,99.35620448529356
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi100/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi100/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi100/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi100/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi100/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi100/prev_analysis/701.csv
index 8fb0971b0c..b6e142aea6 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi100/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi100/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,23.976047904191617,8,36,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi100/timestamps.csv
index 3ffd0533dd..8a056e56c7 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,856550,856555,33554432,256,0,0,8,32,6464,0x0,0x7fa7c2a04180,12074986772983985,12074986773041058,12074986773364415,12074986773464237
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,856550,856555,32768,256,0,0,24,24,12480,0x0,0x7fa7c2a35100,12074986787949045,12074986788051185,12074986788058225,12074986788064139
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,856550,856555,4194304,256,0,0,24,24,12928,0x7fa8ce69a900,0x7fa7c2a35140,12074986788108862,12074986788122704,12074986788249903,12074986788253321
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi200/pmc_perf.csv
index c38d592edf..15660e6a9e 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBufferAligned.kd,0,0,0,143633,143633,33554432,256,0,0,4,32,4160,0x0,0x7f52c3c04280,3060888,2970020,38588351,524288,239990325,392,224,0,382610,382610,0,0,616,0,4718592,4714698,112,3782,898846,0,524288,3670016,3663163,224,6629,1048576,1048576,1048576,16022625257429,16025461787106,16025462025348,16022774125203
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,143633,143633,32768,256,0,0,12,24,13888,0x0,0x7f52c3c23f80,194472,98162,1048056,512,1290098,504,56,0,24308,24308,0,0,560,0,8192,6207,56,1929,676,0,0,512,0,56,456,0,512,0,16022779363606,16025466939141,16025466947461,16022779509623
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,143633,143633,4194304,256,0,0,12,24,14336,0x7f52d2570380,0x7f52c3c23fc0,1307784,1207045,15600643,65536,96894331,392,56,0,163472,163472,0,0,448,0,917504,913427,0,4077,525176,0,0,65536,63800,56,1680,0,65536,0,16022779562971,16025467041542,16025467133862,16022779919993
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi200/prev_analysis/1.csv
index aabdc045a6..1baf4528a1 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,3354423.0,3354423.0,3354423.0,7.8758339988246915
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,1722092.0,1722092.0,1722092.0,4.043291714462967
 "void benchmark_func<double, 256, 8u, 512u>(double, double*) [clone .kd]",1,1711852.0,1711852.0,1711852.0,4.019249266582075
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi200/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi200/prev_analysis/1202.csv
index 1ad8a5f9e5..3accf653e6 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,18896.06455349494,1830.9808731079102,258389.72326660156,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi200/prev_analysis/1901.csv
index e7e320f9b9..bf2402a001 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,128.0,il1_fetch_
 IL1 Hit,99.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi200/prev_analysis/201.csv
index 92f7c286fd..7b1545b054 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,,Gb/sec,22630.4,
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,,Gb/sec,22630.4,
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99251018172134,Pct,100,99.99251018172134
 Instr Cache BW,1688.3229153756615,Gb/s,6092.8,27.710131883135197
 Scalar L1D Cache Hit Rate,99.34855885913464,Pct,100,99.34855885913464
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi200/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi200/prev_analysis/701.csv
index d28098ed25..9d9e3a3dab 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi200/timestamps.csv
index e5bccbaf4a..ccfebc523b 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_SQC/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,143794,143794,33554432,256,0,0,4,32,4160,0x0,0x7f24c3c04280,16025461758366,16025461787106,16025462025348,16025462096648
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,143794,143794,32768,256,0,0,12,24,13888,0x0,0x7f24c3c23f80,16025466923291,16025466939141,16025466947461,16025466967660
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,143794,143794,4194304,256,0,0,12,24,14336,0x7f24caee9380,0x7f24c3c23fc0,16025466972220,16025467041542,16025467133862,16025467136077
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi100/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi100/pmc_dispatch_info.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi100/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi100/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi100/pmc_perf.csv
index da0a1bdbdc..2fefcfed43 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,GRBM_COUNT,GRBM_GUI_ACTIVE,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,GRBM_COUNT,GRBM_GUI_ACTIVE,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBuffer.kd,0,0,0,859003,859008,33554432,256,0,0,8,32,6464,0x0,0x7fe216404180,4050960,3839309,57277865,524288,367224834,506369,506369,54608419,54503566,0,0,17483596,1048576,0,37640446,1048576,0,1048576,0,1048576,52690157,52476635,54330552,53979516,54506700,4194304,4194304,4194304,0,0,0,302809,0,0,0,0,0,1048576,12075036785139935,12075053930670524,12075053930994841,12075037032390637
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,859003,859008,32768,256,0,0,24,24,12480,0x0,0x7fe216435100,222080,78011,1064244,512,1134453,27759,27759,187422,169938,0,0,55306,4096,0,0,4096,4096,0,0,4096,112930,110169,0,0,0,16384,16384,0,0,0,0,3101,0,0,0,0,0,4096,12075037046900972,12075053946463595,12075053946470315,12075037047355808
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,859003,859008,4194304,256,0,0,24,24,12928,0x7fe321fc1900,0x7fe216435140,1740672,1586248,23494145,65536,141654714,217583,217583,22565080,22489456,0,0,20081327,524288,0,0,524288,524288,0,0,524288,21462978,21450493,0,0,0,2097152,2097152,0,0,0,0,9506,0,0,0,0,0,524288,12075037047525954,12075053946537675,12075053946667114,12075037048021645
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi100/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi100/prev_analysis/1.csv
index 17a34c459a..00e457d809 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi100/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi100/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,6053717.0,6053717.0,6053717.0,9.176440674554186
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4524928.0,4524928.0,4524928.0,6.859047647689696
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 256u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,3049898.0,3049898.0,3049898.0,4.623144435136539
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi100/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi100/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi100/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi100/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi100/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi100/prev_analysis/1202.csv
index 095ffd4c2c..134ee26d80 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi100/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi100/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,33803.7306234394,2801.703140258789,547934.5563354492,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi100/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi100/prev_analysis/1901.csv
index ec4d242e32..96c27da0f1 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi100/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi100/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,24.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,,il1_fetch_
 IL1 Hit,,il1_hit_
 IL1_L2 Rd,,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi100/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi100/prev_analysis/2001.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi100/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi100/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi100/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi100/prev_analysis/201.csv
index 07a3c668c7..179480bed5 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi100/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi100/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,,Gb/sec,23070.72,
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,,Gb/sec,23070.72,
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,,Pct,100,
 Instr Cache BW,,Gb/s,4614.144,
 Scalar L1D Cache Hit Rate,,Pct,100,
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi100/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi100/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi100/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi100/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi100/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi100/prev_analysis/701.csv
index 8fb0971b0c..b6e142aea6 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi100/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi100/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,23.976047904191617,8,36,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi100/timestamps.csv
index 172e91f1c5..106a9d2ee3 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,859514,859519,33554432,256,0,0,8,32,6464,0x0,0x7f624e604180,12075053930622059,12075053930670524,12075053930994841,12075053931103644
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,859514,859519,32768,256,0,0,24,24,12480,0x0,0x7f624e635100,12075053946363703,12075053946463595,12075053946470315,12075053946476022
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,859514,859519,4194304,256,0,0,24,24,12928,0x7f635a251900,0x7f624e635140,12075053946523830,12075053946537675,12075053946667114,12075053946670623
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi200/pmc_perf.csv
index 8e793befa3..bcc81f0921 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,GRBM_COUNT,GRBM_GUI_ACTIVE,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,GRBM_COUNT,GRBM_GUI_ACTIVE,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBufferAligned.kd,0,0,0,147071,147071,33554432,256,0,0,4,32,4160,0x0,0x7f2230404280,3046232,2959616,38449381,524288,238753320,380778,380778,30852999.0,30478278.0,28313183.0,27565185.0,0.0,0.0,19857447.0,524288.0,0.0,20515113.0,524288.0,0.0,524288.0,0.0,0.0,29700912.0,28009036.0,29452305.0,2097152.0,2097152.0,4194304.0,47.0,0.0,0.0,1254675.0,0.0,0.0,0.0,0.0,0.0,0.0,16101851410638,16113797745640,16113797987402,16101999674671
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,147071,147071,32768,256,0,0,12,24,13888,0x0,0x7f2230423f80,266208,166403,1409253,512,1733528,33275,33275,38325.0,35129.0,32231.0,30913.0,0.0,0.0,15119.0,4096.0,0.0,0.0,4096.0,4096.0,0.0,0.0,4096.0,0.0,0.0,0.0,16384.0,16384.0,0.0,0.0,0.0,0.0,1304.0,0.0,0.0,0.0,0.0,0.0,4096.0,16102005090371,16113802798629,16113802811909,16102005278617
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,147071,147071,4194304,256,0,0,12,24,14336,0x7f22334cd380,0x7f2230423fc0,1374336,1252892,16191606,65536,82797523,171791,171791,12587106.0,12351663.0,11701257.0,11681359.0,0.0,0.0,11376649.0,524288.0,0.0,0.0,524288.0,524288.0,0.0,0.0,524288.0,0.0,0.0,0.0,2097152.0,2097152.0,0.0,262.0,0.0,0.0,45422.0,0.0,0.0,0.0,0.0,0.0,524288.0,16102005568720,16113802883750,16113802976070,16102005848414
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi200/prev_analysis/1.csv
index fc1833e501..dbba4c6218 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,3357620.0,3357620.0,3357620.0,7.839350677007344
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,1725290.0,1725290.0,1725290.0,4.02819655873327
 "void benchmark_func<double, 256, 8u, 512u>(double, double*) [clone .kd]",1,1714730.0,1714730.0,1714730.0,4.003541135204342
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi200/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi200/prev_analysis/1202.csv
index f1dfe0bdb9..6545f1c1ed 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,18337.137277203405,1821.5432739257812,258179.00286865234,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi200/prev_analysis/1901.csv
index 26b1a63642..350477527a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,,il1_fetch_
 IL1 Hit,,il1_hit_
 IL1_L2 Rd,,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi200/prev_analysis/201.csv
index a68da7a926..055e24ffb6 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,,Gb/sec,22630.4,
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,,Gb/sec,22630.4,
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,,Pct,100,
 Instr Cache BW,,Gb/s,6092.8,
 Scalar L1D Cache Hit Rate,,Pct,100,
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi200/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi200/prev_analysis/701.csv
index d28098ed25..9d9e3a3dab 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi200/timestamps.csv
index 8ac7a744d1..a6691c4005 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TA/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,147544,147544,33554432,256,0,0,4,32,4160,0x0,0x7fcc98204280,16113797720310,16113797745640,16113797987402,16113798106852
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,147544,147544,32768,256,0,0,12,24,13888,0x0,0x7fcc98223f80,16113802783178,16113802798629,16113802811909,16113802830147
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,147544,147544,4194304,256,0,0,12,24,14336,0x7fcc9b2f0380,0x7fcc98223fc0,16113802834797,16113802883750,16113802976070,16113802978134
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi100/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi100/pmc_dispatch_info.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi100/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi100/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi100/pmc_perf.csv
index f75d74191e..de9b2ceb2c 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,GRBM_COUNT,GRBM_GUI_ACTIVE,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,CPC_ME1_DC0_SPI_BUSY,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,GRBM_COUNT,GRBM_GUI_ACTIVE,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,CPC_ME1_DC0_SPI_BUSY,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBuffer.kd,0,0,0,872934,872939,33554432,256,0,0,8,32,6464,0x0,0x7f970cc04180,4049040,3837075,524288,57413220,373101951,506129,506129,54833614,54738710,506129,0,0,0,17361985,1048576,0,37523899,1048576,0,1048576,0,1048576,52695309,52477686,730,504332,54162781,53856170,11220,2050,54339683,4194304,2794,501241,4194304,4194304,0,18476,0,0,474253,0,371434,0,0,0,0,0,1048576,12075385622091322,12075402664851029,12075402665174706,12075385867587035
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,872934,872939,32768,256,0,0,24,24,12480,0x0,0x7f970cc35100,225376,75482,512,1053630,1123188,28171,28171,93860,75128,28171,0,0,0,59218,4096,0,0,4096,4096,0,0,4096,141574,139070,607,27671,0,0,11255,2047,0,16384,2790,25057,16384,0,0,20777,0,0,697,0,3240,0,0,0,0,0,4096,12075385882196000,12075402679915257,12075402679922137,12075385882645275
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,872934,872939,4194304,256,0,0,24,24,12928,0x7f981888b900,0x7f970cc35140,1727248,1553463,65536,22987143,155996017,215905,215905,22346704,22331739,215905,0,0,0,19931789,524288,0,0,524288,524288,0,0,524288,22264316,22261737,763,213950,0,0,11233,2080,0,2097152,2836,216237,2097152,0,0,21448,0,0,187504,0,6450,0,0,0,0,0,524288,12075385882813137,12075402679981496,12075402680111895,12075385883325870
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi100/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi100/prev_analysis/1.csv
index 2022da6815..eb580db600 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi100/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi100/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,6059155.0,6059155.0,6059155.0,9.192847380000831
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4527646.0,4527646.0,4527646.0,6.869267854786888
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 256u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,3054858.0,3054858.0,3054858.0,4.634778836582755
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi100/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi100/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi100/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi100/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi100/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi100/prev_analysis/1202.csv
index dd14d88e4d..6192741952 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi100/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi100/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,33784.61210070399,2846.5419845581055,547947.7280883789,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi100/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi100/prev_analysis/1901.csv
index a6b89a1ea7..549db58b59 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi100/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi100/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,24.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,,il1_fetch_
 IL1 Hit,,il1_hit_
 IL1_L2 Rd,,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi100/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi100/prev_analysis/2001.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi100/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi100/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi100/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi100/prev_analysis/201.csv
index 1fea9afbb7..00efc0d277 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi100/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi100/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,,Gb/sec,23070.72,
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,,Gb/sec,23070.72,
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,,Pct,100,
 Instr Cache BW,,Gb/s,4614.144,
 Scalar L1D Cache Hit Rate,,Pct,100,
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi100/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi100/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi100/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi100/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi100/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi100/prev_analysis/701.csv
index 8fb0971b0c..b6e142aea6 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi100/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi100/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,23.976047904191617,8,36,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi100/timestamps.csv
index b8180e383b..9be170ed3e 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,873448,873453,33554432,256,0,0,8,32,6464,0x0,0x7f47ac404180,12075402664803599,12075402664851029,12075402665174706,12075402665287268
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,873448,873453,32768,256,0,0,24,24,12480,0x0,0x7f47ac435100,12075402679814105,12075402679915257,12075402679922137,12075402679928087
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,873448,873453,4194304,256,0,0,24,24,12928,0x7f48b80c6900,0x7f47ac435140,12075402679968402,12075402679981496,12075402680111895,12075402680115946
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi200/pmc_perf.csv
index 7d315f5296..ad64990e7c 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,GRBM_COUNT,GRBM_GUI_ACTIVE,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,CPC_ME1_DC0_SPI_BUSY,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,GRBM_COUNT,GRBM_GUI_ACTIVE,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,CPC_ME1_DC0_SPI_BUSY,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBufferAligned.kd,0,0,0,167083,167083,33554432,256,0,0,4,32,4160,0x0,0x7f8363204280,3086808,2999011,524288,38918341,242075056,385850,385850,31154135.0,30779652.0,385850,0,28168866.0,27415965.0,302,382191,0.0,0.0,20013585.0,524288.0,0.0,21003499.0,524288.0,0.0,524288.0,0.0,0.0,29832601.0,28135522.0,8745,926,29348060.0,2097152.0,1260,382206,2097152.0,4194304.0,0,8855,63.0,0.0,368904,0.0,1263998.0,0.0,0.0,0.0,0.0,0.0,0.0,16637050166018,16649012699076,16649012939874,16637200745348
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,167083,167083,32768,256,0,0,12,24,13888,0x0,0x7f8363223f80,269216,156386,512,1393739,1714305,33651,33651,36195.0,33014.0,33651,0,33826.0,32392.0,302,33272,0.0,0.0,12538.0,4096.0,0.0,0.0,4096.0,4096.0,0.0,0.0,4096.0,0.0,0.0,11453,1045,0.0,16384.0,1448,31358,16384.0,0.0,0,30645,0.0,0.0,499,0.0,1468.0,0.0,0.0,0.0,0.0,0.0,4096.0,16637206202632,16649017715526,16649017729126,16637206404855
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,167083,167083,4194304,256,0,0,12,24,14336,0x7f8366150380,0x7f8363223fc0,1391232,1264100,65536,16329141,80980352,173903,173903,11635542.0,11313721.0,173903,0,11561935.0,11534318.0,402,178431,0.0,0.0,9789470.0,524288.0,0.0,0.0,524288.0,524288.0,0.0,0.0,524288.0,0.0,0.0,19769,4736,0.0,2097152.0,7042,166599,2097152.0,0.0,0,15734,181.0,0.0,153819,0.0,32910.0,0.0,0.0,0.0,0.0,0.0,524288.0,16637206694015,16649017795366,16649017887685,16637206980965
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi200/prev_analysis/1.csv
index aa065cc44a..735b4c044d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,3357901.0,3357901.0,3357901.0,7.841562787805866
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,1725110.0,1725110.0,1725110.0,4.028575702759484
 "void benchmark_func<double, 256, 8u, 512u>(double, double*) [clone .kd]",1,1715030.0,1715030.0,1715030.0,4.005036309280915
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi200/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi200/prev_analysis/1202.csv
index 19a4b69a2b..968300c320 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,18146.72036469054,1846.8861083984375,258119.48901367188,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi200/prev_analysis/1901.csv
index d98a96bbea..c47e4ff3af 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,,il1_fetch_
 IL1 Hit,,il1_hit_
 IL1_L2 Rd,,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi200/prev_analysis/201.csv
index a68da7a926..055e24ffb6 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,,Gb/sec,22630.4,
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,,Gb/sec,22630.4,
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,,Pct,100,
 Instr Cache BW,,Gb/s,6092.8,
 Scalar L1D Cache Hit Rate,,Pct,100,
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi200/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi200/prev_analysis/701.csv
index d28098ed25..9d9e3a3dab 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi200/timestamps.csv
index 661f0235f8..15f43de2d1 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TA_CPC/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,167556,167556,33554432,256,0,0,4,32,4160,0x0,0x7f5678404280,16649012672586,16649012699076,16649012939874,16649013055803
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,167556,167556,32768,256,0,0,12,24,13888,0x0,0x7f5678423f80,16649017699376,16649017715526,16649017729126,16649017746554
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,167556,167556,4194304,256,0,0,12,24,14336,0x7f567b46b380,0x7f5678423fc0,16649017751024,16649017795366,16649017887685,16649017890059
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi100/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi100/pmc_dispatch_info.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi100/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi100/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi100/pmc_perf.csv
index 322d2d149d..38f5007268 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,GRBM_COUNT,GRBM_GUI_ACTIVE,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TCC_EA_ATOMIC_LEVEL_sum,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,GRBM_COUNT,GRBM_GUI_ACTIVE,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TCC_EA_ATOMIC_LEVEL_sum,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBuffer.kd,0,0,0,864972,864977,33554432,256,0,0,8,32,6464,0x0,0x7f090a604180,4083024,3882683,524288,510377,510377,16332064,15438920,0,0,0,96,10706,0,8388944,8399654,0,4194727,4204927,11207,8388608,0,4194378,4194386,4194386,0,229584,0,0,216344,0,0,10877,0,21736,0,0,0,147145,4128850,65536,4063243,0,10595,4194349,13173364,611242633,12075191621159880,12075203455198412,12075203455524809,12075191864510615
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,864972,864977,32768,256,0,0,24,24,12480,0x0,0x7f090a635100,217704,74338,512,27212,27212,870784,191747,0,0,0,48,172,0,8624,8891,0,470,8421,8891,0,0,31,0,0,0,0,0,0,0,0,0,8374,0,344,0,0,0,52670,0,0,0,0,8373,0,3091898,0,12075191879361132,12075203470647997,12075203470655037,12075191879878283
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,864972,864977,4194304,256,0,0,24,24,12928,0x7f091615d900,0x7f090a635140,1715592,1546607,65536,214448,214448,6862336,6110609,0,0,0,48,5465,0,2097536,2098946,0,423,2098523,2099804,0,0,31,0,0,0,0,0,0,0,0,0,2098745,0,3168,0,0,332108,384983,0,0,1966100,0,2102035,0,831698689,0,12075191880009557,12075203470706876,12075203470837595,12075191880624029
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi100/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi100/prev_analysis/1.csv
index 2c47b8d9c9..1b2c2c92ac 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi100/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi100/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,6053876.0,6053876.0,6053876.0,9.176195273556337
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4526207.0,4526207.0,4526207.0,6.860622728403687
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 256u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,3049897.0,3049897.0,3049897.0,4.622897865141877
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi100/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi100/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi100/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi100/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi100/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi100/prev_analysis/1202.csv
index d92c0479fa..2d4898d1f7 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi100/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi100/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,,,,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi100/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi100/prev_analysis/1901.csv
index 901a2a9413..958a90334e 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi100/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi100/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,24.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,,il1_fetch_
 IL1 Hit,,il1_hit_
 IL1_L2 Rd,,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,0.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,44.0,hbm_rd_
 HBM Wr,0.0,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi100/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi100/prev_analysis/2001.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi100/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi100/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi100/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi100/prev_analysis/201.csv
index ee1eb34571..90a9551a93 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi100/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi100/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,,Gb/sec,23070.72,
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,,Gb/sec,23070.72,
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,,Pct,100,
 Instr Cache BW,,Gb/s,4614.144,
 Scalar L1D Cache Hit Rate,,Pct,100,
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi100/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi100/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi100/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi100/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi100/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi100/prev_analysis/701.csv
index 8fb0971b0c..b6e142aea6 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi100/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi100/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,23.976047904191617,8,36,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi100/timestamps.csv
index b1421763b9..d0738fb2e8 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,865329,865334,33554432,256,0,0,8,32,6464,0x0,0x7f8515404180,12075203455152141,12075203455198412,12075203455524809,12075203455631712
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,865329,865334,32768,256,0,0,24,24,12480,0x0,0x7f8515435100,12075203470548813,12075203470647997,12075203470655037,12075203470660932
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,865329,865334,4194304,256,0,0,24,24,12928,0x7f8620ffe900,0x7f8515435140,12075203470694073,12075203470706876,12075203470837595,12075203470841227
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi200/pmc_perf.csv
index 8b0ccf5b14..4d7affc0a0 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,GRBM_COUNT,GRBM_GUI_ACTIVE,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,TCC_EA_ATOMIC_LEVEL_sum,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,GRBM_COUNT,GRBM_GUI_ACTIVE,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,TCC_EA_ATOMIC_LEVEL_sum,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBufferAligned.kd,0,0,0,155691,155691,33554432,256,0,0,4,32,4160,0x0,0x7f018c604280,3035792,2948345,524288,379473,379473,12143136.0,9351792.0,0.0,0.0,56.0,304.0,0.0,4194696.0,0.0,4195057.0,0.0,2097594.0,2097463.0,750.0,4194304.0,0.0,2064387.0,4128768.0,4128768.0,0.0,1450770.0,0.0,0.0,1457360.0,0.0,0.0,309.0,0.0,602.0,0.0,0.0,0.0,190929.0,2064384.0,0.0,2031623.0,0.0,142.0,4128768.0,526448.0,1629445996.0,16335241863961,16343179280950,16343179518712,16335386682896
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,155691,155691,32768,256,0,0,12,24,13888,0x0,0x7f018c623f80,200912,102738,512,25113,25113,803616.0,259457.0,0.0,0.0,0.0,61.0,0.0,4600.0,0.0,4660.0,0.0,499.0,4161.0,4660.0,0.0,0.0,31.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,8259.0,0.0,116.0,0.0,0.0,0.0,53619.0,0.0,0.0,0.0,0.0,8205.0,0.0,3416027.0,0.0,16335392065267,16343184405785,16343184412985,16335392328611
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,155691,155691,4194304,256,0,0,12,24,14336,0x7f018f696380,0x7f018c623fc0,1313056,1205448,65536,164131,164131,5252192.0,4725074.0,0.0,0.0,0.0,184.0,0.0,1048968.0,0.0,1049133.0,0.0,388.0,1048745.0,1049146.0,0.0,0.0,31.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,2097337.0,0.0,356.0,0.0,0.0,334375.0,964875.0,0.0,0.0,983046.0,0.0,2097265.0,0.0,1476812669.0,0.0,16335392404579,16343184447706,16343184539866,16335392983106
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi200/prev_analysis/1.csv
index d654a324a2..a04bf70bb7 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,3354264.0,3354264.0,3354264.0,7.879248116740126
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,1720492.0,1720492.0,1720492.0,4.041477758121141
 "void benchmark_func<double, 256, 8u, 512u>(double, double*) [clone .kd]",1,1711532.0,1711532.0,1711532.0,4.020430499131988
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi200/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi200/prev_analysis/1202.csv
index d92c0479fa..2d4898d1f7 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,,,,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi200/prev_analysis/1901.csv
index 6761c55dc5..dd8c3e288e 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,,il1_fetch_
 IL1 Hit,,il1_hit_
 IL1_L2 Rd,,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,0.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,44.0,hbm_rd_
 HBM Wr,0.0,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi200/prev_analysis/201.csv
index cc94e24d7b..2e75da141c 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,,Gb/sec,22630.4,
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,,Gb/sec,22630.4,
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,,Pct,100,
 Instr Cache BW,,Gb/s,6092.8,
 Scalar L1D Cache Hit Rate,,Pct,100,
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi200/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi200/prev_analysis/701.csv
index d28098ed25..9d9e3a3dab 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi200/timestamps.csv
index bdb840fb68..405fb8f173 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TCC/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,156034,156034,33554432,256,0,0,4,32,4160,0x0,0x7fe2d8a04280,16343179251330,16343179280950,16343179518712,16343179625622
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,156034,156034,32768,256,0,0,12,24,13888,0x0,0x7fe2d8a23f80,16343184389807,16343184405785,16343184412985,16343184423136
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,156034,156034,4194304,256,0,0,12,24,14336,0x7fe2dbae5380,0x7fe2d8a23fc0,16343184437766,16343184447706,16343184539866,16343184542333
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi100/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi100/pmc_dispatch_info.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi100/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi100/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi100/pmc_perf.csv
index 92e8a7e24a..d35a25327c 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBuffer.kd,0,0,0,862685,862690,33554432,256,0,0,8,32,6464,0x0,0x7f0bba004180,4050064,3843144,57232741,524288,368076551,506257,506257,58058469,55385035,79,12247551,0,0,0,1048576,67108864,67108864,0,67108864,0,0,360,33554432,15339,16608641,0,16777216,639589777,0,2792631690,0,8388608,0,0,0,0,0,0,0,0,0,0,0,0,8388608,0,42220429,12075136458560390,12075147439751938,12075147440072415,12075136699500264
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,862685,862690,32768,256,0,0,24,24,12480,0x0,0x7f0bba035100,226920,77847,1062129,512,1133979,28364,28364,1554407,637475,291,132899,0,0,0,4096,65536,65536,65536,0,0,0,360,16384,120,15064,0,16384,12492250,17737144,0,8192,0,0,0,0,0,0,0,0,0,0,0,0,8192,0,0,432660,12075136714450868,12075147454470885,12075147454477285,12075136714965805
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,862685,862690,4194304,256,0,0,24,24,12928,0x7f0cc5b86900,0x7f0bba035140,1840808,1667146,24636127,65536,120864602,230100,230100,25423007,24090444,29114,4906443,0,0,0,524288,8388608,8388608,8388608,0,0,0,360,2097152,7602,2018400,0,2097152,960258060,1572300696,0,2097152,0,0,0,0,0,0,0,0,0,0,0,0,2097152,0,0,16147101,12075136715314513,12075147454541604,12075147454675843,12075136715955484
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi100/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi100/prev_analysis/1.csv
index 47cf37a2bf..599c8c5994 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi100/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi100/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,6051634.0,6051634.0,6051634.0,9.170708809097045
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4526206.0,4526206.0,4526206.0,6.859059426923025
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 256u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,3049577.0,3049577.0,3049577.0,4.621360554508045
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi100/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi100/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi100/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi100/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi100/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi100/prev_analysis/1202.csv
index 271d22cf09..a71543905e 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi100/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi100/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,33570.82415255244,2808.2012252807617,547911.3511352539,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi100/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi100/prev_analysis/1901.csv
index 4bcf66aa60..9d3f121fcb 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi100/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi100/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,24.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,,il1_fetch_
 IL1 Hit,,il1_hit_
 IL1_L2 Rd,,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,30.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi100/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi100/prev_analysis/2001.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi100/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi100/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi100/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi100/prev_analysis/201.csv
index f888d3c25d..81ef129fd8 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi100/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi100/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,,Gb/sec,23070.72,
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,,Gb/sec,23070.72,
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,,Pct,100,
 Instr Cache BW,,Gb/s,4614.144,
 Scalar L1D Cache Hit Rate,,Pct,100,
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi100/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi100/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi100/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi100/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi100/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi100/prev_analysis/701.csv
index 8fb0971b0c..b6e142aea6 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi100/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi100/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,23.976047904191617,8,36,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi100/timestamps.csv
index 2c60754c08..231959fc6d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,863012,863017,33554432,256,0,0,8,32,6464,0x0,0x7ff876004180,12075147439705970,12075147439751938,12075147440072415,12075147440177957
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,863012,863017,32768,256,0,0,24,24,12480,0x0,0x7ff876035100,12075147454372485,12075147454470885,12075147454477285,12075147454482670
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,863012,863017,4194304,256,0,0,24,24,12928,0x7ff981bfa900,0x7ff876035140,12075147454526472,12075147454541604,12075147454675843,12075147454679055
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi200/pmc_perf.csv
index 7ee7f7d2a9..23c7509106 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBufferAligned.kd,0,0,0,152567,152567,33554432,256,0,0,4,32,4160,0x0,0x7f7117c04280,3043368,2955630,38400365,524288,238477969,380420,380420,38664982.0,37830227.0,11.0,4089548.0,0.0,0.0,0.0,524288.0,33554432.0,33554432.0,0.0,33554432.0,0.0,0.0,104.0,8388608.0,13312.0,8242176.0,0.0,8388608.0,314404782.0,0.0,1469333319.0,0.0,4194304.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,4194304.0,0.0,19094396.0,16255303836302,16263272627979,16263272865101,16255451542868
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,152567,152567,32768,256,0,0,12,24,13888,0x0,0x7f7117c23f80,208968,111356,1076857,512,1305726,26120,26120,1683791.0,192332.0,180.0,0.0,0.0,0.0,0.0,4096.0,65536.0,65536.0,65536.0,0.0,0.0,0.0,104.0,16384.0,104.0,15240.0,0.0,16384.0,7508346.0,8929386.0,0.0,8192.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,8192.0,0.0,0.0,94902.0,16255457325460,16263277888332,16263277896172,16255457561965
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,152567,152567,4194304,256,0,0,12,24,14336,0x7f713e388380,0x7f7117c23fc0,1363064,1236158,15988066,65536,87270038,170382,170382,16306243.0,14590160.0,24287.0,807059.0,0.0,0.0,0.0,524288.0,8388608.0,8388608.0,8388608.0,0.0,0.0,0.0,208.0,2097152.0,6820.0,2025717.0,0.0,2097152.0,991611334.0,2296375566.0,0.0,2097152.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,2097152.0,0.0,0.0,11623527.0,16255458107063,16263277967853,16263278060333,16255458436986
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi200/prev_analysis/1.csv
index c74e2d22c6..3be3623203 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,3352822.0,3352822.0,3352822.0,7.877287107187259
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,1719531.0,1719531.0,1719531.0,4.039951830639627
 "void benchmark_func<double, 256, 8u, 512u>(double, double*) [clone .kd]",1,1711211.0,1711211.0,1711211.0,4.020404407981401
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi200/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi200/prev_analysis/1202.csv
index 8fc4497332..32d9373791 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,18841.864743946557,1819.442512512207,258568.00024414062,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi200/prev_analysis/1901.csv
index bd050f8d56..d955856c66 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,,il1_fetch_
 IL1 Hit,,il1_hit_
 IL1_L2 Rd,,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,3.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi200/prev_analysis/201.csv
index 997871219f..15b50d3159 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,,Gb/sec,22630.4,
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,,Gb/sec,22630.4,
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,,Pct,100,
 Instr Cache BW,,Gb/s,6092.8,
 Scalar L1D Cache Hit Rate,,Pct,100,
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi200/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi200/prev_analysis/701.csv
index d28098ed25..9d9e3a3dab 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi200/timestamps.csv
index 0460442817..7e867ad298 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TCP/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,152884,152884,33554432,256,0,0,4,32,4160,0x0,0x7faac0204280,16263272597989,16263272627979,16263272865101,16263272975281
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,152884,152884,32768,256,0,0,12,24,13888,0x0,0x7faac0223f80,16263277872962,16263277888332,16263277896172,16263277919581
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,152884,152884,4194304,256,0,0,12,24,14336,0x7faac3119380,0x7faac0223fc0,16263277920561,16263277967853,16263278060333,16263278062978
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi100/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi100/pmc_dispatch_info.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi100/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi100/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi100/pmc_perf.csv
index 6b79a6d842..d1c97c7fd3 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,GRBM_COUNT,GRBM_GUI_ACTIVE,TD_TD_BUSY_sum,TD_TC_STALL_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,GRBM_COUNT,GRBM_GUI_ACTIVE,TD_TD_BUSY_sum,TD_TC_STALL_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBuffer.kd,0,0,0,860709,860715,33554432,256,0,0,8,32,6464,0x0,0x7f588cc04180,4038864,3835198,57371238,524288,367403680,504857,504857,55595309,54413933,1048576,1048576,0,1048576,12075089892782251,12075093208489155,12075093208815232,12075090134629592
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,860709,860715,32768,256,0,0,24,24,12480,0x0,0x7f588cc35100,218424,73402,1035867,512,1105318,27302,27302,592232,571748,4096,4096,0,0,12075090149202244,12075093223931152,12075093223937872,12075090149710528
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,860709,860715,4194304,256,0,0,24,24,12928,0x7f59987a3900,0x7f588cc35140,1790312,1602551,23768599,65536,142188998,223788,223788,23284372,21124335,524288,524288,0,0,12075090149874072,12075093224005071,12075093224143150,12075090150529119
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi100/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi100/prev_analysis/1.csv
index aef3828662..c890192137 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi100/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi100/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,6054039.0,6054039.0,6054039.0,9.17959762507417
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4525569.0,4525569.0,4525569.0,6.862014341914429
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 256u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,3051339.0,3051339.0,3051339.0,4.626673901125544
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi100/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi100/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi100/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi100/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi100/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi100/prev_analysis/1202.csv
index 9406146636..6a7e03e784 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi100/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi100/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,33599.41984037297,2803.067626953125,547908.8068847656,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi100/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi100/prev_analysis/1901.csv
index dd6c8947a7..e5902eb696 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi100/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi100/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,24.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,,il1_fetch_
 IL1 Hit,,il1_hit_
 IL1_L2 Rd,,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi100/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi100/prev_analysis/2001.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi100/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi100/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi100/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi100/prev_analysis/201.csv
index 07a3c668c7..179480bed5 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi100/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi100/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,,Gb/sec,23070.72,
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,,Gb/sec,23070.72,
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,,Pct,100,
 Instr Cache BW,,Gb/s,4614.144,
 Scalar L1D Cache Hit Rate,,Pct,100,
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi100/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi100/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi100/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi100/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi100/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi100/prev_analysis/701.csv
index 8fb0971b0c..b6e142aea6 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi100/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi100/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,23.976047904191617,8,36,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi100/timestamps.csv
index 97e83702c5..a8b747c6a9 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,860821,860826,33554432,256,0,0,8,32,6464,0x0,0x7fc432204180,12075093208441641,12075093208489155,12075093208815232,12075093208922645
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,860821,860826,32768,256,0,0,24,24,12480,0x0,0x7fc432235100,12075093223823516,12075093223931152,12075093223937872,12075093223943489
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,860821,860826,4194304,256,0,0,24,24,12928,0x7fc53ddef900,0x7fc432235140,12075093223991688,12075093224005071,12075093224143150,12075093224146646
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi200/pmc_perf.csv
index 2a1806e6a8..3a5045aa5f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,GRBM_COUNT,GRBM_GUI_ACTIVE,TD_TD_BUSY_sum,TD_TC_STALL_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,TD_COALESCABLE_WAVEFRONT_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,GRBM_COUNT,GRBM_GUI_ACTIVE,TD_TD_BUSY_sum,TD_TC_STALL_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,TD_COALESCABLE_WAVEFRONT_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBufferAligned.kd,0,0,0,149693,149693,33554432,256,0,0,4,32,4160,0x0,0x7f890e804280,3042432,2952965,38366152,524288,237911746,380303,380303,37856543.0,37298308.0,7883.0,524288.0,0.0,524288.0,0.0,16180290879309,16183289197144,16183289434105,16180439261285
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,149693,149693,32768,256,0,0,12,24,13888,0x0,0x7f890e823f80,200488,100215,1102370,512,1354619,25060,25060,283880.0,265123.0,0.0,4096.0,0.0,0.0,4096.0,16180444841491,16183294361816,16183294370297,16180445030567
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,149693,149693,4194304,256,0,0,12,24,14336,0x7f8911908380,0x7f890e823fc0,1336000,1216950,15743598,65536,90042619,166999,166999,14689464.0,12554811.0,2139.0,524288.0,0.0,0.0,524288.0,16180445328961,16183294445977,16183294537978,16180445603214
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi200/prev_analysis/1.csv
index 0c47df1f2d..70de2cbd19 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,3354742.0,3354742.0,3354742.0,7.874485460797985
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,1721131.0,1721131.0,1721131.0,4.039959268292076
 "void benchmark_func<double, 256, 8u, 512u>(double, double*) [clone .kd]",1,1712812.0,1712812.0,1712812.0,4.020432328650108
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi200/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi200/prev_analysis/1202.csv
index fac8e3f987..d66860e02e 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,18846.920010778005,1815.122573852539,258284.05364990234,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi200/prev_analysis/1901.csv
index 179e4e485d..d782418057 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,,il1_fetch_
 IL1 Hit,,il1_hit_
 IL1_L2 Rd,,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi200/prev_analysis/201.csv
index 8234d902f8..ddc645b2a4 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,,Gb/sec,22630.4,
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,,Gb/sec,22630.4,
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,,Pct,100,
 Instr Cache BW,,Gb/s,6092.8,
 Scalar L1D Cache Hit Rate,,Pct,100,
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi200/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi200/prev_analysis/701.csv
index d28098ed25..9d9e3a3dab 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi200/timestamps.csv
index 5af9d962b2..7ec466a254 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_TD/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,149854,149854,33554432,256,0,0,4,32,4160,0x0,0x7fc5e4404280,16183289169342,16183289197144,16183289434105,16183289492135
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,149854,149854,32768,256,0,0,12,24,13888,0x0,0x7fc5e4423f80,16183294346368,16183294361816,16183294370297,16183294394017
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,149854,149854,4194304,256,0,0,12,24,14336,0x7fc5febd0380,0x7fc5e4423fc0,16183294400107,16183294445977,16183294537978,16183294540374
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/SQ_IFETCH_LEVEL.csv
index 1d07b8f84c..aa848934a7 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/SQ_IFETCH_LEVEL.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,921977,921982,33554432,256,0,0,8,32,6464,0x0,0x7fef51804180,500265,500265,524288,6291456,793051,101503448,12076344617046446,12076344859521245,12076344859842363,12076344859951985
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,921977,921982,32768,256,0,0,24,24,12480,0x0,0x7fef51835100,28595,28595,512,8192,9069,1168320,12076344874062529,12076344874378397,12076344874384957,12076344874394085
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,921977,921982,4194304,256,0,0,24,24,12928,0x7ff05d4a8900,0x7fef51835140,219851,219851,65536,917504,140868,18017056,12076344874453576,12076344874677595,12076344874811835,12076344874815909
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/SQ_INST_LEVEL_LDS.csv
index c17e149c20..21931d44c8 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/SQ_INST_LEVEL_LDS.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,923776,923781,33554432,256,0,0,8,32,6464,0x0,0x7fae55c04180,0,0,0,12076370985727071,12076371227941065,12076371228264424,12076371228377496
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,923776,923781,32768,256,0,0,24,24,12480,0x0,0x7fae55c35100,0,0,0,12076371243321709,12076371243625434,12076371243631354,12076371243644008
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,923776,923781,4194304,256,0,0,24,24,12928,0x7faf6179d900,0x7fae55c35140,0,0,0,12076371243694221,12076371243916793,12076371244048792,12076371244052096
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/SQ_INST_LEVEL_SMEM.csv
index 0fdd05a71f..47a3df3d9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/SQ_INST_LEVEL_SMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,923397,923402,33554432,256,0,0,8,32,6464,0x0,0x7f1b0e804180,4194304,3152620,403345080,12076368453169184,12076368700065492,12076368700389970,12076368700502522
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,923397,923402,32768,256,0,0,24,24,12480,0x0,0x7f1b0e835100,512,24484,3121824,12076368715262483,12076368715563296,12076368715569536,12076368715573751
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,923397,923402,4194304,256,0,0,24,24,12928,0x7f1c1a557900,0x7f1b0e835140,65536,185462,23668128,12076368715636578,12076368715862494,12076368715994174,12076368715997128
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/SQ_INST_LEVEL_VMEM.csv
index 5a744c6edb..a3c9bfa70a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/SQ_INST_LEVEL_VMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,923588,923593,33554432,256,0,0,8,32,6464,0x0,0x7fb460c04180,1048576,11160259,1427270340,12076369721544664,12076369965512173,12076369965839212,12076369965952014
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,923588,923593,32768,256,0,0,24,24,12480,0x0,0x7fb460c35100,4096,118993,15227252,12076369980939898,12076369981259465,12076369981265705,12076369981275071
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,923588,923593,4194304,256,0,0,24,24,12928,0x7fb56c7a1900,0x7fb460c35140,524288,12411615,1588640340,12076369981333169,12076369981552424,12076369981683463,12076369981686446
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/SQ_LEVEL_WAVES.csv
index dc7bf6091e..1f12282a0c 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/SQ_LEVEL_WAVES.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,923964,923971,33554432,256,0,0,8,32,6464,0x0,0x7f7218204180,503794,503794,17388,4030360,524288,372264229,3830546,0,1503874120,12076372249654203,12076372493766415,12076372494090093,12076372494202225
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,923964,923971,32768,256,0,0,24,24,12480,0x0,0x7f7218235100,28906,28906,21866,231256,512,1154300,79191,0,4631488,12076372509083762,12076372509413495,12076372509420535,12076372509428051
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,923964,923971,4194304,256,0,0,24,24,12928,0x7f7323f35900,0x7f7218235140,212452,212452,22451,1699624,65536,147821134,1535677,0,593101892,12076372509498252,12076372509743573,12076372509872852,12076372509876204
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/pmc_dispatch_info.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/pmc_perf.csv
index 9ba139aa8d..b2abd72359 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBuffer.kd,0,0,0,922712,922717,33554432,256,0,0,8,32,6464,0x0,0x7f06dac04180,1048576,0,1048576,9437184,0,4194304,1048576,0,503419,503419,57711719,55198566,122,12253771,54351053,54250719,55164911,53995410,4027352,3831906,503419,0,503419,0,16109408,15220409,0,0,0,0,0,17407785,1048576,0,507129,0,0,0,507129,0,0,0,507129,0,0,0,507129,0,0,0,507129,0,0,0,507129,0,0,0,507129,0,0,0,507129,0,0,0,507129,0,0,0,507129,0,0,0,507129,0,0,0,507129,0,0,0,507129,0,0,0,507129,0,0,0,507129,0,0,0,507129,0,0,0,507129,0,0,0,507129,0,0,0,507129,0,0,0,507129,0,0,0,507129,0,0,0,507129,0,0,0,507129,0,0,0,507129,0,0,0,507129,0,0,0,507129,0,0,0,507129,0,0,0,507129,0,0,0,507129,0,0,0,507129,0,0,0,507129,0,0,0,507129,0,0,0,37818757,48,0,0,0,4,0,0,0,52,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,2607,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2717,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,3,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,48,0,0,0,1,0,0,0,2680,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,2696,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,17,0,0,0,1048576,0,0,19902,131072,131072,0,596527,131072,131072,0,0,131072,131072,0,0,131080,131080,0,0,131072,131072,0,0,131076,131076,0,0,131072,131072,0,1420,131072,131072,0,0,131072,131072,0,0,131072,131072,0,6193,131076,131076,0,0,131076,131076,0,3238548,131072,131072,0,0,131072,131072,0,265,131072,131072,0,272,131076,131076,0,3276553,131076,131076,0,781,131072,131072,0,0,131076,131076,0,0,131072,131072,0,0,131072,131072,0,0,131080,131080,0,2960257,131074,131074,0,0,131076,131076,0,0,131072,131072,0,0,131072,131072,0,0,131084,131084,0,0,131072,131072,0,2955906,131076,131076,0,0,131076,131076,0,266,131072,131072,0,0,131084,131084,1048576,0,44852,0,0,29812647,786,0,0,17293863,1081,0,0,17112018,899,0,0,17294033,50001,0,0,30716409,874,0,0,17392474,897,0,0,17950119,1096,0,0,18782196,760,0,0,16783514,1144,0,0,17034420,1287,0,0,16957346,1765,0,0,17167840,1196,0,0,17057790,1807,0,0,17609989,1389,0,0,18172573,1039,0,0,18622053,978,0,0,16455855,1073,0,0,17026113,1301,0,0,17060087,943,0,0,17077618,44272,0,0,29062024,1123,0,0,17389007,871,0,0,18097624,1018,0,0,18808919,48451,0,0,29375987,1810,0,0,17031091,1761,0,0,17200435,1750,0,0,17175356,1126,0,0,17021832,1633,0,0,17334725,1725,0,0,18121510,746,0,0,18681908,1048576,131072,133651,2579,264723,131307,131077,240,262384,131072,131075,3,262147,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131120,48,262192,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,133806,2734,264878,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,133722,2650,264794,131213,131075,144,262288,131072,131072,0,262144,131072,131121,49,262193,131072,131072,0,262144,131072,131072,0,262144,131072,131096,24,262168,131119,131073,48,262192,131072,131072,0,262144,131072,131072,0,262144,131072,131073,1,262145,131072,131072,0,262144,131072,133634,2562,264706,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,262144,0,262144,262336,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262288,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,0,0,3145728,524288,32505856,369890088,219522013,117862219,482364,0,0,0,1048576,52859375,52611675,1048576,1048576,131072,524288,730,504163,4121,0,96,10812,0,8388944,32505856,4025432,3828084,57252875,11534336,0,0,14155776,67108864,67108864,0,67108864,54296954,53942365,0,1048576,244502,768790,11096,2888,0,498998,8399621,0,4194727,4204894,13631488,0,3670016,1048576,1048576,0,4194304,9437184,0,0,360,33554432,54182964,4194304,0,0,2778,499716,0,11096,8388608,0,4194378,905969664,6291456,0,0,0,524288,524288,0,15324,16608801,0,16777216,4194304,4194304,0,0,0,17144,4194343,4194343,0,223755,0,0,0,33554432,0,0,0,0,631778347,0,2769617615,0,0,0,0,0,469459,0,0,215567,0,0,8388608,336,144,0,0,0,480,8388608,0,0,0,0,359054,0,0,0,10905,0,21792,0,6291456,6289297,96,2742,1898777,0,0,0,0,0,0,0,0,0,3145728,0,0,0,157592,4194304,4189878,144,4282,2097152,524288,1572864,0,0,0,0,0,0,524288,0,4128842,65536,4063247,0,0,8388608,0,42274933,0,1048576,10786,4194397,13236671,608470520,12076346710884882,12076373388975990,12076373389301426,12076346955407977
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,922712,922717,32768,256,0,0,24,24,12480,0x0,0x7f06dac35100,0,4096,4096,512,0,512,4096,0,29156,29156,1569047,647694,209,127358,87782,64480,639580,619118,233248,90429,29156,0,29156,0,932992,207709,0,0,0,0,0,55548,4096,0,28282,0,0,0,28282,0,0,0,28282,0,0,0,28282,0,0,0,28282,0,0,0,28282,0,0,0,28282,0,0,0,28282,0,0,0,28282,0,0,0,28282,0,0,0,28282,0,0,0,28282,0,0,0,28282,0,0,0,28282,0,0,0,28282,0,0,0,28282,0,0,0,28282,0,0,0,28282,0,0,0,28282,0,0,0,28282,0,0,0,28282,0,0,0,28282,0,0,0,28282,0,0,0,28282,0,0,0,28282,0,0,0,28282,0,0,0,28282,0,0,0,28282,0,0,0,28282,0,0,0,28282,0,0,0,28282,0,0,0,28282,0,0,0,0,304,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,257,0,0,0,304,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,257,0,0,0,376,0,0,0,4096,4096,0,112496,0,0,0,95167,0,0,0,78196,0,0,0,83995,0,0,0,88689,0,0,0,129913,0,0,0,160481,0,0,0,95787,0,0,0,78268,0,0,0,91646,0,0,0,201711,0,0,0,71255,0,0,0,79667,0,0,0,91543,0,0,0,93964,0,0,0,68390,0,0,0,128547,0,0,0,122961,0,0,0,79819,0,0,0,87433,0,0,0,128043,0,0,0,80269,0,0,0,101457,0,0,0,86851,0,0,0,111337,0,0,0,82386,0,0,0,84134,0,0,0,76132,0,0,0,90410,0,0,0,84409,0,0,0,74879,0,0,0,89587,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4096,0,304,304,304,47,257,304,304,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,188,260,448,448,0,256,256,256,0,257,257,257,0,256,256,256,188,260,448,448,0,305,305,305,0,256,256,256,0,256,256,256,0,376,376,376,0,256,256,256,0,256,256,256,0,256,256,256,0,257,257,257,0,256,256,256,0,256,256,256,0,256,256,256,47,257,304,304,0,256,256,256,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,304,0,0,256,0,0,0,0,512,512,35328,1118743,1065952,16439,11944,0,0,0,4096,64950,61900,4096,4096,128,512,600,27249,4103,0,48,219,0,8624,36352,221056,73117,1035247,26624,0,0,30208,65536,65536,65536,0,0,0,0,0,114,626,11324,2999,0,23652,8893,0,470,8423,1024,0,1024,4096,0,4096,512,512,0,0,360,16384,0,16384,0,0,2855,24514,0,8892,0,0,31,1933312,8192,0,0,0,512,512,0,120,15064,0,16384,16384,0,0,0,0,20833,0,0,0,0,0,0,0,32768,0,0,0,0,12347004,17058359,0,8192,0,0,0,0,696,0,0,0,0,0,1024,432,48,0,0,0,480,0,0,0,0,0,3248,0,0,0,8422,0,440,0,8192,6576,48,1568,1086,0,0,0,0,0,0,0,0,0,2560,0,0,0,50691,512,0,48,464,0,512,0,0,0,0,0,0,0,512,0,0,0,0,0,8192,0,0,442954,0,4096,8422,0,3073678,0,12076346970390081,12076373404607003,12076373404613563,12076346971396351
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,922712,922717,4194304,256,0,0,24,24,12928,0x7f080abf5900,0x7f06dac35140,0,524288,524288,65536,0,65536,524288,0,225871,225871,25049687,23758270,30784,6904191,22403791,22203180,23738564,21573483,1806968,1653993,225871,0,225871,0,7227872,6505011,0,0,0,0,0,20599041,524288,0,223103,0,0,0,223103,0,0,0,223103,0,0,0,223103,0,0,0,223103,0,0,0,223103,0,0,0,223103,0,0,0,223103,0,0,0,223103,0,0,0,223103,0,0,0,223103,0,0,0,223103,0,0,0,223103,0,0,0,223103,0,0,0,223103,0,0,0,223103,0,0,0,223103,0,0,0,223103,0,0,0,223103,0,0,0,223103,0,0,0,223103,0,0,0,223103,0,0,0,223103,0,0,0,223103,0,0,0,223103,0,0,0,223103,0,0,0,223103,0,0,0,223103,0,0,0,223103,0,0,0,223103,0,0,0,223103,0,0,0,223103,0,0,0,0,65584,0,9978,0,65536,0,14468,0,65540,0,5622,0,65536,0,31190,0,65536,0,524,0,65537,0,15798,0,65536,0,18437,0,66805,0,58536,0,65536,0,5587,0,65536,0,2073,0,65536,0,1425,0,65536,0,856,0,65536,0,813,0,65536,0,985,0,65536,0,2655,0,65536,0,1067,0,65537,0,1337,0,65536,0,832,0,65536,0,7714,0,65536,0,31289,0,65537,0,776,0,65584,0,10811,0,65537,0,4071,0,65536,0,28849,0,65536,0,872,0,65536,0,739,0,65536,0,2052,0,68043,0,58062,0,65537,0,16954,0,65536,0,12775,0,65540,0,3074,0,65656,0,3327,0,524288,524288,0,35917037,0,0,0,38994302,0,0,0,38792761,0,0,0,43229851,0,0,0,34734070,0,0,0,45347540,0,0,0,36379612,0,0,0,39412899,0,0,0,33537554,0,0,0,33231131,0,0,0,39372481,0,0,0,38827555,0,0,0,35646770,0,0,0,34637458,0,0,0,33937971,0,0,0,36431943,0,0,0,44550855,0,0,0,34661661,0,0,0,32990988,0,0,0,34055754,0,0,0,33880112,0,0,0,38745034,0,0,0,49851893,0,0,0,39938051,0,0,0,37746131,0,0,0,36664783,0,0,0,36334201,0,0,0,47218783,0,0,0,34109126,0,0,0,39865985,0,0,0,36715102,0,0,0,34504496,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,524288,0,65584,65584,65584,47,65537,65584,65584,188,65540,65728,65728,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,67673,67673,67673,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,67843,67843,67843,0,65536,65536,65536,0,65536,65536,65536,0,65585,65585,65585,0,65536,65536,65536,0,65536,65536,65536,0,65656,65656,65656,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65537,65537,65537,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,188,65540,65728,65728,0,65536,65536,65536,65536,0,0,65536,0,0,65728,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65728,0,0,65536,0,0,0,0,65536,65536,4128768,148566124,53016320,91289964,198760,0,0,0,524288,22353721,22349001,524288,524288,16384,65536,764,216270,4097,0,48,2734,0,2097536,4259840,1710712,1545496,22878315,3014656,0,0,3473408,8388608,8388608,8388608,0,0,0,0,0,218388,236624,11385,2985,0,209922,2099497,0,423,2099074,131072,0,131072,524288,0,524288,65536,65536,0,0,360,2097152,0,2097152,30233,0,2886,223071,0,2102165,0,0,31,222298112,917504,0,0,0,65536,65536,0,7597,2016466,0,2097152,2097152,0,562940,564706,0,20201,0,0,0,0,0,0,0,4194304,0,0,0,0,1086628692,1849808766,0,2097152,0,0,0,0,191235,0,0,0,0,0,131072,384,48,0,0,0,432,0,0,0,0,0,5235,0,0,0,2098306,0,2290,0,917504,914643,48,7853,208481,0,0,0,0,0,0,0,0,0,327680,0,0,413705,466643,65536,64048,48,1440,0,65536,0,0,0,0,0,0,0,65536,0,0,0,1966091,0,2097152,0,0,14283021,0,524288,2102059,0,846396750,0,12076346972033966,12076373404680443,12076373404815161,12076346973269943
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/prev_analysis/1.csv
index fe563f7640..437cda9764 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,6054034.0,6054034.0,6054034.0,9.169568049732888
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4526685.0,4526685.0,4526685.0,6.85621292302044
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 256u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,3048136.0,3048136.0,3048136.0,4.616771309318813
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/prev_analysis/1001.csv
index ca08330db0..0e3bf5267e 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,46.862275449101794,Instr per wave
 SMEM,1.8083832335329342,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/prev_analysis/101.csv
index c16a854f21..a526d2bffc 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx908
 mi100
 48
 1228.8
-SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/prev_analysis/1202.csv
index a21ee502df..4389811399 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,33770.14574939477,2822.0374145507812,547866.8856201172,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/prev_analysis/1901.csv
index 600b81af21..a00f1fef9a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,2.0,smem_
 VALU,735.0,valu_
 MFMA,,mfma_
 VMEM,8.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,22.0,br_
 VGPR,24.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,67894.0,wavefronts_
 Workgroups,16973.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,163.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,0.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,44.0,hbm_rd_
 HBM Wr,0.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,70.0,vl1_coales_
 VL1 Stall,29.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,35.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/prev_analysis/2001.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/prev_analysis/201.csv
index c3f7c52087..c03162bb97 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,59.181161093240085,Pct,100,59.181161093240085
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,63.96718864264706,Threads,64,99.94873225413603
 IPC - Issue,0.8437210211508805,Instr/cycle,5,16.87442042301761
-LDS BW,0.0,Gb/sec,23070.72,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,23070.72,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99346627122303,Pct,100,99.99346627122303
 Instr Cache BW,1408.5936500760986,Gb/s,4614.144,30.527734940134042
 Scalar L1D Cache Hit Rate,99.3562044853476,Pct,100,99.3562044853476
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/prev_analysis/602.csv
index abfc6cf40a..90cf036336 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,57278.479041916165,0,712969,Simd
 Insufficient SIMD VGPRs,606995.5628742515,0,31500516,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/prev_analysis/701.csv
index d3f1bff5a3..1071413faa 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,23.976047904191617,8,36,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/sysinfo.csv
index 01b24fa520..2db207180b 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-no_roof_dev0,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 11:31:59 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+no_roof_dev0,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 11:31:59 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/timestamps.csv
index 194474b4ed..91d72bd032 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,924015,924020,33554432,256,0,0,8,32,6464,0x0,0x7f8e6d404180,12076373388931820,12076373388975990,12076373389301426,12076373389409648
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,924015,924020,32768,256,0,0,24,24,12480,0x0,0x7f8e6d435100,12076373404491137,12076373404607003,12076373404613563,12076373404619515
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,924015,924020,4194304,256,0,0,24,24,12928,0x7f8f79130900,0x7f8e6d435140,12076373404666713,12076373404680443,12076373404815161,12076373404818856
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/SQ_IFETCH_LEVEL.csv
index ccc291461e..5c982468bf 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/SQ_IFETCH_LEVEL.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,225945,225945,33554432,256,0,0,4,32,4160,0x0,0x7f4f31404280,382117,382117,524288,4718592,680988,76295704,17646657372978,17645951454996,17646804678693,17646804792183
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,225945,225945,32768,256,0,0,12,24,13888,0x0,0x7f4f31423f80,33793,33793,512,8192,6062,677160,17646809965962,17646804678693,17646810097590,17646810102069
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,225945,225945,4194304,256,0,0,12,24,14336,0x7f4f34465380,0x7f4f31423fc0,164478,164478,65536,917504,141940,15901772,17646810140378,17646810097590,17646810482551,17646810484759
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/SQ_INST_LEVEL_LDS.csv
index 8405ca4dcc..b8be32715e 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/SQ_INST_LEVEL_LDS.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,227793,227793,33554432,256,0,0,4,32,4160,0x0,0x7f9c41a04280,0,0,0,17666060261741,17665354064386,17666205691980,17666205802350
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,227793,227793,32768,256,0,0,12,24,13888,0x0,0x7f9c41a23f80,0,0,0,17666210975250,17666205691980,17666211105746,17666211110206
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,227793,227793,4194304,256,0,0,12,24,14336,0x7f9c44aa2380,0x7f9c41a23fc0,0,0,0,17666211143506,17666211105746,17666211474706,17666211477197
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/SQ_INST_LEVEL_SMEM.csv
index 2915606879..95b3a63bc9 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/SQ_INST_LEVEL_SMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,225723,225723,33554432,256,0,0,4,32,4160,0x0,0x7fd037c04280,3670016,2919078,326948072,17645722477347,17617601275899,17645870450194,17645870563574
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,225723,225723,32768,256,0,0,12,24,13888,0x0,0x7fd037c23f80,512,95950,10742592,17645875725974,17645870450194,17645875853887,17645875858550
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,225723,225723,4194304,256,0,0,12,24,14336,0x7fd15e487380,0x7fd037c23fc0,65536,646678,72446904,17645875892209,17645875853887,17645876227168,17645876229951
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/SQ_INST_LEVEL_VMEM.csv
index aa8b92c3ab..798abaf719 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/SQ_INST_LEVEL_VMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,227571,227571,33554432,256,0,0,4,32,4160,0x0,0x7fdceec04280,524288,5456727,611147984,17665121372550,17662835928871,17665274814988,17665274925738
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,227571,227571,32768,256,0,0,12,24,13888,0x0,0x7fdceec23f80,4096,47634,5330268,17665280086847,17665274814988,17665280215795,17665280220394
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,227571,227571,4194304,256,0,0,12,24,14336,0x7fdcf1c9b380,0x7fdceec23fc0,524288,11193529,1253611932,17665280255313,17665280215795,17665280582035,17665280584445
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/SQ_LEVEL_WAVES.csv
index 4e28dd7552..db77dd9a89 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/SQ_LEVEL_WAVES.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,226167,226167,33554432,256,0,0,4,32,4160,0x0,0x7ff7a9404280,382686,382686,8869,3061496,524288,240410490,2973861,0,977856292,17647592662202,17646886584362,17647738091815,17647738183285
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,226167,226167,32768,256,0,0,12,24,13888,0x0,0x7ff7a9423f80,32710,32710,29152,261688,512,1692092,158331,0,6782424,17647743319055,17647738091815,17647743459988,17647743464431
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,226167,226167,4194304,256,0,0,12,24,14336,0x7ff7ac312380,0x7ff7a9423fc0,164884,164884,13879,1319080,65536,71638008,1209198,0,288286460,17647743508910,17647743459988,17647743858229,17647743860681
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/pmc_perf.csv
index e674cc41f8..76f89a45a0 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDI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],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBufferAligned.kd,0,0,0,226933,226933,33554432,256,0,0,4,32,4160,0x0,0x7f4abc604280,3078352,2993260,524288,38881508,242807543,392,224,0,384793,384793,39155121.0,38119984.0,2.0,4155241.0,31215648.0,30849243.0,38095507.0,37534948.0,3076641,2999667,384793,0,384793,0,12313376.0,9486587.0,0.0,0.0,0,0,616,0,4718592,4714946,112,3534,375370,0.0,0.0,0.0,524288.0,28459217.0,27729453.0,7775.0,524288.0,131072,524288,302,384194,2262,0,56.0,305.0,0.0,4194696.0,0,0,0,0,0,7340032,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,20172821.0,524288.0,0,384315,0,0,0,384315,0,0,0,384315,0,0,0,384315,0,0,0,384315,0,0,0,384315,0,0,0,384315,0,0,0,384315,0,0,0,384315,0,0,0,384315,0,0,0,384315,0,0,0,384315,0,0,0,384315,0,0,0,384315,0,0,0,384315,0,0,0,384315,0,0,0,384315,0,0,0,384315,0,0,0,384315,0,0,0,384315,0,0,0,384315,0,0,0,384315,0,0,0,384315,0,0,0,384315,0,0,0,384315,0,0,0,384315,0,0,0,384315,0,0,0,384315,0,0,0,384315,0,0,0,384315,0,0,0,384315,0,0,0,384315,0,0,0,0,0,0.0,21562002.0,33,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2,0,0,0,2,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,113,0,0,0,0,0,0,0,34,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,4,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,56,0,0,0,32,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,524288.0,0.0,0,44884,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,282195,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,44721,129024,129024,0,0,129024,129024,0,0,129024,129024,0,822,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,165,129024,129024,0,26794,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,885,129024,129024,0,0,129024,129024,0,207197,129024,129024,0,0,129024,129024,0,157,129024,129024,0,47293,129024,129024,0,0,129024,129024,0,178,129024,129024,0,171,129024,129024,0,187,129024,129024,524288.0,0.0,44617,0,0,50883312,46185,0,0,51121109,44762,0,0,50281532,46679,0,0,51642364,44863,0,0,51178424,45597,0,0,51449362,45219,0,0,51055717,48981,0,0,53185811,44472,0,0,50761535,47798,0,0,51616025,45342,0,0,50650187,47731,0,0,52148955,46052,0,0,51522824,46425,0,0,51709355,45969,0,0,51355669,49117,0,0,53354514,44990,0,0,50764688,44443,0,0,50483611,44867,0,0,50537141,47270,0,0,52102964,45009,0,0,51255772,46301,0,0,51323454,44695,0,0,50958058,47088,0,0,52591095,44254,0,0,50611610,45539,0,0,51051350,45528,0,0,50565558,48583,0,0,52588679,46903,0,0,51931951,47730,0,0,52036075,45933,0,0,51211346,48637,0,0,53100915,0.0,65536,65680,144,131216,65536,65536,0,131072,65536,65592,56,131128,65536,65536,0,131072,65646,65538,112,131184,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65568,32,131104,65536,65536,0,131072,65536,65536,0,131072,65536,65539,3,131075,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65537,1,131073,65536,65570,34,131106,65536,65537,1,131073,65591,65537,56,131128,65536,65536,0,131072,65758,65538,224,131296,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65568,32,131104,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65591,65537,56,131128,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131184,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131296,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131128,0,131072,1048061,0,524288,3670016,3663316,224,6476,1048576,33554432.0,33554432.0,0.0,33554432.0,30174510.0,28545521.0,0.0,524288.0,217122,537990,8810,927,0,383482,4195053.0,0.0,2097594.0,2097459.0,1048576,1048576,0,524288,0,524288,7340032,0,0.0,0.0,104.0,8388608.0,29613777.0,2097152.0,0.0,205583,0,1508,383709,0,754.0,4194304.0,0.0,2064387.0,25690112,9437184,0,0,0,0,0,0,13278.0,8242550.0,0.0,8388608.0,2097152.0,4194304.0,9888155,0,0,8666,4128768.0,4128768.0,0.0,1490797.0,0,0,0,0,0,0,5767168,1048576,315504507.0,0.0,1471492425.0,0.0,47.0,0.0,0,0,372800,0.0,0.0,1488423.0,0.0,3670016,524288,0,0,0,2621440,524288,181881441,4194304.0,0.0,0.0,0.0,0.0,1169110.0,0,0,0.0,308.0,0.0,600.0,42569807,24117248,0,0,9437184,11010048,0,3145728,0.0,0.0,0.0,0.0,0.0,0.0,0,1572864,0.0,0.0,0.0,199614.0,524288,524288,0,3670016,7340032,603979776,4718592,0,0.0,0.0,0.0,0.0,0.0,0.0,524288,0,2064384.0,0.0,2031623.0,0.0,0,0,524288,0,0,0,0,33554432,0.0,4194304.0,0.0,18908230.0,0.0,0.0,142.0,4128768.0,674469.0,1697269966.0,17649031032297,17666847854280,17666848094760,17649178658797
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,226933,226933,32768,256,0,0,12,24,13888,0x0,0x7f4abc623f80,264096,159430,512,1367721,1678051,504,56,0,33011,33011,2303587.0,145853.0,221.0,0.0,33140.0,29425.0,139552.0,120724.0,264088,166318,33011,0,33011,0,1056352.0,369295.0,0.0,0.0,0,0,560,0,8192,6131,56,2005,23235,0.0,0.0,0.0,4096.0,29199.0,27689.0,0.0,4096.0,128,512,302,32060,2225,0,0.0,60.0,0.0,4600.0,0,0,0,0,0,1024,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,28724.0,4096.0,0,32737,0,0,0,32737,0,0,0,32737,0,0,0,32737,0,0,0,32737,0,0,0,32737,0,0,0,32737,0,0,0,32737,0,0,0,32737,0,0,0,32737,0,0,0,32737,0,0,0,32737,0,0,0,32737,0,0,0,32737,0,0,0,32737,0,0,0,32737,0,0,0,32737,0,0,0,32737,0,0,0,32737,0,0,0,32737,0,0,0,32737,0,0,0,32737,0,0,0,32737,0,0,0,32737,0,0,0,32737,0,0,0,32737,0,0,0,32737,0,0,0,32737,0,0,0,32737,0,0,0,32737,0,0,0,32737,0,0,0,32737,0,0,0,0,0,0.0,0.0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,312,0,0,0,256,0,0,0,259,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,258,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,4096.0,4096.0,0,75674,0,0,0,75421,0,0,0,77928,0,0,0,84517,0,0,0,78981,0,0,0,74810,0,0,0,79855,0,0,0,86246,0,0,0,84244,0,0,0,81346,0,0,0,77416,0,0,0,84129,0,0,0,79073,0,0,0,79670,0,0,0,81018,0,0,0,89027,0,0,0,79984,0,0,0,86714,0,0,0,76055,0,0,0,79390,0,0,0,83292,0,0,0,80139,0,0,0,76452,0,0,0,87630,0,0,0,645419,0,0,0,79605,0,0,0,73321,0,0,0,84836,0,0,0,80722,0,0,0,121703,0,0,0,79338,0,0,0,95447,0,0,0.0,0.0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4096.0,0,184,184,184,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,222,130,352,352,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,129,129,129,0,128,128,128,222,130,352,352,0,128,128,128,0,128,128,128,0,129,129,129,0,130,130,130,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,55,129,184,184,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,352,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,352,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,184,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,656,0,0,512,0,56,456,0,65536.0,65536.0,65536.0,0.0,0.0,0.0,0.0,0.0,6,518,11514,1055,0,31042,4659.0,0.0,499.0,4160.0,512,0,0,0,4096,4096,512,0,0.0,0.0,104.0,16384.0,0.0,16384.0,4096.0,0,0,1295,31585,0,4662.0,0.0,0.0,31.0,35328,26112,0,0,0,0,0,0,104.0,15240.0,0.0,16384.0,16384.0,0.0,0,0,0,29539,0.0,0.0,0.0,0.0,0,0,0,0,0,0,10752,3584,4615157.0,5714337.0,0.0,8192.0,0.0,0.0,0,0,497,0.0,0.0,0.0,0.0,512,4096,0,0,0,512,512,1635379,0.0,0.0,0.0,0.0,0.0,1311.0,0,0,0.0,8261.0,0.0,120.0,12412,32256,0,0,26112,1024,0,1024,0.0,0.0,0.0,0.0,0.0,0.0,0,1024,0.0,0.0,0.0,42166.0,4096,0,4096,512,512,1671168,8192,0,0.0,0.0,0.0,0.0,0.0,0.0,512,0,0.0,0.0,0.0,0.0,0,0,512,0,0,0,0,32768,8192.0,0.0,0.0,138048.0,0.0,4096.0,8205.0,0.0,3486856.0,0.0,17649184883870,17666852915403,17666852928683,17649185361808
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,226933,226933,4194304,256,0,0,12,24,14336,0x7f4abf6b7380,0x7f4abc623fc0,1351584,1256900,65536,16243203,95034876,392,56,0,168947,168947,16573262.0,15131318.0,23287.0,574886.0,14509566.0,14423227.0,15124742.0,12985351.0,1351576,1264054,168947,0,168947,0,5406304.0,4895797.0,0.0,0.0,0,0,448,0,917504,913914,0,3590,158640,0.0,0.0,0.0,524288.0,14537654.0,14530996.0,2188.0,524288.0,16384,65536,302,168703,2259,0,0.0,165.0,0.0,1048968.0,0,0,0,0,0,131072,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,10788102.0,524288.0,0,168723,0,0,0,168723,0,0,0,168723,0,0,0,168723,0,0,0,168723,0,0,0,168723,0,0,0,168723,0,0,0,168723,0,0,0,168723,0,0,0,168723,0,0,0,168723,0,0,0,168723,0,0,0,168723,0,0,0,168723,0,0,0,168723,0,0,0,168723,0,0,0,168723,0,0,0,168723,0,0,0,168723,0,0,0,168723,0,0,0,168723,0,0,0,168723,0,0,0,168723,0,0,0,168723,0,0,0,168723,0,0,0,168723,0,0,0,168723,0,0,0,168723,0,0,0,168723,0,0,0,168723,0,0,0,168723,0,0,0,168723,0,0,0,0,0,0.0,0.0,65539,0,18942,0,65536,0,21456,0,65536,0,15408,0,65536,0,22220,0,65536,0,25494,0,65536,0,29236,0,65536,0,31951,0,65536,0,24825,0,65536,0,10731,0,65536,0,20313,0,65536,0,16727,0,65536,0,16355,0,65536,0,15018,0,65536,0,18786,0,65537,0,26149,0,65536,0,23625,0,65592,0,17195,0,65536,0,23665,0,65598,0,15576,0,65536,0,22006,0,65537,0,21735,0,65536,0,17416,0,65536,0,25476,0,65540,0,20629,0,65540,0,29114,0,65536,0,19273,0,65536,0,25335,0,65597,0,20910,0,65536,0,30522,0,65536,0,14406,0,65536,0,19361,0,65536,0,27495,0,524288.0,524288.0,0,37891799,0,0,0,46600994,0,0,0,44686852,0,0,0,42572501,0,0,0,46390249,0,0,0,46161249,0,0,0,47660325,0,0,0,45032346,0,0,0,38796285,0,0,0,39091777,0,0,0,40344304,0,0,0,45013942,0,0,0,40193233,0,0,0,46891375,0,0,0,44225894,0,0,0,45451208,0,0,0,43705956,0,0,0,41215962,0,0,0,40206859,0,0,0,42824635,0,0,0,42227431,0,0,0,44048212,0,0,0,45799955,0,0,0,37544774,0,0,0,38032032,0,0,0,41645303,0,0,0,37252061,0,0,0,41245446,0,0,0,42957000,0,0,0,45187462,0,0,0,42428989,0,0,0,45002382,0,0,0.0,0.0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,524288.0,0,32824,32824,32824,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32769,32769,32769,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32769,32769,32769,0,32828,32828,32828,0,32770,32770,32770,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,166,32770,32936,32936,222,32770,32992,32992,0,32768,32768,32768,0,32768,32768,32768,0,32828,32828,32828,0,32769,32769,32769,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32936,0,0,32992,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,930096,0,0,65536,63800,56,1680,0,8388608.0,8388608.0,8388608.0,0.0,0.0,0.0,0.0,0.0,159074,169848,10276,2613,0,161990,1049150.0,0.0,388.0,1048762.0,65536,0,0,0,524288,524288,131072,0,0.0,0.0,104.0,2097152.0,0.0,2097152.0,524288.0,43495,0,2922,162446,0,1049148.0,0.0,0.0,31.0,4063232,2883584,0,0,0,0,0,0,6607.0,2027582.0,0.0,2097152.0,2097152.0,0.0,1237610,0,0,13584,0.0,0.0,0.0,0.0,262144,0,0,0,0,0,1507328,458752,981844610.0,2256023952.0,0.0,2097152.0,85.0,0.0,0,0,148354,0.0,0.0,0.0,0.0,65536,524288,0,0,0,65536,65536,48802446,0.0,0.0,0.0,0.0,0.0,19665.0,0,0,0.0,2097345.0,0.0,372.0,21657885,3735552,0,0,2883584,196608,0,131072,0.0,0.0,0.0,0.0,0.0,0.0,0,131072,0.0,0.0,496855.0,1492754.0,524288,0,524288,65536,131072,184549376,917504,0,0.0,0.0,0.0,0.0,0.0,0.0,65536,0,0.0,0.0,983046.0,0.0,0,0,65536,0,0,0,0,4194304,2097152.0,0.0,0.0,12334739.0,0.0,524288.0,2097285.0,0.0,1435141765.0,0.0,17649186460650,17666852994123,17666853086443,17649187248990
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/prev_analysis/1.csv
index 0c1d5f64f0..99a2682d55 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,3359042.0,3359042.0,3359042.0,7.842681923663712
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,1726081.0,1726081.0,1726081.0,4.030049120397834
 "void benchmark_func<double, 256, 8u, 512u>(double, double*) [clone .kd]",1,1715842.0,1715842.0,1715842.0,4.006143131661643
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/prev_analysis/1001.csv
index f475f954a6..fb5988001a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,494.8622754491018,Instr per wave
 VMEM,7.958083832335329,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,0.0,Instr per wave
 SALU,24.520958083832337,Instr per wave
 SMEM,1.8023952095808384,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/prev_analysis/101.csv
index 35b05b5af7..14660e5bc7 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx90a
 mi200
 56
 1638.4
-SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/prev_analysis/1202.csv
index 8ad5b54687..bd030ea836 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,18737.51036862128,1852.4745407104492,258259.13153076172,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/prev_analysis/1901.csv
index 69a18b88b7..3b7c5381a4 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,2.0,smem_
 VALU,495.0,valu_
 MFMA,0.0,mfma_
 VMEM,8.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,10.0,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,67894.0,wavefronts_
 Workgroups,16973.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,128.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,0.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,44.0,hbm_rd_
 HBM Wr,0.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,70.0,vl1_coales_
 VL1 Stall,1.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,25.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/prev_analysis/201.csv
index 92f42aa9e4..671744f71b 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,57.88407767430634,Pct,100,57.88407767430634
 MFMA Util,0.0,Pct,100,0.0
 VALU Active Threads/Wave,64.0,Threads,64,100.0
 IPC - Issue,1.0,Instr/cycle,5,20.0
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99253474950464,Pct,100,99.99253474950464
 Instr Cache BW,1672.5803170527652,Gb/s,6092.8,27.45175152725783
 Scalar L1D Cache Hit Rate,99.34855886066374,Pct,100,99.34855886066374
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/prev_analysis/602.csv
index 7040dc8adf..d29bfce20d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,13315117.526946107,0,388662889,Simd
 Insufficient SIMD VGPRs,0.0,0,0,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/prev_analysis/701.csv
index 12250d77c0..db0925a109 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/sysinfo.csv
index 7fc973449d..b9c023228f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-no_roof_dev0,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:47:26 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+no_roof_dev0,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:47:26 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/timestamps.csv
index 943d0f9cad..94f455516d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev0/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,227876,227876,33554432,256,0,0,4,32,4160,0x0,0x7fb18ae04280,17666847829849,17666847854280,17666848094760,17666848207280
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,227876,227876,32768,256,0,0,12,24,13888,0x0,0x7fb18ae23f80,17666852899852,17666852915403,17666852928683,17666852945621
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,227876,227876,4194304,256,0,0,12,24,14336,0x7fb18dee7380,0x7fb18ae23fc0,17666852950601,17666852994123,17666853086443,17666853088557
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/SQ_IFETCH_LEVEL.csv
index b39969b13a..af0a841c60 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/SQ_IFETCH_LEVEL.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,932515,932520,33554432,256,0,0,8,32,6464,0x0,0x7f2944204180,508265,508265,524288,6291456,792565,101477192,12076556929710543,12076557176241617,12076557176568016,12076557176676059
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,932515,932520,32768,256,0,0,24,24,12480,0x0,0x7f2944235100,28363,28363,512,8192,8635,1107692,12076557191205876,12076557191512278,12076557191518678,12076557191528146
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,932515,932520,4194304,256,0,0,24,24,12928,0x7f2a4fd72900,0x7f2944235140,216051,216051,65536,917504,134724,17278016,12076557191585613,12076557191818037,12076557191949396,12076557191953567
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/SQ_INST_LEVEL_LDS.csv
index 8dc1dcb985..9d91fdf51e 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/SQ_INST_LEVEL_LDS.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,934310,934315,33554432,256,0,0,8,32,6464,0x0,0x7fe0b2804180,0,0,0,12076583103277409,12076583350784357,12076583351105636,12076583351181440
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,934310,934315,32768,256,0,0,24,24,12480,0x0,0x7fe0b2835100,0,0,0,12076583365891623,12076583366248076,12076583366253996,12076583366293771
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,934310,934315,4194304,256,0,0,24,24,12928,0x7fe1be40f900,0x7fe0b2835140,0,0,0,12076583366334607,12076583366645195,12076583366779115,12076583366792028
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/SQ_INST_LEVEL_SMEM.csv
index 00c6c5143f..4c9c764fe6 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/SQ_INST_LEVEL_SMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,933932,933937,33554432,256,0,0,8,32,6464,0x0,0x7f50c9e04180,4194304,3026778,387708664,12076580593303992,12076580835081657,12076580835403256,12076580835511998
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,933932,933937,32768,256,0,0,24,24,12480,0x0,0x7f50c9e35100,512,22622,2882472,12076580850266293,12076580850562316,12076580850568876,12076580850574296
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,933932,933937,4194304,256,0,0,24,24,12928,0x7f51d59df900,0x7f50c9e35140,65536,194834,24923496,12076580850637594,12076580850851595,12076580850985994,12076580850989989
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/SQ_INST_LEVEL_VMEM.csv
index 7a1dc5ff64..b8702fe2d9 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/SQ_INST_LEVEL_VMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,934122,934127,33554432,256,0,0,8,32,6464,0x0,0x7fca5da04180,1048576,11108396,1421457788,12076581840838508,12076582090748091,12076582091071450,12076582091162892
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,934122,934127,32768,256,0,0,24,24,12480,0x0,0x7fca5da35100,4096,116231,14895344,12076582105471919,12076582105773368,12076582105780248,12076582105792615
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,934122,934127,4194304,256,0,0,24,24,12928,0x7fcb6970e900,0x7fca5da35140,524288,12683711,1623499964,12076582105848519,12076582106075607,12076582106205207,12076582106209591
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/SQ_LEVEL_WAVES.csv
index d0c3ff6cda..86bf2263ab 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/SQ_LEVEL_WAVES.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,934498,934503,33554432,256,0,0,8,32,6464,0x0,0x7fde5d004180,500797,500797,17231,4006384,524288,373690390,3804362,0,1509592576,12076584395757149,12076584640371641,12076584640694200,12076584640807462
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,934498,934503,32768,256,0,0,24,24,12480,0x0,0x7fde5d035100,28136,28136,20883,225096,512,1180922,79224,0,4737808,12076584656094107,12076584656416631,12076584656423671,12076584656431845
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,934498,934503,4194304,256,0,0,24,24,12928,0x7fdf68d5f900,0x7fde5d035140,222388,222388,21727,1779112,65536,136066187,1612700,0,546074316,12076584656495484,12076584656745750,12076584656882070,12076584656885379
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/pmc_dispatch_info.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/pmc_perf.csv
index 899b730fa5..f11e408db4 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBuffer.kd,0,0,0,933249,933254,33554432,256,0,0,8,32,6464,0x0,0x7fe578404180,1048576,0,1048576,9437184,0,4194304,1048576,0,504081,504081,57873195,55391845,130,11936125,54659877,54580618,55360991,54184231,4032648,3842670,504081,0,504081,0,16130592,15262383,0,0,0,0,0,17532100,1048576,0,503504,0,0,0,503504,0,0,0,503504,0,0,0,503504,0,0,0,503504,0,0,0,503504,0,0,0,503504,0,0,0,503504,0,0,0,503504,0,0,0,503504,0,0,0,503504,0,0,0,503504,0,0,0,503504,0,0,0,503504,0,0,0,503504,0,0,0,503504,0,0,0,503504,0,0,0,503504,0,0,0,503504,0,0,0,503504,0,0,0,503504,0,0,0,503504,0,0,0,503504,0,0,0,503504,0,0,0,503504,0,0,0,503504,0,0,0,503504,0,0,0,503504,0,0,0,503504,0,0,0,503504,0,0,0,503504,0,0,0,503504,0,0,0,37760647,48,0,0,0,5,0,0,0,2750,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2441,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,56,0,0,0,48,0,0,0,0,0,0,0,7,0,0,0,2742,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,48,0,0,0,0,0,0,0,2743,0,0,0,0,0,0,0,1048576,0,0,2979759,131076,131076,0,1455,131072,131072,0,542081,131072,131072,0,0,131072,131072,0,3322295,131080,131080,0,0,131072,131072,0,0,131072,131072,0,1764,131076,131076,0,1488,131076,131076,0,0,131072,131072,0,0,131080,131080,0,0,131072,131072,0,0,131072,131072,0,0,131076,131076,0,268,131072,131072,0,0,131080,131080,0,0,131076,131076,0,783,131072,131072,0,0,131080,131080,0,0,131076,131076,0,3231349,131078,131078,0,0,131072,131072,0,0,131072,131072,0,272,131072,131072,0,3198327,131072,131072,0,736,131072,131072,0,0,131076,131076,0,0,131072,131072,0,15628,131080,131080,0,0,131072,131072,0,0,131076,131076,0,0,131076,131076,1048576,0,1545,0,0,17357969,1211,0,0,17412417,1397,0,0,17253905,49476,0,0,30310579,1469,0,0,17438128,1029,0,0,17336668,1954,0,0,18089694,49992,0,0,31148305,1687,0,0,17234975,848,0,0,17155817,1762,0,0,17062018,1080,0,0,16819659,1990,0,0,17620928,1208,0,0,17374989,1087,0,0,17834696,1819,0,0,18599508,1662,0,0,16984254,1439,0,0,16951853,1403,0,0,17213859,41395,0,0,28789180,1595,0,0,17424412,1062,0,0,17413506,1552,0,0,17973775,1855,0,0,18516255,1618,0,0,17052614,824,0,0,16852542,1636,0,0,17078055,1178,0,0,16788544,1412,0,0,17674180,976,0,0,17640764,1713,0,0,18072517,39696,0,0,30494144,1048576,131072,131072,0,262144,131260,131124,240,262384,131072,131072,0,262144,131072,133774,2702,264846,131119,131074,49,262193,131072,131072,0,262144,131072,131072,0,262144,131072,133631,2559,264703,131072,131073,1,262145,131072,131072,0,262144,131072,131120,48,262192,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131092,20,262164,131072,131072,0,262144,131213,131075,144,262288,131072,131072,0,262144,131072,133578,2506,264650,131072,131072,0,262144,131072,131072,0,262144,131072,131075,3,262147,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131119,131121,96,262240,131072,131072,0,262144,131072,133675,2603,264747,262144,0,262144,262336,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262288,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,0,0,3145728,524288,32505856,368735634,218573165,117656613,481334,0,0,0,1048576,52519152,52281249,1048576,1048576,131072,524288,741,504180,4307,0,96,10679,0,8388944,32505856,4028456,3827488,57223232,11534336,0,0,14155776,67108864,67108864,0,67108864,54445743,54106652,0,1048576,240704,764992,11581,1989,0,499311,8399960,0,4194727,4205233,13631488,0,3670016,1048576,1048576,0,4194304,9437184,0,0,360,33554432,53776308,4194304,0,0,2382,499468,0,11006,8388608,0,4194350,905969664,6291456,0,0,0,524288,524288,0,15330,16608717,0,16777216,4194304,4194304,0,0,0,16220,4194360,4194360,0,226870,0,0,0,33554432,0,0,0,0,626793430,0,2759504132,0,0,0,0,0,479173,0,0,219154,0,0,8388608,336,144,0,0,0,480,8388608,0,0,0,0,283864,0,0,0,10631,0,21244,0,6291456,6289462,96,2199,1833721,0,0,0,0,0,0,0,0,0,3145728,0,0,0,149283,4194304,4189855,144,4305,2097152,524288,1572864,0,0,0,0,0,0,524288,0,4128845,65535,4063244,0,0,8388608,0,42146884,0,1048576,10919,4194388,13446234,613403664,12076559019729022,12076585535799471,12076585536125708,12076559265760882
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,933249,933254,32768,256,0,0,24,24,12480,0x0,0x7fe578435100,0,4096,4096,512,0,512,4096,0,28582,28582,1457627,573710,226,131002,95097,69822,565644,545236,228656,82995,28582,0,28582,0,914624,195391,0,0,0,0,0,57895,4096,0,27950,0,0,0,27950,0,0,0,27950,0,0,0,27950,0,0,0,27950,0,0,0,27950,0,0,0,27950,0,0,0,27950,0,0,0,27950,0,0,0,27950,0,0,0,27950,0,0,0,27950,0,0,0,27950,0,0,0,27950,0,0,0,27950,0,0,0,27950,0,0,0,27950,0,0,0,27950,0,0,0,27950,0,0,0,27950,0,0,0,27950,0,0,0,27950,0,0,0,27950,0,0,0,27950,0,0,0,27950,0,0,0,27950,0,0,0,27950,0,0,0,27950,0,0,0,27950,0,0,0,27950,0,0,0,27950,0,0,0,27950,0,0,0,0,304,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,382,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,304,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,4096,4096,0,149826,0,0,0,110383,0,0,0,87061,0,0,0,85864,0,0,0,105934,0,0,0,80598,0,0,0,71934,0,0,0,98389,0,0,0,97849,0,0,0,159383,0,0,0,94927,0,0,0,89603,0,0,0,101044,0,0,0,132512,0,0,0,70605,0,0,0,130927,0,0,0,97887,0,0,0,87253,0,0,0,69510,0,0,0,88255,0,0,0,78873,0,0,0,125450,0,0,0,84239,0,0,0,96186,0,0,0,123476,0,0,0,71197,0,0,0,103079,0,0,0,78753,0,0,0,177628,0,0,0,95752,0,0,0,105722,0,0,0,76772,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4096,0,256,256,256,0,304,304,304,0,256,256,256,0,256,256,256,0,257,257,257,0,256,256,256,0,256,256,256,0,256,256,256,0,257,257,257,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,188,260,448,448,0,377,377,377,0,256,256,256,0,256,256,256,188,260,448,448,0,256,256,256,0,256,256,256,0,256,256,256,0,257,257,257,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,47,305,352,352,47,257,304,304,0,256,256,256,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,304,0,0,256,0,0,0,0,512,512,35328,1075962,999833,39777,12079,0,0,0,4096,115212,112524,4096,4096,128,512,606,27917,4338,0,48,219,0,8624,36352,215768,68232,956912,26624,0,0,30208,65536,65536,65536,0,0,0,0,0,116,628,11591,1997,0,22739,8843,0,470,8373,1024,0,1024,4096,0,4096,512,512,0,0,360,16384,0,16384,0,0,2713,25078,0,8891,0,0,31,1933312,8192,0,0,0,512,512,0,120,15064,0,16384,16384,0,0,0,0,20390,0,0,0,0,0,0,0,32768,0,0,0,0,12358795,17114908,0,8192,0,0,0,0,697,0,0,0,0,0,1024,432,48,0,0,0,480,0,0,0,0,0,2816,0,0,0,8422,0,440,0,8192,6559,48,1585,1128,0,0,0,0,0,0,0,0,0,2560,0,0,0,50747,512,0,48,464,0,512,0,0,0,0,0,0,0,512,0,0,0,0,0,8192,0,0,433565,0,4096,8420,0,3222527,0,12076559280623137,12076585552066419,12076585552073299,12076559281617657
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,933249,933254,4194304,256,0,0,24,24,12928,0x7fe684124900,0x7fe578435140,0,524288,524288,65536,0,65536,524288,0,221100,221100,24409877,23161654,31316,8830279,22007895,21825789,23145968,20979800,1768800,1611339,221100,0,221100,0,7075200,6334945,0,0,0,0,0,19978766,524288,0,212356,0,0,0,212356,0,0,0,212356,0,0,0,212356,0,0,0,212356,0,0,0,212356,0,0,0,212356,0,0,0,212356,0,0,0,212356,0,0,0,212356,0,0,0,212356,0,0,0,212356,0,0,0,212356,0,0,0,212356,0,0,0,212356,0,0,0,212356,0,0,0,212356,0,0,0,212356,0,0,0,212356,0,0,0,212356,0,0,0,212356,0,0,0,212356,0,0,0,212356,0,0,0,212356,0,0,0,212356,0,0,0,212356,0,0,0,212356,0,0,0,212356,0,0,0,212356,0,0,0,212356,0,0,0,212356,0,0,0,212356,0,0,0,0,65584,0,4066,0,65536,0,8873,0,67793,0,58309,0,65536,0,1528,0,65536,0,3346,0,65536,0,8636,0,65536,0,220,0,65536,0,5148,0,65536,0,0,0,65537,0,906,0,65536,0,341,0,65536,0,2560,0,65536,0,22,0,65536,0,0,0,65772,0,17651,0,65536,0,2719,0,65536,0,4134,0,65536,0,7715,0,68005,0,73135,0,65536,0,138,0,65536,0,7583,0,65537,0,4791,0,65536,0,3287,0,65536,0,1300,0,65536,0,87,0,65536,0,732,0,65536,0,1204,0,65536,0,0,0,65584,0,0,0,65536,0,0,0,65540,0,191,0,65536,0,0,0,524288,524288,0,53144077,0,0,0,37791591,0,0,0,38335785,0,0,0,36907051,0,0,0,40326184,0,0,0,40738633,0,0,0,36352586,0,0,0,40716555,0,0,0,35264755,0,0,0,37093836,0,0,0,34157501,0,0,0,40305633,0,0,0,36977401,0,0,0,35607633,0,0,0,33429528,0,0,0,38309034,0,0,0,32430838,0,0,0,33974096,0,0,0,37825214,0,0,0,38548269,0,0,0,34235595,0,0,0,38779275,0,0,0,32732303,0,0,0,35696987,0,0,0,44554198,0,0,0,41020246,0,0,0,35478884,0,0,0,38005494,0,0,0,43366407,0,0,0,43836062,0,0,0,31704228,0,0,0,37180239,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,524288,0,65536,65536,65536,0,65584,65584,65584,188,65540,65728,65728,0,67966,67966,67966,0,65537,65537,65537,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65537,65537,65537,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65657,65657,65657,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,68260,68260,68260,0,65536,65536,65536,0,65536,65536,65536,0,65537,65537,65537,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,47,65585,65632,65632,188,65540,65728,65728,0,65536,65536,65536,65536,0,0,65536,0,0,65728,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65728,0,0,65536,0,0,0,0,65536,65536,4128768,122811791,46365117,72186834,206058,0,0,0,524288,22009108,21995270,524288,524288,16384,65536,765,223879,4282,0,48,4343,0,2097536,4259840,1736184,1569989,23287730,3014656,0,0,3473408,8388608,8388608,8388608,0,0,0,0,0,200069,220913,11891,2220,0,212796,2100271,0,423,2099848,131072,0,131072,524288,0,524288,65536,65536,0,0,360,2097152,0,2097152,35687,0,2372,213266,0,2099420,0,0,31,222298112,917504,0,0,0,65536,65536,0,7591,2019306,0,2097152,2097152,0,789819,792560,0,20835,0,0,0,0,0,0,0,4194304,0,0,0,0,984880077,1575932887,0,2097152,0,0,0,0,196427,0,0,0,0,0,131072,384,48,0,0,0,432,0,0,0,0,0,6008,0,0,0,2098847,0,3372,0,917504,914777,48,7385,216346,0,0,0,0,0,0,0,0,0,327680,0,0,584153,637255,65536,64048,48,1440,0,65536,0,0,0,0,0,0,0,65536,0,0,0,1966093,0,2097152,0,0,14542316,0,524288,2101759,0,888993577,0,12076559282249452,12076585552150098,12076585552288977,12076559283505098
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/prev_analysis/1.csv
index d600fd9266..12ecd6562e 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,6055800.0,6055800.0,6055800.0,9.15474969194293
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4526050.0,4526050.0,4526050.0,6.842176895409079
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 256u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,3053900.0,3053900.0,3053900.0,4.616679891050648
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/prev_analysis/1001.csv
index ca08330db0..0e3bf5267e 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,46.862275449101794,Instr per wave
 SMEM,1.8083832335329342,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/prev_analysis/101.csv
index 7c6ba75d64..d861d44f34 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx908
 mi100
 48
 1228.8
-SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/prev_analysis/1202.csv
index 1cef242301..9e3ebe3097 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,33643.322656414464,2813.2296295166016,547894.4779052734,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/prev_analysis/1901.csv
index f4de82f2b1..a419d97b9a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,2.0,smem_
 VALU,735.0,valu_
 MFMA,,mfma_
 VMEM,8.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,22.0,br_
 VGPR,24.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,67894.0,wavefronts_
 Workgroups,16973.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,163.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,0.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,44.0,hbm_rd_
 HBM Wr,0.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,70.0,vl1_coales_
 VL1 Stall,30.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,34.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/prev_analysis/2001.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/prev_analysis/201.csv
index 72810256e4..fd7c67df56 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,59.425843642273406,Pct,100,59.425843642273406
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,63.96708782410844,Threads,64,99.94857472516944
 IPC - Issue,0.8437193447296479,Instr/cycle,5,16.87438689459296
-LDS BW,0.0,Gb/sec,23070.72,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,23070.72,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99342608416744,Pct,100,99.99342608416744
 Instr Cache BW,1406.748903821575,Gb/s,4614.144,30.4877546912618
 Scalar L1D Cache Hit Rate,99.35620448523463,Pct,100,99.35620448523463
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/prev_analysis/602.csv
index ad230ac597..a995a5e649 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,64104.071856287424,0,789819,Simd
 Insufficient SIMD VGPRs,628273.6706586826,0,42754588,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/prev_analysis/701.csv
index d3f1bff5a3..1071413faa 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,23.976047904191617,8,36,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/sysinfo.csv
index ae10afa978..141a41ade1 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-no_roof_dev01p3,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 11:35:31 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+no_roof_dev01p3,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 11:35:31 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/timestamps.csv
index f2541af5e2..9b358b8a03 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev01p3/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,934549,934554,33554432,256,0,0,8,32,6464,0x0,0x7f43d3a04180,12076585535757218,12076585535799471,12076585536125708,12076585536237040
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,934549,934554,32768,256,0,0,24,24,12480,0x0,0x7f43d3a35100,12076585551962501,12076585552066419,12076585552073299,12076585552079840
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,934549,934554,4194304,256,0,0,24,24,12928,0x7f4503d10900,0x7f43d3a35140,12076585552136776,12076585552150098,12076585552288977,12076585552292365
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/SQ_IFETCH_LEVEL.csv
index 03a01bfe61..4a2f55ae3e 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/SQ_IFETCH_LEVEL.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,926968,926973,33554432,256,0,0,8,32,6464,0x0,0x7f3fb4e04180,507433,507433,524288,6291456,795333,101905788,12076439414027292,12076439657819397,12076439658144676,12076439658284951
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,926968,926973,32768,256,0,0,24,24,12480,0x0,0x7f3fb4e35100,28241,28241,512,8192,8509,1094060,12076439672958666,12076439673294010,12076439673300410,12076439673315099
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,926968,926973,4194304,256,0,0,24,24,12928,0x7f40c09c1900,0x7f3fb4e35140,225971,225971,65536,917504,140404,17987496,12076439673371353,12076439673647928,12076439673785848,12076439673790573
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/SQ_INST_LEVEL_LDS.csv
index c28de6c490..be41907a56 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/SQ_INST_LEVEL_LDS.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,928763,928768,33554432,256,0,0,8,32,6464,0x0,0x7f591da04180,0,0,0,12076465923458877,12076466170011840,12076466170336959,12076466170440112
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,928763,928768,32768,256,0,0,24,24,12480,0x0,0x7f591da35100,0,0,0,12076466184947237,12076466185251105,12076466185257345,12076466185273424
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,928763,928768,4194304,256,0,0,24,24,12928,0x7f5a295f1900,0x7f591da35140,0,0,0,12076466185326612,12076466185549503,12076466185684223,12076466185688315
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/SQ_INST_LEVEL_SMEM.csv
index d3934e2c66..6b9c27d91c 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/SQ_INST_LEVEL_SMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,928385,928390,33554432,256,0,0,8,32,6464,0x0,0x7fd00fa04180,4194304,3182000,406926560,12076463402711409,12076463645392376,12076463645714295,12076463645823988
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,928385,928390,32768,256,0,0,24,24,12480,0x0,0x7fd00fa35100,512,23142,2974448,12076463660292571,12076463660588566,12076463660594646,12076463660600033
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,928385,928390,4194304,256,0,0,24,24,12928,0x7fd13fc54900,0x7fd00fa35140,65536,186772,23959520,12076463660666507,12076463660874165,12076463661008245,12076463661012490
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/SQ_INST_LEVEL_VMEM.csv
index 35476addb0..52203fb419 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/SQ_INST_LEVEL_VMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,928575,928580,33554432,256,0,0,8,32,6464,0x0,0x7f4a0e404180,1048576,11157117,1428297752,12076464660275752,12076464906261378,12076464906585377,12076464906693759
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,928575,928580,32768,256,0,0,24,24,12480,0x0,0x7f4a0e435100,4096,144675,18530584,12076464921080300,12076464921392523,12076464921399883,12076464921408150
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,928575,928580,4194304,256,0,0,24,24,12928,0x7f4b1a12a900,0x7f4a0e435140,524288,11893137,1522338348,12076464921469154,12076464921684682,12076464921818602,12076464921822751
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/SQ_LEVEL_WAVES.csv
index 2260085020..8acca20698 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/SQ_LEVEL_WAVES.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,928953,928958,33554432,256,0,0,8,32,6464,0x0,0x7f1658a04180,500940,500940,16904,4007528,524288,373798857,3810180,0,1509957092,12076467186971133,12076467431680597,12076467432003316,12076467432113719
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,928953,928958,32768,256,0,0,24,24,12480,0x0,0x7f1658a35100,27215,27215,19721,217728,512,1100258,72824,0,4415100,12076467446646050,12076467446979306,12076467446985226,12076467446994569
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,928953,928958,4194304,256,0,0,24,24,12928,0x7f1764577900,0x7f1658a35140,209180,209180,22063,1673448,65536,154881828,1507503,0,621346880,12076467447062826,12076467447311945,12076467447439145,12076467447443564
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/pmc_dispatch_info.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/pmc_perf.csv
index 7edbfc56b2..cf7367f499 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBuffer.kd,0,0,0,927702,927707,33554432,256,0,0,8,32,6464,0x0,0x7fc246e04180,1048576,0,1048576,9437184,0,4194304,1048576,0,504736,504736,57938759,55509579,176,12047726,54734322,54644326,55467939,54299582,4037888,3847042,504736,0,504736,0,16151552,15283428,0,0,0,0,0,17625750,1048576,0,507091,0,0,0,507091,0,0,0,507091,0,0,0,507091,0,0,0,507091,0,0,0,507091,0,0,0,507091,0,0,0,507091,0,0,0,507091,0,0,0,507091,0,0,0,507091,0,0,0,507091,0,0,0,507091,0,0,0,507091,0,0,0,507091,0,0,0,507091,0,0,0,507091,0,0,0,507091,0,0,0,507091,0,0,0,507091,0,0,0,507091,0,0,0,507091,0,0,0,507091,0,0,0,507091,0,0,0,507091,0,0,0,507091,0,0,0,507091,0,0,0,507091,0,0,0,507091,0,0,0,507091,0,0,0,507091,0,0,0,507091,0,0,0,37629113,1,0,0,0,52,0,0,0,0,0,0,0,20,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2663,0,0,0,0,0,0,0,0,0,0,0,3,0,0,0,2702,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,3,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,1,0,0,0,0,0,0,0,2804,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2688,0,0,0,1048576,0,0,3570637,131076,131076,0,22445,131072,131072,0,0,131072,131072,0,0,131076,131076,0,0,131072,131072,0,0,131076,131076,0,0,131076,131076,0,0,131076,131076,0,0,131072,131072,0,0,131076,131076,0,1157,131076,131076,0,0,131072,131072,0,3004082,131072,131072,0,0,131072,131072,0,0,131072,131072,0,0,131072,131072,0,2917922,131072,131072,0,783,131072,131072,0,0,131072,131072,0,259,131072,131072,0,0,131072,131072,0,0,131076,131076,0,6173,131072,131072,0,0,131076,131076,0,1538,131072,131072,0,0,131072,131072,0,0,131072,131072,0,0,131076,131076,0,3170227,131076,131076,0,0,131072,131072,0,0,131072,131072,0,0,131072,131072,1048576,0,1102,0,0,16970614,1613,0,0,17028584,1555,0,0,17623495,46834,0,0,30403888,853,0,0,17206288,1118,0,0,17168305,1640,0,0,18275002,48536,0,0,31125394,1107,0,0,17076927,1058,0,0,17077027,1288,0,0,17197455,1216,0,0,16804339,1669,0,0,17394346,1003,0,0,17165430,783,0,0,18190758,1388,0,0,18523565,1623,0,0,16767095,1015,0,0,16780925,1056,0,0,17317147,41708,0,0,28910950,918,0,0,17107178,1707,0,0,17286498,904,0,0,18244511,1616,0,0,18484255,774,0,0,16450729,1005,0,0,16689271,1048,0,0,17102726,899,0,0,16608666,932,0,0,16950060,1119,0,0,17243893,909,0,0,18171352,46857,0,0,31094351,1048576,131072,131073,1,262145,131260,131076,192,262336,131072,131073,1,262145,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131121,49,262193,131072,131072,0,262144,131072,133616,2544,264688,131072,131072,0,262144,131072,133630,2558,264702,131072,131072,0,262144,131072,131072,0,262144,131072,131124,52,262196,131213,133738,2807,264951,131072,131072,0,262144,131072,131072,0,262144,131119,131074,49,262193,131072,131072,0,262144,131072,131072,0,262144,131072,133729,2657,264801,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131094,22,262166,131119,131073,48,262192,131072,131072,0,262144,131072,131120,48,262192,131072,131072,0,262144,262144,0,262144,262336,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262288,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,0,0,3145728,524288,32505856,368876180,218141219,118229105,475443,0,0,0,1048576,52387390,52183632,1048576,1048576,131072,524288,685,497946,4193,0,96,10616,0,8388944,32505856,4054488,3852590,57493792,11534336,0,0,14155776,67108864,67108864,0,67108864,54396099,54002868,0,1048576,237956,762244,10979,1983,0,502818,8399865,0,4194727,4205138,13631488,0,3670016,1048576,1048576,0,4194304,9437184,0,0,360,33554432,53560983,4194304,0,0,2528,501081,0,11061,8388608,0,4194381,905969664,6291456,0,0,0,524288,524288,0,15327,16608761,0,16777216,4194304,4194304,0,0,0,16466,4194364,4194364,0,216244,0,0,0,33554432,0,0,0,0,641208263,0,2812113953,0,0,0,0,0,473828,0,0,214769,0,0,8388608,336,144,0,0,0,480,8388608,0,0,0,0,385070,0,0,0,10603,0,21188,0,6291456,6289436,96,2222,1842473,0,0,0,0,0,0,0,0,0,3145728,0,0,0,149857,4194304,4189862,144,4298,2097152,524288,1572864,0,0,0,0,0,0,524288,0,4128866,65532,4063247,0,0,8388608,0,42441260,0,1048576,10584,4194352,12794067,606914362,12076441547383013,12076468330694593,12076468331021790,12076441789424240
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,927702,927707,32768,256,0,0,24,24,12480,0x0,0x7fc246e35100,0,4096,4096,512,0,512,4096,0,28309,28309,1569842,623978,219,129664,93167,75758,615844,595380,226472,90477,28309,0,28309,0,905888,198852,0,0,0,0,0,62634,4096,0,27288,0,0,0,27288,0,0,0,27288,0,0,0,27288,0,0,0,27288,0,0,0,27288,0,0,0,27288,0,0,0,27288,0,0,0,27288,0,0,0,27288,0,0,0,27288,0,0,0,27288,0,0,0,27288,0,0,0,27288,0,0,0,27288,0,0,0,27288,0,0,0,27288,0,0,0,27288,0,0,0,27288,0,0,0,27288,0,0,0,27288,0,0,0,27288,0,0,0,27288,0,0,0,27288,0,0,0,27288,0,0,0,27288,0,0,0,27288,0,0,0,27288,0,0,0,27288,0,0,0,27288,0,0,0,27288,0,0,0,27288,0,0,0,0,257,0,0,0,304,0,0,0,256,0,0,0,376,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,257,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,4096,4096,0,119217,0,0,0,101401,0,0,0,87807,0,0,0,100330,0,0,0,87985,0,0,0,118258,0,0,0,73414,0,0,0,85085,0,0,0,101470,0,0,0,83748,0,0,0,81459,0,0,0,75206,0,0,0,89826,0,0,0,84859,0,0,0,98815,0,0,0,101662,0,0,0,81363,0,0,0,82238,0,0,0,97074,0,0,0,121336,0,0,0,78158,0,0,0,130036,0,0,0,182251,0,0,0,95545,0,0,0,136227,0,0,0,101348,0,0,0,77997,0,0,0,86539,0,0,0,131555,0,0,0,93744,0,0,0,75751,0,0,0,79502,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4096,0,257,257,257,0,256,256,256,0,257,257,257,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,305,305,305,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,188,260,448,448,0,256,256,256,0,304,304,304,0,256,256,256,188,260,448,448,0,256,256,256,0,257,257,257,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,376,376,376,47,257,304,304,0,256,256,256,47,257,304,304,0,256,256,256,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,304,0,0,256,0,0,0,0,512,512,35328,1132023,1076824,18847,11826,0,0,0,4096,68051,65057,4096,4096,128,512,597,27986,4356,0,48,172,0,8624,36352,220232,77654,1076183,26624,0,0,30208,65536,65536,65536,0,0,0,0,0,116,628,11140,2042,0,23439,8891,0,470,8421,1024,0,1024,4096,0,4096,512,512,0,0,360,16384,0,16384,0,0,2527,25918,0,8891,0,0,31,1933312,8192,0,0,0,512,512,0,120,15064,0,16384,16384,0,0,0,0,19538,0,0,0,0,0,0,0,32768,0,0,0,0,11458503,15325557,0,8192,0,0,0,0,696,0,0,0,0,0,1024,432,48,0,0,0,480,0,0,0,0,0,3298,0,0,0,8421,0,438,0,8192,6563,48,1581,1092,0,0,0,0,0,0,0,0,0,2560,0,0,0,49911,512,0,48,464,0,512,0,0,0,0,0,0,0,512,0,0,0,0,0,8192,0,0,438791,0,4096,8421,0,3413724,0,12076441804469896,12076468346293873,12076468346300433,12076441805476980
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,927702,927707,4194304,256,0,0,24,24,12928,0x7fc376e63900,0x7fc246e35140,0,524288,524288,65536,0,65536,524288,0,216215,216215,23974397,22766983,31753,10728916,21893222,21750532,22753620,20587065,1729720,1582307,216215,0,216215,0,6918880,6206065,0,0,0,0,0,19946677,524288,0,222778,0,0,0,222778,0,0,0,222778,0,0,0,222778,0,0,0,222778,0,0,0,222778,0,0,0,222778,0,0,0,222778,0,0,0,222778,0,0,0,222778,0,0,0,222778,0,0,0,222778,0,0,0,222778,0,0,0,222778,0,0,0,222778,0,0,0,222778,0,0,0,222778,0,0,0,222778,0,0,0,222778,0,0,0,222778,0,0,0,222778,0,0,0,222778,0,0,0,222778,0,0,0,222778,0,0,0,222778,0,0,0,222778,0,0,0,222778,0,0,0,222778,0,0,0,222778,0,0,0,222778,0,0,0,222778,0,0,0,222778,0,0,0,0,65537,0,5525,0,65584,0,17021,0,65540,0,2948,0,65656,0,20079,0,65536,0,8905,0,65536,0,33478,0,65536,0,2830,0,68112,0,59172,0,65536,0,3289,0,65536,0,3799,0,65536,0,187,0,65537,0,2136,0,65537,0,6366,0,65536,0,5334,0,65536,0,448,0,65536,0,14660,0,65536,0,61606,0,65536,0,18456,0,65536,0,5777,0,65536,0,27554,0,65536,0,40829,0,65536,0,9790,0,65536,0,5655,0,65536,0,29602,0,65536,0,1596,0,65537,0,21322,0,65536,0,828,0,65536,0,6655,0,65536,0,1747,0,65536,0,8548,0,65540,0,0,0,66034,0,37384,0,524288,524288,0,33325492,0,0,0,36354822,0,0,0,37237819,0,0,0,41420227,0,0,0,36613336,0,0,0,41605147,0,0,0,41147552,0,0,0,36655019,0,0,0,35191997,0,0,0,38223536,0,0,0,38515086,0,0,0,41939164,0,0,0,50991076,0,0,0,32963271,0,0,0,35821884,0,0,0,45913685,0,0,0,38863231,0,0,0,35922078,0,0,0,36019784,0,0,0,38936495,0,0,0,40851621,0,0,0,43501465,0,0,0,34257046,0,0,0,46653486,0,0,0,31687275,0,0,0,33408663,0,0,0,36340123,0,0,0,38713768,0,0,0,32812831,0,0,0,34999100,0,0,0,37339970,0,0,0,40484775,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,524288,0,65537,65537,65537,0,65536,65536,65536,188,65541,65729,65729,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65585,65585,65585,0,65536,65536,65536,0,67758,67758,67758,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65584,65584,65584,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65537,65537,65537,0,65536,65536,65536,0,65536,65536,65536,0,67932,67932,67932,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65656,65656,65656,47,65537,65584,65584,0,65536,65536,65536,188,65540,65728,65728,0,65536,65536,65536,65536,0,0,65536,0,0,65728,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65728,0,0,65536,0,0,0,0,65536,65536,4128768,128654570,48343376,76051354,203242,0,0,0,524288,22271221,22259771,524288,524288,16384,65536,751,220786,4058,0,48,3805,0,2097536,4259840,1837288,1674118,24777287,3014656,0,0,3473408,8388608,8388608,8388608,0,0,0,0,0,155824,193741,10884,2311,0,225609,2103057,0,423,2102634,131072,0,131072,524288,0,524288,65536,65536,0,0,360,2097152,0,2097152,32812,0,2537,216397,0,2100418,0,0,31,222298112,917504,0,0,0,65536,65536,0,7601,2016053,0,2097152,2097152,0,604712,606559,0,20982,0,0,0,0,0,0,0,4194304,0,0,0,0,1021778473,1709867950,0,2097152,0,0,0,0,196049,0,0,0,0,0,131072,384,48,0,0,0,432,0,0,0,0,0,14077,0,0,0,2102422,0,10522,0,917504,914660,48,7584,203203,0,0,0,0,0,0,0,0,0,327680,0,0,602598,656028,65536,64048,48,1440,0,65536,0,0,0,0,0,0,0,65536,0,0,0,1966100,0,2097152,0,0,15574552,0,524288,2100999,0,978262555,0,12076441806112351,12076468346366193,12076468346502032,12076441807336799
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/prev_analysis/1.csv
index 44ecb369a3..5564aa9481 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,6053721.0,6053721.0,6053721.0,9.175751708539597
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4526690.0,4526690.0,4526690.0,6.861198839776246
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 256u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,3050380.0,3050380.0,3050380.0,4.623524853011067
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/prev_analysis/1001.csv
index ca08330db0..0e3bf5267e 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,46.862275449101794,Instr per wave
 SMEM,1.8083832335329342,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/prev_analysis/101.csv
index 43e36e731b..01298a993c 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx908
 mi100
 48
 1228.8
-SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/prev_analysis/1202.csv
index eebb5a3e4f..1c58eb2322 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,33604.52904451107,2814.3019104003906,547947.557800293,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/prev_analysis/1901.csv
index d1ee3087ca..063f347e5b 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,2.0,smem_
 VALU,735.0,valu_
 MFMA,,mfma_
 VMEM,8.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,22.0,br_
 VGPR,24.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,67894.0,wavefronts_
 Workgroups,16973.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,163.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,0.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,44.0,hbm_rd_
 HBM Wr,0.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,70.0,vl1_coales_
 VL1 Stall,30.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,36.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/prev_analysis/2001.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/prev_analysis/201.csv
index 55ab45cdcf..227bcd8943 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,59.44489254761303,Pct,100,59.44489254761303
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,63.96727862778705,Threads,64,99.94887285591727
 IPC - Issue,0.8437214675406081,Instr/cycle,5,16.87442935081216
-LDS BW,0.0,Gb/sec,23070.72,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,23070.72,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.9934211709301,Pct,100,99.9934211709301
 Instr Cache BW,1407.7973203543945,Gb/s,4614.144,30.51047649042584
 Scalar L1D Cache Hit Rate,99.356204485269,Pct,100,99.356204485269
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/prev_analysis/602.csv
index deda5e37c7..f7bfdabd07 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,59763.59880239521,0,700793,Simd
 Insufficient SIMD VGPRs,643533.0419161677,0,34820461,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/prev_analysis/701.csv
index d3f1bff5a3..1071413faa 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,23.976047904191617,8,36,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/sysinfo.csv
index eb0c1a7bc2..58c1a4c5bd 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-no_roof_dev1,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 11:33:34 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+no_roof_dev1,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 11:33:34 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/timestamps.csv
index 961bd3ca6a..df9a2ed391 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,929002,929007,33554432,256,0,0,8,32,6464,0x0,0x7fa51ae04180,12076468330647501,12076468330694593,12076468331021790,12076468331126923
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,929002,929007,32768,256,0,0,24,24,12480,0x0,0x7fa51ae35100,12076468346194490,12076468346293873,12076468346300433,12076468346306258
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,929002,929007,4194304,256,0,0,24,24,12928,0x7fa64ad93900,0x7fa51ae35140,12076468346351793,12076468346366193,12076468346502032,12076468346505158
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/SQ_IFETCH_LEVEL.csv
index 6412065ac0..361074d6fa 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/SQ_IFETCH_LEVEL.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,232035,232035,33554432,256,0,0,4,32,4160,0x0,0x7f429e604280,381210,381210,524288,4718592,680524,76266500,17752490411396,17751806206970,17752638943560,17752639035100
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,232035,232035,32768,256,0,0,12,24,13888,0x0,0x7f429e623f80,32983,32983,512,8192,5848,657992,17752644182501,17752638943560,17752644310611,17752644315338
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,232035,232035,4194304,256,0,0,12,24,14336,0x7f42a16d8380,0x7f429e623fc0,164440,164440,65536,917504,142097,15926236,17752644352517,17752644310611,17752644683092,17752644685579
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/SQ_INST_LEVEL_LDS.csv
index 9229c5f361..9e748327b8 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/SQ_INST_LEVEL_LDS.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,233883,233883,33554432,256,0,0,4,32,4160,0x0,0x7fef7d804280,0,0,0,17771865923907,17771150937598,17772015517711,17772015603501
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,233883,233883,32768,256,0,0,12,24,13888,0x0,0x7fef7d823f80,0,0,0,17772020782361,17772015517711,17772020919002,17772020923968
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,233883,233883,4194304,256,0,0,12,24,14336,0x7fef8077b380,0x7fef7d823fc0,0,0,0,17772020958037,17772020919002,17772021289083,17772021292088
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/SQ_INST_LEVEL_SMEM.csv
index 87a7a8bb98..554a88363f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/SQ_INST_LEVEL_SMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,231813,231813,33554432,256,0,0,4,32,4160,0x0,0x7fdad1804280,3670016,3220060,360645976,17751575046256,17723549593242,17751726576924,17751726690614
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,231813,231813,32768,256,0,0,12,24,13888,0x0,0x7fdad1823f80,512,96490,10797968,17751731849825,17751726576924,17751731975175,17751731979802
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,231813,231813,4194304,256,0,0,12,24,14336,0x7fdad484b380,0x7fdad1823fc0,65536,641868,71902856,17751732015081,17751731975175,17751732340296,17751732342793
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/SQ_INST_LEVEL_VMEM.csv
index c1c1d40548..e2aa0bb92b 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/SQ_INST_LEVEL_VMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,233661,233661,33554432,256,0,0,4,32,4160,0x0,0x7f26c9a04280,524288,5453099,610663232,17770923710438,17768618657335,17771069395018,17771069511318
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,233661,233661,32768,256,0,0,12,24,13888,0x0,0x7f26c9a23f80,4096,45985,5142772,17771074705659,17771069395018,17771074847505,17771074851805
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,233661,233661,4194304,256,0,0,12,24,14336,0x7f26cca12380,0x7f26c9a23fc0,524288,11358602,1272134688,17771074887594,17771074847505,17771075217106,17771075219536
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/SQ_LEVEL_WAVES.csv
index 6bf4f01644..8412b72a24 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/SQ_LEVEL_WAVES.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,232257,232257,33554432,256,0,0,4,32,4160,0x0,0x7f53dc604280,381404,381404,8610,3051240,524288,239498614,2965849,0,974233212,17753430057891,17752720771176,17753573521681,17753573610911
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,232257,232257,32768,256,0,0,12,24,13888,0x0,0x7f53dc623f80,33220,33220,29727,265768,512,1721826,163668,0,6900964,17753578768272,17753573521681,17753578907773,17753578912579
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,232257,232257,4194304,256,0,0,12,24,14336,0x7f53fafda380,0x7f53dc623fc0,166092,166092,14725,1328744,65536,70611309,1209508,0,284180948,17753578956998,17753578907773,17753579304414,17753579307059
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/pmc_perf.csv
index 24e98303a0..d353e3856a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDI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],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBufferAligned.kd,0,0,0,233023,233023,33554432,256,0,0,4,32,4160,0x0,0x7f4d44404280,3067232,2981189,524288,38731398,241641153,392,224,0,383403,383403,38996768.0,38057085.0,8.0,4142718.0,31162121.0,30795105.0,38030688.0,37469712.0,3065521,2987585,383403,0,383403,0,12268896.0,9468849.0,0.0,0.0,0,0,616,0,4718592,4714719,112,3761,385898,0.0,0.0,0.0,524288.0,28982595.0,28295278.0,7836.0,524288.0,131072,524288,302,395024,2320,0,56.0,300.0,0.0,4194696.0,0,0,0,0,0,7340032,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,20072526.0,524288.0,0,384238,0,0,0,384238,0,0,0,384238,0,0,0,384238,0,0,0,384238,0,0,0,384238,0,0,0,384238,0,0,0,384238,0,0,0,384238,0,0,0,384238,0,0,0,384238,0,0,0,384238,0,0,0,384238,0,0,0,384238,0,0,0,384238,0,0,0,384238,0,0,0,384238,0,0,0,384238,0,0,0,384238,0,0,0,384238,0,0,0,384238,0,0,0,384238,0,0,0,384238,0,0,0,384238,0,0,0,384238,0,0,0,384238,0,0,0,384238,0,0,0,384238,0,0,0,384238,0,0,0,384238,0,0,0,384238,0,0,0,384238,0,0,0,0,0,0.0,20559645.0,32,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,36,0,0,0,1,0,0,0,1,0,0,0,0,0,0,0,4,0,0,0,0,0,0,0,0,0,0,0,112,0,0,0,0,0,0,0,35,0,0,0,56,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,524288.0,0.0,0,0,129024,129024,0,279123,129024,129024,0,0,129024,129024,0,45337,129024,129024,0,651,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,176,129024,129024,0,43820,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,201,129024,129024,0,25259,129024,129024,0,540805,129024,129024,0,0,129024,129024,0,473,129024,129024,0,0,129024,129024,0,156,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,45511,129024,129024,0,184,129024,129024,524288.0,0.0,43817,0,0,50457539,44810,0,0,50516147,44074,0,0,50133747,45888,0,0,51650083,44114,0,0,50804107,44350,0,0,50811067,44264,0,0,50610905,47341,0,0,52559239,44714,0,0,50714461,45462,0,0,50637907,45504,0,0,50639462,47021,0,0,52056040,46106,0,0,51520269,46147,0,0,51522621,44958,0,0,50870509,49486,0,0,53298512,43724,0,0,50319638,45660,0,0,50617850,43741,0,0,49878617,46499,0,0,51833562,43652,0,0,50878003,46165,0,0,51553716,46051,0,0,51165617,46438,0,0,52225808,45279,0,0,50587193,45641,0,0,50772379,45335,0,0,50367054,48943,0,0,52350585,45712,0,0,51452408,46108,0,0,51472068,44837,0,0,50791190,49239,0,0,53123444,0.0,65536,65536,0,131072,65536,65539,3,131075,65536,65570,34,131106,65536,65536,0,131072,65646,65538,112,131184,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65592,56,131128,65536,65648,112,131184,65536,65568,32,131104,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65537,1,131073,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65568,32,131104,65536,65536,0,131072,65758,65538,224,131296,65536,65536,0,131072,65591,65537,56,131128,65536,65536,0,131072,65536,65536,0,131072,65536,65537,1,131073,65536,65536,0,131072,65536,65568,32,131104,65536,65536,0,131072,65591,65537,56,131128,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131184,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131296,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131128,0,131072,1148944,0,524288,3670016,3663233,224,6559,1048576,33554432.0,33554432.0,0.0,33554432.0,30306809.0,28670152.0,0.0,524288.0,222756,537687,8743,922,0,385045,4195054.0,0.0,2097594.0,2097460.0,1048576,1048576,0,524288,0,524288,7340032,0,0.0,0.0,104.0,8388608.0,29552291.0,2097152.0,0.0,203766,0,1334,383095,0,754.0,4194304.0,0.0,2064387.0,25690112,9437184,0,0,0,0,0,0,13283.0,8242495.0,0.0,8388608.0,2097152.0,4194304.0,10029222,0,0,8757,4128768.0,4128768.0,0.0,1477379.0,0,0,0,0,0,0,5767168,1048576,312434623.0,0.0,1459889553.0,0.0,57.0,0.0,0,0,370583,0.0,0.0,1440994.0,0.0,3670016,524288,0,0,0,2621440,524288,177249518,4194304.0,0.0,0.0,0.0,0.0,1204744.0,0,0,0.0,312.0,0.0,608.0,43163411,24117248,0,0,9437184,11010048,0,3145728,0.0,0.0,0.0,0.0,0.0,0.0,0,1572864,0.0,0.0,0.0,198388.0,524288,524288,0,3670016,7340032,603979776,4718592,0,0.0,0.0,0.0,0.0,0.0,0.0,524288,0,2064384.0,0.0,2031623.0,0.0,0,0,524288,0,0,0,0,33554432,0.0,4194304.0,0.0,19035791.0,0.0,0.0,143.0,4128768.0,1007245.0,1655433095.0,17754865908881,17772687966279,17772688205319,17755014874437
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,233023,233023,32768,256,0,0,12,24,13888,0x0,0x7f4d44423f80,259192,158265,512,1336926,1597190,504,56,0,32398,32398,2288481.0,143085.0,184.0,0.0,33242.0,29544.0,136820.0,118032.0,259184,165158,32398,0,32398,0,1036736.0,379064.0,0.0,0.0,0,0,560,0,8192,6191,56,1945,23016,0.0,0.0,0.0,4096.0,32667.0,31216.0,0.0,4096.0,128,512,302,32168,2350,0,0.0,60.0,0.0,4600.0,0,0,0,0,0,1024,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,12350.0,4096.0,0,32748,0,0,0,32748,0,0,0,32748,0,0,0,32748,0,0,0,32748,0,0,0,32748,0,0,0,32748,0,0,0,32748,0,0,0,32748,0,0,0,32748,0,0,0,32748,0,0,0,32748,0,0,0,32748,0,0,0,32748,0,0,0,32748,0,0,0,32748,0,0,0,32748,0,0,0,32748,0,0,0,32748,0,0,0,32748,0,0,0,32748,0,0,0,32748,0,0,0,32748,0,0,0,32748,0,0,0,32748,0,0,0,32748,0,0,0,32748,0,0,0,32748,0,0,0,32748,0,0,0,32748,0,0,0,32748,0,0,0,32748,0,0,0,0,0,0.0,0.0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,258,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,312,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,4096.0,4096.0,0,106751,0,0,0,84817,0,0,0,80117,0,0,0,84345,0,0,0,84123,0,0,0,77155,0,0,0,76956,0,0,0,81463,0,0,0,76681,0,0,0,76805,0,0,0,74623,0,0,0,82680,0,0,0,101415,0,0,0,76144,0,0,0,77965,0,0,0,83914,0,0,0,73310,0,0,0,100444,0,0,0,74781,0,0,0,98607,0,0,0,80484,0,0,0,79409,0,0,0,673591,0,0,0,84844,0,0,0,82072,0,0,0,80107,0,0,0,70297,0,0,0,80423,0,0,0,112951,0,0,0,86006,0,0,0,84053,0,0,0,82656,0,0,0.0,0.0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4096.0,0,128,128,128,0,129,129,129,0,129,129,129,0,128,128,128,0,128,128,128,222,130,352,352,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,184,184,184,0,128,128,128,0,128,128,128,0,128,128,128,222,130,352,352,0,128,128,128,0,129,129,129,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,55,129,184,184,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,352,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,352,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,184,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,652,0,0,512,0,56,456,0,65536.0,65536.0,65536.0,0.0,0.0,0.0,0.0,0.0,6,518,11350,1000,0,30787,4659.0,0.0,499.0,4160.0,512,0,0,0,4096,4096,512,0,0.0,0.0,104.0,16384.0,0.0,16384.0,4096.0,0,0,1315,32099,0,4661.0,0.0,0.0,31.0,35328,26112,0,0,0,0,0,0,104.0,15240.0,0.0,16384.0,16384.0,0.0,0,0,0,29158,0.0,0.0,0.0,0.0,0,0,0,0,0,0,10752,3584,3933349.0,5253975.0,0.0,8192.0,2.0,0.0,0,0,499,0.0,0.0,0.0,0.0,512,4096,0,0,0,512,512,1638372,0.0,0.0,0.0,0.0,0.0,1321.0,0,0,0.0,8263.0,0.0,124.0,21688,32256,0,0,26112,1024,0,1024,0.0,0.0,0.0,0.0,0.0,0.0,0,1024,0.0,0.0,0.0,48723.0,4096,0,4096,512,512,1671168,8192,0,0.0,0.0,0.0,0.0,0.0,0.0,512,0,0.0,0.0,0.0,0.0,0,0,512,0,0,0,0,32768,8192.0,0.0,0.0,123389.0,0.0,4096.0,8204.0,0.0,3191974.0,0.0,17755021082352,17772693094929,17772693107729,17755021568230
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,233023,233023,4194304,256,0,0,12,24,14336,0x7f4d47438380,0x7f4d44423fc0,1318224,1212581,65536,15707649,72291013,392,56,0,164777,164777,15994602.0,14511595.0,24106.0,677320.0,12911947.0,12475860.0,14505184.0,12369596.0,1318216,1219286,164777,0,164777,0,5272864.0,4739839.0,0.0,0.0,0,0,448,0,917504,913793,0,3711,153160,0.0,0.0,0.0,524288.0,13569254.0,13551524.0,2217.0,524288.0,16384,65536,302,164079,2631,0,0.0,185.0,0.0,1048968.0,0,0,0,0,0,131072,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,10729909.0,524288.0,0,164943,0,0,0,164943,0,0,0,164943,0,0,0,164943,0,0,0,164943,0,0,0,164943,0,0,0,164943,0,0,0,164943,0,0,0,164943,0,0,0,164943,0,0,0,164943,0,0,0,164943,0,0,0,164943,0,0,0,164943,0,0,0,164943,0,0,0,164943,0,0,0,164943,0,0,0,164943,0,0,0,164943,0,0,0,164943,0,0,0,164943,0,0,0,164943,0,0,0,164943,0,0,0,164943,0,0,0,164943,0,0,0,164943,0,0,0,164943,0,0,0,164943,0,0,0,164943,0,0,0,164943,0,0,0,164943,0,0,0,164943,0,0,0,0,0,0.0,0.0,65537,0,7781,0,65537,0,12458,0,65536,0,25990,0,65536,0,18063,0,65536,0,19094,0,65536,0,16493,0,65536,0,15486,0,65537,0,35929,0,65536,0,11636,0,65541,0,7547,0,65536,0,5262,0,65536,0,13383,0,65536,0,14824,0,65536,0,23604,0,65537,0,8200,0,65536,0,14589,0,65536,0,30848,0,65536,0,16814,0,65593,0,26921,0,65536,0,23853,0,65539,0,12360,0,65536,0,29619,0,65536,0,9646,0,65539,0,15886,0,65540,0,14515,0,65648,0,14217,0,65536,0,29530,0,65601,0,9065,0,65536,0,14870,0,65536,0,28163,0,65536,0,30850,0,65536,0,22359,0,524288.0,524288.0,0,46210271,0,0,0,41173300,0,0,0,44855449,0,0,0,42914975,0,0,0,51179336,0,0,0,47915252,0,0,0,49634419,0,0,0,49610560,0,0,0,48383365,0,0,0,40686580,0,0,0,38435605,0,0,0,47039320,0,0,0,49621205,0,0,0,42619095,0,0,0,48157592,0,0,0,48876121,0,0,0,48171787,0,0,0,48832930,0,0,0,48053457,0,0,0,47805578,0,0,0,45572032,0,0,0,48216447,0,0,0,50386250,0,0,0,41996170,0,0,0,39348328,0,0,0,49126336,0,0,0,38422460,0,0,0,40704511,0,0,0,46410057,0,0,0,43649847,0,0,0,45776485,0,0,0,44087143,0,0,0.0,0.0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,524288.0,0,32768,32768,32768,0,32769,32769,32769,0,32823,32823,32823,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32824,32824,32824,0,32813,32813,32813,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32769,32769,32769,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32769,32769,32769,166,32770,32936,32936,222,32770,32992,32992,0,32768,32768,32768,0,32768,32768,32768,0,32770,32770,32770,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32936,0,0,32992,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,903479,0,0,65536,63800,56,1680,0,8388608.0,8388608.0,8388608.0,0.0,0.0,0.0,0.0,0.0,124186,148704,10079,2561,0,162010,1049155.0,0.0,388.0,1048767.0,65536,0,0,0,524288,524288,131072,0,0.0,0.0,104.0,2097152.0,0.0,2097152.0,524288.0,63909,0,2359,162171,0,1049154.0,0.0,0.0,31.0,4063232,2883584,0,0,0,0,0,0,6610.0,2027064.0,0.0,2097152.0,2097152.0,0.0,1755047,0,0,14938,0.0,0.0,0.0,0.0,262144,0,0,0,0,0,1507328,458752,895682153.0,2325305617.0,0.0,2097152.0,25.0,0.0,0,0,151263,0.0,0.0,0.0,0.0,65536,524288,0,0,0,65536,65536,48499298,0.0,0.0,0.0,0.0,0.0,15151.0,0,0,0.0,2097342.0,0.0,366.0,21382275,3735552,0,0,2883584,196608,0,131072,0.0,0.0,0.0,0.0,0.0,0.0,0,131072,0.0,0.0,417476.0,1289604.0,524288,0,524288,65536,131072,184549376,917504,0,0.0,0.0,0.0,0.0,0.0,0.0,65536,0,0.0,0.0,983046.0,0.0,0,0,65536,0,0,0,0,4194304,2097152.0,0.0,0.0,12354882.0,0.0,524288.0,2097265.0,0.0,1448153741.0,0.0,17755022664402,17772693175089,17772693267570,17755023464522
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/prev_analysis/1.csv
index 6876ce29db..ba04a7262d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,3357928.0,3357928.0,3357928.0,7.848044209322157
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,1726083.0,1726083.0,1726083.0,4.034147156508245
 "void benchmark_func<double, 256, 8u, 512u>(double, double*) [clone .kd]",1,1715523.0,1715523.0,1715523.0,4.009466655064961
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/prev_analysis/1001.csv
index f475f954a6..fb5988001a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,494.8622754491018,Instr per wave
 VMEM,7.958083832335329,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,0.0,Instr per wave
 SALU,24.520958083832337,Instr per wave
 SMEM,1.8023952095808384,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/prev_analysis/101.csv
index c1353cb24d..300e9c43b1 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx90a
 mi200
 56
 1638.4
-SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/prev_analysis/1202.csv
index efd2307a32..98f1c39666 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,18361.129298821183,1843.5756912231445,258338.73376464844,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/prev_analysis/1901.csv
index 340c70024b..857b1a80dc 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,2.0,smem_
 VALU,495.0,valu_
 MFMA,0.0,mfma_
 VMEM,8.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,10.0,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,67894.0,wavefronts_
 Workgroups,16973.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,128.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,0.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,44.0,hbm_rd_
 HBM Wr,0.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,70.0,vl1_coales_
 VL1 Stall,2.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,25.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/prev_analysis/201.csv
index bedf711635..90a7fef95d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,58.406841134878334,Pct,100,58.406841134878334
 MFMA Util,0.0,Pct,100,0.0
 VALU Active Threads/Wave,64.0,Threads,64,100.0
 IPC - Issue,1.0,Instr/cycle,5,20.0
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99259051240679,Pct,100,99.99259051240679
 Instr Cache BW,1675.5596335734238,Gb/s,6092.8,27.500650498513387
 Scalar L1D Cache Hit Rate,99.34855885983424,Pct,100,99.34855885983424
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/prev_analysis/602.csv
index f0ed5341c7..e831f161d4 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,12535276.491017964,0,360467281,Simd
 Insufficient SIMD VGPRs,0.0,0,0,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/prev_analysis/701.csv
index 12250d77c0..db0925a109 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/sysinfo.csv
index 7056797c27..d22f206ac8 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-no_roof_dev1,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:49:12 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+no_roof_dev1,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:49:12 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/timestamps.csv
index 7525315ca7..d5fdb01d11 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dev1/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,233966,233966,33554432,256,0,0,4,32,4160,0x0,0x7f9943804280,17772687942278,17772687966279,17772688205319,17772688294519
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,233966,233966,32768,256,0,0,12,24,13888,0x0,0x7f9943823f80,17772693079650,17772693094929,17772693107729,17772693125979
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,233966,233966,4194304,256,0,0,12,24,14336,0x7f9946887380,0x7f9943823fc0,17772693128869,17772693175089,17772693267570,17772693269515
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/SQ_IFETCH_LEVEL.csv
index 3560be9c02..27974429f1 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/SQ_IFETCH_LEVEL.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,896956,896961,33554432,256,0,0,8,32,6464,0x0,0x7f9436204180,500033,500033,524288,6291456,794317,101511600,12075867444478178,12075867691412384,12075867691733022,12075867691843405
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,896956,896961,32768,256,0,0,24,24,12480,0x0,0x7f9436235100,27843,27843,512,8192,9180,1186932,12075867706506305,12075867706823139,12075867706829539,12075867706838392
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,896956,896961,4194304,256,0,0,24,24,12928,0x7f9541dcf900,0x7f9436235140,227292,227292,65536,917504,140453,17976128,12075867706904195,12075867707135937,12075867707274977,12075867707279362
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/SQ_INST_LEVEL_LDS.csv
index bf024b7b78..aa53fa5b51 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/SQ_INST_LEVEL_LDS.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,898754,898759,33554432,256,0,0,8,32,6464,0x0,0x7fb241204180,0,0,0,12075893891707921,12075894133458591,12075894133782269,12075894133892821
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,898754,898759,32768,256,0,0,24,24,12480,0x0,0x7fb241235100,0,0,0,12075894148574947,12075894148876150,12075894148882870,12075894148888340
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,898754,898759,4194304,256,0,0,24,24,12928,0x7fb34cedb900,0x7fb241235140,0,0,0,12075894148946518,12075894149174388,12075894149307988,12075894149312027
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/SQ_INST_LEVEL_SMEM.csv
index 4526ddc536..085046c625 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/SQ_INST_LEVEL_SMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,898376,898381,33554432,256,0,0,8,32,6464,0x0,0x7f2da1004180,4194304,3107474,397802792,12075891375932245,12075891619777677,12075891620103275,12075891620206818
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,898376,898381,32768,256,0,0,24,24,12480,0x0,0x7f2da1035100,512,21496,2743368,12075891635045094,12075891635348079,12075891635354479,12075891635359859
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,898376,898381,4194304,256,0,0,24,24,12928,0x7f2eacc0b900,0x7f2da1035140,65536,170358,21941736,12075891635426263,12075891635638958,12075891635772077,12075891635776233
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/SQ_INST_LEVEL_VMEM.csv
index 1993a6c3ea..236a05b805 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/SQ_INST_LEVEL_VMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,898566,898571,33554432,256,0,0,8,32,6464,0x0,0x7f15fb204180,1048576,11084724,1418552312,12075892634418174,12075892880996864,12075892881321822,12075892881419575
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,898566,898571,32768,256,0,0,24,24,12480,0x0,0x7f15fb235100,4096,105534,13508884,12075892896267910,12075892896572303,12075892896579023,12075892896589007
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,898566,898571,4194304,256,0,0,24,24,12928,0x7f172b19d900,0x7f15fb235140,524288,11724874,1500801268,12075892896648237,12075892896867021,12075892897001101,12075892897010711
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/SQ_LEVEL_WAVES.csv
index 9b31f03e95..3320b3f877 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/SQ_LEVEL_WAVES.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,898945,898950,33554432,256,0,0,8,32,6464,0x0,0x7fb3e1404180,502713,502713,17029,4021712,524288,369748218,3817340,0,1493757504,12075895142242394,12075895385647549,12075895385970427,12075895386081619
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,898945,898950,32768,256,0,0,24,24,12480,0x0,0x7fb3e1435100,27559,27559,20298,220480,512,1072246,72366,0,4302916,12075895400602936,12075895400932312,12075895400938232,12075895400947647
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,898945,898950,4194304,256,0,0,24,24,12928,0x7fb4ed041900,0x7fb3e1435140,221493,221493,19784,1771952,65536,143641180,1602587,0,576371800,12075895401022125,12075895401273911,12075895401408630,12075895401413152
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/pmc_dispatch_info.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/pmc_perf.csv
index 4b28d082b2..ea85d796ba 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBuffer.kd,0,0,0,897691,897696,33554432,256,0,0,8,32,6464,0x0,0x7fd7e4804180,1048576,0,1048576,9437184,0,4194304,1048576,0,505782,505782,58033275,55532942,99,12553208,54629020,54533345,55468839,54286032,4046256,3853342,505782,0,505782,0,16185024,15350190,0,0,0,0,0,17372335,1048576,0,504472,0,0,0,504472,0,0,0,504472,0,0,0,504472,0,0,0,504472,0,0,0,504472,0,0,0,504472,0,0,0,504472,0,0,0,504472,0,0,0,504472,0,0,0,504472,0,0,0,504472,0,0,0,504472,0,0,0,504472,0,0,0,504472,0,0,0,504472,0,0,0,504472,0,0,0,504472,0,0,0,504472,0,0,0,504472,0,0,0,504472,0,0,0,504472,0,0,0,504472,0,0,0,504472,0,0,0,504472,0,0,0,504472,0,0,0,504472,0,0,0,504472,0,0,0,504472,0,0,0,504472,0,0,0,504472,0,0,0,504472,0,0,0,37674981,48,0,0,0,4,0,0,0,3,0,0,0,2633,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2694,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,89,0,0,0,1,0,0,0,3,0,0,0,0,0,0,0,2607,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,49,0,0,0,49,0,0,0,0,0,0,0,2677,0,0,0,1048576,0,0,2970844,131080,131080,0,1409,131072,131072,0,0,131076,131076,0,0,131072,131072,0,2962623,131076,131076,0,0,131072,131072,0,1769,131072,131072,0,25921,131072,131072,0,0,131076,131076,0,0,131072,131072,0,517,131072,131072,0,1427,131076,131076,0,0,131072,131072,0,0,131072,131072,0,0,131072,131072,0,0,131076,131076,0,0,131072,131072,0,784,131076,131076,0,0,131072,131072,0,0,131072,131072,0,3002834,131073,131073,0,0,131076,131076,0,14257,131072,131072,0,0,131072,131072,0,2898240,131072,131072,0,0,131080,131080,0,0,131072,131072,0,0,131072,131072,0,5851,131076,131076,0,0,131072,131072,0,559781,131072,131072,0,0,131076,131076,1048576,0,1205,0,0,17517182,1025,0,0,17148831,1400,0,0,17348184,1873,0,0,17207512,820,0,0,17613246,41234,0,0,28683300,885,0,0,18026103,1099,0,0,18408341,1055,0,0,17459534,47608,0,0,30320321,1741,0,0,17106110,680,0,0,16913338,915,0,0,17527535,2108,0,0,17519343,50573,0,0,31007970,1742,0,0,18643653,2185,0,0,17084724,1361,0,0,16939964,1071,0,0,17192586,1012,0,0,16743112,1279,0,0,17555436,49418,0,0,30975203,1217,0,0,18132490,1507,0,0,18797451,1288,0,0,17226222,1145,0,0,16852245,853,0,0,16984852,728,0,0,17093738,1466,0,0,17865909,863,0,0,17494863,894,0,0,18229090,1329,0,0,18441408,1048576,131072,131072,0,262144,131260,131124,240,262384,131072,131073,1,262145,131119,133655,2630,264774,131072,131072,0,262144,131072,131072,0,262144,131072,131073,1,262145,131072,133769,2697,264841,131072,131072,0,262144,131072,131072,0,262144,131119,131073,48,262192,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131213,131075,144,262288,131072,131072,0,262144,131072,131089,17,262161,131072,131075,3,262147,131072,131072,0,262144,131072,131120,48,262192,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131120,48,262192,131072,133752,2680,264824,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,133672,2600,264744,262144,0,262144,262336,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262288,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,0,0,3145728,524288,32505856,366811653,219331226,114974571,482620,0,0,0,1048576,52323996,52079325,1048576,1048576,131072,524288,685,505166,6315,0,96,10671,0,8388944,32505856,4024200,3815922,57079671,11534336,0,0,14155776,67108864,67108864,0,67108864,54125581,53751057,0,1048576,239170,763458,11811,2546,0,498754,8399544,0,4194727,4204817,13631488,0,3670016,1048576,1048576,0,4194304,9437184,0,0,360,33554432,54400640,4194304,0,0,2804,504818,0,11248,8388608,0,4194350,905969664,6291456,0,0,0,524288,524288,0,15329,16608707,0,16777216,4194304,4194304,0,0,0,17090,4194380,4194380,0,217542,0,0,0,33554432,0,0,0,0,630531958,0,2769108527,0,0,0,0,0,476194,0,0,223507,0,0,8388608,336,144,0,0,0,480,8388608,0,0,0,0,342684,0,0,0,10613,0,21208,0,6291456,6289329,96,2688,2022400,0,0,0,0,0,0,0,0,0,3145728,0,0,0,155426,4194304,4189860,144,4300,2097152,524288,1572864,0,0,0,0,0,0,524288,0,4128873,65531,4063248,0,0,8388608,0,42369263,0,1048576,10598,4194348,12981522,607628197,12075869575839578,12075896272365659,12075896272694135,12075869822460793
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,897691,897696,32768,256,0,0,24,24,12480,0x0,0x7fd7e4835100,0,4096,4096,512,0,512,4096,0,28700,28700,1559207,653010,230,126921,89894,66302,644940,624345,229600,89769,28700,0,28700,0,918400,208347,0,0,0,0,0,62533,4096,0,29043,0,0,0,29043,0,0,0,29043,0,0,0,29043,0,0,0,29043,0,0,0,29043,0,0,0,29043,0,0,0,29043,0,0,0,29043,0,0,0,29043,0,0,0,29043,0,0,0,29043,0,0,0,29043,0,0,0,29043,0,0,0,29043,0,0,0,29043,0,0,0,29043,0,0,0,29043,0,0,0,29043,0,0,0,29043,0,0,0,29043,0,0,0,29043,0,0,0,29043,0,0,0,29043,0,0,0,29043,0,0,0,29043,0,0,0,29043,0,0,0,29043,0,0,0,29043,0,0,0,29043,0,0,0,29043,0,0,0,29043,0,0,0,0,304,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,260,0,0,0,376,0,0,0,257,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,305,0,0,0,257,0,0,0,256,0,0,0,4096,4096,0,77685,0,0,0,86016,0,0,0,80806,0,0,0,163460,0,0,0,79151,0,0,0,135778,0,0,0,123732,0,0,0,130063,0,0,0,92892,0,0,0,80892,0,0,0,80739,0,0,0,73208,0,0,0,78275,0,0,0,85109,0,0,0,68524,0,0,0,66992,0,0,0,125608,0,0,0,113151,0,0,0,65738,0,0,0,90928,0,0,0,126162,0,0,0,81677,0,0,0,97004,0,0,0,90024,0,0,0,105704,0,0,0,86791,0,0,0,82976,0,0,0,67291,0,0,0,170984,0,0,0,83848,0,0,0,85969,0,0,0,77159,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4096,0,256,256,256,0,304,304,304,0,257,257,257,0,256,256,256,0,256,256,256,0,256,256,256,0,257,257,257,0,256,256,256,0,256,256,256,0,256,256,256,47,257,304,304,0,256,256,256,0,256,256,256,0,256,256,256,188,260,448,448,0,256,256,256,0,256,256,256,0,256,256,256,188,260,448,448,0,377,377,377,0,256,256,256,0,256,256,256,0,304,304,304,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,47,257,304,304,0,256,256,256,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,304,0,0,256,0,0,0,0,512,512,35328,1072304,1011571,24381,11314,0,0,0,4096,80604,77706,4096,4096,128,512,594,27153,4386,0,48,219,0,8624,36352,223504,72516,1014899,26624,0,0,30208,65536,65536,65536,0,0,0,0,0,115,627,11809,2439,0,23745,8844,0,470,8374,1024,0,1024,4096,0,4096,512,512,0,0,360,16384,0,16384,0,0,3356,25259,0,8892,0,0,31,1933312,8192,0,0,0,512,512,0,120,15064,0,16384,16384,0,0,0,0,20232,0,0,0,0,0,0,0,32768,0,0,0,0,12815512,17261350,0,8192,0,0,0,0,695,0,0,0,0,0,1024,432,48,0,0,0,480,0,0,0,0,0,3152,0,0,0,8421,0,438,0,8192,6549,48,1595,1112,0,0,0,0,0,0,0,0,0,2560,0,0,0,49937,512,0,48,464,0,512,0,0,0,0,0,0,0,512,0,0,0,0,0,8192,0,0,437764,0,4096,8372,0,3223685,0,12075869837392693,12075896287991030,12075896287998070,12075869838388093
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,897691,897696,4194304,256,0,0,24,24,12928,0x7fd8f0429900,0x7fd7e4835140,0,524288,524288,65536,0,65536,524288,0,213356,213356,23453417,22263306,33478,13972408,21619387,21528134,22249008,20075506,1706848,1547575,213356,0,213356,0,6827392,6093930,0,0,0,0,0,20423671,524288,0,223945,0,0,0,223945,0,0,0,223945,0,0,0,223945,0,0,0,223945,0,0,0,223945,0,0,0,223945,0,0,0,223945,0,0,0,223945,0,0,0,223945,0,0,0,223945,0,0,0,223945,0,0,0,223945,0,0,0,223945,0,0,0,223945,0,0,0,223945,0,0,0,223945,0,0,0,223945,0,0,0,223945,0,0,0,223945,0,0,0,223945,0,0,0,223945,0,0,0,223945,0,0,0,223945,0,0,0,223945,0,0,0,223945,0,0,0,223945,0,0,0,223945,0,0,0,223945,0,0,0,223945,0,0,0,223945,0,0,0,223945,0,0,0,0,65584,0,6899,0,65536,0,0,0,65540,0,1333,0,67469,0,50919,0,65536,0,8761,0,65536,0,402,0,65536,0,3617,0,65536,0,2376,0,65536,0,0,0,65536,0,0,0,65537,0,0,0,65536,0,3769,0,65536,0,0,0,65536,0,0,0,65536,0,0,0,65656,0,5950,0,65537,0,1419,0,65536,0,617,0,65536,0,1971,0,68154,0,84503,0,65536,0,165,0,65536,0,0,0,65536,0,0,0,65537,0,0,0,65536,0,565,0,65536,0,4818,0,65536,0,2195,0,65536,0,133,0,65536,0,1266,0,65585,0,2698,0,65540,0,1226,0,65536,0,4074,0,524288,524288,0,49888923,0,0,0,29381427,0,0,0,29434306,0,0,0,30188085,0,0,0,27654865,0,0,0,33087785,0,0,0,26791064,0,0,0,28223215,0,0,0,26915365,0,0,0,28275134,0,0,0,27720595,0,0,0,27881856,0,0,0,30563957,0,0,0,33335771,0,0,0,28777023,0,0,0,31405403,0,0,0,29439826,0,0,0,29668710,0,0,0,28878703,0,0,0,34694253,0,0,0,28709000,0,0,0,33812066,0,0,0,26321745,0,0,0,31394692,0,0,0,43450860,0,0,0,28282339,0,0,0,27320010,0,0,0,30651137,0,0,0,29325328,0,0,0,30092597,0,0,0,27830984,0,0,0,28249657,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,524288,0,65536,65536,65536,0,65584,65584,65584,188,65541,65729,65729,0,68307,68307,68307,0,65536,65536,65536,0,65536,65536,65536,0,65537,65537,65537,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,47,65537,65584,65584,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65657,65657,65657,0,65536,65536,65536,0,65536,65536,65536,0,65584,65584,65584,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,188,65540,65728,65728,0,68115,68115,68115,65536,0,0,65536,0,0,65728,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65728,0,0,65536,0,0,0,0,65536,65536,4128768,129934015,49695572,75978603,201190,0,0,0,524288,21631882,21619182,524288,524288,16384,65536,733,218122,4145,0,48,3260,0,2097536,4259840,1800352,1624612,24097081,3014656,0,0,3473408,8388608,8388608,8388608,0,0,0,0,0,161899,198849,11600,2464,0,220867,2102158,0,423,2101735,131072,0,131072,524288,0,524288,65536,65536,0,0,360,2097152,0,2097152,30407,0,2939,219965,0,2101886,0,0,31,222298112,917504,0,0,0,65536,65536,0,7577,2018823,0,2097152,2097152,0,660803,662959,0,22796,0,0,0,0,0,0,0,4194304,0,0,0,0,924760855,1437327062,0,2097152,0,0,0,0,198343,0,0,0,0,0,131072,384,48,0,0,0,432,0,0,0,0,0,11313,0,0,0,2101537,0,8752,0,917504,914555,48,7627,183938,0,0,0,0,0,0,0,0,0,327680,0,0,518403,572134,65536,64048,48,1440,0,65536,0,0,0,0,0,0,0,65536,0,0,0,1966096,0,2097152,0,0,16932533,0,524288,2100116,0,1122855084,0,12075869839022472,12075896288057109,12075896288194548,12075869840284117
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/prev_analysis/1.csv
index a238d7be31..a6d4f0be14 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,6050510.0,6050510.0,6050510.0,9.178693027875996
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4526203.0,4526203.0,4526203.0,6.86630183552319
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 256u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,3048935.0,3048935.0,3048935.0,4.625269345385282
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/prev_analysis/1001.csv
index ca08330db0..0e3bf5267e 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,46.862275449101794,Instr per wave
 SMEM,1.8083832335329342,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/prev_analysis/101.csv
index 0cb52be3c6..fba85ea69d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx908
 mi100
 48
 1228.8
-SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/prev_analysis/1202.csv
index ffe7df1382..492921c7e6 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,33277.073708768374,2798.5508193969727,547845.0401000977,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/prev_analysis/1901.csv
index 37517d0057..554e68becb 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,2.0,smem_
 VALU,735.0,valu_
 MFMA,,mfma_
 VMEM,8.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,22.0,br_
 VGPR,24.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,67894.0,wavefronts_
 Workgroups,16973.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,163.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,0.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,44.0,hbm_rd_
 HBM Wr,0.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,70.0,vl1_coales_
 VL1 Stall,31.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,35.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/prev_analysis/2001.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/prev_analysis/201.csv
index a7aa073637..3e7e848687 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,59.699633114569615,Pct,100,59.699633114569615
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,63.96712358011139,Threads,64,99.94863059392405
 IPC - Issue,0.843720876890558,Instr/cycle,5,16.874417537811162
-LDS BW,0.0,Gb/sec,23070.72,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,23070.72,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99339862920725,Pct,100,99.99339862920725
 Instr Cache BW,1410.6761941269442,Gb/s,4614.144,30.572868859899998
 Scalar L1D Cache Hit Rate,99.35620448525918,Pct,100,99.35620448525918
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/prev_analysis/602.csv
index e70bdf2d02..b1c02f8bc2 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,59701.59281437126,0,660803,Simd
 Insufficient SIMD VGPRs,631564.7365269461,0,34054270,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/prev_analysis/701.csv
index d3f1bff5a3..1071413faa 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,23.976047904191617,8,36,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/sysinfo.csv
index 8cc21a1d81..7c914af3d0 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-no_roof_dispatches,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 11:24:02 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+no_roof_dispatches,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 11:24:02 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/timestamps.csv
index c2fc419e2e..cb6e0edf81 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,898994,898999,33554432,256,0,0,8,32,6464,0x0,0x7fdc81004180,12075896272320224,12075896272365659,12075896272694135,12075896272800557
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,898994,898999,32768,256,0,0,24,24,12480,0x0,0x7fdc81035100,12075896287883347,12075896287991030,12075896287998070,12075896288012347
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,898994,898999,4194304,256,0,0,24,24,12928,0x7fdd8ccc3900,0x7fdc81035140,12075896288041672,12075896288057109,12075896288194548,12075896288197661
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/SQ_IFETCH_LEVEL.csv
index bb70fb3da0..ef9835a693 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/SQ_IFETCH_LEVEL.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,196758,196758,33554432,256,0,0,4,32,4160,0x0,0x7fc3bda04280,379580,379580,524288,4718592,686797,76969300,17173312147312,17172609328565,17173460182116,17173460295496
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,196758,196758,32768,256,0,0,12,24,13888,0x0,0x7fc3bda23f80,33304,33304,512,8192,6010,670548,17173465444595,17173460182116,17173465576360,17173465580681
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,196758,196758,4194304,256,0,0,12,24,14336,0x7fc3c0ab1380,0x7fc3bda23fc0,170667,170667,65536,917504,141990,15949520,17173465618570,17173465576360,17173465950600,17173465952831
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/SQ_INST_LEVEL_LDS.csv
index 8bf5dfea8e..1215ddb4e2 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/SQ_INST_LEVEL_LDS.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,198606,198606,33554432,256,0,0,4,32,4160,0x0,0x7f067d004280,0,0,0,17192728533864,17192015134405,17192881061785,17192881175054
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,198606,198606,32768,256,0,0,12,24,13888,0x0,0x7f067d023f80,0,0,0,17192886374272,17192881061785,17192886501463,17192886506188
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,198606,198606,4194304,256,0,0,12,24,14336,0x7f067ff2b380,0x7f067d023fc0,0,0,0,17192886540997,17192886501463,17192886869303,17192886871798
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/SQ_INST_LEVEL_SMEM.csv
index cc4534e96d..204082286b 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/SQ_INST_LEVEL_SMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,196536,196536,33554432,256,0,0,4,32,4160,0x0,0x7f2de0e04280,3670016,3093798,346422856,17172376854009,17144371429272,17172529001099,17172529113759
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,196536,196536,32768,256,0,0,12,24,13888,0x0,0x7f2de0e23f80,512,99320,11140688,17172534294136,17172529001099,17172534423180,17172534428033
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,196536,196536,4194304,256,0,0,12,24,14336,0x7f2de3d6b380,0x7f2de0e23fc0,65536,625066,70042416,17172534462532,17172534423180,17172534795340,17172534798043
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/SQ_INST_LEVEL_VMEM.csv
index 2dff54533a..a1812e5ece 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/SQ_INST_LEVEL_VMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,198384,198384,33554432,256,0,0,4,32,4160,0x0,0x7fa51be04280,524288,5486034,614431996,17191785527924,17189466058473,17191934114114,17191934203052
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,198384,198384,32768,256,0,0,12,24,13888,0x0,0x7fa51be23f80,4096,47095,5274648,17191939345832,17191934114114,17191939472829,17191939477618
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,198384,198384,4194304,256,0,0,12,24,14336,0x7fa53a7f8380,0x7fa51be23fc0,524288,10935983,1224795228,17191939510887,17191939472829,17191939839549,17191939842328
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/SQ_LEVEL_WAVES.csv
index 74c801c187..e60ce1847f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/SQ_LEVEL_WAVES.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,196980,196980,33554432,256,0,0,4,32,4160,0x0,0x7f1867c04280,382355,382355,8904,3058848,524288,240694258,2971165,0,979009156,17174249083587,17173543423885,17174395082868,17174395195338
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,196980,196980,32768,256,0,0,12,24,13888,0x0,0x7f1867c23f80,32824,32824,29316,262600,512,1729446,160252,0,6930940,17174400312608,17174395082868,17174400448629,17174400453174
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,196980,196980,4194304,256,0,0,12,24,14336,0x7f198e588380,0x7f1867c23fc0,165264,165264,14189,1322120,65536,77476199,1209159,0,311635992,17174400497513,17174400448629,17174400839349,17174400841553
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/pmc_perf.csv
index d4150d9870..07f25e3df2 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDI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],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBufferAligned.kd,0,0,0,197746,197746,33554432,256,0,0,4,32,4160,0x0,0x7f9f95e04280,3088816,3002286,524288,38958304,243743237,392,224,0,386101,386101,39272914.0,38180809.0,3.0,4195176.0,31301909.0,30938579.0,38156689.0,37597011.0,3087105,3008685,386101,0,386101,0,12355232.0,9504508.0,0.0,0.0,0,0,616,0,4718592,4714722,112,3758,375482,0.0,0.0,0.0,524288.0,28466900.0,27744970.0,7910.0,524288.0,131072,524288,302,384901,2291,0,56.0,301.0,0.0,4194696.0,0,0,0,0,0,7340032,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,20102098.0,524288.0,0,383418,0,0,0,383418,0,0,0,383418,0,0,0,383418,0,0,0,383418,0,0,0,383418,0,0,0,383418,0,0,0,383418,0,0,0,383418,0,0,0,383418,0,0,0,383418,0,0,0,383418,0,0,0,383418,0,0,0,383418,0,0,0,383418,0,0,0,383418,0,0,0,383418,0,0,0,383418,0,0,0,383418,0,0,0,383418,0,0,0,383418,0,0,0,383418,0,0,0,383418,0,0,0,383418,0,0,0,383418,0,0,0,383418,0,0,0,383418,0,0,0,383418,0,0,0,383418,0,0,0,383418,0,0,0,383418,0,0,0,383418,0,0,0,0,0,0.0,20232432.0,0,0,0,0,0,0,0,0,0,0,0,0,33,0,0,0,2,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,32,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,56,0,0,0,0,0,0,0,0,0,0,0,35,0,0,0,5,0,0,0,1,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,112,0,0,0,0,0,0,0,0,0,0,0,32,0,0,0,1,0,0,0,524288.0,0.0,0,0,129024,129024,0,0,129024,129024,0,867,129024,129024,0,44469,129024,129024,0,329,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,44271,129024,129024,0,0,129024,129024,0,282755,129024,129024,0,252,129024,129024,0,194,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,28870,129024,129024,0,1028,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,254005,129024,129024,0,184,129024,129024,524288.0,0.0,44919,0,0,50735498,45279,0,0,50646468,43676,0,0,49912728,46356,0,0,51756838,44515,0,0,50991920,46519,0,0,51569269,45249,0,0,50877078,47001,0,0,52829535,45522,0,0,50806453,46605,0,0,51134122,44836,0,0,50198435,47807,0,0,52253131,46570,0,0,51880148,46198,0,0,51555081,46243,0,0,51244305,48903,0,0,53163787,43505,0,0,50277826,44428,0,0,50385329,44012,0,0,49996201,46836,0,0,51796224,44466,0,0,51221530,45352,0,0,51139723,44477,0,0,50522289,47524,0,0,52596866,45857,0,0,50760312,45356,0,0,50690141,44559,0,0,50145911,47835,0,0,52137322,45600,0,0,51426709,46877,0,0,51645631,45663,0,0,51172232,49009,0,0,53008741,0.0,65591,65625,144,131216,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65646,65538,112,131184,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65568,32,131104,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65537,1,131073,65536,65570,34,131106,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65758,65650,336,131408,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65568,32,131104,65536,65536,0,131072,65536,65536,0,131072,65536,65539,3,131075,65591,65537,56,131128,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131184,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131296,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131128,0,131072,1138008,0,524288,3670016,3663241,224,6551,1048576,33554432.0,33554432.0,0.0,33554432.0,30159785.0,28514113.0,0.0,524288.0,218062,536618,8701,915,0,383803,4195052.0,0.0,2097594.0,2097458.0,1048576,1048576,0,524288,0,524288,7340032,0,0.0,0.0,104.0,8388608.0,29506608.0,2097152.0,0.0,202077,0,1205,383924,0,753.0,4194304.0,0.0,2064387.0,25690112,9437184,0,0,0,0,0,0,13293.0,8242385.0,0.0,8388608.0,2097152.0,4194304.0,10077853,0,0,8806,4128768.0,4128768.0,0.0,1497824.0,0,0,0,0,0,0,5767168,1048576,315747814.0,0.0,1472527970.0,0.0,41.0,0.0,0,0,373577,0.0,0.0,1486799.0,0.0,3670016,524288,0,0,0,2621440,524288,176495595,4194304.0,0.0,0.0,0.0,0.0,1226229.0,0,0,0.0,313.0,0.0,610.0,42562647,24117248,0,0,9437184,11010048,0,3145728,0.0,0.0,0.0,0.0,0.0,0.0,0,1572864,0.0,0.0,0.0,178227.0,524288,524288,0,3670016,7340032,603979776,4718592,0,0.0,0.0,0.0,0.0,0.0,0.0,524288,0,2064384.0,0.0,2031623.0,0.0,0,0,524288,0,0,0,0,33554432,0.0,4194304.0,0.0,19066872.0,0.0,0.0,141.0,4128768.0,657400.0,1664424767.0,17175675271897,17193547618085,17193547856485,17175823629047
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,197746,197746,32768,256,0,0,12,24,13888,0x0,0x7f9f95e23f80,256392,152622,512,1307660,1590782,504,56,0,32048,32048,2215655.0,136977.0,201.0,0.0,33101.0,29898.0,130720.0,111896.0,256384,159610,32048,0,32048,0,1025536.0,361857.0,0.0,0.0,0,0,560,0,8192,6148,56,1988,23565,0.0,0.0,0.0,4096.0,29216.0,27674.0,0.0,4096.0,128,512,302,32631,2304,0,0.0,59.0,0.0,4600.0,0,0,0,0,0,1024,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,16289.0,4096.0,0,34041,0,0,0,34041,0,0,0,34041,0,0,0,34041,0,0,0,34041,0,0,0,34041,0,0,0,34041,0,0,0,34041,0,0,0,34041,0,0,0,34041,0,0,0,34041,0,0,0,34041,0,0,0,34041,0,0,0,34041,0,0,0,34041,0,0,0,34041,0,0,0,34041,0,0,0,34041,0,0,0,34041,0,0,0,34041,0,0,0,34041,0,0,0,34041,0,0,0,34041,0,0,0,34041,0,0,0,34041,0,0,0,34041,0,0,0,34041,0,0,0,34041,0,0,0,34041,0,0,0,34041,0,0,0,34041,0,0,0,34041,0,0,0,0,0,0.0,0.0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,257,0,0,0,258,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,312,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,4096.0,4096.0,0,83020,0,0,0,104972,0,0,0,94215,0,0,0,83234,0,0,0,79549,0,0,0,79290,0,0,0,80412,0,0,0,86637,0,0,0,77977,0,0,0,75861,0,0,0,76370,0,0,0,83107,0,0,0,82699,0,0,0,80583,0,0,0,81854,0,0,0,85294,0,0,0,83379,0,0,0,83124,0,0,0,83477,0,0,0,83224,0,0,0,77392,0,0,0,81376,0,0,0,79317,0,0,0,89032,0,0,0,78849,0,0,0,79175,0,0,0,77812,0,0,0,84448,0,0,0,79547,0,0,0,86483,0,0,0,662221,0,0,0,86953,0,0,0.0,0.0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4096.0,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,222,130,352,352,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,222,130,352,352,0,128,128,128,0,128,128,128,0,129,129,129,0,129,129,129,0,128,128,128,0,128,128,128,0,128,128,128,0,184,184,184,55,129,184,184,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,129,129,129,0,128,128,128,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,352,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,352,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,184,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,652,0,0,512,0,56,456,0,65536.0,65536.0,65536.0,0.0,0.0,0.0,0.0,0.0,6,518,11515,1032,0,31171,4659.0,0.0,499.0,4160.0,512,0,0,0,4096,4096,512,0,0.0,0.0,104.0,16384.0,0.0,16384.0,4096.0,0,0,1362,31387,0,4659.0,0.0,0.0,31.0,35328,26112,0,0,0,0,0,0,104.0,15240.0,0.0,16384.0,16384.0,0.0,0,0,0,29895,0.0,0.0,0.0,0.0,0,0,0,0,0,0,10752,3584,3839702.0,5466986.0,0.0,8192.0,2.0,0.0,0,0,497,0.0,0.0,0.0,0.0,512,4096,0,0,0,512,512,1671227,0.0,0.0,0.0,0.0,0.0,1350.0,0,0,0.0,8262.0,0.0,122.0,19776,32256,0,0,26112,1024,0,1024,0.0,0.0,0.0,0.0,0.0,0.0,0,1024,0.0,0.0,0.0,52660.0,4096,0,4096,512,512,1671168,8192,0,0.0,0.0,0.0,0.0,0.0,0.0,512,0,0.0,0.0,0.0,0.0,0,0,512,0,0,0,0,32768,8192.0,0.0,0.0,110290.0,0.0,4096.0,8206.0,0.0,3364520.0,0.0,17175829843737,17193552660320,17193552673760,17175830329053
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,197746,197746,4194304,256,0,0,12,24,14336,0x7f9f98d2d380,0x7f9f95e23fc0,1309832,1203950,65536,15572549,71135105,392,56,0,163728,163728,15882438.0,14481525.0,24565.0,510148.0,12611430.0,12172531.0,14474526.0,12336466.0,1309824,1210882,163728,0,163728,0,5239296.0,4726257.0,0.0,0.0,0,0,448,0,917504,912779,0,4725,152708,0.0,0.0,0.0,524288.0,12817192.0,12785400.0,2287.0,524288.0,16384,65536,302,163594,2270,0,0.0,183.0,0.0,1048968.0,0,0,0,0,0,131072,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,10712803.0,524288.0,0,164664,0,0,0,164664,0,0,0,164664,0,0,0,164664,0,0,0,164664,0,0,0,164664,0,0,0,164664,0,0,0,164664,0,0,0,164664,0,0,0,164664,0,0,0,164664,0,0,0,164664,0,0,0,164664,0,0,0,164664,0,0,0,164664,0,0,0,164664,0,0,0,164664,0,0,0,164664,0,0,0,164664,0,0,0,164664,0,0,0,164664,0,0,0,164664,0,0,0,164664,0,0,0,164664,0,0,0,164664,0,0,0,164664,0,0,0,164664,0,0,0,164664,0,0,0,164664,0,0,0,164664,0,0,0,164664,0,0,0,164664,0,0,0,0,0,0.0,0.0,65536,0,4646,0,65536,0,13742,0,65536,0,8236,0,65536,0,20698,0,65536,0,13313,0,65536,0,22774,0,65536,0,9572,0,65536,0,15238,0,65536,0,22265,0,65536,0,6404,0,65536,0,19740,0,65536,0,21760,0,65536,0,10346,0,65536,0,6140,0,65536,0,7558,0,65536,0,48057,0,65536,0,24215,0,65536,0,29530,0,65536,0,24889,0,65536,0,4648,0,65538,0,11982,0,65596,0,7929,0,65537,0,6193,0,65540,0,9851,0,65540,0,3736,0,65537,0,20468,0,65536,0,7223,0,65592,0,19860,0,65536,0,4970,0,65537,0,10626,0,65599,0,8493,0,65536,0,34665,0,524288.0,524288.0,0,38707416,0,0,0,38299733,0,0,0,40630893,0,0,0,45617510,0,0,0,48756568,0,0,0,46455211,0,0,0,45634043,0,0,0,52267164,0,0,0,49482305,0,0,0,42711080,0,0,0,42244530,0,0,0,40560868,0,0,0,43194777,0,0,0,42448538,0,0,0,42429815,0,0,0,38743964,0,0,0,50137569,0,0,0,47800603,0,0,0,39819134,0,0,0,43740490,0,0,0,48548294,0,0,0,47248965,0,0,0,48495021,0,0,0,39910916,0,0,0,40353888,0,0,0,51055120,0,0,0,36869808,0,0,0,40231824,0,0,0,42923511,0,0,0,40051020,0,0,0,42430487,0,0,0,52654342,0,0,0.0,0.0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,524288.0,0,32769,32769,32769,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32769,32769,32769,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32769,32769,32769,0,32827,32827,32827,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32824,32824,32824,166,32770,32936,32936,222,32770,32992,32992,0,32768,32768,32768,0,32768,32768,32768,0,32830,32830,32830,0,32768,32768,32768,0,32768,32768,32768,0,32769,32769,32769,0,32768,32768,32768,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32936,0,0,32992,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,900709,0,0,65536,63800,56,1680,0,8388608.0,8388608.0,8388608.0,0.0,0.0,0.0,0.0,0.0,123920,146960,10171,2549,0,162704,1049149.0,0.0,388.0,1048761.0,65536,0,0,0,524288,524288,131072,0,0.0,0.0,104.0,2097152.0,0.0,2097152.0,524288.0,44491,0,2791,161409,0,1049153.0,0.0,0.0,31.0,4063232,2883584,0,0,0,0,0,0,6617.0,2027319.0,0.0,2097152.0,2097152.0,0.0,1440217,0,0,13103,0.0,0.0,0.0,0.0,262144,0,0,0,0,0,1507328,458752,1001842532.0,2198854550.0,0.0,2097152.0,68.0,0.0,0,0,150400,0.0,0.0,0.0,0.0,65536,524288,0,0,0,65536,65536,47412687,0.0,0.0,0.0,0.0,0.0,6143.0,0,0,0.0,2097336.0,0.0,354.0,25508952,3735552,0,0,2883584,196608,0,131072,0.0,0.0,0.0,0.0,0.0,0.0,0,131072,0.0,0.0,609007.0,1721136.0,524288,0,524288,65536,131072,184549376,917504,0,0.0,0.0,0.0,0.0,0.0,0.0,65536,0,0.0,0.0,983047.0,0.0,0,0,65536,0,0,0,0,4194304,2097152.0,0.0,0.0,12315314.0,0.0,524288.0,2097287.0,0.0,1464535466.0,0.0,17175831424883,17193552744800,17193552837120,17175832169823
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/prev_analysis/1.csv
index b48547ff1c..98a621eda5 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,3357758.0,3357758.0,3357758.0,7.844267316107299
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,1725919.0,1725919.0,1725919.0,4.032026727938283
 "void benchmark_func<double, 256, 8u, 512u>(double, double*) [clone .kd]",1,1715998.0,1715998.0,1715998.0,4.008849662752793
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/prev_analysis/1001.csv
index f475f954a6..fb5988001a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,494.8622754491018,Instr per wave
 VMEM,7.958083832335329,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,0.0,Instr per wave
 SALU,24.520958083832337,Instr per wave
 SMEM,1.8023952095808384,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/prev_analysis/101.csv
index 8fadc1b7f8..20a5e4b37a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx90a
 mi200
 56
 1638.4
-SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/prev_analysis/1202.csv
index 757d8729b6..db79015fa9 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,18194.473645832724,1859.6133193969727,258320.66766357422,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/prev_analysis/1901.csv
index a4420077d2..f61dfb8098 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,2.0,smem_
 VALU,495.0,valu_
 MFMA,0.0,mfma_
 VMEM,8.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,10.0,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,67894.0,wavefronts_
 Workgroups,16973.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,128.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,0.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,44.0,hbm_rd_
 HBM Wr,0.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,70.0,vl1_coales_
 VL1 Stall,2.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,26.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/prev_analysis/201.csv
index ca51fdd78b..4ded6d05ed 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,58.38404099215452,Pct,100,58.38404099215452
 MFMA Util,0.0,Pct,100,0.0
 VALU Active Threads/Wave,64.0,Threads,64,100.0
 IPC - Issue,1.0,Instr/cycle,5,20.0
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99255025550661,Pct,100,99.99255025550661
 Instr Cache BW,1673.9742993370203,Gb/s,6092.8,27.4746307007783
 Scalar L1D Cache Hit Rate,99.34855885991422,Pct,100,99.34855885991422
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/prev_analysis/602.csv
index fa16d86957..e3ed055490 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,12432435.45508982,0,377177020,Simd
 Insufficient SIMD VGPRs,0.0,0,0,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/prev_analysis/701.csv
index 12250d77c0..db0925a109 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/sysinfo.csv
index 93af180815..fe2873cc76 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-no_roof_dispatches,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:39:32 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+no_roof_dispatches,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:39:32 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/timestamps.csv
index c379ca0ae3..583c998fdc 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_dispatches/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,198689,198689,33554432,256,0,0,4,32,4160,0x0,0x7f85e6804280,17193547592713,17193547618085,17193547856485,17193547944304
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,198689,198689,32768,256,0,0,12,24,13888,0x0,0x7f85e6823f80,17193552644605,17193552660320,17193552673760,17193552690764
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,198689,198689,4194304,256,0,0,12,24,14336,0x7f85e982a380,0x7f85e6823fc0,17193552696214,17193552744800,17193552837120,17193552839250
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/SQ_IFETCH_LEVEL.csv
index 48a2fb14e4..2adedfdc8f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/SQ_IFETCH_LEVEL.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,937517,937522,33554432,256,0,0,8,32,6464,0x0,0x7f87b2804180,500625,500625,524288,6291456,791650,101536536,12076652578802215,12076652824528590,12076652824850349,12076652824961421
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,937517,937522,32768,256,0,0,24,24,12480,0x0,0x7f87b2835100,27666,27666,512,8192,8785,1127396,12076652839172816,12076652839487363,12076652839493923,12076652839502961
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,937517,937522,4194304,256,0,0,24,24,12928,0x7f88e2958900,0x7f87b2835140,212660,212660,65536,917504,148982,19036652,12076652839559796,12076652839791521,12076652839921281,12076652839925366
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/SQ_INST_LEVEL_LDS.csv
index 44dcce1f1d..93047e863c 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/SQ_INST_LEVEL_LDS.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,939318,939323,33554432,256,0,0,8,32,6464,0x0,0x7f08cb804180,0,0,0,12076678613271081,12076678858542679,12076678858868598,12076678858980561
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,939318,939323,32768,256,0,0,24,24,12480,0x0,0x7f08cb835100,0,0,0,12076678873637605,12076678873931677,12076678873937757,12076678873942893
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,939318,939323,4194304,256,0,0,24,24,12928,0x7f09fb937900,0x7f08cb835140,0,0,0,12076678874013995,12076678874227196,12076678874367516,12076678874371540
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/SQ_INST_LEVEL_SMEM.csv
index f07f9022a7..2f03f7c0b1 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/SQ_INST_LEVEL_SMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,938938,938943,33554432,256,0,0,8,32,6464,0x0,0x7fc810804180,4194304,3187018,407850576,12076676098532391,12076676343991333,12076676344316452,12076676344437604
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,938938,938943,32768,256,0,0,24,24,12480,0x0,0x7fc810835100,512,21578,2750664,12076676358884037,12076676359180237,12076676359186957,12076676359192110
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,938938,938943,4194304,256,0,0,24,24,12928,0x7fc91c3e4900,0x7fc810835140,65536,162338,20806568,12076676359250939,12076676359471756,12076676359603916,12076676359607693
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/SQ_INST_LEVEL_VMEM.csv
index a80f2880f2..075162b59a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/SQ_INST_LEVEL_VMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,939129,939134,33554432,256,0,0,8,32,6464,0x0,0x7f3fa8604180,1048576,11046711,1413901440,12076677358683255,12076677603070214,12076677603393093,12076677603500825
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,939129,939134,32768,256,0,0,24,24,12480,0x0,0x7f3fa8635100,4096,111785,14306048,12076677618294063,12076677618593535,12076677618600095,12076677618605041
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,939129,939134,4194304,256,0,0,24,24,12928,0x7f40b4311900,0x7f3fa8635140,524288,10523952,1347106268,12076677618664381,12076677618883934,12076677619022334,12076677619026104
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/SQ_LEVEL_WAVES.csv
index 451cf5dd50..24d2f14605 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/SQ_LEVEL_WAVES.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,939506,939511,33554432,256,0,0,8,32,6464,0x0,0x7faeece04180,502888,502888,16448,4023112,524288,361986460,3820910,0,1462740208,12076679873029846,12076680119463705,12076680119787064,12076680119895196
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,939506,939511,32768,256,0,0,24,24,12480,0x0,0x7faeece35100,27764,27764,20306,222120,512,1164582,77484,0,4672624,12076680134243806,12076680134572980,12076680134579380,12076680134587525
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,939506,939511,4194304,256,0,0,24,24,12928,0x7faff8a38900,0x7faeece35140,217613,217613,19999,1740912,65536,133551548,1569192,0,536021288,12076680134660752,12076680134894099,12076680135026899,12076680135030740
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/pmc_dispatch_info.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/pmc_perf.csv
index cd05aadd27..25ecfc8c51 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBuffer.kd,0,0,0,938251,938256,33554432,256,0,0,8,32,6464,0x0,0x7f0ad8a04180,1048576,0,1048576,9437184,0,4194304,1048576,0,509775,509775,58605419,56002863,169,11811570,55179775,55079304,55947918,54771659,4078200,3891486,509775,0,509775,0,16312800,15448422,0,0,0,0,0,17554377,1048576,0,503584,0,0,0,503584,0,0,0,503584,0,0,0,503584,0,0,0,503584,0,0,0,503584,0,0,0,503584,0,0,0,503584,0,0,0,503584,0,0,0,503584,0,0,0,503584,0,0,0,503584,0,0,0,503584,0,0,0,503584,0,0,0,503584,0,0,0,503584,0,0,0,503584,0,0,0,503584,0,0,0,503584,0,0,0,503584,0,0,0,503584,0,0,0,503584,0,0,0,503584,0,0,0,503584,0,0,0,503584,0,0,0,503584,0,0,0,503584,0,0,0,503584,0,0,0,503584,0,0,0,503584,0,0,0,503584,0,0,0,503584,0,0,0,37062810,72,0,0,0,4,0,0,0,0,0,0,0,48,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,2396,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2593,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,3,0,0,0,43,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2657,0,0,0,0,0,0,0,50,0,0,0,0,0,0,0,2606,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1048576,0,0,261,131072,131072,0,19898,131072,131072,0,0,131072,131072,0,3097250,131072,131072,0,534,131072,131072,0,0,131072,131072,0,0,131072,131072,0,0,131080,131080,0,2805858,131076,131076,0,0,131072,131072,0,0,131072,131072,0,1426,131072,131072,0,0,131076,131076,0,0,131072,131072,0,0,131072,131072,0,3163222,131072,131072,0,0,131076,131076,0,1050,131072,131072,0,0,131072,131072,0,3294515,131072,131072,0,8605,131076,131076,0,502056,131072,131072,0,0,131080,131080,0,0,131076,131076,0,0,131072,131072,0,0,131076,131076,0,794,131072,131072,0,0,131072,131072,0,0,131072,131072,0,0,131076,131076,0,0,131072,131072,0,0,131072,131072,1048576,0,1079,0,0,17564562,848,0,0,17284421,1736,0,0,17062097,1135,0,0,17314441,45538,0,0,29634397,727,0,0,17088060,988,0,0,17988478,861,0,0,18620808,45643,0,0,30024598,836,0,0,17382000,1189,0,0,17183621,1225,0,0,17077880,737,0,0,17310348,846,0,0,17323701,872,0,0,18064686,45818,0,0,30958697,1040,0,0,16806936,893,0,0,16914937,844,0,0,17049048,832,0,0,17022334,47248,0,0,30629855,1227,0,0,17379892,899,0,0,17999887,1799,0,0,18817070,1211,0,0,16983975,1207,0,0,16819679,818,0,0,16833592,1041,0,0,16976329,660,0,0,17513897,1459,0,0,17434783,1169,0,0,17888487,845,0,0,18625666,1048576,131072,131072,0,262144,131260,131124,240,262384,131072,131072,0,262144,131072,131072,0,262144,131072,133620,2548,264692,131072,131072,0,262144,131119,131073,48,262192,131072,131072,0,262144,131072,133596,2524,264668,131072,131072,0,262144,131072,131072,0,262144,131072,131120,48,262192,131072,131072,0,262144,131072,131072,0,262144,131119,131073,48,262192,131072,133721,2649,264793,131072,131072,0,262144,131213,131075,144,262288,131072,131120,48,262192,131072,131072,0,262144,131072,133714,2642,264786,131072,131072,0,262144,131072,131075,3,262147,131072,131072,0,262144,131072,131093,21,262165,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,262144,0,262144,262336,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262288,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,0,0,3145728,524288,32505856,366196373,218723156,114967361,480188,0,0,0,1048576,52501506,52262897,1048576,1048576,131072,524288,685,501812,4452,0,96,10792,0,8388944,32505856,4042344,3834119,57273056,11534336,0,0,14155776,67108864,67108864,0,67108864,54311893,53950144,0,1048576,249632,773920,11988,2878,0,500759,8399792,0,4194727,4205065,13631488,0,3670016,1048576,1048576,0,4194304,9437184,0,0,360,33554432,53922219,4194304,0,0,2904,497484,0,11028,8388608,0,4194359,905969664,6291456,0,0,0,524288,524288,0,15347,16608503,0,16777216,4194304,4194304,0,0,0,16691,4194376,4194376,0,227712,0,0,0,33554432,0,0,0,0,634200374,0,2783193592,0,0,0,0,0,476537,0,0,215700,0,0,8388608,336,144,0,0,0,480,8388608,0,0,0,0,421125,0,0,0,10833,0,21648,0,6291456,6289506,96,2149,1999647,0,0,0,0,0,0,0,0,0,3145728,0,0,0,147257,4194304,4189867,144,4293,2097152,524288,1572864,0,0,0,0,0,0,524288,0,4128844,65536,4063243,0,0,8388608,0,42260640,0,1048576,10841,4194360,13224545,608878216,12076654699947414,12076681005262671,12076681005588108,12076654943855342
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,938251,938256,32768,256,0,0,24,24,12480,0x0,0x7f0ad8a35100,0,4096,4096,512,0,512,4096,0,27760,27760,1449227,569100,252,121248,88941,68800,561020,540354,222080,82441,27760,0,27760,0,888320,198580,0,0,0,0,0,59257,4096,0,27866,0,0,0,27866,0,0,0,27866,0,0,0,27866,0,0,0,27866,0,0,0,27866,0,0,0,27866,0,0,0,27866,0,0,0,27866,0,0,0,27866,0,0,0,27866,0,0,0,27866,0,0,0,27866,0,0,0,27866,0,0,0,27866,0,0,0,27866,0,0,0,27866,0,0,0,27866,0,0,0,27866,0,0,0,27866,0,0,0,27866,0,0,0,27866,0,0,0,27866,0,0,0,27866,0,0,0,27866,0,0,0,27866,0,0,0,27866,0,0,0,27866,0,0,0,27866,0,0,0,27866,0,0,0,27866,0,0,0,27866,0,0,0,0,425,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,376,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,306,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,4096,4096,0,132882,0,0,0,106772,0,0,0,85482,0,0,0,127593,0,0,0,84878,0,0,0,81796,0,0,0,75480,0,0,0,110959,0,0,0,81638,0,0,0,80793,0,0,0,82175,0,0,0,65757,0,0,0,85430,0,0,0,86102,0,0,0,70900,0,0,0,78421,0,0,0,77147,0,0,0,101209,0,0,0,102953,0,0,0,109381,0,0,0,180890,0,0,0,84670,0,0,0,92471,0,0,0,131435,0,0,0,118178,0,0,0,134897,0,0,0,80364,0,0,0,85986,0,0,0,109485,0,0,0,85700,0,0,0,86177,0,0,0,91042,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4096,0,256,256,256,0,304,304,304,0,256,256,256,0,256,256,256,0,257,257,257,0,256,256,256,0,256,256,256,0,256,256,256,0,257,257,257,0,256,256,256,0,256,256,256,0,304,304,304,0,256,256,256,0,256,256,256,235,261,496,496,0,256,256,256,0,256,256,256,0,256,256,256,188,260,448,448,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,377,377,377,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,47,257,304,304,0,256,256,256,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,304,0,0,256,0,0,0,0,512,512,35328,1104392,1000648,67392,11825,0,0,0,4096,151286,148683,4096,4096,128,512,594,27197,4384,0,48,339,0,8624,36352,224280,76677,1050967,26624,0,0,30208,65536,65536,65536,0,0,0,0,0,116,628,12015,2048,0,23677,8891,0,470,8421,1024,0,1024,4096,0,4096,512,512,0,0,360,16384,0,16384,0,0,3222,25146,0,8844,0,0,31,1933312,8192,0,0,0,512,512,0,120,15064,0,16384,16384,0,0,0,0,21076,0,0,0,0,0,0,0,32768,0,0,0,0,11971432,16373370,0,8192,0,0,0,0,695,0,0,0,0,0,1024,432,48,0,0,0,480,0,0,0,0,0,3240,0,0,0,8422,0,440,0,8192,6532,48,1612,1084,0,0,0,0,0,0,0,0,0,2560,0,0,0,50738,512,0,48,464,0,512,0,0,0,0,0,0,0,512,0,0,0,0,0,8192,0,0,441795,0,4096,8373,0,3009963,0,12076654958815410,12076681020777256,12076681020784136,12076654959811272
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,938251,938256,4194304,256,0,0,24,24,12928,0x7f0be46e8900,0x7f0ad8a35140,0,524288,524288,65536,0,65536,524288,0,223082,223082,24858519,23599056,30472,8055376,23236851,23166795,23590176,21430564,1784656,1640169,223082,0,223082,0,7138624,6432951,0,0,0,0,0,20416892,524288,0,223021,0,0,0,223021,0,0,0,223021,0,0,0,223021,0,0,0,223021,0,0,0,223021,0,0,0,223021,0,0,0,223021,0,0,0,223021,0,0,0,223021,0,0,0,223021,0,0,0,223021,0,0,0,223021,0,0,0,223021,0,0,0,223021,0,0,0,223021,0,0,0,223021,0,0,0,223021,0,0,0,223021,0,0,0,223021,0,0,0,223021,0,0,0,223021,0,0,0,223021,0,0,0,223021,0,0,0,223021,0,0,0,223021,0,0,0,223021,0,0,0,223021,0,0,0,223021,0,0,0,223021,0,0,0,223021,0,0,0,223021,0,0,0,0,65705,0,3286,0,65536,0,6648,0,65540,0,10357,0,65536,0,4893,0,65537,0,11848,0,65536,0,798,0,65536,0,6725,0,67841,0,93764,0,65536,0,8283,0,65536,0,2331,0,65536,0,12309,0,65555,0,5590,0,65536,0,1470,0,65536,0,5126,0,65536,0,2329,0,65536,0,6837,0,65536,0,278,0,65536,0,1279,0,65536,0,2081,0,65536,0,14373,0,65536,0,13246,0,65536,0,5680,0,65536,0,7411,0,65536,0,12592,0,65536,0,2317,0,65586,0,657,0,65536,0,5403,0,66994,0,56830,0,65536,0,5575,0,65536,0,6714,0,65540,0,18638,0,65536,0,7366,0,524288,524288,0,31834153,0,0,0,33378676,0,0,0,32329969,0,0,0,37025825,0,0,0,31755841,0,0,0,38313444,0,0,0,29852137,0,0,0,37729684,0,0,0,43093099,0,0,0,33753679,0,0,0,36460898,0,0,0,39460592,0,0,0,31224321,0,0,0,37158029,0,0,0,32266436,0,0,0,49832636,0,0,0,29943844,0,0,0,36612628,0,0,0,33335272,0,0,0,37011792,0,0,0,36851003,0,0,0,37070482,0,0,0,31222416,0,0,0,33247174,0,0,0,33573081,0,0,0,31460694,0,0,0,31763617,0,0,0,33863867,0,0,0,33866224,0,0,0,32817388,0,0,0,32578571,0,0,0,36947968,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,524288,0,65536,65536,65536,0,65584,65584,65584,188,65540,65728,65728,0,65536,65536,65536,0,66545,66545,66545,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65537,65537,65537,0,65536,65536,65536,0,65536,65536,65536,0,65584,65584,65584,0,65536,65536,65536,0,65536,65536,65536,47,65537,65584,65584,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,67502,67502,67502,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65657,65657,65657,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,188,65540,65728,65728,0,65536,65536,65536,65536,0,0,65536,0,0,65728,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65728,0,0,65536,0,0,0,0,65536,65536,4128768,143186145,52051948,86874357,202609,0,0,0,524288,22300326,22292909,524288,524288,16384,65536,734,219934,4119,0,48,3183,0,2097536,4259840,1747752,1576237,23355121,3014656,0,0,3473408,8388608,8388608,8388608,0,0,0,0,0,181049,208972,11864,2081,0,214146,2100811,0,423,2100388,131072,0,131072,524288,0,524288,65536,65536,0,0,360,2097152,0,2097152,31803,0,2893,216920,0,2101069,0,0,31,222298112,917504,0,0,0,65536,65536,0,7604,2018383,0,2097152,2097152,0,754889,757368,0,19746,0,0,0,0,0,0,0,4194304,0,0,0,0,1172489831,2126240898,0,2097152,0,0,0,0,185257,0,0,0,0,0,131072,384,48,0,0,0,432,0,0,0,0,0,2429,0,0,0,2099716,0,5110,0,917504,914305,48,5678,199980,0,0,0,0,0,0,0,0,0,327680,0,0,617598,669936,65536,64048,48,1440,0,65536,0,0,0,0,0,0,0,65536,0,0,0,1966101,0,2097152,0,0,14113924,0,524288,2101778,0,894117635,0,12076654960447616,12076681020852616,12076681020990854,12076654961702009
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/prev_analysis/1.csv
index df42d4b9c8..6fc4336c78 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,6056597.0,6056597.0,6056597.0,9.180250903841973
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4527008.0,4527008.0,4527008.0,6.861785468589016
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 256u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,3053898.0,3053898.0,3053898.0,4.6289277418889165
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/prev_analysis/1001.csv
index ca08330db0..0e3bf5267e 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,46.862275449101794,Instr per wave
 SMEM,1.8083832335329342,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/prev_analysis/101.csv
index 141b2a842a..550a42dc6a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx908
 mi100
 48
 1228.8
-SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/prev_analysis/1202.csv
index 94127ea9c4..71bfca0e37 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,33863.388680509466,2793.856605529785,547886.2246704102,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/prev_analysis/1901.csv
index f9f6184f6d..48525418bb 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,2.0,smem_
 VALU,735.0,valu_
 MFMA,,mfma_
 VMEM,8.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,22.0,br_
 VGPR,24.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,67894.0,wavefronts_
 Workgroups,16973.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,163.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,0.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,44.0,hbm_rd_
 HBM Wr,0.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,70.0,vl1_coales_
 VL1 Stall,33.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,33.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/prev_analysis/2001.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/prev_analysis/201.csv
index 9ee565c4d7..41b8f06d38 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,60.09616022911762,Pct,100,60.09616022911762
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,63.9677650296124,Threads,64,99.94963285876938
 IPC - Issue,0.8437263557468556,Instr/cycle,5,16.874527114937113
-LDS BW,0.0,Gb/sec,23070.72,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,23070.72,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99341238002381,Pct,100,99.99341238002381
 Instr Cache BW,1410.1057376255528,Gb/s,4614.144,30.560505645804568
 Scalar L1D Cache Hit Rate,99.35620448529356,Pct,100,99.35620448529356
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/prev_analysis/602.csv
index ae772f7770..2443a43da9 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,69435.84431137725,0,819270,Simd
 Insufficient SIMD VGPRs,640385.5149700599,0,39580436,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/prev_analysis/701.csv
index d3f1bff5a3..1071413faa 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,23.976047904191617,8,36,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/sysinfo.csv
index 9da7e7eb00..2b7fdb07cf 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-no_roof_invdev,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 11:37:07 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+no_roof_invdev,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 11:37:07 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/timestamps.csv
index dc6102ff58..e5bc888f54 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,939557,939562,33554432,256,0,0,8,32,6464,0x0,0x7f8c5ba04180,12076681005217443,12076681005262671,12076681005588108,12076681005684051
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,939557,939562,32768,256,0,0,24,24,12480,0x0,0x7f8c5ba35100,12076681020673052,12076681020777256,12076681020784136,12076681020790902
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,939557,939562,4194304,256,0,0,24,24,12928,0x7f8d8bce8900,0x7f8c5ba35140,12076681020835384,12076681020852616,12076681020990854,12076681020995582
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/SQ_IFETCH_LEVEL.csv
index 62d14ab8bd..08423d0b84 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/SQ_IFETCH_LEVEL.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,239151,239151,33554432,256,0,0,4,32,4160,0x0,0x7f8d3f204280,379238,379238,524288,4718592,686655,76764596,17882013304921,17881305334850,17882161465692,17882161579382
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,239151,239151,32768,256,0,0,12,24,13888,0x0,0x7f8d3f223f80,33346,33346,512,8192,5742,644124,17882166715465,17882161465692,17882166845065,17882166850062
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,239151,239151,4194304,256,0,0,12,24,14336,0x7f8e422c0380,0x7f8d3f223fc0,169264,169264,65536,917504,141792,15880896,17882166887101,17882166845065,17882167227786,17882167230562
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/SQ_INST_LEVEL_LDS.csv
index 72fe6ba074..b9f2d352db 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/SQ_INST_LEVEL_LDS.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,240999,240999,33554432,256,0,0,4,32,4160,0x0,0x7f04d4e04280,0,0,0,17901353710702,17900633406329,17901502999770,17901503110360
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,240999,240999,32768,256,0,0,12,24,13888,0x0,0x7f04d4e23f80,0,0,0,17901508217074,17901502999770,17901508342818,17901508347461
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,240999,240999,4194304,256,0,0,12,24,14336,0x7f04d7d15380,0x7f04d4e23fc0,0,0,0,17901508382310,17901508342818,17901508706019,17901508708492
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/SQ_INST_LEVEL_SMEM.csv
index d02ce78fff..1041103c8f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/SQ_INST_LEVEL_SMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,238929,238929,33554432,256,0,0,4,32,4160,0x0,0x7fdd84e04280,3670016,2902110,325207384,17881076348658,17852771848170,17881225035805,17881225149595
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,238929,238929,32768,256,0,0,12,24,13888,0x0,0x7fdd84e23f80,512,97748,10939872,17881230308258,17881225035805,17881230441738,17881230446304
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,238929,238929,4194304,256,0,0,12,24,14336,0x7fdd87df7380,0x7fdd84e23fc0,65536,622016,69610472,17881230480554,17881230441738,17881230812299,17881230814635
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/SQ_INST_LEVEL_VMEM.csv
index 2fcae42447..64780af26e 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/SQ_INST_LEVEL_VMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,240777,240777,33554432,256,0,0,4,32,4160,0x0,0x7fc403c04280,524288,5512431,617331268,17900405892256,17898133752894,17900553171013,17900553285333
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,240777,240777,32768,256,0,0,12,24,13888,0x0,0x7fc403c23f80,4096,51758,5797460,17900558432536,17900553171013,17900558566706,17900558571573
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,240777,240777,4194304,256,0,0,12,24,14336,0x7fc40ad3f380,0x7fc403c23fc0,524288,10887755,1219370292,17900558605112,17900558566706,17900558938227,17900558940804
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/SQ_LEVEL_WAVES.csv
index b0e49d29a0..5e9d1337e9 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/SQ_LEVEL_WAVES.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,239373,239373,33554432,256,0,0,4,32,4160,0x0,0x7f891c804280,383462,383462,8974,3067704,524288,241388657,2979571,0,981808900,17882952870682,17882242635587,17883100042547,17883100152907
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,239373,239373,32768,256,0,0,12,24,13888,0x0,0x7f891c823f80,33702,33702,30293,269624,512,1800017,172391,0,7214092,17883105319280,17883100042547,17883105454082,17883105458776
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,239373,239373,4194304,256,0,0,12,24,14336,0x7f891f72c380,0x7f891c823fc0,164239,164239,14020,1313920,65536,85171657,1211511,0,342412204,17883105501405,17883105454082,17883105839043,17883105841617
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/pmc_perf.csv
index 0654060985..d2cf0ac3e1 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDI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],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBufferAligned.kd,0,0,0,240139,240139,33554432,256,0,0,4,32,4160,0x0,0x7f7620204280,3084216,2997507,524288,38945223,243719439,392,224,0,385526,385526,39210280.0,38146935.0,9.0,4150728.0,31290054.0,30922166.0,38126373.0,37567515.0,3082505,3003901,385526,0,385526,0,12336832.0,9453053.0,0.0,0.0,0,0,616,0,4718592,4714872,112,3608,374474,0.0,0.0,0.0,524288.0,28416510.0,27674928.0,7896.0,524288.0,131072,524288,302,383663,2345,0,56.0,305.0,0.0,4194696.0,0,0,0,0,0,7340032,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,20123410.0,524288.0,0,383809,0,0,0,383809,0,0,0,383809,0,0,0,383809,0,0,0,383809,0,0,0,383809,0,0,0,383809,0,0,0,383809,0,0,0,383809,0,0,0,383809,0,0,0,383809,0,0,0,383809,0,0,0,383809,0,0,0,383809,0,0,0,383809,0,0,0,383809,0,0,0,383809,0,0,0,383809,0,0,0,383809,0,0,0,383809,0,0,0,383809,0,0,0,383809,0,0,0,383809,0,0,0,383809,0,0,0,383809,0,0,0,383809,0,0,0,383809,0,0,0,383809,0,0,0,383809,0,0,0,383809,0,0,0,383809,0,0,0,383809,0,0,0,0,0,0.0,21066865.0,0,0,0,0,0,0,0,0,0,0,0,0,34,0,0,0,2,0,0,0,0,0,0,0,112,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,35,0,0,0,61,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,0,0,1,0,0,0,524288.0,0.0,0,44040,129024,129024,0,0,129024,129024,0,283959,129024,129024,0,0,129024,129024,0,333,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,159,129024,129024,0,44951,129024,129024,0,446312,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,166,129024,129024,0,25725,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,887,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,44956,129024,129024,0,0,129024,129024,0,0,129024,129024,0,891,129024,129024,0,187,129024,129024,524288.0,0.0,44838,0,0,50895764,45728,0,0,50785562,44662,0,0,50159552,47741,0,0,51978383,44878,0,0,51091667,46645,0,0,51853049,45934,0,0,51036566,47487,0,0,52711564,44623,0,0,50873259,46045,0,0,51022796,45911,0,0,50766742,47733,0,0,52276740,46393,0,0,51595096,46285,0,0,51590296,45676,0,0,51208717,49084,0,0,53224721,44361,0,0,50520902,45136,0,0,50709162,43964,0,0,50178595,46537,0,0,51893632,45410,0,0,51433671,46073,0,0,51374205,44858,0,0,50897054,48339,0,0,53103235,45533,0,0,51003775,46216,0,0,51071864,46304,0,0,50850069,48132,0,0,52518064,45319,0,0,51529869,47161,0,0,51788132,45847,0,0,51210385,48358,0,0,52987239,0.0,65536,65680,144,131216,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65646,65538,112,131184,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65592,56,131128,65536,65568,32,131104,65591,65537,56,131128,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65537,1,131073,65536,65538,2,131074,65536,65536,0,131072,65536,65572,36,131108,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65758,65538,224,131296,65536,65537,1,131073,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65568,32,131104,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65591,65537,56,131128,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131184,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131296,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131128,0,131072,1033073,0,524288,3670016,3663324,224,6468,1048576,33554432.0,33554432.0,0.0,33554432.0,30472722.0,28826429.0,0.0,524288.0,223406,536207,8815,968,0,386031,4195056.0,0.0,2097594.0,2097462.0,1048576,1048576,0,524288,0,524288,7340032,0,0.0,0.0,104.0,8388608.0,28604891.0,2097152.0,0.0,186884,0,1223,376588,0,749.0,4194304.0,0.0,2064387.0,25690112,9437184,0,0,0,0,0,0,13275.0,8242583.0,0.0,8388608.0,2097152.0,4194304.0,9708950,0,0,8743,4128768.0,4128768.0,0.0,1482081.0,0,0,0,0,0,0,5767168,1048576,312665876.0,0.0,1461849882.0,0.0,51.0,0.0,0,0,370515,0.0,0.0,1448712.0,0.0,3670016,524288,0,0,0,2621440,524288,177353799,4194304.0,0.0,0.0,0.0,0.0,1199893.0,0,0,0.0,309.0,0.0,602.0,42708892,24117248,0,0,9437184,11010048,0,3145728,0.0,0.0,0.0,0.0,0.0,0.0,0,1572864,0.0,0.0,0.0,203550.0,524288,524288,0,3670016,7340032,603979776,4718592,0,0.0,0.0,0.0,0.0,0.0,0.0,524288,0,2064384.0,0.0,2031623.0,0.0,0,0,524288,0,0,0,0,33554432,0.0,4194304.0,0.0,18865746.0,0.0,0.0,142.0,4128768.0,977928.0,1696192627.0,17884374408389,17902181338101,17902181578101,17884524734020
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,240139,240139,32768,256,0,0,12,24,13888,0x0,0x7f7620223f80,262760,162139,512,1371043,1653379,504,56,0,32844,32844,2338713.0,159478.0,208.0,0.0,38585.0,35636.0,153156.0,134320.0,262752,169022,32844,0,32844,0,1051008.0,404285.0,0.0,0.0,0,0,560,0,8192,6141,56,1995,22667,0.0,0.0,0.0,4096.0,33475.0,32146.0,0.0,4096.0,128,512,302,31878,2314,0,0.0,62.0,0.0,4600.0,0,0,0,0,0,1024,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,16713.0,4096.0,0,32951,0,0,0,32951,0,0,0,32951,0,0,0,32951,0,0,0,32951,0,0,0,32951,0,0,0,32951,0,0,0,32951,0,0,0,32951,0,0,0,32951,0,0,0,32951,0,0,0,32951,0,0,0,32951,0,0,0,32951,0,0,0,32951,0,0,0,32951,0,0,0,32951,0,0,0,32951,0,0,0,32951,0,0,0,32951,0,0,0,32951,0,0,0,32951,0,0,0,32951,0,0,0,32951,0,0,0,32951,0,0,0,32951,0,0,0,32951,0,0,0,32951,0,0,0,32951,0,0,0,32951,0,0,0,32951,0,0,0,32951,0,0,0,0,0,0.0,0.0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,260,0,0,0,312,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,257,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,4096.0,4096.0,0,82504,0,0,0,80736,0,0,0,73830,0,0,0,80266,0,0,0,79439,0,0,0,79328,0,0,0,121142,0,0,0,89569,0,0,0,76522,0,0,0,75166,0,0,0,648623,0,0,0,96539,0,0,0,77877,0,0,0,117495,0,0,0,96301,0,0,0,83889,0,0,0,81612,0,0,0,84170,0,0,0,73464,0,0,0,116012,0,0,0,83957,0,0,0,76638,0,0,0,93207,0,0,0,129545,0,0,0,120478,0,0,0,79244,0,0,0,74201,0,0,0,79425,0,0,0,74047,0,0,0,77224,0,0,0,75870,0,0,0,83538,0,0,0.0,0.0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4096.0,0,184,184,184,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,222,130,352,352,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,222,130,352,352,0,129,129,129,0,129,129,129,0,128,128,128,0,129,129,129,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,55,130,185,185,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,352,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,352,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,184,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,654,0,0,512,0,56,456,0,65536.0,65536.0,65536.0,0.0,0.0,0.0,0.0,0.0,8,520,11648,1051,0,31182,4661.0,0.0,499.0,4162.0,512,0,0,0,4096,4096,512,0,0.0,0.0,104.0,16384.0,0.0,16384.0,4096.0,0,0,1447,31066,0,4661.0,0.0,0.0,31.0,35328,26112,0,0,0,0,0,0,104.0,15240.0,0.0,16384.0,16384.0,0.0,0,0,0,30692,0.0,0.0,0.0,0.0,0,0,0,0,0,0,10752,3584,4258406.0,5505946.0,0.0,8192.0,0.0,0.0,0,0,498,0.0,0.0,0.0,0.0,512,4096,0,0,0,512,512,1683461,0.0,0.0,0.0,0.0,0.0,1441.0,0,0,0.0,8261.0,0.0,120.0,16090,32256,0,0,26112,1024,0,1024,0.0,0.0,0.0,0.0,0.0,0.0,0,1024,0.0,0.0,0.0,47693.0,4096,0,4096,512,512,1671168,8192,0,0.0,0.0,0.0,0.0,0.0,0.0,512,0,0.0,0.0,0.0,0.0,0,0,512,0,0,0,0,32768,8192.0,0.0,0.0,119684.0,0.0,4096.0,8206.0,0.0,3322140.0,0.0,17884531006864,17902186371870,17902186385630,17884531485622
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,240139,240139,4194304,256,0,0,12,24,14336,0x7f76231a1380,0x7f7620223fc0,1317432,1212765,65536,15681581,78713879,392,56,0,164678,164678,15997098.0,14515017.0,23275.0,860721.0,13355355.0,13052102.0,14508702.0,12375207.0,1317424,1219558,164678,0,164678,0,5269696.0,4730650.0,0.0,0.0,0,0,448,0,917504,913935,1,3568,154276,0.0,0.0,0.0,524288.0,13090479.0,13061010.0,2156.0,524288.0,16384,65536,302,165152,2319,0,0.0,185.0,0.0,1048968.0,0,0,0,0,0,131072,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,9683259.0,524288.0,0,171559,0,0,0,171559,0,0,0,171559,0,0,0,171559,0,0,0,171559,0,0,0,171559,0,0,0,171559,0,0,0,171559,0,0,0,171559,0,0,0,171559,0,0,0,171559,0,0,0,171559,0,0,0,171559,0,0,0,171559,0,0,0,171559,0,0,0,171559,0,0,0,171559,0,0,0,171559,0,0,0,171559,0,0,0,171559,0,0,0,171559,0,0,0,171559,0,0,0,171559,0,0,0,171559,0,0,0,171559,0,0,0,171559,0,0,0,171559,0,0,0,171559,0,0,0,171559,0,0,0,171559,0,0,0,171559,0,0,0,171559,0,0,0,0,0,0.0,0.0,65536,0,19959,0,65537,0,26372,0,65536,0,19817,0,65538,0,27846,0,65536,0,17183,0,65536,0,12564,0,65649,0,16080,0,65536,0,26450,0,65536,0,32783,0,65536,0,21078,0,65536,0,16678,0,65536,0,18993,0,65537,0,20302,0,65536,0,10178,0,65536,0,15687,0,65536,0,19513,0,65537,0,14989,0,65536,0,11759,0,65536,0,16999,0,65536,0,17487,0,65537,0,11705,0,65595,0,21453,0,65539,0,16440,0,65539,0,25609,0,65540,0,12605,0,65536,0,19262,0,65537,0,23085,0,65536,0,11199,0,65536,0,17752,0,65536,0,21635,0,65595,0,25115,0,65536,0,27947,0,524288.0,524288.0,0,47201992,0,0,0,40670016,0,0,0,40655638,0,0,0,48004062,0,0,0,48088757,0,0,0,47398506,0,0,0,46243613,0,0,0,46984412,0,0,0,40490741,0,0,0,40656359,0,0,0,41213472,0,0,0,41978647,0,0,0,41246388,0,0,0,42158405,0,0,0,39863030,0,0,0,46364327,0,0,0,43442509,0,0,0,48020056,0,0,0,41013922,0,0,0,47892713,0,0,0,41912404,0,0,0,46928479,0,0,0,47992355,0,0,0,40128178,0,0,0,39506053,0,0,0,42066921,0,0,0,40691603,0,0,0,42954724,0,0,0,46325778,0,0,0,42143312,0,0,0,43376783,0,0,0,43198419,0,0,0.0,0.0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,524288.0,0,32825,32825,32825,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32770,32770,32770,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32769,32769,32769,0,32769,32769,32769,0,32768,32768,32768,0,32828,32828,32828,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,166,32771,32937,32937,222,32770,32992,32992,0,32768,32768,32768,0,32768,32768,32768,0,32831,32831,32831,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32936,0,0,32992,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,904932,0,0,65536,63800,56,1680,0,8388608.0,8388608.0,8388608.0,0.0,0.0,0.0,0.0,0.0,124490,147240,10126,2494,0,162239,1049148.0,0.0,388.0,1048760.0,65536,0,0,0,524288,524288,131072,0,0.0,0.0,104.0,2097152.0,0.0,2097152.0,524288.0,41788,0,2806,162667,0,1049158.0,0.0,0.0,31.0,4063232,2883584,0,0,0,0,0,0,6582.0,2028513.0,0.0,2097152.0,2097152.0,0.0,1397459,0,0,13926,0.0,0.0,0.0,0.0,262144,0,0,0,0,0,1507328,458752,977011952.0,2248630907.0,0.0,2097152.0,127.0,0.0,0,0,148650,0.0,0.0,0.0,0.0,65536,524288,0,0,0,65536,65536,45238176,0.0,0.0,0.0,0.0,0.0,10412.0,0,0,0.0,2097322.0,0.0,326.0,31855107,3735552,0,0,2883584,196608,0,131072,0.0,0.0,0.0,0.0,0.0,0.0,0,131072,0.0,0.0,429711.0,1402589.0,524288,0,524288,65536,131072,184549376,917504,0,0.0,0.0,0.0,0.0,0.0,0.0,65536,0,0.0,0.0,983047.0,0.0,0,0,65536,0,0,0,0,4194304,2097152.0,0.0,0.0,12339745.0,0.0,524288.0,2097287.0,0.0,1484892706.0,0.0,17884532580075,17902186457151,17902186549631,17884533338506
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/prev_analysis/1.csv
index 3f7969c6f1..2d5d42ef52 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,3358247.0,3358247.0,3358247.0,7.841107693779027
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,1724964.0,1724964.0,1724964.0,4.027585967289435
 "void benchmark_func<double, 256, 8u, 512u>(double, double*) [clone .kd]",1,1715683.0,1715683.0,1715683.0,4.005915935125047
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/prev_analysis/1001.csv
index f475f954a6..fb5988001a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,494.8622754491018,Instr per wave
 VMEM,7.958083832335329,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,0.0,Instr per wave
 SALU,24.520958083832337,Instr per wave
 SMEM,1.8023952095808384,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/prev_analysis/101.csv
index c71bf34ae1..e22f54e2a9 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx90a
 mi200
 56
 1638.4
-SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/prev_analysis/1202.csv
index 64613a88ac..6c428aee9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,18461.74683014647,1859.431755065918,258324.11932373047,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/prev_analysis/1901.csv
index 3f118c6484..b1dfdc687d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,2.0,smem_
 VALU,495.0,valu_
 MFMA,0.0,mfma_
 VMEM,8.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,10.0,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,67894.0,wavefronts_
 Workgroups,16973.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,128.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,0.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,44.0,hbm_rd_
 HBM Wr,0.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,70.0,vl1_coales_
 VL1 Stall,2.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,26.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/prev_analysis/201.csv
index cb3fdfc7a2..61b621be06 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,58.39854293391994,Pct,100,58.39854293391994
 MFMA Util,0.0,Pct,100,0.0
 VALU Active Threads/Wave,64.0,Threads,64,100.0
 IPC - Issue,1.0,Instr/cycle,5,20.0
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99254367534697,Pct,100,99.99254367534697
 Instr Cache BW,1672.586818855879,Gb/s,6092.8,27.451858240150322
 Scalar L1D Cache Hit Rate,99.3485588607437,Pct,100,99.3485588607437
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/prev_analysis/602.csv
index 70947418d6..b1423265fa 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,12753962.2754491,0,376423830,Simd
 Insufficient SIMD VGPRs,0.0,0,0,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/prev_analysis/701.csv
index 12250d77c0..db0925a109 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/sysinfo.csv
index 052d196303..6d948a2527 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-no_roof_invdev,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:51:21 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+no_roof_invdev,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:51:21 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/timestamps.csv
index 25e0b0209e..0bfe8275c7 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_invdev/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,241082,241082,33554432,256,0,0,4,32,4160,0x0,0x7fc858804280,17902181312910,17902181338101,17902181578101,17902181695071
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,241082,241082,32768,256,0,0,12,24,13888,0x0,0x7fc858823f80,17902186356686,17902186371870,17902186385630,17902186404015
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,241082,241082,4194304,256,0,0,12,24,14336,0x7fc85b8fa380,0x7fc858823fc0,17902186408295,17902186457151,17902186549631,17902186551831
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/SQ_IFETCH_LEVEL.csv
index 3e2aadafa9..37374cdee1 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/SQ_IFETCH_LEVEL.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,891955,891960,33554432,256,0,0,8,32,6464,0x0,0x7f0b04c04180,504049,504049,524288,6291456,792157,101383004,12075771750480474,12075772016597788,12075772016921466,12075772017053738
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,891955,891960,32768,256,0,0,24,24,12480,0x0,0x7f0b04c35100,27910,27910,512,8192,8828,1126004,12075772031449973,12075772031764391,12075772031770791,12075772031775408
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,891955,891960,4194304,256,0,0,24,24,12928,0x7f0c1087f900,0x7f0b04c35140,224283,224283,65536,917504,141121,18035380,12075772031837984,12075772032080069,12075772032216708,12075772032220555
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/SQ_INST_LEVEL_LDS.csv
index c7f9b8d725..a1bb14debf 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/SQ_INST_LEVEL_LDS.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,893755,893760,33554432,256,0,0,8,32,6464,0x0,0x7fd889a04180,0,0,0,12075798230651999,12075798476719297,12075798477042655,12075798477156377
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,893755,893760,32768,256,0,0,24,24,12480,0x0,0x7fd889a35100,0,0,0,12075798492176060,12075798492479285,12075798492485525,12075798492496045
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,893755,893760,4194304,256,0,0,24,24,12928,0x7fd995625900,0x7fd889a35140,0,0,0,12075798492547180,12075798492769363,12075798492906962,12075798492910144
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/SQ_INST_LEVEL_SMEM.csv
index ef2df8b2ab..749863bf08 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/SQ_INST_LEVEL_SMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,893377,893382,33554432,256,0,0,8,32,6464,0x0,0x7f5d85c04180,4194304,3175830,406074984,12075795672823739,12075795919169304,12075795919493302,12075795919606594
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,893377,893382,32768,256,0,0,24,24,12480,0x0,0x7f5d85c35100,512,21972,2820736,12075795934016855,12075795934318833,12075795934325553,12075795934330968
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,893377,893382,4194304,256,0,0,24,24,12928,0x7f5e918f2900,0x7f5d85c35140,65536,169716,21725344,12075795934396590,12075795934607791,12075795934742351,12075795934746340
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/SQ_INST_LEVEL_VMEM.csv
index 12ca4f5f77..cbf2a8e1a1 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/SQ_INST_LEVEL_VMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,893567,893572,33554432,256,0,0,8,32,6464,0x0,0x7f2a3cc04180,1048576,11154568,1428377696,12075796935392627,12075797180760701,12075797181084059,12075797181207263
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,893567,893572,32768,256,0,0,24,24,12480,0x0,0x7f2a3cc35100,4096,117082,14996888,12075797195755189,12075797196092310,12075797196098389,12075797196117232
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,893567,893572,4194304,256,0,0,24,24,12928,0x7f2b487e7900,0x7f2a3cc35140,524288,10184761,1303631264,12075797196165833,12075797196466868,12075797196605907,12075797196611220
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/SQ_LEVEL_WAVES.csv
index cccb1c4265..b75d16ac17 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/SQ_LEVEL_WAVES.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,893945,893950,33554432,256,0,0,8,32,6464,0x0,0x7f2445604180,503507,503507,15894,4028064,524288,367258848,3824059,0,1483856936,12075799494872357,12075799740229344,12075799740552542,12075799740660744
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,893945,893950,32768,256,0,0,24,24,12480,0x0,0x7f2445635100,27892,27892,20589,223144,512,1120452,75556,0,4495960,12075799755260757,12075799755576709,12075799755583109,12075799755591562
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,893945,893950,4194304,256,0,0,24,24,12928,0x7f25512c8900,0x7f2445635140,218956,218956,22340,1751656,65536,150297970,1575643,0,603009688,12075799755658396,12075799755902148,12075799756035107,12075799756039494
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/pmc_dispatch_info.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/pmc_perf.csv
index 7b91386a52..a393a6ec42 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBuffer.kd,0,0,0,892691,892696,33554432,256,0,0,8,32,6464,0x0,0x7f0772404180,1048576,0,1048576,9437184,0,4194304,1048576,0,501390,501390,57531161,55266835,164,12649226,54525818,54434372,55231450,54060753,4011120,3819872,501390,0,501390,0,16044480,15231137,0,0,0,0,0,17396315,1048576,0,505095,0,0,0,505095,0,0,0,505095,0,0,0,505095,0,0,0,505095,0,0,0,505095,0,0,0,505095,0,0,0,505095,0,0,0,505095,0,0,0,505095,0,0,0,505095,0,0,0,505095,0,0,0,505095,0,0,0,505095,0,0,0,505095,0,0,0,505095,0,0,0,505095,0,0,0,505095,0,0,0,505095,0,0,0,505095,0,0,0,505095,0,0,0,505095,0,0,0,505095,0,0,0,505095,0,0,0,505095,0,0,0,505095,0,0,0,505095,0,0,0,505095,0,0,0,505095,0,0,0,505095,0,0,0,505095,0,0,0,505095,0,0,0,37402523,48,0,0,0,5,0,0,0,1,0,0,0,2676,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,20,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,1,0,0,0,2565,0,0,0,0,0,0,0,4,0,0,0,0,0,0,0,2734,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,48,0,0,0,0,0,0,0,0,0,0,0,4,0,0,0,0,0,0,0,2617,0,0,0,1048576,0,0,0,131076,131076,0,19880,131072,131072,0,0,131072,131072,0,3202546,131072,131072,0,272,131072,131072,0,0,131072,131072,0,0,131080,131080,0,0,131076,131076,0,7332,131072,131072,0,0,131072,131072,0,0,131076,131076,0,0,131072,131072,0,0,131072,131072,0,262,131072,131072,0,0,131080,131080,0,2998683,131072,131072,0,0,131072,131072,0,1306,131072,131072,0,0,131072,131072,0,3168438,131076,131076,0,0,131072,131072,0,0,131072,131072,0,0,131072,131072,0,0,131072,131072,0,539783,131078,131078,0,0,131076,131076,0,815,131076,131076,0,0,131080,131080,0,277,131072,131072,0,0,131076,131076,0,1540,131072,131072,0,3098570,131072,131072,1048576,0,829,0,0,17095868,694,0,0,17201775,1082,0,0,17316375,1637,0,0,17380868,844,0,0,17351999,906,0,0,17607568,860,0,0,17834507,814,0,0,18431996,1002,0,0,17497463,1216,0,0,17550295,1080,0,0,16840678,51802,0,0,30422699,898,0,0,17456869,43592,0,0,28977107,1145,0,0,18095880,1025,0,0,18532759,678,0,0,16890779,44395,0,0,29846295,1533,0,0,16975796,1516,0,0,17176522,871,0,0,17340827,853,0,0,17522234,942,0,0,17942225,50534,0,0,31650723,1512,0,0,16721596,888,0,0,16821656,1106,0,0,16599296,1548,0,0,16916106,822,0,0,17271867,842,0,0,17657311,1208,0,0,17839029,899,0,0,18538981,1048576,131119,131073,48,262192,131260,131076,192,262336,131072,131073,1,262145,131072,131096,24,262168,131072,131072,0,262144,131072,131072,0,262144,131072,131073,1,262145,131072,133707,2635,264779,131072,131120,48,262192,131072,131072,0,262144,131119,131073,48,262192,131072,133735,2663,264807,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131213,131075,144,262288,131072,131072,0,262144,131072,131072,0,262144,131072,131075,3,262147,131072,131072,0,262144,131072,131120,48,262192,131072,131072,0,262144,131072,131072,0,262144,131072,131120,48,262192,131072,131072,0,262144,131072,133671,2599,264743,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,133658,2586,264730,262144,0,262144,262336,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262288,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,0,0,3145728,524288,32505856,374197525,217420697,124270972,477879,0,0,0,1048576,52901284,52707528,1048576,1048576,131072,524288,757,499700,4114,0,96,10720,0,8388944,32505856,4020800,3826819,57246750,11534336,0,0,14155776,67108864,67108864,0,67108864,54305416,53930383,0,1048576,242528,766816,11076,1968,0,498489,8399673,0,4194727,4204946,13631488,0,3670016,1048576,1048576,0,4194304,9437184,0,0,360,33554432,53823935,4194304,0,0,2394,497909,0,10791,8388608,0,4194367,905969664,6291456,0,0,0,524288,524288,0,15330,16608747,0,16777216,4194304,4194304,0,0,0,17567,4194348,4194348,0,215380,0,0,0,33554432,0,0,0,0,636404063,0,2785691367,0,0,0,0,0,475964,0,0,221994,0,0,8388608,336,144,0,0,0,480,8388608,0,0,0,0,344766,0,0,0,10712,0,21406,0,6291456,6289401,96,2247,1939779,0,0,0,0,0,0,0,0,0,3145728,0,0,0,155665,4194304,4189855,144,4305,2097152,524288,1572864,0,0,0,0,0,0,524288,0,4128847,65533,4063246,0,0,8388608,0,42340815,0,1048576,10730,4194397,13203756,605436802,12075773882416693,12075800624292466,12075800624617742,12075774127615594
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,892691,892696,32768,256,0,0,24,24,12480,0x0,0x7f0772435100,0,4096,4096,512,0,512,4096,0,29414,29414,1536107,632656,225,152321,89352,71400,624616,604207,235312,88227,29414,0,29414,0,941248,206301,0,0,0,0,0,59366,4096,0,28169,0,0,0,28169,0,0,0,28169,0,0,0,28169,0,0,0,28169,0,0,0,28169,0,0,0,28169,0,0,0,28169,0,0,0,28169,0,0,0,28169,0,0,0,28169,0,0,0,28169,0,0,0,28169,0,0,0,28169,0,0,0,28169,0,0,0,28169,0,0,0,28169,0,0,0,28169,0,0,0,28169,0,0,0,28169,0,0,0,28169,0,0,0,28169,0,0,0,28169,0,0,0,28169,0,0,0,28169,0,0,0,28169,0,0,0,28169,0,0,0,28169,0,0,0,28169,0,0,0,28169,0,0,0,28169,0,0,0,28169,0,0,0,0,304,0,0,0,257,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,376,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,261,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,4096,4096,0,83228,0,0,0,100996,0,0,0,102854,0,0,0,87853,0,0,0,93497,0,0,0,104230,0,0,0,93628,0,0,0,78513,0,0,0,167267,0,0,0,79354,0,0,0,90728,0,0,0,69381,0,0,0,98822,0,0,0,88504,0,0,0,79854,0,0,0,69957,0,0,0,82164,0,0,0,122285,0,0,0,64512,0,0,0,84279,0,0,0,120026,0,0,0,132144,0,0,0,107145,0,0,0,87679,0,0,0,114917,0,0,0,180217,0,0,0,78539,0,0,0,90022,0,0,0,186960,0,0,0,115688,0,0,0,96513,0,0,0,106298,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4096,0,256,256,256,0,256,256,256,0,257,257,257,0,377,377,377,0,256,256,256,0,256,256,256,0,257,257,257,0,256,256,256,0,256,256,256,0,256,256,256,47,257,304,304,0,256,256,256,0,256,256,256,0,256,256,256,188,260,448,448,0,256,256,256,0,256,256,256,0,256,256,256,188,260,448,448,0,256,256,256,0,256,256,256,0,256,256,256,0,304,304,304,0,256,256,256,0,256,256,256,0,304,304,304,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,47,257,304,304,0,256,256,256,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,304,0,0,256,0,0,0,0,512,512,35328,1067587,1014708,16527,11053,0,0,0,4096,67156,64162,4096,4096,128,512,623,26245,4193,0,48,172,0,8624,36352,214336,73158,1021935,26624,0,0,30208,65536,65536,65536,0,0,0,0,0,115,627,11261,2007,0,22674,8843,0,470,8373,1024,0,1024,4096,0,4096,512,512,0,0,360,16384,0,16384,0,0,2416,25587,0,8963,0,0,31,1933312,8192,0,0,0,512,512,0,120,15064,0,16384,16384,0,0,0,0,20864,0,0,0,0,0,0,0,32768,0,0,0,0,11992520,16793314,0,8192,0,0,0,0,697,0,0,0,0,0,1024,432,48,0,0,0,480,0,0,0,0,0,3110,0,0,0,8422,0,440,0,8192,6526,48,1618,1066,0,0,0,0,0,0,0,0,0,2560,0,0,0,53666,512,0,48,464,0,512,0,0,0,0,0,0,0,512,0,0,0,0,0,8192,0,0,328044,0,4096,8374,0,2990140,0,12075774142493624,12075800639194481,12075800639201361,12075774143470139
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,892691,892696,4194304,256,0,0,24,24,12928,0x7f087dfa8900,0x7f0772435140,0,524288,524288,65536,0,65536,524288,0,227685,227685,25214657,23924314,30521,5825865,22663360,22505743,23899196,21732186,1821480,1664991,227685,0,227685,0,7285920,6560291,0,0,0,0,0,19708395,524288,0,223305,0,0,0,223305,0,0,0,223305,0,0,0,223305,0,0,0,223305,0,0,0,223305,0,0,0,223305,0,0,0,223305,0,0,0,223305,0,0,0,223305,0,0,0,223305,0,0,0,223305,0,0,0,223305,0,0,0,223305,0,0,0,223305,0,0,0,223305,0,0,0,223305,0,0,0,223305,0,0,0,223305,0,0,0,223305,0,0,0,223305,0,0,0,223305,0,0,0,223305,0,0,0,223305,0,0,0,223305,0,0,0,223305,0,0,0,223305,0,0,0,223305,0,0,0,223305,0,0,0,223305,0,0,0,223305,0,0,0,223305,0,0,0,0,65584,0,5442,0,65537,0,1044,0,65541,0,14520,0,65536,0,6728,0,65536,0,17973,0,65536,0,1079,0,65536,0,7058,0,65536,0,13014,0,65656,0,20826,0,65536,0,9193,0,65536,0,40040,0,65536,0,22334,0,65536,0,6530,0,65537,0,45814,0,65537,0,13416,0,65897,0,34262,0,65536,0,3734,0,65536,0,31137,0,65536,0,26249,0,68052,0,92078,0,65536,0,9193,0,65536,0,3035,0,65536,0,6015,0,65536,0,2980,0,65536,0,4264,0,65536,0,17174,0,65536,0,6120,0,65536,0,7472,0,65536,0,52202,0,65536,0,11063,0,65540,0,17498,0,65536,0,30552,0,524288,524288,0,35475628,0,0,0,37999008,0,0,0,35570770,0,0,0,36778407,0,0,0,38476614,0,0,0,37315783,0,0,0,33696538,0,0,0,40839283,0,0,0,40979736,0,0,0,38569960,0,0,0,36341277,0,0,0,34970384,0,0,0,34416081,0,0,0,38943931,0,0,0,33074023,0,0,0,39349212,0,0,0,35274959,0,0,0,30874611,0,0,0,36007774,0,0,0,55280294,0,0,0,38905762,0,0,0,37863635,0,0,0,36973883,0,0,0,40907964,0,0,0,43851171,0,0,0,45609346,0,0,0,38342391,0,0,0,39477129,0,0,0,44569937,0,0,0,42135128,0,0,0,37046119,0,0,0,40601419,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,524288,0,65536,65536,65536,0,65536,65536,65536,188,65541,65729,65729,0,65657,65657,65657,0,65536,65536,65536,0,65536,65536,65536,0,65537,65537,65537,0,67776,67776,67776,0,65536,65536,65536,0,65536,65536,65536,47,65537,65584,65584,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65584,65584,65584,0,65536,65536,65536,0,65536,65536,65536,0,65584,65584,65584,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,188,65540,65728,65728,0,67003,67003,67003,65536,0,0,65536,0,0,65728,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65728,0,0,65536,0,0,0,0,65536,65536,4128768,120897844,48709362,67928642,202599,0,0,0,524288,21678685,21664250,524288,524288,16384,65536,787,219238,3991,0,48,3574,0,2097536,4259840,1705744,1543017,22878147,3014656,0,0,3473408,8388608,8388608,8388608,0,0,0,0,0,184267,210754,11578,2037,0,209258,2099805,0,423,2099382,131072,0,131072,524288,0,524288,65536,65536,0,0,360,2097152,0,2097152,37118,0,2382,210791,0,2099393,0,0,31,222298112,917504,0,0,0,65536,65536,0,7573,2019437,0,2097152,2097152,0,735616,738059,0,20613,0,0,0,0,0,0,0,4194304,0,0,0,0,1005754461,1643756705,0,2097152,0,0,0,0,196846,0,0,0,0,0,131072,384,48,0,0,0,432,0,0,0,0,0,13407,0,0,0,2102165,0,10008,0,917504,914768,48,7455,180480,0,0,0,0,0,0,0,0,0,327680,0,0,408754,462236,65536,64048,48,1440,0,65536,0,0,0,0,0,0,0,65536,0,0,0,1966093,0,2097152,0,0,16607814,0,524288,2100211,0,1065408703,0,12075774144104678,12075800639261520,12075800639392399,12075774145356264
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/prev_analysis/1.csv
index 15a38e6c5e..33488e8333 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,6052429.0,6052429.0,6052429.0,9.172677802718628
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4526202.0,4526202.0,4526202.0,6.859624890439964
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 256u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,3051495.0,3051495.0,3051495.0,4.624652424936645
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/prev_analysis/1001.csv
index ca08330db0..0e3bf5267e 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,46.862275449101794,Instr per wave
 SMEM,1.8083832335329342,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/prev_analysis/101.csv
index 092ee5ef25..dc8308fcb4 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx908
 mi100
 48
 1228.8
-SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/prev_analysis/1202.csv
index 96187fbe03..4d2ddadb92 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,33392.83843176379,2854.900550842285,547857.0892944336,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/prev_analysis/1901.csv
index f1f8587015..aa44ffa8f5 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,2.0,smem_
 VALU,735.0,valu_
 MFMA,,mfma_
 VMEM,8.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,22.0,br_
 VGPR,24.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,67894.0,wavefronts_
 Workgroups,16973.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,163.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,0.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,44.0,hbm_rd_
 HBM Wr,0.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,70.0,vl1_coales_
 VL1 Stall,29.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,35.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/prev_analysis/2001.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/prev_analysis/201.csv
index 817929432b..3f689471e8 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,59.04454912314589,Pct,100,59.04454912314589
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,63.967704561105116,Threads,64,99.94953837672675
 IPC - Issue,0.843725669981346,Instr/cycle,5,16.87451339962692
-LDS BW,0.0,Gb/sec,23070.72,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,23070.72,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99338428109172,Pct,100,99.99338428109172
 Instr Cache BW,1408.3939061532603,Gb/s,4614.144,30.523405991517826
 Scalar L1D Cache Hit Rate,99.35620448523463,Pct,100,99.35620448523463
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/prev_analysis/602.csv
index 91841ea796..7f9db13582 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,57005.05389221557,0,782955,Simd
 Insufficient SIMD VGPRs,533023.8622754491,0,29662104,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/prev_analysis/701.csv
index d3f1bff5a3..1071413faa 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,23.976047904191617,8,36,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/sysinfo.csv
index 147fb1d518..ae1a5fbc19 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-no_roof_kernels,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 11:22:26 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+no_roof_kernels,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 11:22:26 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/timestamps.csv
index 4188ac2d7f..a63d9318e6 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,893996,894001,33554432,256,0,0,8,32,6464,0x0,0x7f407f004180,12075800624243814,12075800624292466,12075800624617742,12075800624722904
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,893996,894001,32768,256,0,0,24,24,12480,0x0,0x7f407f035100,12075800639093611,12075800639194481,12075800639201361,12075800639206802
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,893996,894001,4194304,256,0,0,24,24,12928,0x7f41af0ba900,0x7f407f035140,12075800639248890,12075800639261520,12075800639392399,12075800639395683
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/SQ_IFETCH_LEVEL.csv
index 37994fe77d..d01fbc3bfc 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/SQ_IFETCH_LEVEL.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,190668,190668,33554432,256,0,0,4,32,4160,0x0,0x7f267d404280,392789,392789,524288,4718592,681255,76280600,17067586978161,17066871790709,17067737752746,17067737868495
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,190668,190668,32768,256,0,0,12,24,13888,0x0,0x7f267d423f80,32921,32921,512,8192,5936,671060,17067743048378,17067737752746,17067743182984,17067743187754
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,190668,190668,4194304,256,0,0,12,24,14336,0x7f2680413380,0x7f267d423fc0,167627,167627,65536,917504,142126,15920468,17067743224963,17067743182984,17067743570824,17067743573374
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/SQ_INST_LEVEL_LDS.csv
index 7993840a05..710e528805 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/SQ_INST_LEVEL_LDS.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,192516,192516,33554432,256,0,0,4,32,4160,0x0,0x7f8eb1404280,0,0,0,17086968873560,17086252370832,17087119123774,17087119236943
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,192516,192516,32768,256,0,0,12,24,13888,0x0,0x7f8eb1423f80,0,0,0,17087124403068,17087119123774,17087124532089,17087124536354
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,192516,192516,4194304,256,0,0,12,24,14336,0x7f8eb4398380,0x7f8eb1423fc0,0,0,0,17087124571283,17087124532089,17087124899609,17087124901844
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/SQ_INST_LEVEL_SMEM.csv
index 666c515a94..4a2a24e664 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/SQ_INST_LEVEL_SMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,190446,190446,33554432,256,0,0,4,32,4160,0x0,0x7f80a1a04280,3670016,2921942,328111616,17066641676275,17038503035333,17066791110057,17066791221226
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,190446,190446,32768,256,0,0,12,24,13888,0x0,0x7f80a1a23f80,512,102214,11451128,17066796399489,17066791110057,17066796529893,17066796534465
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,190446,190446,4194304,256,0,0,12,24,14336,0x7f80a4915380,0x7f80a1a23fc0,65536,618258,69270840,17066796569514,17066796529893,17066796899973,17066796902465
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/SQ_INST_LEVEL_VMEM.csv
index 8af7fd965c..b1ccd1dd25 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/SQ_INST_LEVEL_VMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,192294,192294,33554432,256,0,0,4,32,4160,0x0,0x7f0a4a004280,524288,5450925,610407536,17086023739683,17083758935398,17086171723210,17086171814889
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,192294,192294,32768,256,0,0,12,24,13888,0x0,0x7f0a4a023f80,4096,48623,5445124,17086176984734,17086171723210,17086177112478,17086177117210
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,192294,192294,4194304,256,0,0,12,24,14336,0x7f0a4d0c5380,0x7f0a4a023fc0,524288,10883817,1218946056,17086177152179,17086177112478,17086177479997,17086177482790
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/SQ_LEVEL_WAVES.csv
index 1a82f47a61..6ee393f269 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/SQ_LEVEL_WAVES.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,190890,190890,33554432,256,0,0,4,32,4160,0x0,0x7fa30c804280,380229,380229,8925,3041840,524288,238698839,2953751,0,971064344,17068533720385,17067819612432,17068679613438,17068679722917
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,190890,190890,32768,256,0,0,12,24,13888,0x0,0x7fa30c823f80,33933,33933,30415,271472,512,1766494,168728,0,7079372,17068684921260,17068679613438,17068685060312,17068685064946
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,190890,190890,4194304,256,0,0,12,24,14336,0x7fa30f8b7380,0x7fa30c823fc0,164582,164582,13723,1316664,65536,79222107,1212056,0,318623984,17068685110005,17068685060312,17068685451671,17068685454245
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/pmc_perf.csv
index d298af68dc..eaa4851e98 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_BUSY_CU_CYCLES,SQ_WAVE_CYCLES,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDI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],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_INT64,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBufferAligned.kd,0,0,0,191656,191656,33554432,256,0,0,4,32,4160,0x0,0x7fc9fec04280,3090168,3002990,524288,39000959,243836867,392,224,0,386270,386270,39280220.0,38213064.0,3.0,4155204.0,31329694.0,30966009.0,38182020.0,37620058.0,3088457,3009397,386270,0,386270,0,12360640.0,9503526.0,0.0,0.0,0,0,616,0,4718592,4714993,112,3487,377274,0.0,0.0,0.0,524288.0,28610727.0,27892228.0,7698.0,524288.0,131072,524288,302,386492,2352,0,56.0,304.0,0.0,4194696.0,0,0,0,0,0,7340032,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,20165109.0,524288.0,0,385565,0,0,0,385565,0,0,0,385565,0,0,0,385565,0,0,0,385565,0,0,0,385565,0,0,0,385565,0,0,0,385565,0,0,0,385565,0,0,0,385565,0,0,0,385565,0,0,0,385565,0,0,0,385565,0,0,0,385565,0,0,0,385565,0,0,0,385565,0,0,0,385565,0,0,0,385565,0,0,0,385565,0,0,0,385565,0,0,0,385565,0,0,0,385565,0,0,0,385565,0,0,0,385565,0,0,0,385565,0,0,0,385565,0,0,0,385565,0,0,0,385565,0,0,0,385565,0,0,0,385565,0,0,0,385565,0,0,0,385565,0,0,0,0,0,0.0,21018296.0,0,0,0,0,0,0,0,0,35,0,0,0,56,0,0,0,2,0,0,0,112,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,1,0,0,0,32,0,0,0,0,0,0,0,4,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,0,0,2,0,0,0,1,0,0,0,524288.0,0.0,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,320728,129024,129024,0,333,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,43772,129024,129024,0,207080,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,179,129024,129024,0,0,129024,129024,0,27360,129024,129024,0,1073,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,0,129024,129024,0,825,129024,129024,0,0,129024,129024,0,44035,129024,129024,0,186,129024,129024,524288.0,0.0,44410,0,0,50867243,45584,0,0,50922472,45127,0,0,50493999,46452,0,0,51775530,45524,0,0,51503080,46090,0,0,51541756,44710,0,0,50835965,47196,0,0,52734157,44088,0,0,50532420,46755,0,0,51428115,45970,0,0,50758927,48834,0,0,52723668,45429,0,0,51549951,46979,0,0,51642497,46763,0,0,51574126,49698,0,0,53546040,43780,0,0,50305015,46175,0,0,51056364,43728,0,0,50355117,46121,0,0,51809897,44972,0,0,51325372,45909,0,0,51439277,43824,0,0,50752319,48034,0,0,52758399,45126,0,0,50909203,46693,0,0,51334542,45142,0,0,50670992,46892,0,0,52183230,46066,0,0,51827269,46747,0,0,51831597,45844,0,0,51233581,47965,0,0,52930308,0.0,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65570,34,131106,65646,65538,112,131184,65536,65536,0,131072,65536,65592,56,131128,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65568,32,131104,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65570,34,131106,65813,65652,393,131465,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65536,0,131072,65536,65568,32,131104,65591,65537,56,131128,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131184,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131296,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131072,0,131072,131128,0,131072,1064638,0,524288,3670016,3663335,224,6457,1048576,33554432.0,33554432.0,0.0,33554432.0,29843552.0,28188978.0,0.0,524288.0,212218,536698,9065,931,0,380141,4195055.0,0.0,2097594.0,2097461.0,1048576,1048576,0,524288,0,524288,7340032,0,0.0,0.0,104.0,8388608.0,29819053.0,2097152.0,0.0,216471,0,1181,387640,0,747.0,4194304.0,0.0,2064387.0,25690112,9437184,0,0,0,0,0,0,13300.0,8242308.0,0.0,8388608.0,2097152.0,4194304.0,9860837,0,0,8820,4128768.0,4128768.0,0.0,1492981.0,0,0,0,0,0,0,5767168,1048576,315284809.0,0.0,1471417211.0,0.0,56.0,0.0,0,0,371153,0.0,0.0,1489135.0,0.0,3670016,524288,0,0,0,2621440,524288,176573812,4194304.0,0.0,0.0,0.0,0.0,1215612.0,0,0,0.0,311.0,0.0,606.0,40685105,24117248,0,0,9437184,11010048,0,3145728,0.0,0.0,0.0,0.0,0.0,0.0,0,1572864,0.0,0.0,0.0,179177.0,524288,524288,0,3670016,7340032,603979776,4718592,0,0.0,0.0,0.0,0.0,0.0,0.0,524288,0,2064384.0,0.0,2031623.0,0.0,0,0,524288,0,0,0,0,33554432,0.0,4194304.0,0.0,19138815.0,0.0,0.0,139.0,4128768.0,659949.0,1654956821.0,17069959817569,17087794577422,17087794817742,17070107342541
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,191656,191656,32768,256,0,0,12,24,13888,0x0,0x7fc9fec23f80,265336,160547,512,1374841,1638769,504,56,0,33166,33166,2320483.0,153043.0,162.0,0.0,32857.0,29541.0,146760.0,127989.0,265328,167680,33166,0,33166,0,1061312.0,386339.0,0.0,0.0,0,0,560,0,8192,6194,56,1942,24915,0.0,0.0,0.0,4096.0,29181.0,27654.0,0.0,4096.0,128,512,302,34122,2350,0,0.0,60.0,0.0,4600.0,0,0,0,0,0,1024,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,17167.0,4096.0,0,33022,0,0,0,33022,0,0,0,33022,0,0,0,33022,0,0,0,33022,0,0,0,33022,0,0,0,33022,0,0,0,33022,0,0,0,33022,0,0,0,33022,0,0,0,33022,0,0,0,33022,0,0,0,33022,0,0,0,33022,0,0,0,33022,0,0,0,33022,0,0,0,33022,0,0,0,33022,0,0,0,33022,0,0,0,33022,0,0,0,33022,0,0,0,33022,0,0,0,33022,0,0,0,33022,0,0,0,33022,0,0,0,33022,0,0,0,33022,0,0,0,33022,0,0,0,33022,0,0,0,33022,0,0,0,33022,0,0,0,33022,0,0,0,0,0,0.0,0.0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,316,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,258,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,258,0,0,0,256,0,0,0,4096.0,4096.0,0,123053,0,0,0,77214,0,0,0,77936,0,0,0,81836,0,0,0,80640,0,0,0,79668,0,0,0,105320,0,0,0,85504,0,0,0,84302,0,0,0,73927,0,0,0,76541,0,0,0,85518,0,0,0,81900,0,0,0,639679,0,0,0,86130,0,0,0,91428,0,0,0,78644,0,0,0,84123,0,0,0,77233,0,0,0,80582,0,0,0,88861,0,0,0,82623,0,0,0,81463,0,0,0,104602,0,0,0,91145,0,0,0,85552,0,0,0,74893,0,0,0,82043,0,0,0,76290,0,0,0,80513,0,0,0,79537,0,0,0,84894,0,0,0.0,0.0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4096.0,0,128,128,128,0,128,128,128,0,128,128,128,0,129,129,129,0,128,128,128,222,130,352,352,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,222,130,352,352,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,129,129,129,0,185,185,185,55,129,184,184,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,0,128,128,128,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,352,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,352,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,184,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,128,0,0,696,0,0,512,0,56,456,0,65536.0,65536.0,65536.0,0.0,0.0,0.0,0.0,0.0,6,518,11221,1148,0,30654,4659.0,0.0,499.0,4160.0,512,0,0,0,4096,4096,512,0,0.0,0.0,104.0,16384.0,0.0,16384.0,4096.0,0,0,1311,31913,0,4660.0,0.0,0.0,31.0,35328,26112,0,0,0,0,0,0,104.0,15240.0,0.0,16384.0,16384.0,0.0,0,0,0,29991,0.0,0.0,0.0,0.0,0,0,0,0,0,0,10752,3584,3959924.0,5343068.0,0.0,8192.0,2.0,0.0,0,0,497,0.0,0.0,0.0,0.0,512,4096,0,0,0,512,512,1707164,0.0,0.0,0.0,0.0,0.0,1388.0,0,0,0.0,8261.0,0.0,120.0,13108,32256,0,0,26112,1024,0,1024,0.0,0.0,0.0,0.0,0.0,0.0,0,1024,0.0,0.0,0.0,52400.0,4096,0,4096,512,512,1671168,8192,0,0.0,0.0,0.0,0.0,0.0,0.0,512,0,0.0,0.0,0.0,0.0,0,0,512,0,0,0,0,32768,8192.0,0.0,0.0,120701.0,0.0,4096.0,8205.0,0.0,3384774.0,0.0,17070113533026,17087799627169,17087799640289,17070114014942
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,191656,191656,4194304,256,0,0,12,24,14336,0x7fca01cc7380,0x7fc9fec23fc0,1364648,1259260,65536,16269140,96091354,392,56,0,170580,170580,16606039.0,15111086.0,23531.0,550094.0,14797021.0,14758539.0,15104746.0,12963241.0,1364640,1266784,170580,0,170580,0,5458560.0,4918848.0,0.0,0.0,0,0,448,0,917504,913620,0,3884,153373,0.0,0.0,0.0,524288.0,13843045.0,13831183.0,2196.0,524288.0,16384,65536,302,163726,2369,0,0.0,184.0,0.0,1048968.0,0,0,0,0,0,131072,0,0,0.0,0.0,0.0,0,0,0,0,0,0,0,0,11590239.0,524288.0,0,166831,0,0,0,166831,0,0,0,166831,0,0,0,166831,0,0,0,166831,0,0,0,166831,0,0,0,166831,0,0,0,166831,0,0,0,166831,0,0,0,166831,0,0,0,166831,0,0,0,166831,0,0,0,166831,0,0,0,166831,0,0,0,166831,0,0,0,166831,0,0,0,166831,0,0,0,166831,0,0,0,166831,0,0,0,166831,0,0,0,166831,0,0,0,166831,0,0,0,166831,0,0,0,166831,0,0,0,166831,0,0,0,166831,0,0,0,166831,0,0,0,166831,0,0,0,166831,0,0,0,166831,0,0,0,166831,0,0,0,166831,0,0,0,0,0,0.0,0.0,65536,0,23101,0,65536,0,18083,0,65585,0,15605,0,65537,0,17795,0,65536,0,17557,0,65592,0,21386,0,65536,0,23597,0,65536,0,27129,0,65536,0,19155,0,65536,0,16780,0,65536,0,20303,0,65591,0,17450,0,65537,0,21197,0,65536,0,15157,0,65536,0,19782,0,65536,0,15311,0,65536,0,19636,0,65536,0,16986,0,65536,0,18677,0,65536,0,21790,0,65536,0,23933,0,65536,0,20525,0,65536,0,25750,0,65540,0,23054,0,65540,0,16467,0,65536,0,31370,0,65536,0,14971,0,65536,0,17096,0,65536,0,16508,0,65536,0,14675,0,65538,0,19395,0,65536,0,22235,0,524288.0,524288.0,0,40476394,0,0,0,44180632,0,0,0,43611234,0,0,0,45093020,0,0,0,41114813,0,0,0,49804463,0,0,0,46590917,0,0,0,49437522,0,0,0,42092928,0,0,0,41029744,0,0,0,38922952,0,0,0,50994975,0,0,0,39946650,0,0,0,45070627,0,0,0,49620980,0,0,0,48906393,0,0,0,46057483,0,0,0,43419674,0,0,0,40235685,0,0,0,43115965,0,0,0,43020970,0,0,0,49058964,0,0,0,51040342,0,0,0,41542203,0,0,0,40767846,0,0,0,47593053,0,0,0,42136644,0,0,0,43390425,0,0,0,42889490,0,0,0,45860642,0,0,0,45963911,0,0,0,45351019,0,0,0.0,0.0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,524288.0,0,32768,32768,32768,0,32769,32769,32769,0,32768,32768,32768,0,32771,32771,32771,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32828,32828,32828,0,32825,32825,32825,166,32770,32936,32936,222,32770,32992,32992,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32768,32768,32768,0,32831,32831,32831,0,32768,32768,32768,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32936,0,0,32992,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,32768,0,0,876898,0,0,65536,63800,56,1680,0,8388608.0,8388608.0,8388608.0,0.0,0.0,0.0,0.0,0.0,166190,178587,9806,2401,0,167382,1049135.0,0.0,388.0,1048747.0,65536,0,0,0,524288,524288,131072,0,0.0,0.0,104.0,2097152.0,0.0,2097152.0,524288.0,40945,0,2337,162068,0,1049150.0,0.0,0.0,31.0,4063232,2883584,0,0,0,0,0,0,6611.0,2027491.0,0.0,2097152.0,2097152.0,0.0,1337099,0,0,13937,0.0,0.0,0.0,0.0,262144,0,0,0,0,0,1507328,458752,971197423.0,2308381525.0,0.0,2097152.0,131.0,0.0,0,0,147305,0.0,0.0,0.0,0.0,65536,524288,0,0,0,65536,65536,48878013,0.0,0.0,0.0,0.0,0.0,11586.0,0,0,0.0,2097343.0,0.0,368.0,27799165,3735552,0,0,2883584,196608,0,131072,0.0,0.0,0.0,0.0,0.0,0.0,0,131072,0.0,0.0,574674.0,1603128.0,524288,0,524288,65536,131072,184549376,917504,0,0.0,0.0,0.0,0.0,0.0,0.0,65536,0,0.0,0.0,983047.0,0.0,0,0,65536,0,0,0,0,4194304,2097152.0,0.0,0.0,12362734.0,0.0,524288.0,2097276.0,0.0,1476985091.0,0.0,17070115111281,17087799711169,17087799803489,17070115904249
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/prev_analysis/1.csv
index 063e88ccc4..9daf74d4e9 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,3357752.0,3357752.0,3357752.0,7.842624321900396
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,1724956.0,1724956.0,1724956.0,4.028940159906991
 "void benchmark_func<double, 256, 8u, 512u>(double, double*) [clone .kd]",1,1715196.0,1715196.0,1715196.0,4.006143951794615
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/prev_analysis/1001.csv
index f475f954a6..fb5988001a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,494.8622754491018,Instr per wave
 VMEM,7.958083832335329,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,0.0,Instr per wave
 SALU,24.520958083832337,Instr per wave
 SMEM,1.8023952095808384,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/prev_analysis/101.csv
index 93e8c35767..474790141c 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx90a
 mi200
 56
 1638.4
-SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/prev_analysis/1202.csv
index 405a77b986..3307c69ed4 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,18658.637221422025,1860.3276596069336,258058.71032714844,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/prev_analysis/1901.csv
index 87ed7142a3..f501f78e8f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,2.0,smem_
 VALU,495.0,valu_
 MFMA,0.0,mfma_
 VMEM,8.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,10.0,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,67894.0,wavefronts_
 Workgroups,16973.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,128.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,0.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,44.0,hbm_rd_
 HBM Wr,0.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,70.0,vl1_coales_
 VL1 Stall,1.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,26.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/prev_analysis/201.csv
index 61720d1ca5..64b0dfce36 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,57.626495806897694,Pct,100,57.626495806897694
 MFMA Util,0.0,Pct,100,0.0
 VALU Active Threads/Wave,64.0,Threads,64,100.0
 IPC - Issue,1.0,Instr/cycle,5,20.0
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99259456681887,Pct,100,99.99259456681887
 Instr Cache BW,1673.066401728073,Gb/s,6092.8,27.459729545169264
 Scalar L1D Cache Hit Rate,99.34855886085364,Pct,100,99.34855886085364
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/prev_analysis/602.csv
index d32465dc20..aad2e229b6 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,12869451.850299401,0,375173083,Simd
 Insufficient SIMD VGPRs,0.0,0,0,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/prev_analysis/701.csv
index 12250d77c0..db0925a109 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/sysinfo.csv
index 100da6aa2c..f18f8fbff6 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-no_roof_kernels,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:37:47 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+no_roof_kernels,06fa5f860366,AMD EPYC 7282 16-Core Processor,Ubuntu 20.04.5 LTS,5.11.0-27-generic,5.1.3-66,Wed Sep 28 20:37:47 2022 (),gfx90a,8,104,4,64,32,1024,16,8192,1700,1600,800,1600,32,mi200,56,1638.4,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/timestamps.csv
index f6a14f8bb7..d50f428bce 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_kernels/mi200/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,192599,192599,33554432,256,0,0,4,32,4160,0x0,0x7fe0d0a04280,17087794552242,17087794577422,17087794817742,17087794929171
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,192599,192599,32768,256,0,0,12,24,13888,0x0,0x7fe0d0a23f80,17087799611640,17087799627169,17087799640289,17087799658048
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,192599,192599,4194304,256,0,0,12,24,14336,0x7fe0d3a33380,0x7fe0d0a23fc0,17087799662538,17087799711169,17087799803489,17087799805664
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/SQ_IFETCH_LEVEL.csv
index 480eda5c2f..5d898f148d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/SQ_IFETCH_LEVEL.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,760946,760951,33554432,256,0,0,8,32,6464,0x0,0x7fd2f6804180,502545,502545,524288,6291456,792131,101597024,12073391341307832,12073391580107907,12073391580430625,12073391580540418
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,760946,760951,32768,256,0,0,24,24,12480,0x0,0x7fd2f6835100,27925,27925,512,8192,9386,1198164,12073391594928646,12073391595242775,12073391595249175,12073391595259431
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,760946,760951,4194304,256,0,0,24,24,12928,0x7fd426850900,0x7fd2f6835140,218411,218411,65536,917504,140670,17973492,12073391595322258,12073391595539254,12073391595672533,12073391595676386
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/SQ_INST_LEVEL_LDS.csv
index 2a95a78a23..398c169aa1 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/SQ_INST_LEVEL_LDS.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,762755,762760,33554432,256,0,0,8,32,6464,0x0,0x7fbdb4804180,0,0,0,12073417823489980,12073418068302031,12073418068625230,12073418068736452
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,762755,762760,32768,256,0,0,24,24,12480,0x0,0x7fbdb4835100,0,0,0,12073418083616104,12073418083928919,12073418083935159,12073418083943433
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,762755,762760,4194304,256,0,0,24,24,12928,0x7fbec0538900,0x7fbdb4835140,0,0,0,12073418083997132,12073418084229718,12073418084368437,12073418084372179
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/SQ_INST_LEVEL_SMEM.csv
index aa0a61548a..6fcabd4473 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/SQ_INST_LEVEL_SMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,762376,762381,33554432,256,0,0,8,32,6464,0x0,0x7faf55a04180,4194304,3165486,405166448,12073415275982827,12073415516306716,12073415516630715,12073415516740497
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,762376,762381,32768,256,0,0,24,24,12480,0x0,0x7faf55a35100,512,23150,2970584,12073415531316525,12073415531608445,12073415531614845,12073415531619879
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,762376,762381,4194304,256,0,0,24,24,12928,0x7fb06169b900,0x7faf55a35140,65536,204426,26142520,12073415531685380,12073415531904764,12073415532038523,12073415532042765
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/SQ_INST_LEVEL_VMEM.csv
index 4fbf12456b..28c8a4fe6d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/SQ_INST_LEVEL_VMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,762567,762572,33554432,256,0,0,8,32,6464,0x0,0x7f5fe9604180,1048576,11275156,1444033880,12073416545560388,12073416791439444,12073416791768083,12073416791880846
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,762567,762572,32768,256,0,0,24,24,12480,0x0,0x7f5fe9635100,4096,109779,14053836,12073416806938699,12073416807259294,12073416807265054,12073416807275185
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,762567,762572,4194304,256,0,0,24,24,12928,0x7f60f51e0900,0x7f5fe9635140,524288,10128039,1296440140,12073416807335757,12073416807551133,12073416807691452,12073416807694404
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/SQ_LEVEL_WAVES.csv
index 69daed2bcd..ec9b5f7d81 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/SQ_LEVEL_WAVES.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,762945,762951,33554432,256,0,0,8,32,6464,0x0,0x7ff324404180,505963,505963,18264,4047712,524288,370416796,3843865,0,1496487220,12073419085767826,12073419334592190,12073419334918268,12073419335029890
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,762945,762951,32768,256,0,0,24,24,12480,0x0,0x7ff324435100,27756,27756,20740,222056,512,1174796,78241,0,4713076,12073419349840574,12073419350165910,12073419350172630,12073419350180816
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,762945,762951,4194304,256,0,0,24,24,12928,0x7ff430076900,0x7ff324435140,217820,217820,21369,1742568,65536,128374088,1574421,0,515311628,12073419350248793,12073419350490868,12073419350624308,12073419350627236
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/pmc_dispatch_info.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/pmc_perf.csv
index 537b67fb67..7c33537858 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBuffer.kd,0,0,0,761680,761685,33554432,256,0,0,8,32,6464,0x0,0x7fc26c604180,1048576,0,1048576,9437184,0,4194304,1048576,0,505414,505414,57975780,55647179,120,12501267,54855880,54764053,55614810,54439106,4043312,3849508,505414,0,505414,0,16173248,15321942,0,0,0,0,0,17480681,1048576,0,504905,0,0,0,504905,0,0,0,504905,0,0,0,504905,0,0,0,504905,0,0,0,504905,0,0,0,504905,0,0,0,504905,0,0,0,504905,0,0,0,504905,0,0,0,504905,0,0,0,504905,0,0,0,504905,0,0,0,504905,0,0,0,504905,0,0,0,504905,0,0,0,504905,0,0,0,504905,0,0,0,504905,0,0,0,504905,0,0,0,504905,0,0,0,504905,0,0,0,504905,0,0,0,504905,0,0,0,504905,0,0,0,504905,0,0,0,504905,0,0,0,504905,0,0,0,504905,0,0,0,504905,0,0,0,504905,0,0,0,504905,0,0,0,37583922,0,0,0,0,101,0,0,0,0,0,0,0,2649,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2732,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,3,0,0,0,3,0,0,0,16,0,0,0,0,0,0,0,48,0,0,0,1,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,2552,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2757,0,0,0,1048576,0,0,5350,131072,131072,0,1464,131076,131076,0,522,131072,131072,0,1627,131072,131072,0,3140638,131072,131072,0,0,131072,131072,0,266,131072,131072,0,0,131072,131072,0,3119628,131076,131076,0,0,131076,131076,0,0,131072,131072,0,563454,131076,131076,0,0,131084,131084,0,0,131072,131072,0,0,131072,131072,0,0,131072,131072,0,0,131072,131072,0,793,131076,131076,0,0,131072,131072,0,0,131076,131076,0,3160575,131072,131072,0,1544,131080,131080,0,14184,131072,131072,0,0,131072,131072,0,2864958,131072,131072,0,954,131072,131072,0,0,131072,131072,0,30235,131072,131072,0,0,131072,131072,0,0,131080,131080,0,0,131072,131072,0,0,131072,131072,1048576,0,43326,0,0,29217450,862,0,0,17068561,1159,0,0,17272462,1538,0,0,17346603,51950,0,0,30957724,1108,0,0,17369529,754,0,0,17925151,922,0,0,18612102,1626,0,0,17229065,1470,0,0,17011601,1020,0,0,16836363,1613,0,0,16984697,998,0,0,17190471,1550,0,0,17339372,1256,0,0,17851098,1066,0,0,18542474,1755,0,0,16682565,1101,0,0,16780157,1196,0,0,16834003,1029,0,0,16835055,47394,0,0,30099647,1493,0,0,17370668,1052,0,0,17773458,1119,0,0,18792871,51035,0,0,30089429,865,0,0,16689293,871,0,0,16792680,1143,0,0,16910310,860,0,0,17101495,1629,0,0,17210539,689,0,0,17822470,960,0,0,18563132,1048576,131072,131073,1,262145,131260,131076,192,262336,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131137,65,262209,131072,131072,0,262144,131072,131072,0,262144,131072,131075,3,262147,131072,133697,2625,264769,131072,131073,1,262145,131072,131072,0,262144,131072,131073,1,262145,131072,131072,0,262144,131072,131120,48,262192,131213,133667,2736,264880,131072,131072,0,262144,131072,131072,0,262144,131119,131073,48,262192,131072,131073,1,262145,131072,131072,0,262144,131072,133736,2664,264808,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,133568,2496,264640,131119,131073,48,262192,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,262144,0,262144,262336,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262288,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,0,0,3145728,524288,32505856,365554155,217792416,115255883,478526,0,0,0,1048576,52309214,52072018,1048576,1048576,131072,524288,714,500636,4383,0,96,10540,0,8388944,32505856,4023696,3817042,57060800,11534336,0,0,14155776,67108864,67108864,0,67108864,53986316,53599989,0,1048576,240443,764731,11573,2159,0,498587,8399812,0,4194727,4205085,13631488,0,3670016,1048576,1048576,0,4194304,9437184,0,0,360,33554432,54116629,4194304,0,0,2428,499152,0,10991,8388608,0,4194355,905969664,6291456,0,0,0,524288,524288,0,15348,16608514,0,16777216,4194304,4194304,0,0,0,17255,4194366,4194366,0,218586,0,0,0,33554432,0,0,0,0,623825200,0,2748095888,0,0,0,0,0,475382,0,0,213164,0,0,8388608,336,144,0,0,0,480,8388608,0,0,0,0,321162,0,0,0,10780,0,21542,0,6291456,6289598,96,1955,1853149,0,0,0,0,0,0,0,0,0,3145728,0,0,0,160465,4194304,4189857,144,4303,2097152,524288,1572864,0,0,0,0,0,0,524288,0,4128863,65529,4063251,0,0,8388608,0,41959814,0,1048576,10600,4194376,12873159,612840099,12073393449620423,12073420227791147,12073420228118984,12073393695958504
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,761680,761685,32768,256,0,0,24,24,12480,0x0,0x7fc26c635100,0,4096,4096,512,0,512,4096,0,29308,29308,1484807,588452,217,133259,126889,110310,580332,559773,234464,84803,29308,0,29308,0,937856,198235,0,0,0,0,0,69974,4096,0,28085,0,0,0,28085,0,0,0,28085,0,0,0,28085,0,0,0,28085,0,0,0,28085,0,0,0,28085,0,0,0,28085,0,0,0,28085,0,0,0,28085,0,0,0,28085,0,0,0,28085,0,0,0,28085,0,0,0,28085,0,0,0,28085,0,0,0,28085,0,0,0,28085,0,0,0,28085,0,0,0,28085,0,0,0,28085,0,0,0,28085,0,0,0,28085,0,0,0,28085,0,0,0,28085,0,0,0,28085,0,0,0,28085,0,0,0,28085,0,0,0,28085,0,0,0,28085,0,0,0,28085,0,0,0,28085,0,0,0,28085,0,0,0,0,256,0,0,0,353,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,260,0,0,0,376,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,4096,4096,0,274468,0,0,0,98377,0,0,0,79779,0,0,0,79864,0,0,0,101774,0,0,0,98322,0,0,0,78023,0,0,0,83127,0,0,0,89646,0,0,0,86040,0,0,0,80485,0,0,0,73629,0,0,0,99241,0,0,0,96230,0,0,0,74469,0,0,0,71781,0,0,0,87872,0,0,0,85340,0,0,0,68515,0,0,0,128241,0,0,0,83022,0,0,0,126472,0,0,0,106444,0,0,0,75191,0,0,0,92117,0,0,0,223645,0,0,0,79724,0,0,0,105196,0,0,0,130101,0,0,0,176084,0,0,0,92074,0,0,0,142340,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4096,0,257,257,257,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,376,376,376,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,257,257,257,0,256,256,256,188,261,449,449,0,256,256,256,0,304,304,304,0,256,256,256,188,260,448,448,0,256,256,256,0,256,256,256,0,257,257,257,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,47,257,304,304,0,256,256,256,47,257,304,304,0,256,256,256,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,304,0,0,256,0,0,0,0,512,512,35328,1126973,1073103,17518,11950,0,0,0,4096,73596,70575,4096,4096,128,512,623,28469,4313,0,48,172,0,8624,36352,221560,75007,1054073,26624,0,0,30208,65536,65536,65536,0,0,0,0,0,114,626,11789,2147,0,23397,8891,0,470,8421,1024,0,1024,4096,0,4096,512,512,0,0,360,16384,0,16384,0,0,2377,26186,0,8891,0,0,31,1933312,8192,0,0,0,512,512,0,120,15064,0,16384,16384,0,0,0,0,20401,0,0,0,0,0,0,0,32768,0,0,0,0,12468718,17485358,0,8192,0,0,0,0,695,0,0,0,0,0,1024,432,48,0,0,0,480,0,0,0,0,0,3012,0,0,0,8373,0,342,0,8192,6560,48,1584,1084,0,0,0,0,0,0,0,0,0,2560,0,0,0,50073,512,0,48,464,0,512,0,0,0,0,0,0,0,512,0,0,0,0,0,8192,0,0,424565,0,4096,8421,0,3511014,0,12073393710939424,12073420244026605,12073420244033805,12073393711927390
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,761680,761685,4194304,256,0,0,24,24,12928,0x7fc378175900,0x7fc26c635140,0,524288,524288,65536,0,65536,524288,0,227399,227399,25212557,24034723,29714,5709760,23094530,22950742,24016132,21854923,1819192,1664851,227399,0,227399,0,7276768,6567852,0,0,0,0,0,20088702,524288,0,218637,0,0,0,218637,0,0,0,218637,0,0,0,218637,0,0,0,218637,0,0,0,218637,0,0,0,218637,0,0,0,218637,0,0,0,218637,0,0,0,218637,0,0,0,218637,0,0,0,218637,0,0,0,218637,0,0,0,218637,0,0,0,218637,0,0,0,218637,0,0,0,218637,0,0,0,218637,0,0,0,218637,0,0,0,218637,0,0,0,218637,0,0,0,218637,0,0,0,218637,0,0,0,218637,0,0,0,218637,0,0,0,218637,0,0,0,218637,0,0,0,218637,0,0,0,218637,0,0,0,218637,0,0,0,218637,0,0,0,218637,0,0,0,0,65536,0,38972,0,65633,0,40121,0,65540,0,9907,0,65876,0,40254,0,65536,0,34268,0,65536,0,17332,0,65536,0,9423,0,65536,0,9150,0,65536,0,7753,0,65536,0,14761,0,65536,0,40143,0,65536,0,25393,0,65537,0,6274,0,65536,0,5730,0,65536,0,37685,0,65536,0,19880,0,65536,0,31038,0,65536,0,13140,0,65536,0,4590,0,65656,0,37358,0,65536,0,48959,0,65536,0,19302,0,65537,0,25306,0,65536,0,48153,0,65537,0,52064,0,65536,0,60249,0,65536,0,40762,0,65536,0,13868,0,65536,0,5414,0,65536,0,52135,0,65540,0,7298,0,66965,0,55446,0,524288,524288,0,28104058,0,0,0,28215203,0,0,0,25339775,0,0,0,25406854,0,0,0,45510645,0,0,0,25571542,0,0,0,24896936,0,0,0,25800346,0,0,0,25435955,0,0,0,29331235,0,0,0,23984553,0,0,0,24946046,0,0,0,25506590,0,0,0,26153740,0,0,0,24884295,0,0,0,25670101,0,0,0,25469744,0,0,0,27978473,0,0,0,23514711,0,0,0,23453395,0,0,0,24088786,0,0,0,27362382,0,0,0,26779051,0,0,0,26552094,0,0,0,48228298,0,0,0,24789005,0,0,0,23696441,0,0,0,25127045,0,0,0,27520053,0,0,0,27945521,0,0,0,26272139,0,0,0,27483783,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,524288,0,65537,65537,65537,0,65536,65536,65536,188,65540,65728,65728,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65657,65657,65657,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,67925,67925,67925,0,65537,65537,65537,0,65536,65536,65536,0,65537,65537,65537,0,65536,65536,65536,0,65584,65584,65584,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65537,65537,65537,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,68275,68275,68275,47,65537,65584,65584,0,65536,65536,65536,188,65540,65728,65728,0,65536,65536,65536,65536,0,0,65536,0,0,65728,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65728,0,0,65536,0,0,0,0,65536,65536,4128768,130312753,52311255,73741658,196458,0,0,0,524288,20809433,20792808,524288,524288,16384,65536,747,214753,4317,0,48,2351,0,2097536,4259840,1789880,1614863,23951878,3014656,0,0,3473408,8388608,8388608,8388608,0,0,0,0,0,174042,204113,11939,2181,0,219460,2101167,0,423,2100744,131072,0,131072,524288,0,524288,65536,65536,0,0,360,2097152,0,2097152,38454,0,2392,223741,0,2102440,0,0,31,222298112,917504,0,0,0,65536,65536,0,7521,2016135,0,2097152,2097152,0,645795,647869,0,22453,0,0,0,0,0,0,0,4194304,0,0,0,0,1029494353,1783889922,0,2097152,0,0,0,0,194318,0,0,0,0,0,131072,384,48,0,0,0,432,0,0,0,0,0,6129,0,0,0,2101331,0,8340,0,917504,914492,50,5502,202066,0,0,0,0,0,0,0,0,0,327680,0,0,618531,671138,65536,64048,48,1440,0,65536,0,0,0,0,0,0,0,65536,0,0,0,1966092,0,2097152,0,0,14365801,0,524288,2101967,0,878796369,0,12073393712564945,12073420244113324,12073420244247403,12073393713816160
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/prev_analysis/1.csv
index 117dd7704a..551551b91a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,6060645.0,6060645.0,6060645.0,9.174628783842092
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4528324.0,4528324.0,4528324.0,6.854995089295439
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 256u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,3056483.0,3056483.0,3056483.0,4.626916262068481
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/prev_analysis/1001.csv
index ca08330db0..0e3bf5267e 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,46.862275449101794,Instr per wave
 SMEM,1.8083832335329342,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/prev_analysis/101.csv
index 981f573dd6..cf1071dc0e 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx908
 mi100
 48
 1228.8
-SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/prev_analysis/1202.csv
index b6b626ed95..50543a6cb5 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,33714.31287183019,2788.956871032715,547930.4672241211,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/prev_analysis/1901.csv
index aa179830c2..bc7d82eb84 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,2.0,smem_
 VALU,735.0,valu_
 MFMA,,mfma_
 VMEM,8.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,22.0,br_
 VGPR,24.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,67894.0,wavefronts_
 Workgroups,16973.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,163.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,0.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,44.0,hbm_rd_
 HBM Wr,0.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,70.0,vl1_coales_
 VL1 Stall,29.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,35.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/prev_analysis/2001.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/prev_analysis/201.csv
index 92c16458c8..c8b93fd89b 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,59.51806456937127,Pct,100,59.51806456937127
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,63.96739926599209,Threads,64,99.94906135311264
 IPC - Issue,0.8437220375900171,Instr/cycle,5,16.874440751800343
-LDS BW,0.0,Gb/sec,23070.72,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,23070.72,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99342737673422,Pct,100,99.99342737673422
 Instr Cache BW,1407.5651864015822,Gb/s,4614.144,30.5054455691366
 Scalar L1D Cache Hit Rate,99.35620448524445,Pct,100,99.35620448524445
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/prev_analysis/602.csv
index 0383d4972e..8c9324ebc0 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,70306.61676646706,0,668384,Simd
 Insufficient SIMD VGPRs,647637.7964071856,0,45257691,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/prev_analysis/701.csv
index d3f1bff5a3..1071413faa 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,23.976047904191617,8,36,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/sysinfo.csv
index 325f4e9fbe..55cd7643fa 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-no_roof_mixbench1,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 10:42:46 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+no_roof_mixbench1,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 10:42:46 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/timestamps.csv
index 45ec382550..a91c56baad 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,762995,763000,33554432,256,0,0,8,32,6464,0x0,0x7ff6fb004180,12073420227749665,12073420227791147,12073420228118984,12073420228229266
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,762995,763000,32768,256,0,0,24,24,12480,0x0,0x7ff6fb035100,12073420243914836,12073420244026605,12073420244033805,12073420244039838
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,762995,763000,4194304,256,0,0,24,24,12928,0x7ff82b006900,0x7ff6fb035140,12073420244098277,12073420244113324,12073420244247403,12073420244250861
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi200/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi200/SQ_IFETCH_LEVEL.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi200/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi200/SQ_IFETCH_LEVEL.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi200/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi200/SQ_INST_LEVEL_LDS.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi200/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi200/SQ_INST_LEVEL_LDS.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi200/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi200/SQ_INST_LEVEL_SMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi200/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi200/SQ_INST_LEVEL_SMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi200/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi200/SQ_INST_LEVEL_VMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi200/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi200/SQ_INST_LEVEL_VMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi200/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi200/SQ_LEVEL_WAVES.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi200/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi200/SQ_LEVEL_WAVES.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi200/pmc_perf.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi200/pmc_perf.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi200/timestamps.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench1/mi200/timestamps.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/SQ_IFETCH_LEVEL.csv
index 6b1cc5cfd8..714d5d4634 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/SQ_IFETCH_LEVEL.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,765953,765958,33554432,256,0,0,8,32,6464,0x0,0x7f6850404180,503361,503361,524288,6291456,793543,101494716,12073488773597681,12073489019069139,12073489019393137,12073489019504460
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,765953,765958,32768,256,0,0,24,24,12480,0x0,0x7f6850435100,26270,26270,512,8192,9599,1226168,12073489033951688,12073489034278338,12073489034284418,12073489034294174
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,765953,765958,4194304,256,0,0,24,24,12928,0x7f695bf80900,0x7f6850435140,216939,216939,65536,917504,139973,17908076,12073489034350459,12073489034581857,12073489034714656,12073489034717621
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/SQ_INST_LEVEL_LDS.csv
index ba290d1613..56f599a372 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/SQ_INST_LEVEL_LDS.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,767749,767754,33554432,256,0,0,8,32,6464,0x0,0x7fd7c8c04180,0,0,0,12073515318486502,12073515563635671,12073515563960309,12073515564075811
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,767749,767754,32768,256,0,0,24,24,12480,0x0,0x7fd7c8c35100,0,0,0,12073515578743469,12073515579060190,12073515579066750,12073515579075606
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,767749,767754,4194304,256,0,0,24,24,12928,0x7fd8d491c900,0x7fd7c8c35140,0,0,0,12073515579135417,12073515579352829,12073515579483388,12073515579486279
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/SQ_INST_LEVEL_SMEM.csv
index 4b44cca28e..a23ee6eda6 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/SQ_INST_LEVEL_SMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,767370,767375,33554432,256,0,0,8,32,6464,0x0,0x7ff388804180,4194304,3126246,399704576,12073512808792320,12073513056035933,12073513056358812,12073513056472504
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,767370,767375,32768,256,0,0,24,24,12480,0x0,0x7ff388835100,512,23822,3031120,12073513071131486,12073513071432427,12073513071438827,12073513071443105
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,767370,767375,4194304,256,0,0,24,24,12928,0x7ff4944a7900,0x7ff388835140,65536,184572,23518496,12073513071501504,12073513071729066,12073513071862505,12073513071865080
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/SQ_INST_LEVEL_VMEM.csv
index 04a5213ea6..5c5f7bf4a3 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/SQ_INST_LEVEL_VMEM.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,767560,767566,33554432,256,0,0,8,32,6464,0x0,0x7f1f5d204180,1048576,11140072,1426732508,12073514065149412,12073514309922056,12073514310245895,12073514310360257
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,767560,767566,32768,256,0,0,24,24,12480,0x0,0x7f1f5d235100,4096,122558,15685184,12073514325056879,12073514325371032,12073514325377592,12073514325385460
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,767560,767566,4194304,256,0,0,24,24,12928,0x7f2068e00900,0x7f1f5d235140,524288,10557459,1351333736,12073514325446023,12073514325663191,12073514325801910,12073514325804609
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/SQ_LEVEL_WAVES.csv
index 064fad2e7e..1d4ac011c4 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/SQ_LEVEL_WAVES.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,767939,767944,33554432,256,0,0,8,32,6464,0x0,0x7fa84de04180,503766,503766,16239,4030136,524288,366923879,3832761,0,1482496184,12073516570403733,12073516816860117,12073516817184115,12073516817310230
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,767939,767944,32768,256,0,0,24,24,12480,0x0,0x7fa84de35100,27327,27327,19948,218624,512,1147056,76118,0,4602304,12073516831909651,12073516832264269,12073516832270669,12073516832287173
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,767939,767944,4194304,256,0,0,24,24,12928,0x7fa959a94900,0x7fa84de35140,224036,224036,19692,1792296,65536,129980282,1633386,0,521724868,12073516832348477,12073516832651627,12073516832789386,12073516832793624
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/pmc_dispatch_info.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/pmc_perf.csv
index 4164b8fa89..8a7a47acbe 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_SH_FIFO_BUSY_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TCC_EA_ATOMIC_LEVEL_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],TA_FLAT_COALESCEABLE_WAVEFRONTS_sum,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_SH_FIFO_CMD_BUSY_sum,TA_SH_FIFO_ADDR_BUSY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,SQ_ACTIVE_INST_ANY,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_SH_FIFO_DATA_BUSY_sum,TA_SH_FIFO_DATA_SFIFO_BUSY_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_SH_FIFO_DATA_TFIFO_BUSY_sum,TA_SQ_TA_CMD_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_SP_TA_ADDR_CYCLES_sum,TA_SP_TA_DATA_CYCLES_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum,TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum,TA_TA_SH_FIFO_STARVED_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_BUFFER_WAVEFRONTS_sum,TA_BUFFER_READ_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TA_BUFFER_TOTAL_CYCLES_sum,TA_BUFFER_COALESCABLE_WAVEFRONTS_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBuffer.kd,0,0,0,766687,766692,33554432,256,0,0,8,32,6464,0x0,0x7f91c1604180,1048576,0,1048576,9437184,0,4194304,1048576,0,502675,502675,57728829,55482211,210,12942345,54856820,54780505,55454783,54278153,4021400,3833044,502675,0,502675,0,16085600,15260947,0,0,0,0,0,17353393,1048576,0,501426,0,0,0,501426,0,0,0,501426,0,0,0,501426,0,0,0,501426,0,0,0,501426,0,0,0,501426,0,0,0,501426,0,0,0,501426,0,0,0,501426,0,0,0,501426,0,0,0,501426,0,0,0,501426,0,0,0,501426,0,0,0,501426,0,0,0,501426,0,0,0,501426,0,0,0,501426,0,0,0,501426,0,0,0,501426,0,0,0,501426,0,0,0,501426,0,0,0,501426,0,0,0,501426,0,0,0,501426,0,0,0,501426,0,0,0,501426,0,0,0,501426,0,0,0,501426,0,0,0,501426,0,0,0,501426,0,0,0,501426,0,0,0,37550931,0,0,0,0,4,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,2568,0,0,0,0,0,0,0,2592,0,0,0,0,0,0,0,48,0,0,0,0,0,0,0,2728,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,3,0,0,0,48,0,0,0,2676,0,0,0,0,0,0,0,48,0,0,0,0,0,0,0,22,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1048576,0,0,0,131072,131072,0,16892,131072,131072,0,0,131076,131076,0,3163302,131073,131073,0,262,131076,131076,0,0,131072,131072,0,1216,131076,131076,0,515067,131080,131080,0,7219,131072,131072,0,0,131072,131072,0,0,131072,131072,0,0,131076,131076,0,261,131076,131076,0,21115,131072,131072,0,0,131072,131072,0,2998028,131072,131072,0,0,131076,131076,0,782,131080,131080,0,0,131072,131072,0,3268851,131072,131072,0,0,131080,131080,0,0,131072,131072,0,266,131072,131072,0,0,131076,131076,0,0,131072,131072,0,0,131072,131072,0,0,131072,131072,0,0,131076,131076,0,0,131072,131072,0,0,131072,131072,0,0,131072,131072,0,3108022,131076,131076,1048576,0,723,0,0,17303846,1682,0,0,17204157,762,0,0,17433306,42236,0,0,29103996,794,0,0,17243246,693,0,0,17262397,1761,0,0,18288036,51561,0,0,31770603,1164,0,0,17493708,1009,0,0,17234017,1100,0,0,17203267,814,0,0,16649920,838,0,0,17314732,1038,0,0,17052945,904,0,0,18093536,1198,0,0,18400794,890,0,0,17064072,1050,0,0,16704513,1167,0,0,17161663,1744,0,0,16822889,795,0,0,17486572,898,0,0,17134258,962,0,0,18138025,1845,0,0,18471892,824,0,0,16903846,1425,0,0,16592825,934,0,0,17260604,43631,0,0,29184534,771,0,0,17227526,939,0,0,17284996,1096,0,0,18263812,43535,0,0,31063751,1048576,131072,131072,0,262144,131260,131076,192,262336,131072,131072,0,262144,131072,133786,2714,264858,131072,131072,0,262144,131072,131072,0,262144,131119,131074,49,262193,131072,131072,0,262144,131072,131318,246,262390,131072,131120,48,262192,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131120,48,262192,131072,131072,0,262144,131072,133831,2759,264903,131072,131072,0,262144,131213,131075,144,262288,131119,131074,49,262193,131072,133779,2707,264851,131072,131072,0,262144,131072,131076,4,262148,131072,131120,48,262192,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131072,0,262144,131072,131073,1,262145,131072,133314,2242,264386,262144,0,262144,262336,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262288,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,262144,0,262144,0,0,3145728,524288,32505856,371773101,219144304,120122941,477497,0,0,0,1048576,52418640,52198662,1048576,1048576,131072,524288,701,498523,4097,0,96,10515,0,8388944,32505856,4018688,3813819,56932443,11534336,0,0,14155776,67108864,67108864,0,67108864,53954408,53593713,0,1048576,244911,769199,11083,2436,0,498164,8399558,0,4194727,4204831,13631488,0,3670016,1048576,1048576,0,4194304,9437184,0,0,360,33554432,54257562,4194304,0,0,2506,501438,0,11040,8388608,0,4194371,905969664,6291456,0,0,0,524288,524288,0,15336,16608665,0,16777216,4194304,4194304,0,0,0,18186,4194372,4194372,0,210648,0,0,0,33554432,0,0,0,0,630968789,0,2756683128,0,0,0,0,0,475784,0,0,225171,0,0,8388608,336,144,0,0,0,480,8388608,0,0,0,0,337058,0,0,0,10523,0,21028,0,6291456,6289517,96,2131,2083619,0,0,0,0,0,0,0,0,0,3145728,0,0,0,148737,4194304,4189863,144,4297,2097152,524288,1572864,0,0,0,0,0,0,524288,0,4128847,65529,4063252,0,0,8388608,0,42447742,0,1048576,10560,4194396,12783827,610624706,12073490934376795,12073517721430385,12073517721754222,12073491180662057
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,766687,766692,32768,256,0,0,24,24,12480,0x0,0x7f91c1635100,0,4096,4096,512,0,512,4096,0,28227,28227,1541267,668078,239,109638,88210,67468,659964,639338,225816,88575,28227,0,28227,0,903264,208404,0,0,0,0,0,59251,4096,0,28195,0,0,0,28195,0,0,0,28195,0,0,0,28195,0,0,0,28195,0,0,0,28195,0,0,0,28195,0,0,0,28195,0,0,0,28195,0,0,0,28195,0,0,0,28195,0,0,0,28195,0,0,0,28195,0,0,0,28195,0,0,0,28195,0,0,0,28195,0,0,0,28195,0,0,0,28195,0,0,0,28195,0,0,0,28195,0,0,0,28195,0,0,0,28195,0,0,0,28195,0,0,0,28195,0,0,0,28195,0,0,0,28195,0,0,0,28195,0,0,0,28195,0,0,0,28195,0,0,0,28195,0,0,0,28195,0,0,0,28195,0,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,260,0,0,0,256,0,0,0,256,0,0,0,256,0,0,0,304,0,0,0,257,0,0,0,256,0,0,0,304,0,0,0,256,0,0,0,377,0,0,0,256,0,0,0,256,0,0,0,257,0,0,0,256,0,0,0,4096,4096,0,81840,0,0,0,100350,0,0,0,112400,0,0,0,89266,0,0,0,103365,0,0,0,116726,0,0,0,92474,0,0,0,106469,0,0,0,175376,0,0,0,79016,0,0,0,76349,0,0,0,67711,0,0,0,86803,0,0,0,115082,0,0,0,72985,0,0,0,67654,0,0,0,121392,0,0,0,84180,0,0,0,88023,0,0,0,80811,0,0,0,124630,0,0,0,124347,0,0,0,85451,0,0,0,88288,0,0,0,82083,0,0,0,79986,0,0,0,86187,0,0,0,75292,0,0,0,78094,0,0,0,111534,0,0,0,67227,0,0,0,80674,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4096,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,47,258,305,305,0,256,256,256,0,377,377,377,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,304,304,304,188,260,448,448,0,256,256,256,0,256,256,256,0,256,256,256,188,261,449,449,0,256,256,256,0,256,256,256,0,256,256,256,0,304,304,304,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,0,256,256,256,47,258,305,305,0,256,256,256,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,448,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,256,0,0,304,0,0,256,0,0,0,0,512,512,35328,1168917,1115836,16729,12202,0,0,0,4096,65130,62111,4096,4096,128,512,588,27140,4044,0,48,219,0,8624,36352,218208,73741,1020909,26624,0,0,30208,65536,65536,65536,0,0,0,0,0,114,626,11222,2416,0,23038,8844,0,470,8374,1024,0,1024,4096,0,4096,512,512,0,0,360,16384,0,16384,0,0,2400,25570,0,8891,0,0,31,1933312,8192,0,0,0,512,512,0,120,15064,0,16384,16384,0,0,0,0,20049,0,0,0,0,0,0,0,32768,0,0,0,0,12611052,17795834,0,8192,0,0,0,0,696,0,0,0,0,0,1024,432,48,0,0,0,480,0,0,0,0,0,2388,0,0,0,8422,0,440,0,8192,6567,48,1577,1110,0,0,0,0,0,0,0,0,0,2560,0,0,0,49540,512,0,48,464,0,512,0,0,0,0,0,0,0,512,0,0,0,0,0,8192,0,0,429916,0,4096,8373,0,3003534,0,12073491195860943,12073517737554518,12073517737561398,12073491196832959
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,766687,766692,4194304,256,0,0,24,24,12928,0x7f92cd1a7900,0x7f91c1635140,0,524288,524288,65536,0,65536,524288,0,218733,218733,24415457,23193027,31949,9157143,22852965,22803662,23183560,21020480,1749864,1611183,218733,0,218733,0,6999456,6308333,0,0,0,0,0,21307559,524288,0,228693,0,0,0,228693,0,0,0,228693,0,0,0,228693,0,0,0,228693,0,0,0,228693,0,0,0,228693,0,0,0,228693,0,0,0,228693,0,0,0,228693,0,0,0,228693,0,0,0,228693,0,0,0,228693,0,0,0,228693,0,0,0,228693,0,0,0,228693,0,0,0,228693,0,0,0,228693,0,0,0,228693,0,0,0,228693,0,0,0,228693,0,0,0,228693,0,0,0,228693,0,0,0,228693,0,0,0,228693,0,0,0,228693,0,0,0,228693,0,0,0,228693,0,0,0,228693,0,0,0,228693,0,0,0,228693,0,0,0,228693,0,0,0,0,65536,0,12086,0,65536,0,7783,0,65540,0,979,0,65536,0,3478,0,65536,0,13673,0,65536,0,1203,0,65537,0,2870,0,65536,0,12051,0,65536,0,3533,0,65536,0,1916,0,65537,0,0,0,67883,0,81432,0,65536,0,2183,0,65536,0,2183,0,65536,0,0,0,65536,0,0,0,65536,0,2824,0,65536,0,1500,0,65536,0,3123,0,65536,0,14012,0,65536,0,234,0,65536,0,13002,0,65584,0,0,0,67258,0,43126,0,65536,0,2684,0,65584,0,19989,0,65536,0,2944,0,65657,0,12414,0,65536,0,221,0,65536,0,0,0,65540,0,9138,0,65536,0,10460,0,524288,524288,0,34666072,0,0,0,33698233,0,0,0,33841594,0,0,0,34722641,0,0,0,34818739,0,0,0,33117937,0,0,0,34799979,0,0,0,33635706,0,0,0,40556277,0,0,0,36069490,0,0,0,32141259,0,0,0,33581238,0,0,0,32526321,0,0,0,37666611,0,0,0,35710499,0,0,0,46072550,0,0,0,31209048,0,0,0,33269623,0,0,0,29181893,0,0,0,47752300,0,0,0,33677176,0,0,0,39056456,0,0,0,34458115,0,0,0,39158096,0,0,0,37604377,0,0,0,41348322,0,0,0,41452217,0,0,0,30896617,0,0,0,42668085,0,0,0,37469647,0,0,0,35544923,0,0,0,36719547,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,524288,0,65536,65536,65536,0,65536,65536,65536,188,65540,65728,65728,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,47,65538,65585,65585,0,65536,65536,65536,0,66015,66015,66015,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65584,65584,65584,0,65536,65536,65536,0,66782,66782,66782,0,65536,65536,65536,0,65536,65536,65536,0,65537,65537,65537,0,67816,67816,67816,0,65536,65536,65536,0,65536,65536,65536,0,65584,65584,65584,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,0,65536,65536,65536,188,65541,65729,65729,0,65536,65536,65536,65536,0,0,65536,0,0,65728,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65536,0,0,65728,0,0,65536,0,0,0,0,65536,65536,4128768,119703295,42498954,72944501,211432,0,0,0,524288,22559029,22543860,524288,524288,16384,65536,727,227781,4028,0,48,5492,0,2097536,4259840,1760168,1593756,23592486,3014656,0,0,3473408,8388608,8388608,8388608,0,0,0,0,0,161260,195506,11107,2459,0,215875,2101082,0,423,2100659,131072,0,131072,524288,0,524288,65536,65536,0,0,360,2097152,0,2097152,29559,0,2391,222510,0,2102108,0,0,31,222298112,917504,0,0,0,65536,65536,0,7606,2016171,0,2097152,2097152,0,580009,581737,0,19064,0,0,0,0,0,0,0,4194304,0,0,0,0,885125203,1402621477,0,2097152,0,0,0,0,197254,0,0,0,0,0,131072,384,48,0,0,0,432,0,0,0,0,0,13627,0,0,0,2102367,0,10412,0,917504,914728,48,7450,183657,0,0,0,0,0,0,0,0,0,327680,0,0,234596,288153,65536,64048,48,1440,0,65536,0,0,0,0,0,0,0,65536,0,0,0,1966100,0,2097152,0,0,16971224,0,524288,2099924,0,1184157236,0,12073491197469292,12073517737638997,12073517737768436,12073491198713844
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/prev_analysis/1.csv
index b908b2524c..e9ea310642 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,6053392.0,6053392.0,6053392.0,9.17032880400236
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4527005.0,4527005.0,4527005.0,6.8579937244048805
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 256u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,3051336.0,3051336.0,3051336.0,4.622491722242563
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/prev_analysis/1001.csv
index ca08330db0..0e3bf5267e 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,46.862275449101794,Instr per wave
 SMEM,1.8083832335329342,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/prev_analysis/101.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/prev_analysis/101.csv
index b91fca6ac9..dc5f73ab09 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/prev_analysis/101.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/prev_analysis/101.csv
@@ -23,4 +23,4 @@ gfx908
 mi100
 48
 1228.8
-SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/prev_analysis/1202.csv
index c38239c88e..b422389a7b 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,33539.29469514036,2836.403663635254,547935.1201171875,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/prev_analysis/1901.csv
index 7daf0acb94..bbb90a38f2 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,2.0,smem_
 VALU,735.0,valu_
 MFMA,,mfma_
 VMEM,8.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,22.0,br_
 VGPR,24.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,67894.0,wavefronts_
 Workgroups,16973.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,163.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,0.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,44.0,hbm_rd_
 HBM Wr,0.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,70.0,vl1_coales_
 VL1 Stall,31.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,34.0,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/prev_analysis/2001.csv
index 789e7e8696..8bd23c6c1a 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/prev_analysis/201.csv
index b6d85c0e52..b613730933 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,59.89623919591283,Pct,100,59.89623919591283
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,63.966712023296324,Threads,64,99.9479875364005
 IPC - Issue,0.8437166068366146,Instr/cycle,5,16.874332136732292
-LDS BW,0.0,Gb/sec,23070.72,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,23070.72,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99343573281499,Pct,100,99.99343573281499
 Instr Cache BW,1407.4076865506725,Gb/s,4614.144,30.502032154841125
 Scalar L1D Cache Hit Rate,99.35620448527392,Pct,100,99.35620448527392
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/prev_analysis/602.csv
index 539a1b8d82..0ba736f221 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,50325.18562874252,0,848027,Simd
 Insufficient SIMD VGPRs,612548.7664670659,0,32137698,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/prev_analysis/701.csv
index d3f1bff5a3..1071413faa 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,23.976047904191617,8,36,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/sysinfo.csv
index 2f5c007a68..63401b16c3 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/sysinfo.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/sysinfo.csv
@@ -1,2 +1,2 @@
 workload_name,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,name,numSQC,hbmBW,ip_blocks
-no_roof_mixbench2,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 10:44:24 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
+no_roof_mixbench2,vesuvius,AMD EPYC 7542 32-Core Processor,,4.18.0-240.15.1.el8_3.x86_64,4.2.0-21,Thu Sep 22 10:44:24 2022 (CDT),gfx908,8,120,4,64,40,1024,16,,1502,1200,300,1200,32,mi100,48,1228.8,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/timestamps.csv
index 0e217bda73..ff2def26f9 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi100/timestamps.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,767988,767993,33554432,256,0,0,8,32,6464,0x0,0x7f5046004180,12073517721390637,12073517721430385,12073517721754222,12073517721862724
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,767988,767993,32768,256,0,0,24,24,12480,0x0,0x7f5046035100,12073517737447236,12073517737554518,12073517737561398,12073517737566849
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,767988,767993,4194304,256,0,0,24,24,12928,0x7f5151c37900,0x7f5046035140,12073517737624716,12073517737638997,12073517737768436,12073517737771760
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi200/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi200/SQ_IFETCH_LEVEL.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi200/SQ_IFETCH_LEVEL.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi200/SQ_IFETCH_LEVEL.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi200/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi200/SQ_INST_LEVEL_LDS.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi200/SQ_INST_LEVEL_LDS.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi200/SQ_INST_LEVEL_LDS.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi200/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi200/SQ_INST_LEVEL_SMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi200/SQ_INST_LEVEL_SMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi200/SQ_INST_LEVEL_SMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi200/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi200/SQ_INST_LEVEL_VMEM.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi200/SQ_INST_LEVEL_VMEM.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi200/SQ_INST_LEVEL_VMEM.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi200/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi200/SQ_LEVEL_WAVES.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi200/SQ_LEVEL_WAVES.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi200/SQ_LEVEL_WAVES.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi200/pmc_perf.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi200/pmc_perf.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi200/timestamps.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi200/timestamps.csv
+++ b/projects/rocprofiler-compute/tests/workloads/no_roof_mixbench2/mi200/timestamps.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_Axes1/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_Axes1/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_Axes1/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_Axes1/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_Axes1/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_Axes1/mi200/pmc_perf.csv
index 3c8b430cc8..d3639c3772 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_Axes1/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_Axes1/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,205593,205593,33554432,256,0,0,4,32,4160,0x0,0x7fb29e004280,0,0,0,0,0,0,0,0,0.0000000000,8388608.0000000000,4194304.0000000000,0.0000000000,0.0000000000,311.0000000000,4128768.0000000000,4128768.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,17328148540641,17298633283344,17328294281885,17328294388625
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,205593,205593,32768,256,0,0,12,24,13888,0x0,0x7fb29e023f80,0,0,0,0,0,0,0,0,8192.0000000000,16384.0000000000,0.0000000000,0.0000000000,0.0000000000,8261.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,17328300094873,17328294281885,17328300453942,17328300461664
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,205593,205593,4194304,256,0,0,12,24,14336,0x7fb2a0fd2380,0x7fb29e023fc0,0,0,0,0,0,0,262144,0,2097152.0000000000,2097152.0000000000,0.0000000000,0.0000000000,0.0000000000,2097345.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,17328301054088,17328300453942,17328301719073,17328301718850
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_Axes1/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_Axes1/mi200/prev_analysis/1.csv
index 33cef4faac..eb6aee867a 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_Axes1/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_Axes1/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 __amd_rocclr_fillBufferAligned.kd,1,29660998541.0,29660998541.0,29660998541.0,99.22771061668342
 "void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",1,6172057.0,6172057.0,6172057.0,0.0206479591393091
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4458908.0,4458908.0,4458908.0,0.014916801674051
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_Axes1/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_Axes1/mi200/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_Axes1/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_Axes1/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_Axes1/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_Axes1/mi200/prev_analysis/1202.csv
index d92c0479fa..2d4898d1f7 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_Axes1/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_Axes1/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,,,,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_Axes1/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_Axes1/mi200/prev_analysis/1901.csv
index 851728a829..b0b25b42c5 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_Axes1/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_Axes1/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,,il1_fetch_
 IL1 Hit,,il1_hit_
 IL1_L2 Rd,,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_Axes1/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_Axes1/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_Axes1/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_Axes1/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_Axes1/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_Axes1/mi200/prev_analysis/201.csv
index 913fc321d1..1cca5e2bc0 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_Axes1/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_Axes1/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,,Pct,100,
 Instr Cache BW,,Gb/s,6092.8,
 Scalar L1D Cache Hit Rate,,Pct,100,
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_Axes1/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_Axes1/mi200/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_Axes1/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_Axes1/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_Axes1/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_Axes1/mi200/prev_analysis/701.csv
index d28098ed25..9d9e3a3dab 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_Axes1/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_Axes1/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_Axes3/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_Axes3/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_Axes3/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_Axes3/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_Axes3/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_Axes3/mi200/pmc_perf.csv
index c083c5d3e5..17ec8109ea 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_Axes3/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_Axes3/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,217141,217141,33554432,256,0,0,4,32,4160,0x0,0x7f2001204280,0,0,0,0,0,0,0,0,0.0000000000,8388608.0000000000,4194304.0000000000,0.0000000000,0.0000000000,310.0000000000,4128768.0000000000,4128768.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,17512325752018,17482642185734,17512476050343,17512476140283
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,217141,217141,32768,256,0,0,12,24,13888,0x0,0x7f2001223f80,0,0,0,0,0,0,0,0,8192.0000000000,16384.0000000000,0.0000000000,0.0000000000,0.0000000000,8262.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,17512482013263,17512476050343,17512482376956,17512482390423
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,217141,217141,4194304,256,0,0,12,24,14336,0x7f20042db380,0x7f2001223fc0,0,0,0,0,0,0,262144,0,2097152.0000000000,2097152.0000000000,0.0000000000,0.0000000000,0.0000000000,2097340.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,17512482980408,17512482376956,17512483669287,17512483670420
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_Axes3/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_Axes3/mi200/prev_analysis/1.csv
index d861d71fe1..7984187748 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_Axes3/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_Axes3/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 __amd_rocclr_fillBufferAligned.kd,1,29833864609.0,29833864609.0,29833864609.0,99.22653947397896
 "void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",1,6326613.0,6326613.0,6326613.0,0.0210421252093404
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4425988.0,4425988.0,4425988.0,0.0147207034271004
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_Axes3/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_Axes3/mi200/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_Axes3/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_Axes3/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_Axes3/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_Axes3/mi200/prev_analysis/1202.csv
index d92c0479fa..2d4898d1f7 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_Axes3/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_Axes3/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,,,,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_Axes3/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_Axes3/mi200/prev_analysis/1901.csv
index 851728a829..b0b25b42c5 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_Axes3/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_Axes3/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,,il1_fetch_
 IL1 Hit,,il1_hit_
 IL1_L2 Rd,,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_Axes3/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_Axes3/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_Axes3/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_Axes3/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_Axes3/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_Axes3/mi200/prev_analysis/201.csv
index b4ae1214a3..6733520a78 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_Axes3/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_Axes3/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,,Pct,100,
 Instr Cache BW,,Gb/s,6092.8,
 Scalar L1D Cache Hit Rate,,Pct,100,
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_Axes3/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_Axes3/mi200/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_Axes3/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_Axes3/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_Axes3/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_Axes3/mi200/prev_analysis/701.csv
index d28098ed25..9d9e3a3dab 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_Axes3/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_Axes3/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_CPC/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_CPC/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_CPC/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_CPC/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_CPC/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_CPC/mi200/pmc_perf.csv
index f6a0376aa1..a5bcce7fac 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_CPC/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_CPC/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,162308,162308,33554432,256,0,0,4,32,4160,0x0,0x7f61e0a04280,0,0,0,0,0,0,0,0,0.0000000000,8388608.0000000000,4194304.0000000000,0.0000000000,0.0000000000,310.0000000000,4128768.0000000000,4128768.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,16520518872806,16491023118595,16520667653084,16520667762073
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,162308,162308,32768,256,0,0,12,24,13888,0x0,0x7f61e0a23f80,0,0,0,0,0,0,0,0,8192.0000000000,16384.0000000000,0.0000000000,0.0000000000,0.0000000000,8260.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,16520673724714,16520667653084,16520674074179,16520674084211
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,162308,162308,4194304,256,0,0,12,24,14336,0x7f61e3a19380,0x7f61e0a23fc0,0,0,0,0,0,0,262144,0,2097152.0000000000,2097152.0000000000,0.0000000000,0.0000000000,0.0000000000,2097346.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,16520674678969,16520674074179,16520675351614,16520675353724
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_CPC/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_CPC/mi200/prev_analysis/1.csv
index 7e2e343e67..eaf8e53faa 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_CPC/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_CPC/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 __amd_rocclr_fillBufferAligned.kd,1,29644534489.0,29644534489.0,29644534489.0,99.22609259689422
 "void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",1,6421095.0,6421095.0,6421095.0,0.0214926689869214
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4435842.0,4435842.0,4435842.0,0.0148476363897876
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_CPC/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_CPC/mi200/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_CPC/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_CPC/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_CPC/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_CPC/mi200/prev_analysis/1202.csv
index d92c0479fa..2d4898d1f7 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_CPC/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_CPC/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,,,,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_CPC/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_CPC/mi200/prev_analysis/1901.csv
index 851728a829..b0b25b42c5 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_CPC/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_CPC/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,,il1_fetch_
 IL1 Hit,,il1_hit_
 IL1_L2 Rd,,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_CPC/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_CPC/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_CPC/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_CPC/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_CPC/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_CPC/mi200/prev_analysis/201.csv
index 411a9aa763..2816f35615 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_CPC/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_CPC/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,,Pct,100,
 Instr Cache BW,,Gb/s,6092.8,
 Scalar L1D Cache Hit Rate,,Pct,100,
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_CPC/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_CPC/mi200/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_CPC/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_CPC/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_CPC/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_CPC/mi200/prev_analysis/701.csv
index d28098ed25..9d9e3a3dab 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_CPC/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_CPC/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_CPF/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_CPF/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_CPF/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_CPF/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_CPF/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_CPF/mi200/pmc_perf.csv
index 1115620497..ea01c83819 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_CPF/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_CPF/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,164619,164619,33554432,256,0,0,4,32,4160,0x0,0x7f2efe004280,0,0,0,0,0,0,0,0,0.0000000000,8388608.0000000000,4194304.0000000000,0.0000000000,0.0000000000,312.0000000000,4128768.0000000000,4128768.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,16589484657008,16559976781510,16589633008293,16589633115713
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,164619,164619,32768,256,0,0,12,24,13888,0x0,0x7f2efe023f80,0,0,0,0,0,0,0,0,8192.0000000000,16384.0000000000,0.0000000000,0.0000000000,0.0000000000,8261.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,16589638947649,16589633008293,16589639310059,16589639322106
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,164619,164619,4194304,256,0,0,12,24,14336,0x7f2f00f64380,0x7f2efe023fc0,0,0,0,0,0,0,262144,0,2097152.0000000000,2097152.0000000000,0.0000000000,0.0000000000,0.0000000000,2097320.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,16589639912225,16589639310059,16589640602540,16589640603050
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_CPF/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_CPF/mi200/prev_analysis/1.csv
index b5d34b562d..f1b292f986 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_CPF/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_CPF/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 __amd_rocclr_fillBufferAligned.kd,1,29656226783.0,29656226783.0,29656226783.0,99.21909562907538
 "void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",1,6301766.0,6301766.0,6301766.0,0.0210834482741572
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4456638.0,4456638.0,4456638.0,0.0149103119267905
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_CPF/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_CPF/mi200/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_CPF/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_CPF/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_CPF/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_CPF/mi200/prev_analysis/1202.csv
index d92c0479fa..2d4898d1f7 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_CPF/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_CPF/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,,,,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_CPF/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_CPF/mi200/prev_analysis/1901.csv
index 851728a829..b0b25b42c5 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_CPF/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_CPF/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,,il1_fetch_
 IL1 Hit,,il1_hit_
 IL1_L2 Rd,,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_CPF/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_CPF/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_CPF/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_CPF/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_CPF/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_CPF/mi200/prev_analysis/201.csv
index dcf7720743..9311a5bc6d 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_CPF/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_CPF/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,,Pct,100,
 Instr Cache BW,,Gb/s,6092.8,
 Scalar L1D Cache Hit Rate,,Pct,100,
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_CPF/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_CPF/mi200/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_CPF/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_CPF/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_CPF/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_CPF/mi200/prev_analysis/701.csv
index d28098ed25..9d9e3a3dab 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_CPF/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_CPF/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv1/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv1/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv1/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv1/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv1/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv1/mi200/pmc_perf.csv
index 8dfe278edb..543bb12a27 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv1/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv1/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,102416,102416,33554432,256,0,0,4,32,4160,0x0,0x7fc9b7004280,0,0,0,0,0,0,0,0,0.0000000000,8388608.0000000000,4194304.0000000000,0.0000000000,0.0000000000,311.0000000000,4128768.0000000000,4128768.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,15330719651419,15243124457419,15330870611126,15330870724846
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,102416,102416,32768,256,0,0,12,24,13888,0x0,0x7fc9b7023f80,0,0,0,0,0,0,0,0,8192.0000000000,16384.0000000000,0.0000000000,0.0000000000,0.0000000000,8260.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,15330876432134,15330870611126,15330876787979,15330876796316
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,102416,102416,4194304,256,0,0,12,24,14336,0x7fc9ba06b380,0x7fc9b7023fc0,0,0,0,0,0,0,262144,0,2097152.0000000000,2097152.0000000000,0.0000000000,0.0000000000,0.0000000000,2097405.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,15330877387372,15330876787979,15330877910389,15330877911280
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv1/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv1/mi200/prev_analysis/1.csv
index 78375d9c52..e05cffe505 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv1/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv1/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 __amd_rocclr_fillBufferAligned.kd,1,87746153707.0,87746153707.0,87746153707.0,99.7419519514935
 "void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",1,6176853.0,6176853.0,6176853.0,0.007021292092126
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4434120.0,4434120.0,4434120.0,0.0050403096352686
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv1/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv1/mi200/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv1/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv1/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv1/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv1/mi200/prev_analysis/1202.csv
index d92c0479fa..2d4898d1f7 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv1/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv1/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,,,,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv1/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv1/mi200/prev_analysis/1901.csv
index 851728a829..b0b25b42c5 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv1/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv1/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,,il1_fetch_
 IL1 Hit,,il1_hit_
 IL1_L2 Rd,,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv1/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv1/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv1/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv1/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv1/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv1/mi200/prev_analysis/201.csv
index a89867acca..07f44b635b 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv1/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv1/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,,Pct,100,
 Instr Cache BW,,Gb/s,6092.8,
 Scalar L1D Cache Hit Rate,,Pct,100,
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv1/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv1/mi200/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv1/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv1/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv1/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv1/mi200/prev_analysis/701.csv
index d28098ed25..9d9e3a3dab 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv1/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv1/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv2/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv2/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv2/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv2/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv2/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv2/mi200/pmc_perf.csv
index d53735c5c0..95681e6dc3 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv2/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv2/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,108518,108518,33554432,256,0,0,4,32,4160,0x0,0x7fdba1c04280,0,0,0,0,0,0,0,0,0.0000000000,8388608.0000000000,4194304.0000000000,0.0000000000,0.0000000000,309.0000000000,4128768.0000000000,4128768.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,15420570686057,15332452330118,15420714021758,15420714151109
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,108518,108518,32768,256,0,0,12,24,13888,0x0,0x7fdba1c23f80,0,0,0,0,0,0,0,0,8192.0000000000,16384.0000000000,0.0000000000,0.0000000000,0.0000000000,8261.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,15420719841538,15420714021758,15420720204852,15420720214030
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,108518,108518,4194304,256,0,0,12,24,14336,0x7fdba4bb6380,0x7fdba1c23fc0,0,0,0,0,0,0,262144,0,2097152.0000000000,2097152.0000000000,0.0000000000,0.0000000000,0.0000000000,2097344.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,15420720807056,15420720204852,15420721482624,15420721484331
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv2/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv2/mi200/prev_analysis/1.csv
index 082a7ed673..c1b28243ed 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv2/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv2/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 __amd_rocclr_fillBufferAligned.kd,1,88261691640.0,88261691640.0,88261691640.0,99.7363062606475
 "void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",1,6183094.0,6183094.0,6183094.0,0.0069869378816992
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4448021.0,4448021.0,4448021.0,0.005026293700774
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv2/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv2/mi200/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv2/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv2/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv2/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv2/mi200/prev_analysis/1202.csv
index d92c0479fa..2d4898d1f7 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv2/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv2/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,,,,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv2/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv2/mi200/prev_analysis/1901.csv
index 851728a829..b0b25b42c5 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv2/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv2/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,,il1_fetch_
 IL1 Hit,,il1_hit_
 IL1_L2 Rd,,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv2/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv2/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv2/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv2/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv2/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv2/mi200/prev_analysis/201.csv
index 6a27174a34..17f52fabb6 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv2/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv2/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,,Pct,100,
 Instr Cache BW,,Gb/s,6092.8,
 Scalar L1D Cache Hit Rate,,Pct,100,
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv2/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv2/mi200/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv2/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv2/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv2/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv2/mi200/prev_analysis/701.csv
index d28098ed25..9d9e3a3dab 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv2/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_int_inv2/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv1/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv1/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv1/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv1/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv1/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv1/mi200/pmc_perf.csv
index 4ab3416a52..6b252b6637 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv1/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv1/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,114620,114620,33554432,256,0,0,4,32,4160,0x0,0x7f2bcfe04280,0,0,0,0,0,0,0,0,0.0000000000,8388608.0000000000,4194304.0000000000,0.0000000000,0.0000000000,311.0000000000,4128768.0000000000,4128768.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,15517088512242,15487363706254,15517236090801,15517236203682
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,114620,114620,32768,256,0,0,12,24,13888,0x0,0x7f2bcfe23f80,0,0,0,0,0,0,0,0,8192.0000000000,16384.0000000000,0.0000000000,0.0000000000,0.0000000000,8262.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,15517241884213,15517236090801,15517242251349,15517242259244
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,114620,114620,4194304,256,0,0,12,24,14336,0x7f2bee72c380,0x7f2bcfe23fc0,0,0,0,0,0,0,262144,0,2097152.0000000000,2097152.0000000000,0.0000000000,0.0000000000,0.0000000000,2097347.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,15517242851931,15517242251349,15517243495363,15517243496306
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv1/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv1/mi200/prev_analysis/1.csv
index bf8bcc9c84..e0e4040bc3 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv1/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv1/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 __amd_rocclr_fillBufferAligned.kd,1,29872384547.0,29872384547.0,29872384547.0,99.22885276496584
 "void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",1,6160548.0,6160548.0,6160548.0,0.0204638538139365
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4464504.0,4464504.0,4464504.0,0.0148300049293885
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv1/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv1/mi200/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv1/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv1/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv1/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv1/mi200/prev_analysis/1202.csv
index d92c0479fa..2d4898d1f7 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv1/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv1/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,,,,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv1/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv1/mi200/prev_analysis/1901.csv
index 851728a829..b0b25b42c5 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv1/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv1/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,,il1_fetch_
 IL1 Hit,,il1_hit_
 IL1_L2 Rd,,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv1/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv1/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv1/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv1/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv1/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv1/mi200/prev_analysis/201.csv
index 699705d163..86249fb432 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv1/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv1/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,,Pct,100,
 Instr Cache BW,,Gb/s,6092.8,
 Scalar L1D Cache Hit Rate,,Pct,100,
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv1/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv1/mi200/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv1/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv1/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv1/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv1/mi200/prev_analysis/701.csv
index d28098ed25..9d9e3a3dab 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv1/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv1/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv2/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv2/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv2/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv2/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv2/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv2/mi200/pmc_perf.csv
index f390df1879..3f3cec119e 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv2/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv2/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,120722,120722,33554432,256,0,0,4,32,4160,0x0,0x7ff2fa404280,0,0,0,0,0,0,0,0,0.0000000000,8388608.0000000000,4194304.0000000000,0.0000000000,0.0000000000,311.0000000000,4128768.0000000000,4128768.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,15613780896939,15583988258908,15613931531711,15613931642012
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,120722,120722,32768,256,0,0,12,24,13888,0x0,0x7ff2fa423f80,0,0,0,0,0,0,0,0,8192.0000000000,16384.0000000000,0.0000000000,0.0000000000,0.0000000000,8262.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,15613937395062,15613931531711,15613937764423,15613937771844
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,120722,120722,4194304,256,0,0,12,24,14336,0x7ff2fd3a0380,0x7ff2fa423fc0,0,0,0,0,0,0,262144,0,2097152.0000000000,2097152.0000000000,0.0000000000,0.0000000000,0.0000000000,2097341.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,15613938364360,15613937764423,15613939038358,15613939039145
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv2/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv2/mi200/prev_analysis/1.csv
index b16b0faa69..0e38b2b257 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv2/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv2/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 __amd_rocclr_fillBufferAligned.kd,1,29943272803.0,29943272803.0,29943272803.0,99.22897810704605
 "void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",1,6232712.0,6232712.0,6232712.0,0.0206545772956909
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4452049.0,4452049.0,4452049.0,0.0147536401801821
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv2/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv2/mi200/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv2/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv2/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv2/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv2/mi200/prev_analysis/1202.csv
index d92c0479fa..2d4898d1f7 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv2/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv2/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,,,,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv2/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv2/mi200/prev_analysis/1901.csv
index 851728a829..b0b25b42c5 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv2/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv2/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,,il1_fetch_
 IL1 Hit,,il1_hit_
 IL1_L2 Rd,,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv2/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv2/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv2/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv2/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv2/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv2/mi200/prev_analysis/201.csv
index 579f2b1b43..de37f8d7b2 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv2/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv2/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,,Pct,100,
 Instr Cache BW,,Gb/s,6092.8,
 Scalar L1D Cache Hit Rate,,Pct,100,
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv2/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv2/mi200/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv2/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv2/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv2/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv2/mi200/prev_analysis/701.csv
index d28098ed25..9d9e3a3dab 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv2/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv2/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv3/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv3/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv3/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv3/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv3/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv3/mi200/pmc_perf.csv
index c437d9edce..93b183f3a2 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv3/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv3/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,126824,126824,33554432,256,0,0,4,32,4160,0x0,0x7fd82b004280,0,0,0,0,0,0,0,0,0.0000000000,8388608.0000000000,4194304.0000000000,0.0000000000,0.0000000000,315.0000000000,4128768.0000000000,4128768.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,15710253338650,15680563968401,15710401474468,15710401586078
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,126824,126824,32768,256,0,0,12,24,13888,0x0,0x7fd82b023f80,0,0,0,0,0,0,0,0,8192.0000000000,16384.0000000000,0.0000000000,0.0000000000,0.0000000000,8261.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,15710407289300,15710401474468,15710407651800,15710407660762
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,126824,126824,4194304,256,0,0,12,24,14336,0x7fd82e07d380,0x7fd82b023fc0,0,0,0,0,0,0,262144,0,2097152.0000000000,2097152.0000000000,0.0000000000,0.0000000000,0.0000000000,2097344.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,15710408251788,15710407651800,15710408896611,15710408898504
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv3/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv3/mi200/prev_analysis/1.csv
index c29da335d9..d6270b93d2 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv3/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv3/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 __amd_rocclr_fillBufferAligned.kd,1,29837506067.0,29837506067.0,29837506067.0,99.23941666644711
 "void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",1,6177332.0,6177332.0,6177332.0,0.0205457796257639
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4448845.0,4448845.0,4448845.0,0.0147968393084881
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv3/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv3/mi200/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv3/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv3/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv3/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv3/mi200/prev_analysis/1202.csv
index d92c0479fa..2d4898d1f7 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv3/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv3/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,,,,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv3/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv3/mi200/prev_analysis/1901.csv
index 851728a829..b0b25b42c5 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv3/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv3/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,,il1_fetch_
 IL1 Hit,,il1_hit_
 IL1_L2 Rd,,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv3/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv3/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv3/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv3/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv3/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv3/mi200/prev_analysis/201.csv
index 5ff6ae3ef1..ef4e819b4e 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv3/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv3/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,,Pct,100,
 Instr Cache BW,,Gb/s,6092.8,
 Scalar L1D Cache Hit Rate,,Pct,100,
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv3/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv3/mi200/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv3/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv3/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv3/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv3/mi200/prev_analysis/701.csv
index d28098ed25..9d9e3a3dab 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv3/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv3/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv4/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv4/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv4/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv4/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv4/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv4/mi200/pmc_perf.csv
index ba62f73c16..6662628112 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv4/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv4/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,132926,132926,33554432,256,0,0,4,32,4160,0x0,0x7f89faa04280,0,0,0,0,0,0,0,0,0.0000000000,8388608.0000000000,4194304.0000000000,0.0000000000,0.0000000000,311.0000000000,4128768.0000000000,4128768.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,15806967305719,15777288463617,15807116368340,15807116481120
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,132926,132926,32768,256,0,0,12,24,13888,0x0,0x7f89faa23f80,0,0,0,0,0,0,0,0,8192.0000000000,16384.0000000000,0.0000000000,0.0000000000,0.0000000000,8260.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,15807122193772,15807116368340,15807122551194,15807122559654
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,132926,132926,4194304,256,0,0,12,24,14336,0x7f89fdae8380,0x7f89faa23fc0,0,0,0,0,0,0,262144,0,2097152.0000000000,2097152.0000000000,0.0000000000,0.0000000000,0.0000000000,2097345.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,15807123149841,15807122551194,15807123793172,15807123794577
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv4/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv4/mi200/prev_analysis/1.csv
index a8bc049c6f..278d246a34 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv4/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv4/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 __amd_rocclr_fillBufferAligned.kd,1,29827904723.0,29827904723.0,29827904723.0,99.2408181455058
 "void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",1,6182854.0,6182854.0,6182854.0,0.0205710556987624
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4421975.0,4421975.0,4421975.0,0.0147124117799862
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv4/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv4/mi200/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv4/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv4/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv4/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv4/mi200/prev_analysis/1202.csv
index d92c0479fa..2d4898d1f7 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv4/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv4/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,,,,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv4/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv4/mi200/prev_analysis/1901.csv
index 851728a829..b0b25b42c5 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv4/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv4/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,,il1_fetch_
 IL1 Hit,,il1_hit_
 IL1_L2 Rd,,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv4/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv4/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv4/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv4/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv4/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv4/mi200/prev_analysis/201.csv
index 89cd3dee57..ca0f621002 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv4/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv4/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,,Pct,100,
 Instr Cache BW,,Gb/s,6092.8,
 Scalar L1D Cache Hit Rate,,Pct,100,
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv4/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv4/mi200/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv4/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv4/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv4/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv4/mi200/prev_analysis/701.csv
index d28098ed25..9d9e3a3dab 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv4/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_str_inv4/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int/mi200/pmc_perf.csv
index cb3f4b1207..513a4e18be 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,90213,90213,33554432,256,0,0,4,32,4160,0x0,0x7f7f2e604280,0,0,0,0,0,0,0,0,0.0000000000,8388608.0000000000,4194304.0000000000,0.0000000000,0.0000000000,313.0000000000,4128768.0000000000,4128768.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,15145717486186,15116253847183,15145861543375,15145861655726
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,90213,90213,32768,256,0,0,12,24,13888,0x0,0x7f7f2e623f80,0,0,0,0,0,0,0,0,8192.0000000000,16384.0000000000,0.0000000000,0.0000000000,0.0000000000,8262.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,15145867307003,15145861543375,15145867663284,15145867669984
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,90213,90213,4194304,256,0,0,12,24,14336,0x7f7f316e2380,0x7f7f2e623fc0,0,0,0,0,0,0,262144,0,2097152.0000000000,2097152.0000000000,0.0000000000,0.0000000000,0.0000000000,2097344.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,15145868263630,15145867663284,15145868913538,15145868913375
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int/mi200/prev_analysis/1.csv
index fc1a0c3f4b..f23ab14d46 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 __amd_rocclr_fillBufferAligned.kd,1,29607696192.0,29607696192.0,29607696192.0,99.25074868830563
 "void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",1,6119909.0,6119909.0,6119909.0,0.0205151237102473
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4409152.0,4409152.0,4409152.0,0.0147803339456983
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int/mi200/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int/mi200/prev_analysis/1202.csv
index d92c0479fa..2d4898d1f7 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,,,,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int/mi200/prev_analysis/1901.csv
index 851728a829..b0b25b42c5 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,,il1_fetch_
 IL1 Hit,,il1_hit_
 IL1_L2 Rd,,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int/mi200/prev_analysis/201.csv
index 687baf4e63..ca61587ecf 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,,Pct,100,
 Instr Cache BW,,Gb/s,6092.8,
 Scalar L1D Cache Hit Rate,,Pct,100,
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int/mi200/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int/mi200/prev_analysis/701.csv
index d28098ed25..9d9e3a3dab 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int2/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int2/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int2/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int2/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int2/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int2/mi200/pmc_perf.csv
index a272f70cf1..019a2d30c5 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int2/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int2/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,96314,96314,33554432,256,0,0,4,32,4160,0x0,0x7f595b004280,0,0,0,0,0,0,0,0,0.0000000000,8388608.0000000000,4194304.0000000000,0.0000000000,0.0000000000,309.0000000000,4128768.0000000000,4128768.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,15241382167702,15211932856560,15241530205012,15241530319533
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,96314,96314,32768,256,0,0,12,24,13888,0x0,0x7f595b023f80,0,0,0,0,0,0,0,0,8192.0000000000,16384.0000000000,0.0000000000,0.0000000000,0.0000000000,8261.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,15241536016130,15241530205012,15241536374688,15241536381492
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,96314,96314,4194304,256,0,0,12,24,14336,0x7f595df80380,0x7f595b023fc0,0,0,0,0,0,0,262144,0,2097152.0000000000,2097152.0000000000,0.0000000000,0.0000000000,0.0000000000,2097400.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,15241536971708,15241536374688,15241537488942,15241537488526
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int2/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int2/mi200/prev_analysis/1.csv
index 31e7a768a2..6102e60a91 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int2/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int2/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 __amd_rocclr_fillBufferAligned.kd,1,29597348452.0,29597348452.0,29597348452.0,99.24638013861691
 "void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",1,6169676.0,6169676.0,6169676.0,0.0206882724856633
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4397460.0,4397460.0,4397460.0,0.0147456447834221
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int2/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int2/mi200/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int2/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int2/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int2/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int2/mi200/prev_analysis/1202.csv
index d92c0479fa..2d4898d1f7 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int2/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int2/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,,,,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int2/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int2/mi200/prev_analysis/1901.csv
index 851728a829..b0b25b42c5 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int2/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int2/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,,il1_fetch_
 IL1 Hit,,il1_hit_
 IL1_L2 Rd,,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int2/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int2/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int2/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int2/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int2/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int2/mi200/prev_analysis/201.csv
index f9200ef528..c951db777e 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int2/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int2/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,,Pct,100,
 Instr Cache BW,,Gb/s,6092.8,
 Scalar L1D Cache Hit Rate,,Pct,100,
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int2/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int2/mi200/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int2/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int2/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int2/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int2/mi200/prev_analysis/701.csv
index d28098ed25..9d9e3a3dab 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int2/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_D_val_int2/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_Double_N_flag/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_Double_N_flag/mi200/pmc_perf.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_Double_N_flag/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_Double_N_flag/mi200/pmc_perf.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_HBM/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_HBM/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_HBM/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_HBM/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_HBM/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_HBM/mi200/pmc_perf.csv
index fcb35d4ac1..b700076072 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_HBM/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_HBM/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,174459,174459,33554432,256,0,0,4,32,4160,0x0,0x7ff75ae04280,0,0,0,0,0,0,0,0,0.0000000000,8388608.0000000000,4194304.0000000000,0.0000000000,0.0000000000,311.0000000000,4128768.0000000000,4128768.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,16783573042989,16754148541192,16783724669610,16783724755920
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,174459,174459,32768,256,0,0,12,24,13888,0x0,0x7ff75ae23f80,0,0,0,0,0,0,0,0,8192.0000000000,16384.0000000000,0.0000000000,0.0000000000,0.0000000000,8261.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,16783730483369,16783724669610,16783730847392,16783730853797
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,174459,174459,4194304,256,0,0,12,24,14336,0x7ff75dd33380,0x7ff75ae23fc0,0,0,0,0,0,0,262144,0,2097152.0000000000,2097152.0000000000,0.0000000000,0.0000000000,0.0000000000,2097343.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,16783731445389,16783730847392,16783732090117,16783732090038
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_HBM/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_HBM/mi200/prev_analysis/1.csv
index 7b834f6405..987f0136f6 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_HBM/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_HBM/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 __amd_rocclr_fillBufferAligned.kd,1,29576128418.0,29576128418.0,29576128418.0,99.23625177373926
 "void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",1,6177782.0,6177782.0,6177782.0,0.0207282008412624
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4409754.0,4409754.0,4409754.0,0.0147959682896807
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_HBM/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_HBM/mi200/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_HBM/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_HBM/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_HBM/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_HBM/mi200/prev_analysis/1202.csv
index d92c0479fa..2d4898d1f7 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_HBM/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_HBM/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,,,,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_HBM/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_HBM/mi200/prev_analysis/1901.csv
index 851728a829..b0b25b42c5 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_HBM/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_HBM/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,,il1_fetch_
 IL1 Hit,,il1_hit_
 IL1_L2 Rd,,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_HBM/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_HBM/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_HBM/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_HBM/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_HBM/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_HBM/mi200/prev_analysis/201.csv
index cec346876b..e08672005f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_HBM/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_HBM/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,,Pct,100,
 Instr Cache BW,,Gb/s,6092.8,
 Scalar L1D Cache Hit Rate,,Pct,100,
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_HBM/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_HBM/mi200/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_HBM/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_HBM/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_HBM/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_HBM/mi200/prev_analysis/701.csv
index d28098ed25..9d9e3a3dab 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_HBM/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_HBM/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv1/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv1/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv1/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv1/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv1/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv1/mi200/pmc_perf.csv
index 470d59142d..923951e326 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv1/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv1/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,59702,59702,33554432,256,0,0,4,32,4160,0x0,0x7f9e6da04280,0,0,0,0,0,0,0,0,0.0000000000,8388608.0000000000,4194304.0000000000,0.0000000000,0.0000000000,309.0000000000,4128768.0000000000,4128768.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,14691913001922,14599532832783,14692062114939,14692062228659
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,59702,59702,32768,256,0,0,12,24,13888,0x0,0x7f9e6da23f80,0,0,0,0,0,0,0,0,8192.0000000000,16384.0000000000,0.0000000000,0.0000000000,0.0000000000,8262.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,14692067914950,14692062114939,14692068278978,14692068287890
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,59702,59702,4194304,256,0,0,12,24,14336,0x7f9e7097f380,0x7f9e6da23fc0,0,0,0,0,0,0,262144,0,2097152.0000000000,2097152.0000000000,0.0000000000,0.0000000000,0.0000000000,2097406.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,14692068878895,14692068278978,14692069398505,14692069399671
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv1/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv1/mi200/prev_analysis/1.csv
index bfb8e56c40..60f086e513 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv1/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv1/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 __amd_rocclr_fillBufferAligned.kd,1,92529282156.0,92529282156.0,92529282156.0,99.74940158629208
 "void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",1,6164039.0,6164039.0,6164039.0,0.0066450229298001
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4457308.0,4457308.0,4457308.0,0.004805114611569
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv1/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv1/mi200/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv1/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv1/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv1/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv1/mi200/prev_analysis/1202.csv
index d92c0479fa..2d4898d1f7 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv1/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv1/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,,,,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv1/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv1/mi200/prev_analysis/1901.csv
index 851728a829..b0b25b42c5 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv1/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv1/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,,il1_fetch_
 IL1 Hit,,il1_hit_
 IL1_L2 Rd,,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv1/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv1/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv1/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv1/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv1/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv1/mi200/prev_analysis/201.csv
index 8302d97635..d4f5117903 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv1/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv1/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,,Pct,100,
 Instr Cache BW,,Gb/s,6092.8,
 Scalar L1D Cache Hit Rate,,Pct,100,
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv1/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv1/mi200/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv1/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv1/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv1/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv1/mi200/prev_analysis/701.csv
index d28098ed25..9d9e3a3dab 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv1/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv1/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv2/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv2/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv2/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv2/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv2/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv2/mi200/pmc_perf.csv
index 6ff5a14f04..c52903cf25 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv2/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv2/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,65804,65804,33554432,256,0,0,4,32,4160,0x0,0x7fb582604280,0,0,0,0,0,0,0,0,0.0000000000,8388608.0000000000,4194304.0000000000,0.0000000000,0.0000000000,313.0000000000,4128768.0000000000,4128768.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,14781311140231,14693658144127,14781459685624,14781459799614
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,65804,65804,32768,256,0,0,12,24,13888,0x0,0x7fb582623f80,0,0,0,0,0,0,0,0,8192.0000000000,16384.0000000000,0.0000000000,0.0000000000,0.0000000000,8261.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,14781465472460,14781459685624,14781465837333,14781465846890
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,65804,65804,4194304,256,0,0,12,24,14336,0x7fb585550380,0x7fb582623fc0,0,0,0,0,0,0,262144,0,2097152.0000000000,2097152.0000000000,0.0000000000,0.0000000000,0.0000000000,2097341.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,14781466438725,14781465837333,14781467114459,14781467116558
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv2/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv2/mi200/prev_analysis/1.csv
index f56e4e9e23..15ae629493 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv2/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv2/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 __amd_rocclr_fillBufferAligned.kd,1,87801541497.0,87801541497.0,87801541497.0,99.73410084226498
 "void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",1,6151709.0,6151709.0,6151709.0,0.0069877493640499
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4502572.0,4502572.0,4502572.0,0.0051144884502159
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv2/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv2/mi200/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv2/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv2/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv2/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv2/mi200/prev_analysis/1202.csv
index d92c0479fa..2d4898d1f7 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv2/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv2/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,,,,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv2/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv2/mi200/prev_analysis/1901.csv
index 851728a829..b0b25b42c5 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv2/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv2/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,,il1_fetch_
 IL1 Hit,,il1_hit_
 IL1_L2 Rd,,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv2/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv2/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv2/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv2/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv2/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv2/mi200/prev_analysis/201.csv
index cceb7f0cd9..38fa0692d0 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv2/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv2/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,,Pct,100,
 Instr Cache BW,,Gb/s,6092.8,
 Scalar L1D Cache Hit Rate,,Pct,100,
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv2/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv2/mi200/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv2/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv2/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv2/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv2/mi200/prev_analysis/701.csv
index d28098ed25..9d9e3a3dab 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv2/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_K_int_inv2/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv1/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv1/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv1/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv1/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv1/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv1/mi200/pmc_perf.csv
index 61431d558b..2c1bcf8a96 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv1/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv1/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,71906,71906,33554432,256,0,0,4,32,4160,0x0,0x7f6d79004280,0,0,0,0,0,0,0,0,0.0000000000,8388608.0000000000,4194304.0000000000,0.0000000000,0.0000000000,310.0000000000,4128768.0000000000,4128768.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,14870772139928,14783046182807,14870919443217,14870919556787
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,71906,71906,32768,256,0,0,12,24,13888,0x0,0x7f6d79023f80,0,0,0,0,0,0,0,0,8192.0000000000,16384.0000000000,0.0000000000,0.0000000000,0.0000000000,8260.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,14870925209226,14870919443217,14870925561500,14870925570597
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,71906,71906,4194304,256,0,0,12,24,14336,0x7f6d7c0f8380,0x7f6d79023fc0,0,0,0,0,0,0,262144,0,2097152.0000000000,2097152.0000000000,0.0000000000,0.0000000000,0.0000000000,2097339.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,14870926161133,14870925561500,14870926812549,14870926813746
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv1/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv1/mi200/prev_analysis/1.csv
index b492bc8149..72d0dce625 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv1/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv1/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 __amd_rocclr_fillBufferAligned.kd,1,87873260410.0,87873260410.0,87873260410.0,99.74033164063
 "void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",1,6118283.0,6118283.0,6118283.0,0.0069445423174691
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4458253.0,4458253.0,4458253.0,0.0050603292820034
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv1/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv1/mi200/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv1/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv1/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv1/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv1/mi200/prev_analysis/1202.csv
index d92c0479fa..2d4898d1f7 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv1/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv1/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,,,,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv1/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv1/mi200/prev_analysis/1901.csv
index 851728a829..b0b25b42c5 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv1/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv1/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,,il1_fetch_
 IL1 Hit,,il1_hit_
 IL1_L2 Rd,,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv1/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv1/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv1/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv1/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv1/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv1/mi200/prev_analysis/201.csv
index 91f6e81565..2a362e046c 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv1/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv1/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,,Pct,100,
 Instr Cache BW,,Gb/s,6092.8,
 Scalar L1D Cache Hit Rate,,Pct,100,
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv1/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv1/mi200/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv1/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv1/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv1/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv1/mi200/prev_analysis/701.csv
index d28098ed25..9d9e3a3dab 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv1/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv1/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv2/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv2/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv2/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv2/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv2/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv2/mi200/pmc_perf.csv
index 62e495031e..1fd6eceaeb 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv2/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv2/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,78008,78008,33554432,256,0,0,4,32,4160,0x0,0x7f966c804280,0,0,0,0,0,0,0,0,0.0000000000,8388608.0000000000,4194304.0000000000,0.0000000000,0.0000000000,312.0000000000,4128768.0000000000,4128768.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,14960240010012,14872493531272,14960387588886,14960387702876
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,78008,78008,32768,256,0,0,12,24,13888,0x0,0x7f966c823f80,0,0,0,0,0,0,0,0,8192.0000000000,16384.0000000000,0.0000000000,0.0000000000,0.0000000000,8261.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,14960393408266,14960387588886,14960393770527,14960393780407
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,78008,78008,4194304,256,0,0,12,24,14336,0x7f966f74f380,0x7f966c823fc0,0,0,0,0,0,0,262144,0,2097152.0000000000,2097152.0000000000,0.0000000000,0.0000000000,0.0000000000,2097342.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,14960394372733,14960393770527,14960395010855,14960395012787
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv2/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv2/mi200/prev_analysis/1.csv
index 34b97b520d..cab7ab2d35 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv2/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv2/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 __amd_rocclr_fillBufferAligned.kd,1,87894057614.0,87894057614.0,87894057614.0,99.73147771891544
 "void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",1,6181641.0,6181641.0,6181641.0,0.0070141737495531
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4462897.0,4462897.0,4462897.0,0.0050639522716313
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv2/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv2/mi200/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv2/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv2/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv2/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv2/mi200/prev_analysis/1202.csv
index d92c0479fa..2d4898d1f7 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv2/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv2/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,,,,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv2/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv2/mi200/prev_analysis/1901.csv
index 851728a829..b0b25b42c5 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv2/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv2/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,,il1_fetch_
 IL1 Hit,,il1_hit_
 IL1_L2 Rd,,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv2/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv2/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv2/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv2/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv2/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv2/mi200/prev_analysis/201.csv
index 6dcc06cb88..1f38957dd4 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv2/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv2/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,,Pct,100,
 Instr Cache BW,,Gb/s,6092.8,
 Scalar L1D Cache Hit Rate,,Pct,100,
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv2/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv2/mi200/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv2/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv2/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv2/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv2/mi200/prev_analysis/701.csv
index d28098ed25..9d9e3a3dab 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv2/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv2/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv3/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv3/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv3/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv3/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv3/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv3/mi200/pmc_perf.csv
index 5c7a88dbe1..038744fd8f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv3/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv3/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,84111,84111,33554432,256,0,0,4,32,4160,0x0,0x7f2dfde04280,0,0,0,0,0,0,0,0,0.0000000000,8388608.0000000000,4194304.0000000000,0.0000000000,0.0000000000,312.0000000000,4128768.0000000000,4128768.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,15049861203743,14961989947248,15050009953037,15050010068478
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,84111,84111,32768,256,0,0,12,24,13888,0x0,0x7f2dfde23f80,0,0,0,0,0,0,0,0,8192.0000000000,16384.0000000000,0.0000000000,0.0000000000,0.0000000000,8260.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,15050015807991,15050009953037,15050016173419,15050016180822
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,84111,84111,4194304,256,0,0,12,24,14336,0x7f2e00e0f380,0x7f2dfde23fc0,0,0,0,0,0,0,262144,0,2097152.0000000000,2097152.0000000000,0.0000000000,0.0000000000,0.0000000000,2097333.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,15050016771467,15050016173419,15050017440152,15050017441031
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv3/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv3/mi200/prev_analysis/1.csv
index 4f44566861..e8bf25c40c 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv3/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv3/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 __amd_rocclr_fillBufferAligned.kd,1,88020005789.0,88020005789.0,88020005789.0,99.7384228668172
 "void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",1,6220382.0,6220382.0,6220382.0,0.0070485236253719
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4478899.0,4478899.0,4478899.0,0.0050751907868607
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv3/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv3/mi200/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv3/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv3/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv3/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv3/mi200/prev_analysis/1202.csv
index d92c0479fa..2d4898d1f7 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv3/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv3/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,,,,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv3/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv3/mi200/prev_analysis/1901.csv
index 851728a829..b0b25b42c5 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv3/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv3/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,,il1_fetch_
 IL1 Hit,,il1_hit_
 IL1_L2 Rd,,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv3/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv3/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv3/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv3/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv3/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv3/mi200/prev_analysis/201.csv
index b608ca8ffb..2e818e7515 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv3/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv3/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,,Pct,100,
 Instr Cache BW,,Gb/s,6092.8,
 Scalar L1D Cache Hit Rate,,Pct,100,
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv3/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv3/mi200/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv3/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv3/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv3/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv3/mi200/prev_analysis/701.csv
index d28098ed25..9d9e3a3dab 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv3/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_inv3/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_1/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_1/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_1/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_1/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_1/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_1/mi200/pmc_perf.csv
index fbfa936d7e..1e7f6d0e97 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_1/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_1/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,47261,47261,33554432,256,0,0,4,32,4160,0x0,0x7fd101204280,0,0,0,0,0,0,0,0,0.0000000000,8388608.0000000000,4194304.0000000000,0.0000000000,0.0000000000,313.0000000000,4128768.0000000000,4128768.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,14492681037870,14463287675963,14492824000968,14492824113968
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,47261,47261,32768,256,0,0,12,24,13888,0x0,0x7fd101223f80,0,0,0,0,0,0,0,0,8192.0000000000,16384.0000000000,0.0000000000,0.0000000000,0.0000000000,8262.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,14492829782188,14492824000968,14492830152844,14492830161467
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,47261,47261,4194304,256,0,0,12,24,14336,0x7fd104186380,0x7fd101223fc0,0,0,0,0,0,0,262144,0,2097152.0000000000,2097152.0000000000,0.0000000000,0.0000000000,0.0000000000,2097345.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,14492830752350,14492830152844,14492831419891,14492831420752
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_1/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_1/mi200/prev_analysis/1.csv
index c2a4b5b7d6..8b061106c9 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_1/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_1/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 __amd_rocclr_fillBufferAligned.kd,1,29536325005.0,29536325005.0,29536325005.0,99.2217742174304
 "void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",1,6151876.0,6151876.0,6151876.0,0.0206660798654639
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4444170.0,4444170.0,4444170.0,0.0149293601099402
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_1/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_1/mi200/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_1/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_1/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_1/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_1/mi200/prev_analysis/1202.csv
index d92c0479fa..2d4898d1f7 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_1/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_1/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,,,,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_1/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_1/mi200/prev_analysis/1901.csv
index 851728a829..b0b25b42c5 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_1/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_1/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,,il1_fetch_
 IL1 Hit,,il1_hit_
 IL1_L2 Rd,,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_1/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_1/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_1/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_1/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_1/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_1/mi200/prev_analysis/201.csv
index d2cfe43e62..1f305ec7ea 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_1/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_1/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,,Pct,100,
 Instr Cache BW,,Gb/s,6092.8,
 Scalar L1D Cache Hit Rate,,Pct,100,
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_1/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_1/mi200/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_1/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_1/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_1/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_1/mi200/prev_analysis/701.csv
index d28098ed25..9d9e3a3dab 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_1/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_1/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_2/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_2/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_2/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_2/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_2/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_2/mi200/pmc_perf.csv
index 503dbb2f10..7587d6c6b4 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_2/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_2/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,53363,53363,33554432,256,0,0,4,32,4160,0x0,0x7f9f56404280,0,0,0,0,0,0,0,0,0.0000000000,8388608.0000000000,4194304.0000000000,0.0000000000,0.0000000000,314.0000000000,4128768.0000000000,4128768.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,14597805653980,14568418294807,14597954468896,14597954584216
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,53363,53363,32768,256,0,0,12,24,13888,0x0,0x7f9f56423f80,0,0,0,0,0,0,0,0,8192.0000000000,16384.0000000000,0.0000000000,0.0000000000,0.0000000000,8262.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,14597960260353,14597954468896,14597960629258,14597960637023
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,53363,53363,4194304,256,0,0,12,24,14336,0x7f9f5936c380,0x7f9f56423fc0,0,0,0,0,0,0,262144,0,2097152.0000000000,2097152.0000000000,0.0000000000,0.0000000000,0.0000000000,2097405.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,14597961227437,14597960629258,14597961749266,14597961749593
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_2/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_2/mi200/prev_analysis/1.csv
index 906d757394..f5ea09ba35 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_2/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_2/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 __amd_rocclr_fillBufferAligned.kd,1,29536174089.0,29536174089.0,29536174089.0,99.222806027405
 "void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",1,6160362.0,6160362.0,6160362.0,0.0206949079438233
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4447205.0,4447205.0,4447205.0,0.0149397873180684
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_2/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_2/mi200/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_2/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_2/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_2/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_2/mi200/prev_analysis/1202.csv
index d92c0479fa..2d4898d1f7 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_2/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_2/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,,,,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_2/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_2/mi200/prev_analysis/1901.csv
index 851728a829..b0b25b42c5 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_2/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_2/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,,il1_fetch_
 IL1 Hit,,il1_hit_
 IL1_L2 Rd,,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_2/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_2/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_2/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_2/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_2/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_2/mi200/prev_analysis/201.csv
index 55b311c232..926e90b1d4 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_2/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_2/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,,Pct,100,
 Instr Cache BW,,Gb/s,6092.8,
 Scalar L1D Cache Hit Rate,,Pct,100,
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_2/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_2/mi200/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_2/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_2/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_2/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_2/mi200/prev_analysis/701.csv
index d28098ed25..9d9e3a3dab 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_2/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_K_str_valid_2/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_L2/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_L2/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_L2/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_L2/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_L2/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_L2/mi200/pmc_perf.csv
index 142c75b6a5..ea3e0b565a 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_L2/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_L2/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,180548,180548,33554432,256,0,0,4,32,4160,0x0,0x7fed38804280,0,0,0,0,0,0,0,0,0.0000000000,8388608.0000000000,4194304.0000000000,0.0000000000,0.0000000000,308.0000000000,4128768.0000000000,4128768.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,16889297252062,16859941870963,16889449132973,16889449247823
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,180548,180548,32768,256,0,0,12,24,13888,0x0,0x7fed38823f80,0,0,0,0,0,0,0,0,8192.0000000000,16384.0000000000,0.0000000000,0.0000000000,0.0000000000,8262.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,16889454940162,16889449132973,16889455308684,16889455315941
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,180548,180548,4194304,256,0,0,12,24,14336,0x7fed3b74b380,0x7fed38823fc0,0,0,0,0,0,0,262144,0,2097152.0000000000,2097152.0000000000,0.0000000000,0.0000000000,0.0000000000,2097342.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,16889455908753,16889455308684,16889456571411,16889456571293
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_L2/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_L2/mi200/prev_analysis/1.csv
index 07c75bd93a..6b478f1fd6 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_L2/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_L2/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 __amd_rocclr_fillBufferAligned.kd,1,29507262010.0,29507262010.0,29507262010.0,99.21172457762998
 "void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",1,6175711.0,6175711.0,6175711.0,0.0207644795574525
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4446091.0,4446091.0,4446091.0,0.0149490100297882
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_L2/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_L2/mi200/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_L2/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_L2/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_L2/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_L2/mi200/prev_analysis/1202.csv
index d92c0479fa..2d4898d1f7 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_L2/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_L2/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,,,,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_L2/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_L2/mi200/prev_analysis/1901.csv
index 851728a829..b0b25b42c5 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_L2/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_L2/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,,il1_fetch_
 IL1 Hit,,il1_hit_
 IL1_L2 Rd,,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_L2/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_L2/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_L2/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_L2/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_L2/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_L2/mi200/prev_analysis/201.csv
index bb579b7845..556b9e1e5b 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_L2/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_L2/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,,Pct,100,
 Instr Cache BW,,Gb/s,6092.8,
 Scalar L1D Cache Hit Rate,,Pct,100,
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_L2/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_L2/mi200/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_L2/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_L2/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_L2/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_L2/mi200/prev_analysis/701.csv
index d28098ed25..9d9e3a3dab 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_L2/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_L2/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_LDS/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_LDS/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_LDS/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_LDS/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_LDS/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_LDS/mi200/pmc_perf.csv
index 62f9f581b2..f9650f8114 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_LDS/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_LDS/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,186980,186980,33554432,256,0,0,4,32,4160,0x0,0x7f6c0e204280,0,0,0,0,0,0,0,0,0.0000000000,8388608.0000000000,4194304.0000000000,0.0000000000,0.0000000000,315.0000000000,4128768.0000000000,4128768.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,17002820107975,16973423661369,17002967452947,17002967565777
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,186980,186980,32768,256,0,0,12,24,13888,0x0,0x7f6c0e223f80,0,0,0,0,0,0,0,0,8192.0000000000,16384.0000000000,0.0000000000,0.0000000000,0.0000000000,8262.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,17002973219904,17002967452947,17002973580497,17002973587453
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,186980,186980,4194304,256,0,0,12,24,14336,0x7f6c11230380,0x7f6c0e223fc0,0,0,0,0,0,0,262144,0,2097152.0000000000,2097152.0000000000,0.0000000000,0.0000000000,0.0000000000,2097341.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,17002974180216,17002973580497,17002974838743,17002974839467
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_LDS/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_LDS/mi200/prev_analysis/1.csv
index fff96c691e..eebefd4679 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_LDS/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_LDS/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 __amd_rocclr_fillBufferAligned.kd,1,29543791578.0,29543791578.0,29543791578.0,99.24158692206888
 "void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",1,6127550.0,6127550.0,6127550.0,0.0205832682084433
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4440158.0,4440158.0,4440158.0,0.0149150905340413
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_LDS/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_LDS/mi200/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_LDS/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_LDS/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_LDS/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_LDS/mi200/prev_analysis/1202.csv
index d92c0479fa..2d4898d1f7 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_LDS/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_LDS/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,,,,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_LDS/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_LDS/mi200/prev_analysis/1901.csv
index 851728a829..b0b25b42c5 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_LDS/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_LDS/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,,il1_fetch_
 IL1 Hit,,il1_hit_
 IL1_L2 Rd,,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_LDS/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_LDS/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_LDS/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_LDS/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_LDS/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_LDS/mi200/prev_analysis/201.csv
index f5f89cb3eb..c0e81a9d52 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_LDS/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_LDS/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,,Pct,100,
 Instr Cache BW,,Gb/s,6092.8,
 Scalar L1D Cache Hit Rate,,Pct,100,
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_LDS/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_LDS/mi200/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_LDS/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_LDS/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_LDS/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_LDS/mi200/prev_analysis/701.csv
index d28098ed25..9d9e3a3dab 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_LDS/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_LDS/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_SPI/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_SPI/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_SPI/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_SPI/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_SPI/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_SPI/mi200/pmc_perf.csv
index 27a8f55f1b..a75248e03c 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_SPI/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_SPI/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,159758,159758,33554432,256,0,0,4,32,4160,0x0,0x7f72e1804280,0,0,0,0,0,0,0,0,0.0000000000,8388608.0000000000,4194304.0000000000,0.0000000000,0.0000000000,310.0000000000,4128768.0000000000,4128768.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,16448086270712,16418603047603,16448237267140,16448237380489
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,159758,159758,32768,256,0,0,12,24,13888,0x0,0x7f72e1823f80,0,0,0,0,0,0,0,0,8192.0000000000,16384.0000000000,0.0000000000,0.0000000000,0.0000000000,8261.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,16448243074489,16448237267140,16448243439105,16448243447194
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,159758,159758,4194304,256,0,0,12,24,14336,0x7f72e4853380,0x7f72e1823fc0,0,0,0,0,0,0,262144,0,2097152.0000000000,2097152.0000000000,0.0000000000,0.0000000000,0.0000000000,2097399.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,16448244039551,16448243439105,16448244564219,16448244564891
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_SPI/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_SPI/mi200/prev_analysis/1.csv
index 9fca85c808..bda676d3ff 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_SPI/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_SPI/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 __amd_rocclr_fillBufferAligned.kd,1,29634219537.0,29634219537.0,29634219537.0,99.22571504591832
 "void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",1,6171965.0,6171965.0,6171965.0,0.0206658940215632
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4445555.0,4445555.0,4445555.0,0.0148852704927896
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_SPI/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_SPI/mi200/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_SPI/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_SPI/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_SPI/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_SPI/mi200/prev_analysis/1202.csv
index d92c0479fa..2d4898d1f7 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_SPI/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_SPI/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,,,,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_SPI/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_SPI/mi200/prev_analysis/1901.csv
index 851728a829..b0b25b42c5 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_SPI/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_SPI/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,,il1_fetch_
 IL1 Hit,,il1_hit_
 IL1_L2 Rd,,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_SPI/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_SPI/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_SPI/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_SPI/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_SPI/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_SPI/mi200/prev_analysis/201.csv
index 8f05bb6b6f..14062fdadb 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_SPI/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_SPI/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,,Pct,100,
 Instr Cache BW,,Gb/s,6092.8,
 Scalar L1D Cache Hit Rate,,Pct,100,
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_SPI/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_SPI/mi200/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_SPI/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_SPI/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_SPI/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_SPI/mi200/prev_analysis/701.csv
index d28098ed25..9d9e3a3dab 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_SPI/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_SPI/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_SQ/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_SQ/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_SQ/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_SQ/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_SQ/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_SQ/mi200/pmc_perf.csv
index beb721f504..1c28a0e56f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_SQ/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_SQ/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,141956,141956,33554432,256,0,0,4,32,4160,0x0,0x7fe9f8604280,0,0,0,0,0,0,0,0,0.0000000000,8388608.0000000000,4194304.0000000000,0.0000000000,0.0000000000,311.0000000000,4128768.0000000000,4128768.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,15977203048375,15947876597242,15977351197736,15977351311147
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,141956,141956,32768,256,0,0,12,24,13888,0x0,0x7fe9f8623f80,0,0,0,0,0,0,0,0,8192.0000000000,16384.0000000000,0.0000000000,0.0000000000,0.0000000000,8260.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,15977357064979,15977351197736,15977357414595,15977357422521
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,141956,141956,4194304,256,0,0,12,24,14336,0x7fe9fb6cf380,0x7fe9f8623fc0,0,0,0,0,0,0,262144,0,2097152.0000000000,2097152.0000000000,0.0000000000,0.0000000000,0.0000000000,2097342.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,15977358014418,15977357414595,15977358936530,15977358938757
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_SQ/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_SQ/mi200/prev_analysis/1.csv
index b0a60f819b..56a7361e98 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_SQ/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_SQ/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 __amd_rocclr_fillBufferAligned.kd,1,29474600494.0,29474600494.0,29474600494.0,99.24311811271532
 "void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",1,6216859.0,6216859.0,6216859.0,0.0209326152580996
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4408181.0,4408181.0,4408181.0,0.0148426652206629
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_SQ/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_SQ/mi200/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_SQ/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_SQ/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_SQ/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_SQ/mi200/prev_analysis/1202.csv
index d92c0479fa..2d4898d1f7 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_SQ/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_SQ/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,,,,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_SQ/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_SQ/mi200/prev_analysis/1901.csv
index 851728a829..b0b25b42c5 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_SQ/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_SQ/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,,il1_fetch_
 IL1 Hit,,il1_hit_
 IL1_L2 Rd,,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_SQ/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_SQ/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_SQ/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_SQ/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_SQ/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_SQ/mi200/prev_analysis/201.csv
index b396e9730e..2010ddbeba 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_SQ/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_SQ/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,,Pct,100,
 Instr Cache BW,,Gb/s,6092.8,
 Scalar L1D Cache Hit Rate,,Pct,100,
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_SQ/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_SQ/mi200/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_SQ/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_SQ/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_SQ/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_SQ/mi200/prev_analysis/701.csv
index d28098ed25..9d9e3a3dab 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_SQ/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_SQ/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_SQC/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_SQC/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_SQC/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_SQC/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_SQC/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_SQC/mi200/pmc_perf.csv
index b7af76196f..0cd7400334 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_SQC/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_SQC/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,144607,144607,33554432,256,0,0,4,32,4160,0x0,0x7fe7c7c04280,0,0,0,0,0,0,0,0,0.0000000000,8388608.0000000000,4194304.0000000000,0.0000000000,0.0000000000,310.0000000000,4128768.0000000000,4128768.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,16054221396415,16024817672330,16054365492553,16054365604704
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,144607,144607,32768,256,0,0,12,24,13888,0x0,0x7fe7c7c23f80,0,0,0,0,0,0,0,0,8192.0000000000,16384.0000000000,0.0000000000,0.0000000000,0.0000000000,8261.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,16054371227310,16054365492553,16054371592314,16054371599322
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,144607,144607,4194304,256,0,0,12,24,14336,0x7fe7ee31a380,0x7fe7c7c23fc0,0,0,0,0,0,0,262144,0,2097152.0000000000,2097152.0000000000,0.0000000000,0.0000000000,0.0000000000,2097412.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,16054372190658,16054371592314,16054372738890,16054372738546
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_SQC/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_SQC/mi200/prev_analysis/1.csv
index 48dcc18fa1..a77a1a187d 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_SQC/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_SQC/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 __amd_rocclr_fillBufferAligned.kd,1,29547820223.0,29547820223.0,29547820223.0,99.20713262154166
 "void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",1,6099761.0,6099761.0,6099761.0,0.020480014901934
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4442107.0,4442107.0,4442107.0,0.0149144232955988
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_SQC/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_SQC/mi200/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_SQC/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_SQC/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_SQC/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_SQC/mi200/prev_analysis/1202.csv
index d92c0479fa..2d4898d1f7 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_SQC/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_SQC/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,,,,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_SQC/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_SQC/mi200/prev_analysis/1901.csv
index 851728a829..b0b25b42c5 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_SQC/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_SQC/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,,il1_fetch_
 IL1 Hit,,il1_hit_
 IL1_L2 Rd,,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_SQC/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_SQC/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_SQC/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_SQC/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_SQC/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_SQC/mi200/prev_analysis/201.csv
index 0bafd18828..d12ed7e85d 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_SQC/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_SQC/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,,Pct,100,
 Instr Cache BW,,Gb/s,6092.8,
 Scalar L1D Cache Hit Rate,,Pct,100,
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_SQC/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_SQC/mi200/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_SQC/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_SQC/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_SQC/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_SQC/mi200/prev_analysis/701.csv
index d28098ed25..9d9e3a3dab 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_SQC/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_SQC/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_TA/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_TA/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_TA/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_TA/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_TA/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_TA/mi200/pmc_perf.csv
index 2ac450c803..b5d96e2ecb 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_TA/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_TA/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,148357,148357,33554432,256,0,0,4,32,4160,0x0,0x7f6e8f004280,0,0,0,0,0,0,0,0,0.0000000000,8388608.0000000000,4194304.0000000000,0.0000000000,0.0000000000,311.0000000000,4128768.0000000000,4128768.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,16142398484129,16112925195297,16142549098160,16142549211241
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,148357,148357,32768,256,0,0,12,24,13888,0x0,0x7f6e8f023f80,0,0,0,0,0,0,0,0,8192.0000000000,16384.0000000000,0.0000000000,0.0000000000,0.0000000000,8262.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,16142554907195,16142549098160,16142555269587,16142555277116
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,148357,148357,4194304,256,0,0,12,24,14336,0x7f6e92099380,0x7f6e8f023fc0,0,0,0,0,0,0,262144,0,2097152.0000000000,2097152.0000000000,0.0000000000,0.0000000000,0.0000000000,2097409.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,16142555868513,16142555269587,16142556389119,16142556389932
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_TA/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_TA/mi200/prev_analysis/1.csv
index 5bde258272..b0dfb26e51 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_TA/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_TA/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 __amd_rocclr_fillBufferAligned.kd,1,29623902863.0,29623902863.0,29623902863.0,99.22198287926264
 "void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",1,6171427.0,6171427.0,6171427.0,0.0206705114773863
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4471249.0,4471249.0,4471249.0,0.0149759534987211
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_TA/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_TA/mi200/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_TA/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_TA/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_TA/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_TA/mi200/prev_analysis/1202.csv
index d92c0479fa..2d4898d1f7 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_TA/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_TA/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,,,,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_TA/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_TA/mi200/prev_analysis/1901.csv
index 851728a829..b0b25b42c5 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_TA/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_TA/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,,il1_fetch_
 IL1 Hit,,il1_hit_
 IL1_L2 Rd,,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_TA/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_TA/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_TA/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_TA/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_TA/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_TA/mi200/prev_analysis/201.csv
index d335c5dac8..04339ef9df 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_TA/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_TA/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,,Pct,100,
 Instr Cache BW,,Gb/s,6092.8,
 Scalar L1D Cache Hit Rate,,Pct,100,
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_TA/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_TA/mi200/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_TA/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_TA/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_TA/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_TA/mi200/prev_analysis/701.csv
index d28098ed25..9d9e3a3dab 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_TA/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_TA/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_TA_CPC/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_TA_CPC/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_TA_CPC/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_TA_CPC/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_TA_CPC/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_TA_CPC/mi200/pmc_perf.csv
index 008c2828dc..10159c6b43 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_TA_CPC/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_TA_CPC/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,168369,168369,33554432,256,0,0,4,32,4160,0x0,0x7fe7ed404280,0,0,0,0,0,0,0,0,0.0000000000,8388608.0000000000,4194304.0000000000,0.0000000000,0.0000000000,312.0000000000,4128768.0000000000,4128768.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,16677771755034,16648152677560,16677921588264,16677921702604
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,168369,168369,32768,256,0,0,12,24,13888,0x0,0x7fe7ed423f80,0,0,0,0,0,0,0,0,8192.0000000000,16384.0000000000,0.0000000000,0.0000000000,0.0000000000,8262.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,16677927396104,16677921588264,16677927756439,16677927763102
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,168369,168369,4194304,256,0,0,12,24,14336,0x7fe7f04a4380,0x7fe7ed423fc0,0,0,0,0,0,0,262144,0,2097152.0000000000,2097152.0000000000,0.0000000000,0.0000000000,0.0000000000,2097344.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,16677928354352,16677927756439,16677928997723,16677928997351
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_TA_CPC/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_TA_CPC/mi200/prev_analysis/1.csv
index 4870a44b5d..ff55356dcd 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_TA_CPC/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_TA_CPC/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 __amd_rocclr_fillBufferAligned.kd,1,29768910704.0,29768910704.0,29768910704.0,99.24263136572074
 "void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",1,6168175.0,6168175.0,6168175.0,0.0205632622507078
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4414856.0,4414856.0,4414856.0,0.0147181040951514
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_TA_CPC/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_TA_CPC/mi200/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_TA_CPC/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_TA_CPC/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_TA_CPC/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_TA_CPC/mi200/prev_analysis/1202.csv
index d92c0479fa..2d4898d1f7 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_TA_CPC/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_TA_CPC/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,,,,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_TA_CPC/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_TA_CPC/mi200/prev_analysis/1901.csv
index 851728a829..b0b25b42c5 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_TA_CPC/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_TA_CPC/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,,il1_fetch_
 IL1 Hit,,il1_hit_
 IL1_L2 Rd,,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_TA_CPC/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_TA_CPC/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_TA_CPC/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_TA_CPC/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_TA_CPC/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_TA_CPC/mi200/prev_analysis/201.csv
index 54b43ad243..83e8d722e8 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_TA_CPC/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_TA_CPC/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,,Pct,100,
 Instr Cache BW,,Gb/s,6092.8,
 Scalar L1D Cache Hit Rate,,Pct,100,
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_TA_CPC/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_TA_CPC/mi200/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_TA_CPC/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_TA_CPC/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_TA_CPC/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_TA_CPC/mi200/prev_analysis/701.csv
index d28098ed25..9d9e3a3dab 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_TA_CPC/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_TA_CPC/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_TCC/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_TCC/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_TCC/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_TCC/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_TCC/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_TCC/mi200/pmc_perf.csv
index 249de6e73a..49ddf771d4 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_TCC/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_TCC/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,156848,156848,33554432,256,0,0,4,32,4160,0x0,0x7f380ce04280,0,0,0,0,0,0,0,0,0.0000000000,8388608.0000000000,4194304.0000000000,0.0000000000,0.0000000000,310.0000000000,4128768.0000000000,4128768.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,16371864288421,16342420492463,16372007023849,16372007114530
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,156848,156848,32768,256,0,0,12,24,13888,0x0,0x7f380ce23f80,0,0,0,0,0,0,0,0,8192.0000000000,16384.0000000000,0.0000000000,0.0000000000,0.0000000000,8262.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,16372012904153,16372007023849,16372013279766,16372013293404
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,156848,156848,4194304,256,0,0,12,24,14336,0x7f380fde6380,0x7f380ce23fc0,0,0,0,0,0,0,262144,0,2097152.0000000000,2097152.0000000000,0.0000000000,0.0000000000,0.0000000000,2097345.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,16372013881771,16372013279766,16372014557542,16372014558206
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_TCC/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_TCC/mi200/prev_analysis/1.csv
index 9c026645da..e1e941b37f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_TCC/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_TCC/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 __amd_rocclr_fillBufferAligned.kd,1,29586531386.0,29586531386.0,29586531386.0,99.20248176254292
 "void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",1,6255917.0,6255917.0,6255917.0,0.0209758448533153
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4435252.0,4435252.0,4435252.0,0.0148712263665513
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_TCC/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_TCC/mi200/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_TCC/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_TCC/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_TCC/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_TCC/mi200/prev_analysis/1202.csv
index d92c0479fa..2d4898d1f7 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_TCC/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_TCC/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,,,,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_TCC/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_TCC/mi200/prev_analysis/1901.csv
index 851728a829..b0b25b42c5 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_TCC/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_TCC/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,,il1_fetch_
 IL1 Hit,,il1_hit_
 IL1_L2 Rd,,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_TCC/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_TCC/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_TCC/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_TCC/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_TCC/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_TCC/mi200/prev_analysis/201.csv
index 7d3ecc6e61..a110124fff 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_TCC/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_TCC/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,,Pct,100,
 Instr Cache BW,,Gb/s,6092.8,
 Scalar L1D Cache Hit Rate,,Pct,100,
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_TCC/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_TCC/mi200/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_TCC/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_TCC/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_TCC/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_TCC/mi200/prev_analysis/701.csv
index d28098ed25..9d9e3a3dab 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_TCC/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_TCC/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_TCP/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_TCP/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_TCP/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_TCP/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_TCP/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_TCP/mi200/pmc_perf.csv
index 3acc119a50..6076a831a0 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_TCP/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_TCP/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,153697,153697,33554432,256,0,0,4,32,4160,0x0,0x7f13bc404280,0,0,0,0,0,0,0,0,0.0000000000,8388608.0000000000,4194304.0000000000,0.0000000000,0.0000000000,311.0000000000,4128768.0000000000,4128768.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,16291940271305,16262516612906,16292087754015,16292087868156
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,153697,153697,32768,256,0,0,12,24,13888,0x0,0x7f13bc423f80,0,0,0,0,0,0,0,0,8192.0000000000,16384.0000000000,0.0000000000,0.0000000000,0.0000000000,8260.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,16292093558470,16292087754015,16292093923705,16292093931222
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,153697,153697,4194304,256,0,0,12,24,14336,0x7f13bf474380,0x7f13bc423fc0,0,0,0,0,0,0,262144,0,2097152.0000000000,2097152.0000000000,0.0000000000,0.0000000000,0.0000000000,2097400.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,16292094523139,16292093923705,16292095053962,16292095053377
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_TCP/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_TCP/mi200/prev_analysis/1.csv
index 1b9340193b..038b2222a4 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_TCP/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_TCP/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 __amd_rocclr_fillBufferAligned.kd,1,29571141109.0,29571141109.0,29571141109.0,99.21672136182292
 "void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",1,6169690.0,6169690.0,6169690.0,0.0207004664230735
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4452351.0,4452351.0,4452351.0,0.0149384721727085
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_TCP/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_TCP/mi200/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_TCP/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_TCP/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_TCP/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_TCP/mi200/prev_analysis/1202.csv
index d92c0479fa..2d4898d1f7 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_TCP/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_TCP/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,,,,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_TCP/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_TCP/mi200/prev_analysis/1901.csv
index 851728a829..b0b25b42c5 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_TCP/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_TCP/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,,il1_fetch_
 IL1 Hit,,il1_hit_
 IL1_L2 Rd,,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_TCP/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_TCP/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_TCP/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_TCP/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_TCP/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_TCP/mi200/prev_analysis/201.csv
index ca6284a63e..0d56439b92 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_TCP/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_TCP/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,,Pct,100,
 Instr Cache BW,,Gb/s,6092.8,
 Scalar L1D Cache Hit Rate,,Pct,100,
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_TCP/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_TCP/mi200/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_TCP/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_TCP/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_TCP/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_TCP/mi200/prev_analysis/701.csv
index d28098ed25..9d9e3a3dab 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_TCP/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_TCP/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_TD/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_TD/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_TD/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_TD/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_TD/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_TD/mi200/pmc_perf.csv
index a38176ffce..b3c9739057 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_TD/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_TD/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,150667,150667,33554432,256,0,0,4,32,4160,0x0,0x7fc121804280,0,0,0,0,0,0,0,0,0.0000000000,8388608.0000000000,4194304.0000000000,0.0000000000,0.0000000000,308.0000000000,4128768.0000000000,4128768.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,16211989329428,16182660644078,16212137848671,16212137916452
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,150667,150667,32768,256,0,0,12,24,13888,0x0,0x7fc121823f80,0,0,0,0,0,0,0,0,8192.0000000000,16384.0000000000,0.0000000000,0.0000000000,0.0000000000,8263.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,16212143957969,16212137848671,16212144321901,16212144331870
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,150667,150667,4194304,256,0,0,12,24,14336,0x7fc124780380,0x7fc121823fc0,0,0,0,0,0,0,262144,0,2097152.0000000000,2097152.0000000000,0.0000000000,0.0000000000,0.0000000000,2097341.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,16212144925347,16212144321901,16212145593922,16212145592683
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_TD/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_TD/mi200/prev_analysis/1.csv
index c42ea7b938..a019d6fbbd 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_TD/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_TD/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 __amd_rocclr_fillBufferAligned.kd,1,29477204593.0,29477204593.0,29477204593.0,99.19551611044498
 "void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",1,6473230.0,6473230.0,6473230.0,0.021783456050785
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4461366.0,4461366.0,4461366.0,0.0150132113624059
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_TD/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_TD/mi200/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_TD/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_TD/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_TD/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_TD/mi200/prev_analysis/1202.csv
index d92c0479fa..2d4898d1f7 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_TD/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_TD/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,,,,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_TD/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_TD/mi200/prev_analysis/1901.csv
index 851728a829..b0b25b42c5 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_TD/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_TD/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,,il1_fetch_
 IL1 Hit,,il1_hit_
 IL1_L2 Rd,,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_TD/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_TD/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_TD/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_TD/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_TD/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_TD/mi200/prev_analysis/201.csv
index 156ee4486c..d29abc56ef 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_TD/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_TD/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,,Pct,100,
 Instr Cache BW,,Gb/s,6092.8,
 Scalar L1D Cache Hit Rate,,Pct,100,
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_TD/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_TD/mi200/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_TD/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_TD/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_TD/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_TD/mi200/prev_analysis/701.csv
index d28098ed25..9d9e3a3dab 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_TD/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_TD/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_dev0/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_dev0/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_dev0/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_dev0/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_dev0/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_dev0/mi200/pmc_perf.csv
index a7dd1a1c3d..963902e436 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_dev0/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_dev0/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,228689,228689,33554432,256,0,0,4,32,4160,0x0,0x7fab9ca04280,0,0,0,0,0,0,0,0,0.0000000000,8388608.0000000000,4194304.0000000000,0.0000000000,0.0000000000,309.0000000000,4128768.0000000000,4128768.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,17695745996020,17666284958929,17695893731942,17695893846323
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,228689,228689,32768,256,0,0,12,24,13888,0x0,0x7fab9ca23f80,0,0,0,0,0,0,0,0,8192.0000000000,16384.0000000000,0.0000000000,0.0000000000,0.0000000000,8260.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,17695899546920,17695893731942,17695899908008,17695899915190
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,228689,228689,4194304,256,0,0,12,24,14336,0x7fab9f92d380,0x7fab9ca23fc0,0,0,0,0,0,0,262144,0,2097152.0000000000,2097152.0000000000,0.0000000000,0.0000000000,0.0000000000,2097342.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,17695900506745,17695899908008,17695901168501,17695901168529
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_dev0/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_dev0/mi200/prev_analysis/1.csv
index 11fffc3d2a..74aea7f8df 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_dev0/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_dev0/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 __amd_rocclr_fillBufferAligned.kd,1,29608773013.0,29608773013.0,29608773013.0,99.2264543637425
 "void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",1,6176066.0,6176066.0,6176066.0,0.0206975524054101
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4470104.0,4470104.0,4470104.0,0.0149804441529014
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_dev0/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_dev0/mi200/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_dev0/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_dev0/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_dev0/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_dev0/mi200/prev_analysis/1202.csv
index d92c0479fa..2d4898d1f7 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_dev0/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_dev0/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,,,,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_dev0/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_dev0/mi200/prev_analysis/1901.csv
index 851728a829..b0b25b42c5 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_dev0/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_dev0/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,,il1_fetch_
 IL1 Hit,,il1_hit_
 IL1_L2 Rd,,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_dev0/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_dev0/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_dev0/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_dev0/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_dev0/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_dev0/mi200/prev_analysis/201.csv
index cac5a5ccb4..21e1662a64 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_dev0/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_dev0/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,,Pct,100,
 Instr Cache BW,,Gb/s,6092.8,
 Scalar L1D Cache Hit Rate,,Pct,100,
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_dev0/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_dev0/mi200/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_dev0/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_dev0/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_dev0/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_dev0/mi200/prev_analysis/701.csv
index d28098ed25..9d9e3a3dab 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_dev0/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_dev0/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_dev1/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_dev1/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_dev1/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_dev1/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_dev1/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_dev1/mi200/pmc_perf.csv
index b479fd0130..9c56060a90 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_dev1/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_dev1/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,234779,234779,33554432,256,0,0,4,32,4160,0x0,0x7f6f5c804280,0,0,0,0,0,0,0,0,0.0000000000,8388608.0000000000,4194304.0000000000,0.0000000000,0.0000000000,312.0000000000,4128768.0000000000,4128768.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,17801452679825,17772096258178,17801596602238,17801596717129
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,234779,234779,32768,256,0,0,12,24,13888,0x0,0x7f6f5c823f80,0,0,0,0,0,0,0,0,8192.0000000000,16384.0000000000,0.0000000000,0.0000000000,0.0000000000,8260.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,17801602429427,17801596602238,17801602809336,17801602817287
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,234779,234779,4194304,256,0,0,12,24,14336,0x7f6f5f8a6380,0x7f6f5c823fc0,0,0,0,0,0,0,262144,0,2097152.0000000000,2097152.0000000000,0.0000000000,0.0000000000,0.0000000000,2097340.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,17801603409582,17801602809336,17801604038308,17801604038227
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_dev1/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_dev1/mi200/prev_analysis/1.csv
index cebeed1b9d..c0d3b0923a 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_dev1/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_dev1/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 __amd_rocclr_fillBufferAligned.kd,1,29500344060.0,29500344060.0,29500344060.0,99.22811976903076
 "void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",1,6207098.0,6207098.0,6207098.0,0.0208783552662779
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4464999.0,4464999.0,4464999.0,0.0150185860422335
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_dev1/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_dev1/mi200/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_dev1/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_dev1/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_dev1/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_dev1/mi200/prev_analysis/1202.csv
index d92c0479fa..2d4898d1f7 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_dev1/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_dev1/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,,,,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_dev1/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_dev1/mi200/prev_analysis/1901.csv
index 851728a829..b0b25b42c5 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_dev1/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_dev1/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,,il1_fetch_
 IL1 Hit,,il1_hit_
 IL1_L2 Rd,,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_dev1/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_dev1/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_dev1/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_dev1/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_dev1/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_dev1/mi200/prev_analysis/201.csv
index 57b970cc37..a3ad98b175 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_dev1/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_dev1/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,,Pct,100,
 Instr Cache BW,,Gb/s,6092.8,
 Scalar L1D Cache Hit Rate,,Pct,100,
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_dev1/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_dev1/mi200/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_dev1/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_dev1/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_dev1/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_dev1/mi200/prev_analysis/701.csv
index d28098ed25..9d9e3a3dab 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_dev1/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_dev1/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_dispatches/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_dispatches/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_dispatches/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_dispatches/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_dispatches/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_dispatches/mi200/pmc_perf.csv
index 8bdf2e9a7d..b61d399377 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_dispatches/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_dispatches/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,199502,199502,33554432,256,0,0,4,32,4160,0x0,0x7f7fb9804280,0,0,0,0,0,0,0,0,0.0000000000,8388608.0000000000,4194304.0000000000,0.0000000000,0.0000000000,309.0000000000,4128768.0000000000,4128768.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,17222302751740,17192960227537,17222452892635,17222453005765
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,199502,199502,32768,256,0,0,12,24,13888,0x0,0x7f7fb9823f80,0,0,0,0,0,0,0,0,8192.0000000000,16384.0000000000,0.0000000000,0.0000000000,0.0000000000,8260.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,17222458690561,17222452892635,17222459051391,17222459057791
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,199502,199502,4194304,256,0,0,12,24,14336,0x7f7fbc7c3380,0x7f7fb9823fc0,0,0,0,0,0,0,262144,0,2097152.0000000000,2097152.0000000000,0.0000000000,0.0000000000,0.0000000000,2097341.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,17222459650845,17222459051391,17222460307878,17222460308547
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_dispatches/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_dispatches/mi200/prev_analysis/1.csv
index f8dd3c09f7..f248c6b205 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_dispatches/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_dispatches/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 __amd_rocclr_fillBufferAligned.kd,1,29492665098.0,29492665098.0,29492665098.0,99.22389425434947
 "void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",1,6158756.0,6158756.0,6158756.0,0.020720262209324
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4435846.0,4435846.0,4435846.0,0.0149237755547031
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_dispatches/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_dispatches/mi200/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_dispatches/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_dispatches/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_dispatches/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_dispatches/mi200/prev_analysis/1202.csv
index d92c0479fa..2d4898d1f7 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_dispatches/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_dispatches/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,,,,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_dispatches/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_dispatches/mi200/prev_analysis/1901.csv
index 851728a829..b0b25b42c5 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_dispatches/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_dispatches/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,,il1_fetch_
 IL1 Hit,,il1_hit_
 IL1_L2 Rd,,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_dispatches/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_dispatches/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_dispatches/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_dispatches/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_dispatches/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_dispatches/mi200/prev_analysis/201.csv
index d169954179..45fac41161 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_dispatches/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_dispatches/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,,Pct,100,
 Instr Cache BW,,Gb/s,6092.8,
 Scalar L1D Cache Hit Rate,,Pct,100,
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_dispatches/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_dispatches/mi200/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_dispatches/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_dispatches/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_dispatches/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_dispatches/mi200/prev_analysis/701.csv
index d28098ed25..9d9e3a3dab 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_dispatches/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_dispatches/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_invdev/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_invdev/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_invdev/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_invdev/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_invdev/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_invdev/mi200/pmc_perf.csv
index dac25ed828..cc27732386 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_invdev/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_invdev/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,241894,241894,33554432,256,0,0,4,32,4160,0x0,0x7f6e9cc04280,0,0,0,0,0,0,0,0,0.0000000000,8388608.0000000000,4194304.0000000000,0.0000000000,0.0000000000,310.0000000000,4128768.0000000000,4128768.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,17931286038190,17901582538237,17931431845031,17931431958331
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,241894,241894,32768,256,0,0,12,24,13888,0x0,0x7f6e9cc23f80,0,0,0,0,0,0,0,0,8192.0000000000,16384.0000000000,0.0000000000,0.0000000000,0.0000000000,8262.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,17931437652391,17931431845031,17931438008283,17931438016542
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,241894,241894,4194304,256,0,0,12,24,14336,0x7f6e9fb92380,0x7f6e9cc23fc0,0,0,0,0,0,0,262144,0,2097152.0000000000,2097152.0000000000,0.0000000000,0.0000000000,0.0000000000,2097343.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,17931438610067,17931438008283,17931439296934,17931439297600
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_invdev/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_invdev/mi200/prev_analysis/1.csv
index b7f5aaac13..0891703acd 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_invdev/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_invdev/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 __amd_rocclr_fillBufferAligned.kd,1,29849306794.0,29849306794.0,29849306794.0,99.23161614424411
 "void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",1,6163252.0,6163252.0,6163252.0,0.0204892348383507
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4454736.0,4454736.0,4454736.0,0.0148094110133506
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_invdev/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_invdev/mi200/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_invdev/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_invdev/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_invdev/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_invdev/mi200/prev_analysis/1202.csv
index d92c0479fa..2d4898d1f7 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_invdev/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_invdev/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,,,,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_invdev/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_invdev/mi200/prev_analysis/1901.csv
index 851728a829..b0b25b42c5 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_invdev/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_invdev/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,,il1_fetch_
 IL1 Hit,,il1_hit_
 IL1_L2 Rd,,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_invdev/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_invdev/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_invdev/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_invdev/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_invdev/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_invdev/mi200/prev_analysis/201.csv
index bb5170fb7c..31d2ac16c4 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_invdev/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_invdev/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,,Pct,100,
 Instr Cache BW,,Gb/s,6092.8,
 Scalar L1D Cache Hit Rate,,Pct,100,
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_invdev/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_invdev/mi200/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_invdev/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_invdev/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_invdev/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_invdev/mi200/prev_analysis/701.csv
index d28098ed25..9d9e3a3dab 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_invdev/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_invdev/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_kernels/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_kernels/mi200/pmc_dispatch_info.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_kernels/mi200/pmc_dispatch_info.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_kernels/mi200/pmc_dispatch_info.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_kernels/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_kernels/mi200/pmc_perf.csv
index 5c0ad40d91..8204ddb86a 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_kernels/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_kernels/mi200/pmc_perf.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,193412,193412,33554432,256,0,0,4,32,4160,0x0,0x7f5dc6204280,0,0,0,0,0,0,0,0,0.0000000000,8388608.0000000000,4194304.0000000000,0.0000000000,0.0000000000,311.0000000000,4128768.0000000000,4128768.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,17116536858082,17087199278982,17116683896452,17116683987452
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,193412,193412,32768,256,0,0,12,24,13888,0x0,0x7f5dc6223f80,0,0,0,0,0,0,0,0,8192.0000000000,16384.0000000000,0.0000000000,0.0000000000,0.0000000000,8261.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,17116689727452,17116683896452,17116690093273,17116690095732
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,193412,193412,4194304,256,0,0,12,24,14336,0x7f5dc912d380,0x7f5dc6223fc0,0,0,0,0,0,0,262144,0,2097152.0000000000,2097152.0000000000,0.0000000000,0.0000000000,0.0000000000,2097338.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,17116690694035,17116690093273,17116691336638,17116691338317
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_kernels/mi200/prev_analysis/1.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_kernels/mi200/prev_analysis/1.csv
index fcd0ed0300..a40b7a8982 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_kernels/mi200/prev_analysis/1.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_kernels/mi200/prev_analysis/1.csv
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 __amd_rocclr_fillBufferAligned.kd,1,29484617470.0,29484617470.0,29484617470.0,99.21647074631277
 "void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",1,6196821.0,6196821.0,6196821.0,0.0208524567121215
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4447216.0,4447216.0,4447216.0,0.0149649923935924
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_kernels/mi200/prev_analysis/1001.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_kernels/mi200/prev_analysis/1001.csv
index 1fe2510e1c..704560e97f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_kernels/mi200/prev_analysis/1001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_kernels/mi200/prev_analysis/1001.csv
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_kernels/mi200/prev_analysis/1202.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_kernels/mi200/prev_analysis/1202.csv
index d92c0479fa..2d4898d1f7 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_kernels/mi200/prev_analysis/1202.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_kernels/mi200/prev_analysis/1202.csv
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,,,,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_kernels/mi200/prev_analysis/1901.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_kernels/mi200/prev_analysis/1901.csv
index 851728a829..b0b25b42c5 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_kernels/mi200/prev_analysis/1901.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_kernels/mi200/prev_analysis/1901.csv
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,,il1_fetch_
 IL1 Hit,,il1_hit_
 IL1_L2 Rd,,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_kernels/mi200/prev_analysis/2001.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_kernels/mi200/prev_analysis/2001.csv
index a028847baa..cd4c32ea9f 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_kernels/mi200/prev_analysis/2001.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_kernels/mi200/prev_analysis/2001.csv
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_kernels/mi200/prev_analysis/201.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_kernels/mi200/prev_analysis/201.csv
index b1246ee2ea..3c120a7cc5 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_kernels/mi200/prev_analysis/201.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_kernels/mi200/prev_analysis/201.csv
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,,Pct,100,
 Instr Cache BW,,Gb/s,6092.8,
 Scalar L1D Cache Hit Rate,,Pct,100,
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_kernels/mi200/prev_analysis/602.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_kernels/mi200/prev_analysis/602.csv
index 347bbd25c6..8728ff5450 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_kernels/mi200/prev_analysis/602.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_kernels/mi200/prev_analysis/602.csv
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_kernels/mi200/prev_analysis/701.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_kernels/mi200/prev_analysis/701.csv
index d28098ed25..9d9e3a3dab 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_kernels/mi200/prev_analysis/701.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_kernels/mi200/prev_analysis/701.csv
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_mixbench1/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_mixbench1/mi200/pmc_perf.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_mixbench1/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_mixbench1/mi200/pmc_perf.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/roof_only_mixbench2/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/roof_only_mixbench2/mi200/pmc_perf.csv
index 22456dbcab..74a6d81e5d 100644
--- a/projects/rocprofiler-compute/tests/workloads/roof_only_mixbench2/mi200/pmc_perf.csv
+++ b/projects/rocprofiler-compute/tests/workloads/roof_only_mixbench2/mi200/pmc_perf.csv
@@ -1 +1 @@
-Index,KernelName
+Dispatch_ID,Kernel_Name
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/SQ_IFETCH_LEVEL.csv
new file mode 100644
index 0000000000..06fdffd51f
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/SQ_IFETCH_LEVEL.csv
@@ -0,0 +1,2 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,arch_vgpr,accum_vgpr,SGPR,wave_size,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int) ",2,0,0,184020,184020,1046016,256,0,0,8,8,16,64,0x0,0x7f27901dc900,49077,49077,16344,65374,14272,1828056,170462517797539,170459569892517,170459569917477,170462525395574
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/SQ_IFETCH_LEVEL_error_log.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/SQ_IFETCH_LEVEL_error_log.csv
new file mode 100644
index 0000000000..e339a8af09
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/SQ_IFETCH_LEVEL_error_log.csv
@@ -0,0 +1,5 @@
+,SQ_ACCUM_PREV_HIRES,SQ_IFETCH_LEVEL,GPU_ID,kernel_name,test_name
+0,,,2.0,"vecCopy(double*, double*, double*, int, int) ",logger
+0,3.15,2.45,,"vecCopy(double*, double*, double*, int, int) ",test_path
+0,3.15,2.45,,"vecCopy(double*, double*, double*, int, int) ",test_path
+0,3.15,2.45,,"vecCopy(double*, double*, double*, int, int) ",test_path
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/SQ_INST_LEVEL_LDS.csv
new file mode 100644
index 0000000000..114e4c5582
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/SQ_INST_LEVEL_LDS.csv
@@ -0,0 +1,2 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,arch_vgpr,accum_vgpr,SGPR,wave_size,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int) ",2,0,0,182563,182563,1046016,256,0,0,8,8,16,64,0x0,0x7f64e4a14900,0,0,0,170458716982587,170459569892517,170459569917477,170458724553200
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/SQ_INST_LEVEL_LDS_error_log.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/SQ_INST_LEVEL_LDS_error_log.csv
new file mode 100644
index 0000000000..1055d5574f
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/SQ_INST_LEVEL_LDS_error_log.csv
@@ -0,0 +1,5 @@
+,GPU_ID,kernel_name,test_name
+0,2.0,"vecCopy(double*, double*, double*, int, int) ",logger
+0,,"vecCopy(double*, double*, double*, int, int) ",test_path
+0,,"vecCopy(double*, double*, double*, int, int) ",test_path
+0,,"vecCopy(double*, double*, double*, int, int) ",test_path
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/SQ_INST_LEVEL_SMEM.csv
new file mode 100644
index 0000000000..3cfe2f4b7c
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/SQ_INST_LEVEL_SMEM.csv
@@ -0,0 +1,2 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,arch_vgpr,accum_vgpr,SGPR,wave_size,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int) ",2,0,0,186387,186387,1046016,256,0,0,8,8,16,64,0x0,0x7f03fe608900,65372,219514,28018288,170468686919648,170459569892517,170459569917477,170468694691040
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/SQ_INST_LEVEL_SMEM_error_log.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/SQ_INST_LEVEL_SMEM_error_log.csv
new file mode 100644
index 0000000000..fc751af104
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/SQ_INST_LEVEL_SMEM_error_log.csv
@@ -0,0 +1,5 @@
+,SQ_ACCUM_PREV_HIRES,SQ_INST_LEVEL_SMEM,GPU_ID,kernel_name,test_name
+0,9.15,9.24,2.0,"vecCopy(double*, double*, double*, int, int) ",logger
+0,9.15,9.24,,"vecCopy(double*, double*, double*, int, int) ",test_path
+0,9.15,9.24,,"vecCopy(double*, double*, double*, int, int) ",test_path
+0,9.15,9.24,,"vecCopy(double*, double*, double*, int, int) ",test_path
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/SQ_INST_LEVEL_VMEM.csv
new file mode 100644
index 0000000000..1cc5348f4e
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/SQ_INST_LEVEL_VMEM.csv
@@ -0,0 +1,2 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,arch_vgpr,accum_vgpr,SGPR,wave_size,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int) ",2,0,0,186204,186204,1046016,256,0,0,8,8,16,64,0x0,0x7f140af1e900,32684,657046,84111604,170468251325091,170459569892517,170459569917477,170468258841612
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/SQ_INST_LEVEL_VMEM_error_log.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/SQ_INST_LEVEL_VMEM_error_log.csv
new file mode 100644
index 0000000000..ac50ad237e
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/SQ_INST_LEVEL_VMEM_error_log.csv
@@ -0,0 +1,5 @@
+,SQ_ACCUM_PREV_HIRES,SQ_INST_LEVEL_VMEM,GPU_ID,kernel_name,test_name
+0,,,2.0,"vecCopy(double*, double*, double*, int, int) ",logger
+0,3.38,3.38,,"vecCopy(double*, double*, double*, int, int) ",test_path
+0,3.38,3.38,,"vecCopy(double*, double*, double*, int, int) ",test_path
+0,3.38,3.38,,"vecCopy(double*, double*, double*, int, int) ",test_path
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/SQ_LEVEL_WAVES.csv
new file mode 100644
index 0000000000..f2e8f243de
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/SQ_LEVEL_WAVES.csv
@@ -0,0 +1,2 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,arch_vgpr,accum_vgpr,SGPR,wave_size,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int) ",2,0,0,184930,184930,1046016,256,0,0,8,8,16,64,0x0,0x7f4402e88900,49562,49562,17633,396504,16344,26156281,247544,0,105140276,170464833838064,170459569892517,170459569917477,170464841456046
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/SQ_LEVEL_WAVES_error_log.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/SQ_LEVEL_WAVES_error_log.csv
new file mode 100644
index 0000000000..5d9c05d4b5
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/SQ_LEVEL_WAVES_error_log.csv
@@ -0,0 +1,6 @@
+,CPC_ME1_BUSY_FOR_PACKET_DECODE,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_ACCUM_PREV_HIRES,SQ_BUSY_CYCLES,SQ_CYCLES,SQ_WAVE_CYCLES,GPU_ID,kernel_name,test_name
+0,,,,,5.12,,,2.0,"vecCopy(double*, double*, double*, int, int) ",logger
+0,,,,,5.12,,,,"vecCopy(double*, double*, double*, int, int) ",logger
+0,2.6,1.92,1.92,4.42,5.12,1.92,4.47,,"vecCopy(double*, double*, double*, int, int) ",test_path
+0,2.6,1.92,1.92,4.42,5.12,1.92,4.47,,"vecCopy(double*, double*, double*, int, int) ",test_path
+0,2.6,1.92,1.92,4.42,5.12,1.92,4.47,,"vecCopy(double*, double*, double*, int, int) ",test_path
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/log.txt b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/log.txt
new file mode 100644
index 0000000000..435819ae09
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/log.txt
@@ -0,0 +1,582 @@
+RPL: on '231005_124645' from '/opt/rocm-5.5.1' in '/home1/josantos/omniperf'
+RPL: profiling '""./sample/vcopy 1045876 256""'
+RPL: input file 'Baseline_mi100/perfmon/SQ_INST_LEVEL_LDS.txt'
+RPL: output dir '/tmp/rpl_data_231005_124645_182404'
+RPL: result dir '/tmp/rpl_data_231005_124645_182404/input0_results_231005_124645'
+ROCProfiler: input from "/tmp/rpl_data_231005_124645_182404/input0.xml"
+  gpu_index = 
+  kernel = 
+  range = 
+  3 metrics
+    SQ_INSTS_LDS, SQ_INST_LEVEL_LDS, SQ_ACCUM_PREV_HIRES
+vcopy testing on GCD 0
+Finished allocating vectors on the CPU
+Finished allocating vectors on the GPU
+Finished copying vectors to the GPU
+sw thinks it moved 0.999755 KB per wave 
+Total threads: 1045876, Grid Size: 4086 block Size:256, Wavefronts:16344:
+Launching the  kernel on the GPU
+Finished executing kernel
+Finished copying the output vector from the GPU to the CPU
+Releasing GPU memory
+Releasing CPU memory
+
+ROCPRofiler: 1 contexts collected, output directory /tmp/rpl_data_231005_124645_182404/input0_results_231005_124645
+File 'Baseline_mi100/SQ_INST_LEVEL_LDS.csv' is generating
+RPL: on '231005_124646' from '/opt/rocm-5.5.1' in '/home1/josantos/omniperf'
+RPL: profiling '""./sample/vcopy 1045876 256""'
+RPL: input file 'Baseline_mi100/perfmon/pmc_perf_1.txt'
+RPL: output dir '/tmp/rpl_data_231005_124646_182586'
+RPL: result dir '/tmp/rpl_data_231005_124646_182586/input0_results_231005_124646'
+ROCProfiler: input from "/tmp/rpl_data_231005_124646_182586/input0.xml"
+  gpu_index = 
+  kernel = 
+  range = 
+  27 metrics
+    SQ_INSTS_SALU, SQ_INSTS_VSKIPPED, SQ_INSTS_SMEM, SQ_INSTS_FLAT, SQ_INSTS_LDS, SQ_INSTS_GDS, SQ_INSTS_EXP_GDS, SQ_INSTS_BRANCH, GRBM_SPI_BUSY, TCP_READ_TAGCONFLICT_STALL_CYCLES_sum, TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum, TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum, TCP_TA_TCP_STATE_READ_sum, TA_BUFFER_READ_WAVEFRONTS_sum, TA_BUFFER_WRITE_WAVEFRONTS_sum, TD_COALESCABLE_WAVEFRONT_sum, TD_LOAD_WAVEFRONT_sum, SPI_CSN_NUM_THREADGROUPS, SPI_CSN_WAVE, CPC_CPC_TCIU_BUSY, CPC_CPC_TCIU_IDLE, CPF_CPF_TCIU_BUSY, CPF_CPF_TCIU_STALL, TCC_NC_REQ_sum, TCC_UC_REQ_sum, TCC_CC_REQ_sum, TCC_RW_REQ_sum
+vcopy testing on GCD 0
+Finished allocating vectors on the CPU
+Finished allocating vectors on the GPU
+Finished copying vectors to the GPU
+sw thinks it moved 0.999755 KB per wave 
+Total threads: 1045876, Grid Size: 4086 block Size:256, Wavefronts:16344:
+Launching the  kernel on the GPU
+Finished executing kernel
+Finished copying the output vector from the GPU to the CPU
+Releasing GPU memory
+Releasing CPU memory
+
+ROCPRofiler: 1 contexts collected, output directory /tmp/rpl_data_231005_124646_182586/input0_results_231005_124646
+File 'Baseline_mi100/pmc_perf_1.csv' is generating
+RPL: on '231005_124646' from '/opt/rocm-5.5.1' in '/home1/josantos/omniperf'
+RPL: profiling '""./sample/vcopy 1045876 256""'
+RPL: input file 'Baseline_mi100/perfmon/timestamps.txt'
+RPL: output dir '/tmp/rpl_data_231005_124646_182768'
+RPL: result dir '/tmp/rpl_data_231005_124646_182768/input0_results_231005_124646'
+ROCProfiler: input from "/tmp/rpl_data_231005_124646_182768/input0.xml"
+  gpu_index = 
+  kernel = 
+  range = 
+  0 metrics
+vcopy testing on GCD 0
+Finished allocating vectors on the CPU
+Finished allocating vectors on the GPU
+Finished copying vectors to the GPU
+sw thinks it moved 0.999755 KB per wave 
+Total threads: 1045876, Grid Size: 4086 block Size:256, Wavefronts:16344:
+Launching the  kernel on the GPU
+Finished executing kernel
+Finished copying the output vector from the GPU to the CPU
+Releasing GPU memory
+Releasing CPU memory
+
+ROCPRofiler: 1 contexts collected, output directory /tmp/rpl_data_231005_124646_182768/input0_results_231005_124646
+File 'Baseline_mi100/timestamps.csv' is generating
+RPL: on '231005_124647' from '/opt/rocm-5.5.1' in '/home1/josantos/omniperf'
+RPL: profiling '""./sample/vcopy 1045876 256""'
+RPL: input file 'Baseline_mi100/perfmon/pmc_perf_12.txt'
+RPL: output dir '/tmp/rpl_data_231005_124647_182951'
+RPL: result dir '/tmp/rpl_data_231005_124647_182951/input0_results_231005_124647'
+ROCProfiler: input from "/tmp/rpl_data_231005_124647_182951/input0.xml"
+  gpu_index = 
+  kernel = 
+  range = 
+  128 metrics
+    TCC_EA_RDREQ[0], TCC_EA_RDREQ_32B[0], TCC_EA_RDREQ_DRAM_CREDIT_STALL[0], TCC_EA_RDREQ_GMI_CREDIT_STALL[0], TCC_EA_RDREQ[1], TCC_EA_RDREQ_32B[1], TCC_EA_RDREQ_DRAM_CREDIT_STALL[1], TCC_EA_RDREQ_GMI_CREDIT_STALL[1], TCC_EA_RDREQ[2], TCC_EA_RDREQ_32B[2], TCC_EA_RDREQ_DRAM_CREDIT_STALL[2], TCC_EA_RDREQ_GMI_CREDIT_STALL[2], TCC_EA_RDREQ[3], TCC_EA_RDREQ_32B[3], TCC_EA_RDREQ_DRAM_CREDIT_STALL[3], TCC_EA_RDREQ_GMI_CREDIT_STALL[3], TCC_EA_RDREQ[4], TCC_EA_RDREQ_32B[4], TCC_EA_RDREQ_DRAM_CREDIT_STALL[4], TCC_EA_RDREQ_GMI_CREDIT_STALL[4], TCC_EA_RDREQ[5], TCC_EA_RDREQ_32B[5], TCC_EA_RDREQ_DRAM_CREDIT_STALL[5], TCC_EA_RDREQ_GMI_CREDIT_STALL[5], TCC_EA_RDREQ[6], TCC_EA_RDREQ_32B[6], TCC_EA_RDREQ_DRAM_CREDIT_STALL[6], TCC_EA_RDREQ_GMI_CREDIT_STALL[6], TCC_EA_RDREQ[7], TCC_EA_RDREQ_32B[7], TCC_EA_RDREQ_DRAM_CREDIT_STALL[7], TCC_EA_RDREQ_GMI_CREDIT_STALL[7], TCC_EA_RDREQ[8], TCC_EA_RDREQ_32B[8], TCC_EA_RDREQ_DRAM_CREDIT_STALL[8], TCC_EA_RDREQ_GMI_CREDIT_STALL[8], TCC_EA_RDREQ[9], TCC_EA_RDREQ_32B[9], TCC_EA_RDREQ_DRAM_CREDIT_STALL[9], TCC_EA_RDREQ_GMI_CREDIT_STALL[9], TCC_EA_RDREQ[10], TCC_EA_RDREQ_32B[10], TCC_EA_RDREQ_DRAM_CREDIT_STALL[10], TCC_EA_RDREQ_GMI_CREDIT_STALL[10], TCC_EA_RDREQ[11], TCC_EA_RDREQ_32B[11], TCC_EA_RDREQ_DRAM_CREDIT_STALL[11], TCC_EA_RDREQ_GMI_CREDIT_STALL[11], TCC_EA_RDREQ[12], TCC_EA_RDREQ_32B[12], TCC_EA_RDREQ_DRAM_CREDIT_STALL[12], TCC_EA_RDREQ_GMI_CREDIT_STALL[12], TCC_EA_RDREQ[13], TCC_EA_RDREQ_32B[13], TCC_EA_RDREQ_DRAM_CREDIT_STALL[13], TCC_EA_RDREQ_GMI_CREDIT_STALL[13], TCC_EA_RDREQ[14], TCC_EA_RDREQ_32B[14], TCC_EA_RDREQ_DRAM_CREDIT_STALL[14], TCC_EA_RDREQ_GMI_CREDIT_STALL[14], TCC_EA_RDREQ[15], TCC_EA_RDREQ_32B[15], TCC_EA_RDREQ_DRAM_CREDIT_STALL[15], TCC_EA_RDREQ_GMI_CREDIT_STALL[15], TCC_EA_RDREQ[16], TCC_EA_RDREQ_32B[16], TCC_EA_RDREQ_DRAM_CREDIT_STALL[16], TCC_EA_RDREQ_GMI_CREDIT_STALL[16], TCC_EA_RDREQ[17], TCC_EA_RDREQ_32B[17], TCC_EA_RDREQ_DRAM_CREDIT_STALL[17], TCC_EA_RDREQ_GMI_CREDIT_STALL[17], TCC_EA_RDREQ[18], TCC_EA_RDREQ_32B[18], TCC_EA_RDREQ_DRAM_CREDIT_STALL[18], TCC_EA_RDREQ_GMI_CREDIT_STALL[18], TCC_EA_RDREQ[19], TCC_EA_RDREQ_32B[19], TCC_EA_RDREQ_DRAM_CREDIT_STALL[19], TCC_EA_RDREQ_GMI_CREDIT_STALL[19], TCC_EA_RDREQ[20], TCC_EA_RDREQ_32B[20], TCC_EA_RDREQ_DRAM_CREDIT_STALL[20], TCC_EA_RDREQ_GMI_CREDIT_STALL[20], TCC_EA_RDREQ[21], TCC_EA_RDREQ_32B[21], TCC_EA_RDREQ_DRAM_CREDIT_STALL[21], TCC_EA_RDREQ_GMI_CREDIT_STALL[21], TCC_EA_RDREQ[22], TCC_EA_RDREQ_32B[22], TCC_EA_RDREQ_DRAM_CREDIT_STALL[22], TCC_EA_RDREQ_GMI_CREDIT_STALL[22], TCC_EA_RDREQ[23], TCC_EA_RDREQ_32B[23], TCC_EA_RDREQ_DRAM_CREDIT_STALL[23], TCC_EA_RDREQ_GMI_CREDIT_STALL[23], TCC_EA_RDREQ[24], TCC_EA_RDREQ_32B[24], TCC_EA_RDREQ_DRAM_CREDIT_STALL[24], TCC_EA_RDREQ_GMI_CREDIT_STALL[24], TCC_EA_RDREQ[25], TCC_EA_RDREQ_32B[25], TCC_EA_RDREQ_DRAM_CREDIT_STALL[25], TCC_EA_RDREQ_GMI_CREDIT_STALL[25], TCC_EA_RDREQ[26], TCC_EA_RDREQ_32B[26], TCC_EA_RDREQ_DRAM_CREDIT_STALL[26], TCC_EA_RDREQ_GMI_CREDIT_STALL[26], TCC_EA_RDREQ[27], TCC_EA_RDREQ_32B[27], TCC_EA_RDREQ_DRAM_CREDIT_STALL[27], TCC_EA_RDREQ_GMI_CREDIT_STALL[27], TCC_EA_RDREQ[28], TCC_EA_RDREQ_32B[28], TCC_EA_RDREQ_DRAM_CREDIT_STALL[28], TCC_EA_RDREQ_GMI_CREDIT_STALL[28], TCC_EA_RDREQ[29], TCC_EA_RDREQ_32B[29], TCC_EA_RDREQ_DRAM_CREDIT_STALL[29], TCC_EA_RDREQ_GMI_CREDIT_STALL[29], TCC_EA_RDREQ[30], TCC_EA_RDREQ_32B[30], TCC_EA_RDREQ_DRAM_CREDIT_STALL[30], TCC_EA_RDREQ_GMI_CREDIT_STALL[30], TCC_EA_RDREQ[31], TCC_EA_RDREQ_32B[31], TCC_EA_RDREQ_DRAM_CREDIT_STALL[31], TCC_EA_RDREQ_GMI_CREDIT_STALL[31]
+vcopy testing on GCD 0
+Finished allocating vectors on the CPU
+Finished allocating vectors on the GPU
+Finished copying vectors to the GPU
+sw thinks it moved 0.999755 KB per wave 
+Total threads: 1045876, Grid Size: 4086 block Size:256, Wavefronts:16344:
+Launching the  kernel on the GPU
+Finished executing kernel
+Finished copying the output vector from the GPU to the CPU
+Releasing GPU memory
+Releasing CPU memory
+
+ROCPRofiler: 1 contexts collected, output directory /tmp/rpl_data_231005_124647_182951/input0_results_231005_124647
+File 'Baseline_mi100/pmc_perf_12.csv' is generating
+RPL: on '231005_124647' from '/opt/rocm-5.5.1' in '/home1/josantos/omniperf'
+RPL: profiling '""./sample/vcopy 1045876 256""'
+RPL: input file 'Baseline_mi100/perfmon/pmc_perf_15.txt'
+RPL: output dir '/tmp/rpl_data_231005_124647_183133'
+RPL: result dir '/tmp/rpl_data_231005_124647_183133/input0_results_231005_124647'
+ROCProfiler: input from "/tmp/rpl_data_231005_124647_183133/input0.xml"
+  gpu_index = 
+  kernel = 
+  range = 
+  128 metrics
+    TCC_HIT[0], TCC_MISS[0], TCC_READ[0], TCC_REQ[0], TCC_HIT[1], TCC_MISS[1], TCC_READ[1], TCC_REQ[1], TCC_HIT[2], TCC_MISS[2], TCC_READ[2], TCC_REQ[2], TCC_HIT[3], TCC_MISS[3], TCC_READ[3], TCC_REQ[3], TCC_HIT[4], TCC_MISS[4], TCC_READ[4], TCC_REQ[4], TCC_HIT[5], TCC_MISS[5], TCC_READ[5], TCC_REQ[5], TCC_HIT[6], TCC_MISS[6], TCC_READ[6], TCC_REQ[6], TCC_HIT[7], TCC_MISS[7], TCC_READ[7], TCC_REQ[7], TCC_HIT[8], TCC_MISS[8], TCC_READ[8], TCC_REQ[8], TCC_HIT[9], TCC_MISS[9], TCC_READ[9], TCC_REQ[9], TCC_HIT[10], TCC_MISS[10], TCC_READ[10], TCC_REQ[10], TCC_HIT[11], TCC_MISS[11], TCC_READ[11], TCC_REQ[11], TCC_HIT[12], TCC_MISS[12], TCC_READ[12], TCC_REQ[12], TCC_HIT[13], TCC_MISS[13], TCC_READ[13], TCC_REQ[13], TCC_HIT[14], TCC_MISS[14], TCC_READ[14], TCC_REQ[14], TCC_HIT[15], TCC_MISS[15], TCC_READ[15], TCC_REQ[15], TCC_HIT[16], TCC_MISS[16], TCC_READ[16], TCC_REQ[16], TCC_HIT[17], TCC_MISS[17], TCC_READ[17], TCC_REQ[17], TCC_HIT[18], TCC_MISS[18], TCC_READ[18], TCC_REQ[18], TCC_HIT[19], TCC_MISS[19], TCC_READ[19], TCC_REQ[19], TCC_HIT[20], TCC_MISS[20], TCC_READ[20], TCC_REQ[20], TCC_HIT[21], TCC_MISS[21], TCC_READ[21], TCC_REQ[21], TCC_HIT[22], TCC_MISS[22], TCC_READ[22], TCC_REQ[22], TCC_HIT[23], TCC_MISS[23], TCC_READ[23], TCC_REQ[23], TCC_HIT[24], TCC_MISS[24], TCC_READ[24], TCC_REQ[24], TCC_HIT[25], TCC_MISS[25], TCC_READ[25], TCC_REQ[25], TCC_HIT[26], TCC_MISS[26], TCC_READ[26], TCC_REQ[26], TCC_HIT[27], TCC_MISS[27], TCC_READ[27], TCC_REQ[27], TCC_HIT[28], TCC_MISS[28], TCC_READ[28], TCC_REQ[28], TCC_HIT[29], TCC_MISS[29], TCC_READ[29], TCC_REQ[29], TCC_HIT[30], TCC_MISS[30], TCC_READ[30], TCC_REQ[30], TCC_HIT[31], TCC_MISS[31], TCC_READ[31], TCC_REQ[31]
+vcopy testing on GCD 0
+Finished allocating vectors on the CPU
+Finished allocating vectors on the GPU
+Finished copying vectors to the GPU
+sw thinks it moved 0.999755 KB per wave 
+Total threads: 1045876, Grid Size: 4086 block Size:256, Wavefronts:16344:
+Launching the  kernel on the GPU
+Finished executing kernel
+Finished copying the output vector from the GPU to the CPU
+Releasing GPU memory
+Releasing CPU memory
+
+ROCPRofiler: 1 contexts collected, output directory /tmp/rpl_data_231005_124647_183133/input0_results_231005_124647
+File 'Baseline_mi100/pmc_perf_15.csv' is generating
+RPL: on '231005_124648' from '/opt/rocm-5.5.1' in '/home1/josantos/omniperf'
+RPL: profiling '""./sample/vcopy 1045876 256""'
+RPL: input file 'Baseline_mi100/perfmon/pmc_perf_7.txt'
+RPL: output dir '/tmp/rpl_data_231005_124648_183315'
+RPL: result dir '/tmp/rpl_data_231005_124648_183315/input0_results_231005_124648'
+ROCProfiler: input from "/tmp/rpl_data_231005_124648_183315/input0.xml"
+  gpu_index = 
+  kernel = 
+  range = 
+  20 metrics
+    SQC_DCACHE_REQ_READ_16, SQC_ICACHE_REQ, SQC_ICACHE_HITS, SQC_ICACHE_MISSES, SQC_ICACHE_MISSES_DUPLICATE, SQC_DCACHE_INPUT_VALID_READYB, SQC_DCACHE_ATOMIC, SQC_DCACHE_REQ_READ_8, TCP_TCC_NC_WRITE_REQ_sum, TCP_TCC_NC_ATOMIC_REQ_sum, TCP_TCC_UC_READ_REQ_sum, TCP_TCC_UC_WRITE_REQ_sum, TA_FLAT_WRITE_WAVEFRONTS_sum, TA_FLAT_ATOMIC_WAVEFRONTS_sum, SPI_RA_WVLIM_STALL_CSN, SPI_SWC_CSC_WR, TCC_EA_RDREQ_IO_CREDIT_STALL_sum, TCC_EA_RDREQ_GMI_CREDIT_STALL_sum, TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum, TCC_TAG_STALL_sum
+vcopy testing on GCD 0
+Finished allocating vectors on the CPU
+Finished allocating vectors on the GPU
+Finished copying vectors to the GPU
+sw thinks it moved 0.999755 KB per wave 
+Total threads: 1045876, Grid Size: 4086 block Size:256, Wavefronts:16344:
+Launching the  kernel on the GPU
+Finished executing kernel
+Finished copying the output vector from the GPU to the CPU
+Releasing GPU memory
+Releasing CPU memory
+
+ROCPRofiler: 1 contexts collected, output directory /tmp/rpl_data_231005_124648_183315/input0_results_231005_124648
+File 'Baseline_mi100/pmc_perf_7.csv' is generating
+RPL: on '231005_124648' from '/opt/rocm-5.5.1' in '/home1/josantos/omniperf'
+RPL: profiling '""./sample/vcopy 1045876 256""'
+RPL: input file 'Baseline_mi100/perfmon/pmc_perf_8.txt'
+RPL: output dir '/tmp/rpl_data_231005_124648_183497'
+RPL: result dir '/tmp/rpl_data_231005_124648_183497/input0_results_231005_124648'
+ROCProfiler: input from "/tmp/rpl_data_231005_124648_183497/input0.xml"
+  gpu_index = 
+  kernel = 
+  range = 
+  17 metrics
+    SQC_DCACHE_REQ, SQC_DCACHE_HITS, SQC_DCACHE_MISSES, SQC_DCACHE_MISSES_DUPLICATE, SQC_DCACHE_REQ_READ_1, SQC_DCACHE_REQ_READ_2, SQC_DCACHE_REQ_READ_4, TCP_TCC_UC_ATOMIC_REQ_sum, TCP_TCC_CC_READ_REQ_sum, TCP_TCC_CC_WRITE_REQ_sum, TCP_TCC_CC_ATOMIC_REQ_sum, SPI_VWC_CSC_WR, SPI_RA_BULKY_CU_FULL_CSN, TCC_NORMAL_WRITEBACK_sum, TCC_ALL_TC_OP_WB_WRITEBACK_sum, TCC_NORMAL_EVICT_sum, TCC_ALL_TC_OP_INV_EVICT_sum
+vcopy testing on GCD 0
+Finished allocating vectors on the CPU
+Finished allocating vectors on the GPU
+Finished copying vectors to the GPU
+sw thinks it moved 0.999755 KB per wave 
+Total threads: 1045876, Grid Size: 4086 block Size:256, Wavefronts:16344:
+Launching the  kernel on the GPU
+Finished executing kernel
+Finished copying the output vector from the GPU to the CPU
+Releasing GPU memory
+Releasing CPU memory
+
+ROCPRofiler: 1 contexts collected, output directory /tmp/rpl_data_231005_124648_183497/input0_results_231005_124648
+File 'Baseline_mi100/pmc_perf_8.csv' is generating
+RPL: on '231005_124649' from '/opt/rocm-5.5.1' in '/home1/josantos/omniperf'
+RPL: profiling '""./sample/vcopy 1045876 256""'
+RPL: input file 'Baseline_mi100/perfmon/pmc_perf_9.txt'
+RPL: output dir '/tmp/rpl_data_231005_124649_183679'
+RPL: result dir '/tmp/rpl_data_231005_124649_183679/input0_results_231005_124649'
+ROCProfiler: input from "/tmp/rpl_data_231005_124649_183679/input0.xml"
+  gpu_index = 
+  kernel = 
+  range = 
+  8 metrics
+    TCP_TCC_RW_READ_REQ_sum, TCP_TCC_RW_WRITE_REQ_sum, TCP_TCC_RW_ATOMIC_REQ_sum, TCP_PENDING_STALL_CYCLES_sum, TCC_EA_RDREQ_DRAM_sum, TCC_EA_WRREQ_DRAM_sum, TCC_EA_RDREQ_LEVEL_sum, TCC_EA_WRREQ_LEVEL_sum
+vcopy testing on GCD 0
+Finished allocating vectors on the CPU
+Finished allocating vectors on the GPU
+Finished copying vectors to the GPU
+sw thinks it moved 0.999755 KB per wave 
+Total threads: 1045876, Grid Size: 4086 block Size:256, Wavefronts:16344:
+Launching the  kernel on the GPU
+Finished executing kernel
+Finished copying the output vector from the GPU to the CPU
+Releasing GPU memory
+Releasing CPU memory
+
+ROCPRofiler: 1 contexts collected, output directory /tmp/rpl_data_231005_124649_183679/input0_results_231005_124649
+File 'Baseline_mi100/pmc_perf_9.csv' is generating
+RPL: on '231005_124649' from '/opt/rocm-5.5.1' in '/home1/josantos/omniperf'
+RPL: profiling '""./sample/vcopy 1045876 256""'
+RPL: input file 'Baseline_mi100/perfmon/SQ_IFETCH_LEVEL.txt'
+RPL: output dir '/tmp/rpl_data_231005_124649_183861'
+RPL: result dir '/tmp/rpl_data_231005_124649_183861/input0_results_231005_124649'
+ROCProfiler: input from "/tmp/rpl_data_231005_124649_183861/input0.xml"
+  gpu_index = 
+  kernel = 
+  range = 
+  6 metrics
+    GRBM_COUNT, GRBM_GUI_ACTIVE, SQ_WAVES, SQ_IFETCH, SQ_IFETCH_LEVEL, SQ_ACCUM_PREV_HIRES
+vcopy testing on GCD 0
+Finished allocating vectors on the CPU
+Finished allocating vectors on the GPU
+Finished copying vectors to the GPU
+sw thinks it moved 0.999755 KB per wave 
+Total threads: 1045876, Grid Size: 4086 block Size:256, Wavefronts:16344:
+Launching the  kernel on the GPU
+Finished executing kernel
+Finished copying the output vector from the GPU to the CPU
+Releasing GPU memory
+Releasing CPU memory
+
+ROCPRofiler: 1 contexts collected, output directory /tmp/rpl_data_231005_124649_183861/input0_results_231005_124649
+File 'Baseline_mi100/SQ_IFETCH_LEVEL.csv' is generating
+RPL: on '231005_124649' from '/opt/rocm-5.5.1' in '/home1/josantos/omniperf'
+RPL: profiling '""./sample/vcopy 1045876 256""'
+RPL: input file 'Baseline_mi100/perfmon/pmc_perf_0.txt'
+RPL: output dir '/tmp/rpl_data_231005_124649_184043'
+RPL: result dir '/tmp/rpl_data_231005_124649_184043/input0_results_231005_124649'
+ROCProfiler: input from "/tmp/rpl_data_231005_124649_184043/input0.xml"
+  gpu_index = 
+  kernel = 
+  range = 
+  28 metrics
+    SQ_CYCLES, SQ_BUSY_CYCLES, SQ_BUSY_CU_CYCLES, SQ_WAVES, SQ_WAVE_CYCLES, SQ_INSTS_VMEM_WR, SQ_INSTS_VMEM_RD, SQ_INSTS_VMEM, GRBM_COUNT, GRBM_GUI_ACTIVE, TCP_GATE_EN1_sum, TCP_GATE_EN2_sum, TCP_TD_TCP_STALL_CYCLES_sum, TCP_TCR_TCP_STALL_CYCLES_sum, TA_TA_BUSY_sum, TA_BUFFER_WAVEFRONTS_sum, TD_TD_BUSY_sum, TD_TC_STALL_sum, SPI_CSN_WINDOW_VALID, SPI_CSN_BUSY, CPC_CPC_STAT_BUSY, CPC_CPC_STAT_IDLE, CPF_CPF_STAT_BUSY, CPF_CPF_STAT_STALL, TCC_CYCLE_sum, TCC_BUSY_sum, TCC_PROBE_sum, TCC_PROBE_ALL_sum
+vcopy testing on GCD 0
+Finished allocating vectors on the CPU
+Finished allocating vectors on the GPU
+Finished copying vectors to the GPU
+sw thinks it moved 0.999755 KB per wave 
+Total threads: 1045876, Grid Size: 4086 block Size:256, Wavefronts:16344:
+Launching the  kernel on the GPU
+Finished executing kernel
+Finished copying the output vector from the GPU to the CPU
+Releasing GPU memory
+Releasing CPU memory
+
+ROCPRofiler: 1 contexts collected, output directory /tmp/rpl_data_231005_124649_184043/input0_results_231005_124649
+File 'Baseline_mi100/pmc_perf_0.csv' is generating
+RPL: on '231005_124650' from '/opt/rocm-5.5.1' in '/home1/josantos/omniperf'
+RPL: profiling '""./sample/vcopy 1045876 256""'
+RPL: input file 'Baseline_mi100/perfmon/pmc_perf_6.txt'
+RPL: output dir '/tmp/rpl_data_231005_124650_184225'
+RPL: result dir '/tmp/rpl_data_231005_124650_184225/input0_results_231005_124650'
+ROCProfiler: input from "/tmp/rpl_data_231005_124650_184225/input0.xml"
+  gpu_index = 
+  kernel = 
+  range = 
+  20 metrics
+    SQ_WAVES_SAVED, SQ_INSTS_SMEM_NORM, SQC_TC_INST_REQ, SQC_TC_DATA_READ_REQ, SQC_TC_DATA_WRITE_REQ, SQC_TC_DATA_ATOMIC_REQ, SQC_TC_STALL, SQC_TC_REQ, TCP_TCC_WRITE_REQ_sum, TCP_TCC_ATOMIC_WITH_RET_REQ_sum, TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum, TCP_TCC_NC_READ_REQ_sum, TA_FLAT_WAVEFRONTS_sum, TA_FLAT_READ_WAVEFRONTS_sum, SPI_RA_BAR_CU_FULL_CSN, SPI_RA_TGLIM_CU_FULL_CSN, TCC_EA_ATOMIC_sum, TCC_EA_RDREQ_sum, TCC_EA_RDREQ_32B_sum, TCC_EA_RD_UNCACHED_32B_sum
+vcopy testing on GCD 0
+Finished allocating vectors on the CPU
+Finished allocating vectors on the GPU
+Finished copying vectors to the GPU
+sw thinks it moved 0.999755 KB per wave 
+Total threads: 1045876, Grid Size: 4086 block Size:256, Wavefronts:16344:
+Launching the  kernel on the GPU
+Finished executing kernel
+Finished copying the output vector from the GPU to the CPU
+Releasing GPU memory
+Releasing CPU memory
+
+ROCPRofiler: 1 contexts collected, output directory /tmp/rpl_data_231005_124650_184225/input0_results_231005_124650
+File 'Baseline_mi100/pmc_perf_6.csv' is generating
+RPL: on '231005_124650' from '/opt/rocm-5.5.1' in '/home1/josantos/omniperf'
+RPL: profiling '""./sample/vcopy 1045876 256""'
+RPL: input file 'Baseline_mi100/perfmon/pmc_perf_16.txt'
+RPL: output dir '/tmp/rpl_data_231005_124650_184407'
+RPL: result dir '/tmp/rpl_data_231005_124650_184407/input0_results_231005_124650'
+ROCProfiler: input from "/tmp/rpl_data_231005_124650_184407/input0.xml"
+  gpu_index = 
+  kernel = 
+  range = 
+  96 metrics
+    TCC_RW_REQ[0], TCC_TOO_MANY_EA_WRREQS_STALL[0], TCC_WRITE[0], TCC_RW_REQ[1], TCC_TOO_MANY_EA_WRREQS_STALL[1], TCC_WRITE[1], TCC_RW_REQ[2], TCC_TOO_MANY_EA_WRREQS_STALL[2], TCC_WRITE[2], TCC_RW_REQ[3], TCC_TOO_MANY_EA_WRREQS_STALL[3], TCC_WRITE[3], TCC_RW_REQ[4], TCC_TOO_MANY_EA_WRREQS_STALL[4], TCC_WRITE[4], TCC_RW_REQ[5], TCC_TOO_MANY_EA_WRREQS_STALL[5], TCC_WRITE[5], TCC_RW_REQ[6], TCC_TOO_MANY_EA_WRREQS_STALL[6], TCC_WRITE[6], TCC_RW_REQ[7], TCC_TOO_MANY_EA_WRREQS_STALL[7], TCC_WRITE[7], TCC_RW_REQ[8], TCC_TOO_MANY_EA_WRREQS_STALL[8], TCC_WRITE[8], TCC_RW_REQ[9], TCC_TOO_MANY_EA_WRREQS_STALL[9], TCC_WRITE[9], TCC_RW_REQ[10], TCC_TOO_MANY_EA_WRREQS_STALL[10], TCC_WRITE[10], TCC_RW_REQ[11], TCC_TOO_MANY_EA_WRREQS_STALL[11], TCC_WRITE[11], TCC_RW_REQ[12], TCC_TOO_MANY_EA_WRREQS_STALL[12], TCC_WRITE[12], TCC_RW_REQ[13], TCC_TOO_MANY_EA_WRREQS_STALL[13], TCC_WRITE[13], TCC_RW_REQ[14], TCC_TOO_MANY_EA_WRREQS_STALL[14], TCC_WRITE[14], TCC_RW_REQ[15], TCC_TOO_MANY_EA_WRREQS_STALL[15], TCC_WRITE[15], TCC_RW_REQ[16], TCC_TOO_MANY_EA_WRREQS_STALL[16], TCC_WRITE[16], TCC_RW_REQ[17], TCC_TOO_MANY_EA_WRREQS_STALL[17], TCC_WRITE[17], TCC_RW_REQ[18], TCC_TOO_MANY_EA_WRREQS_STALL[18], TCC_WRITE[18], TCC_RW_REQ[19], TCC_TOO_MANY_EA_WRREQS_STALL[19], TCC_WRITE[19], TCC_RW_REQ[20], TCC_TOO_MANY_EA_WRREQS_STALL[20], TCC_WRITE[20], TCC_RW_REQ[21], TCC_TOO_MANY_EA_WRREQS_STALL[21], TCC_WRITE[21], TCC_RW_REQ[22], TCC_TOO_MANY_EA_WRREQS_STALL[22], TCC_WRITE[22], TCC_RW_REQ[23], TCC_TOO_MANY_EA_WRREQS_STALL[23], TCC_WRITE[23], TCC_RW_REQ[24], TCC_TOO_MANY_EA_WRREQS_STALL[24], TCC_WRITE[24], TCC_RW_REQ[25], TCC_TOO_MANY_EA_WRREQS_STALL[25], TCC_WRITE[25], TCC_RW_REQ[26], TCC_TOO_MANY_EA_WRREQS_STALL[26], TCC_WRITE[26], TCC_RW_REQ[27], TCC_TOO_MANY_EA_WRREQS_STALL[27], TCC_WRITE[27], TCC_RW_REQ[28], TCC_TOO_MANY_EA_WRREQS_STALL[28], TCC_WRITE[28], TCC_RW_REQ[29], TCC_TOO_MANY_EA_WRREQS_STALL[29], TCC_WRITE[29], TCC_RW_REQ[30], TCC_TOO_MANY_EA_WRREQS_STALL[30], TCC_WRITE[30], TCC_RW_REQ[31], TCC_TOO_MANY_EA_WRREQS_STALL[31], TCC_WRITE[31]
+vcopy testing on GCD 0
+Finished allocating vectors on the CPU
+Finished allocating vectors on the GPU
+Finished copying vectors to the GPU
+sw thinks it moved 0.999755 KB per wave 
+Total threads: 1045876, Grid Size: 4086 block Size:256, Wavefronts:16344:
+Launching the  kernel on the GPU
+Finished executing kernel
+Finished copying the output vector from the GPU to the CPU
+Releasing GPU memory
+Releasing CPU memory
+
+ROCPRofiler: 1 contexts collected, output directory /tmp/rpl_data_231005_124650_184407/input0_results_231005_124650
+File 'Baseline_mi100/pmc_perf_16.csv' is generating
+RPL: on '231005_124651' from '/opt/rocm-5.5.1' in '/home1/josantos/omniperf'
+RPL: profiling '""./sample/vcopy 1045876 256""'
+RPL: input file 'Baseline_mi100/perfmon/pmc_perf_4.txt'
+RPL: output dir '/tmp/rpl_data_231005_124651_184589'
+RPL: result dir '/tmp/rpl_data_231005_124651_184589/input0_results_231005_124651'
+ROCProfiler: input from "/tmp/rpl_data_231005_124651_184589/input0.xml"
+  gpu_index = 
+  kernel = 
+  range = 
+  22 metrics
+    SQ_INST_CYCLES_SALU, SQ_THREAD_CYCLES_VALU, SQ_IFETCH, SQ_LDS_BANK_CONFLICT, SQ_LDS_ADDR_CONFLICT, SQ_LDS_UNALIGNED_STALL, SQ_WAVES_EQ_64, SQ_WAVES_LT_64, TCP_UTCL1_TRANSLATION_MISS_sum, TCP_UTCL1_TRANSLATION_HIT_sum, TCP_UTCL1_PERMISSION_MISS_sum, TCP_UTCL1_REQUEST_sum, TA_ADDR_STALLED_BY_TC_CYCLES_sum, TA_TOTAL_WAVEFRONTS_sum, SPI_RA_WAVE_SIMD_FULL_CSN, SPI_RA_VGPR_SIMD_FULL_CSN, CPC_CPC_UTCL2IU_STALL, CPC_ME1_BUSY_FOR_PACKET_DECODE, TCC_EA_WRREQ_sum, TCC_EA_WRREQ_64B_sum, TCC_EA_WR_UNCACHED_32B_sum, TCC_EA_WRREQ_STALL_sum
+vcopy testing on GCD 0
+Finished allocating vectors on the CPU
+Finished allocating vectors on the GPU
+Finished copying vectors to the GPU
+sw thinks it moved 0.999755 KB per wave 
+Total threads: 1045876, Grid Size: 4086 block Size:256, Wavefronts:16344:
+Launching the  kernel on the GPU
+Finished executing kernel
+Finished copying the output vector from the GPU to the CPU
+Releasing GPU memory
+Releasing CPU memory
+
+ROCPRofiler: 1 contexts collected, output directory /tmp/rpl_data_231005_124651_184589/input0_results_231005_124651
+File 'Baseline_mi100/pmc_perf_4.csv' is generating
+RPL: on '231005_124651' from '/opt/rocm-5.5.1' in '/home1/josantos/omniperf'
+RPL: profiling '""./sample/vcopy 1045876 256""'
+RPL: input file 'Baseline_mi100/perfmon/SQ_LEVEL_WAVES.txt'
+RPL: output dir '/tmp/rpl_data_231005_124651_184771'
+RPL: result dir '/tmp/rpl_data_231005_124651_184771/input0_results_231005_124651'
+ROCProfiler: input from "/tmp/rpl_data_231005_124651_184771/input0.xml"
+  gpu_index = 
+  kernel = 
+  range = 
+  9 metrics
+    GRBM_COUNT, GRBM_GUI_ACTIVE, CPC_ME1_BUSY_FOR_PACKET_DECODE, SQ_CYCLES, SQ_WAVES, SQ_WAVE_CYCLES, SQ_BUSY_CYCLES, SQ_LEVEL_WAVES, SQ_ACCUM_PREV_HIRES
+vcopy testing on GCD 0
+Finished allocating vectors on the CPU
+Finished allocating vectors on the GPU
+Finished copying vectors to the GPU
+sw thinks it moved 0.999755 KB per wave 
+Total threads: 1045876, Grid Size: 4086 block Size:256, Wavefronts:16344:
+Launching the  kernel on the GPU
+Finished executing kernel
+Finished copying the output vector from the GPU to the CPU
+Releasing GPU memory
+Releasing CPU memory
+
+ROCPRofiler: 1 contexts collected, output directory /tmp/rpl_data_231005_124651_184771/input0_results_231005_124651
+File 'Baseline_mi100/SQ_LEVEL_WAVES.csv' is generating
+RPL: on '231005_124652' from '/opt/rocm-5.5.1' in '/home1/josantos/omniperf'
+RPL: profiling '""./sample/vcopy 1045876 256""'
+RPL: input file 'Baseline_mi100/perfmon/pmc_perf_2.txt'
+RPL: output dir '/tmp/rpl_data_231005_124652_184953'
+RPL: result dir '/tmp/rpl_data_231005_124652_184953/input0_results_231005_124652'
+ROCProfiler: input from "/tmp/rpl_data_231005_124652_184953/input0.xml"
+  gpu_index = 
+  kernel = 
+  range = 
+  26 metrics
+    SQ_INSTS_SENDMSG, SQ_INSTS, SQ_WAIT_ANY, SQ_WAIT_INST_ANY, SQ_ACTIVE_INST_ANY, SQ_INSTS_VALU, SQ_ACTIVE_INST_VMEM, SQ_ACTIVE_INST_LDS, TCP_VOLATILE_sum, TCP_TOTAL_ACCESSES_sum, TCP_TOTAL_READ_sum, TCP_TOTAL_WRITE_sum, TA_BUFFER_ATOMIC_WAVEFRONTS_sum, TA_BUFFER_TOTAL_CYCLES_sum, TD_ATOMIC_WAVEFRONT_sum, TD_STORE_WAVEFRONT_sum, SPI_RA_REQ_NO_ALLOC, SPI_RA_REQ_NO_ALLOC_CSN, CPC_CPC_STAT_STALL, CPC_UTCL1_STALL_ON_TRANSLATION, CPF_CPF_STAT_IDLE, CPF_CPF_TCIU_IDLE, TCC_REQ_sum, TCC_STREAMING_REQ_sum, TCC_HIT_sum, TCC_MISS_sum
+vcopy testing on GCD 0
+Finished allocating vectors on the CPU
+Finished allocating vectors on the GPU
+Finished copying vectors to the GPU
+sw thinks it moved 0.999755 KB per wave 
+Total threads: 1045876, Grid Size: 4086 block Size:256, Wavefronts:16344:
+Launching the  kernel on the GPU
+Finished executing kernel
+Finished copying the output vector from the GPU to the CPU
+Releasing GPU memory
+Releasing CPU memory
+
+ROCPRofiler: 1 contexts collected, output directory /tmp/rpl_data_231005_124652_184953/input0_results_231005_124652
+File 'Baseline_mi100/pmc_perf_2.csv' is generating
+RPL: on '231005_124652' from '/opt/rocm-5.5.1' in '/home1/josantos/omniperf'
+RPL: profiling '""./sample/vcopy 1045876 256""'
+RPL: input file 'Baseline_mi100/perfmon/pmc_perf_3.txt'
+RPL: output dir '/tmp/rpl_data_231005_124652_185135'
+RPL: result dir '/tmp/rpl_data_231005_124652_185135/input0_results_231005_124652'
+ROCProfiler: input from "/tmp/rpl_data_231005_124652_185135/input0.xml"
+  gpu_index = 
+  kernel = 
+  range = 
+  23 metrics
+    SQ_ACTIVE_INST_VALU, SQ_ACTIVE_INST_SCA, SQ_ACTIVE_INST_EXP_GDS, SQ_ACTIVE_INST_MISC, SQ_ACTIVE_INST_FLAT, SQ_INST_CYCLES_VMEM_WR, SQ_INST_CYCLES_VMEM_RD, SQ_INST_CYCLES_SMEM, TCP_TOTAL_ATOMIC_WITH_RET_sum, TCP_TOTAL_ATOMIC_WITHOUT_RET_sum, TCP_TOTAL_WRITEBACK_INVALIDATES_sum, TCP_TOTAL_CACHE_ACCESSES_sum, TA_BUFFER_COALESCED_READ_CYCLES_sum, TA_BUFFER_COALESCED_WRITE_CYCLES_sum, SPI_RA_RES_STALL_CSN, SPI_RA_TMP_STALL_CSN, CPC_CPC_UTCL2IU_BUSY, CPC_CPC_UTCL2IU_IDLE, CPF_CMP_UTCL1_STALL_ON_TRANSLATION, TCC_READ_sum, TCC_WRITE_sum, TCC_ATOMIC_sum, TCC_WRITEBACK_sum
+vcopy testing on GCD 0
+Finished allocating vectors on the CPU
+Finished allocating vectors on the GPU
+Finished copying vectors to the GPU
+sw thinks it moved 0.999755 KB per wave 
+Total threads: 1045876, Grid Size: 4086 block Size:256, Wavefronts:16344:
+Launching the  kernel on the GPU
+Finished executing kernel
+Finished copying the output vector from the GPU to the CPU
+Releasing GPU memory
+Releasing CPU memory
+
+ROCPRofiler: 1 contexts collected, output directory /tmp/rpl_data_231005_124652_185135/input0_results_231005_124652
+File 'Baseline_mi100/pmc_perf_3.csv' is generating
+RPL: on '231005_124653' from '/opt/rocm-5.5.1' in '/home1/josantos/omniperf'
+RPL: profiling '""./sample/vcopy 1045876 256""'
+RPL: input file 'Baseline_mi100/perfmon/pmc_perf_10.txt'
+RPL: output dir '/tmp/rpl_data_231005_124653_185317'
+RPL: result dir '/tmp/rpl_data_231005_124653_185317/input0_results_231005_124653'
+ROCProfiler: input from "/tmp/rpl_data_231005_124653_185317/input0.xml"
+  gpu_index = 
+  kernel = 
+  range = 
+  1 metrics
+    TCC_EA_ATOMIC_LEVEL_sum
+vcopy testing on GCD 0
+Finished allocating vectors on the CPU
+Finished allocating vectors on the GPU
+Finished copying vectors to the GPU
+sw thinks it moved 0.999755 KB per wave 
+Total threads: 1045876, Grid Size: 4086 block Size:256, Wavefronts:16344:
+Launching the  kernel on the GPU
+Finished executing kernel
+Finished copying the output vector from the GPU to the CPU
+Releasing GPU memory
+Releasing CPU memory
+
+ROCPRofiler: 1 contexts collected, output directory /tmp/rpl_data_231005_124653_185317/input0_results_231005_124653
+File 'Baseline_mi100/pmc_perf_10.csv' is generating
+RPL: on '231005_124653' from '/opt/rocm-5.5.1' in '/home1/josantos/omniperf'
+RPL: profiling '""./sample/vcopy 1045876 256""'
+RPL: input file 'Baseline_mi100/perfmon/pmc_perf_5.txt'
+RPL: output dir '/tmp/rpl_data_231005_124653_185499'
+RPL: result dir '/tmp/rpl_data_231005_124653_185499/input0_results_231005_124653'
+ROCProfiler: input from "/tmp/rpl_data_231005_124653_185499/input0.xml"
+  gpu_index = 
+  kernel = 
+  range = 
+  21 metrics
+    SQ_WAVES_LT_48, SQ_WAVES_LT_32, SQ_WAVES_LT_16, SQ_ITEMS, SQ_LDS_MEM_VIOLATIONS, SQ_LDS_ATOMIC_RETURN, SQ_LDS_IDX_ACTIVE, SQ_WAVES_RESTORED, TCP_TCP_LATENCY_sum, TCP_TCC_READ_REQ_LATENCY_sum, TCP_TCC_WRITE_REQ_LATENCY_sum, TCP_TCC_READ_REQ_sum, TA_ADDR_STALLED_BY_TD_CYCLES_sum, TA_DATA_STALLED_BY_TC_CYCLES_sum, SPI_RA_SGPR_SIMD_FULL_CSN, SPI_RA_LDS_CU_FULL_CSN, CPC_ME1_DC0_SPI_BUSY, TCC_EA_WRREQ_IO_CREDIT_STALL_sum, TCC_EA_WRREQ_GMI_CREDIT_STALL_sum, TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum, TCC_TOO_MANY_EA_WRREQS_STALL_sum
+vcopy testing on GCD 0
+Finished allocating vectors on the CPU
+Finished allocating vectors on the GPU
+Finished copying vectors to the GPU
+sw thinks it moved 0.999755 KB per wave 
+Total threads: 1045876, Grid Size: 4086 block Size:256, Wavefronts:16344:
+Launching the  kernel on the GPU
+Finished executing kernel
+Finished copying the output vector from the GPU to the CPU
+Releasing GPU memory
+Releasing CPU memory
+
+ROCPRofiler: 1 contexts collected, output directory /tmp/rpl_data_231005_124653_185499/input0_results_231005_124653
+File 'Baseline_mi100/pmc_perf_5.csv' is generating
+RPL: on '231005_124654' from '/opt/rocm-5.5.1' in '/home1/josantos/omniperf'
+RPL: profiling '""./sample/vcopy 1045876 256""'
+RPL: input file 'Baseline_mi100/perfmon/pmc_perf_13.txt'
+RPL: output dir '/tmp/rpl_data_231005_124654_185681'
+RPL: result dir '/tmp/rpl_data_231005_124654_185681/input0_results_231005_124654'
+ROCProfiler: input from "/tmp/rpl_data_231005_124654_185681/input0.xml"
+  gpu_index = 
+  kernel = 
+  range = 
+  128 metrics
+    TCC_EA_RDREQ_IO_CREDIT_STALL[0], TCC_EA_RDREQ_LEVEL[0], TCC_EA_WRREQ[0], TCC_EA_WRREQ_64B[0], TCC_EA_RDREQ_IO_CREDIT_STALL[1], TCC_EA_RDREQ_LEVEL[1], TCC_EA_WRREQ[1], TCC_EA_WRREQ_64B[1], TCC_EA_RDREQ_IO_CREDIT_STALL[2], TCC_EA_RDREQ_LEVEL[2], TCC_EA_WRREQ[2], TCC_EA_WRREQ_64B[2], TCC_EA_RDREQ_IO_CREDIT_STALL[3], TCC_EA_RDREQ_LEVEL[3], TCC_EA_WRREQ[3], TCC_EA_WRREQ_64B[3], TCC_EA_RDREQ_IO_CREDIT_STALL[4], TCC_EA_RDREQ_LEVEL[4], TCC_EA_WRREQ[4], TCC_EA_WRREQ_64B[4], TCC_EA_RDREQ_IO_CREDIT_STALL[5], TCC_EA_RDREQ_LEVEL[5], TCC_EA_WRREQ[5], TCC_EA_WRREQ_64B[5], TCC_EA_RDREQ_IO_CREDIT_STALL[6], TCC_EA_RDREQ_LEVEL[6], TCC_EA_WRREQ[6], TCC_EA_WRREQ_64B[6], TCC_EA_RDREQ_IO_CREDIT_STALL[7], TCC_EA_RDREQ_LEVEL[7], TCC_EA_WRREQ[7], TCC_EA_WRREQ_64B[7], TCC_EA_RDREQ_IO_CREDIT_STALL[8], TCC_EA_RDREQ_LEVEL[8], TCC_EA_WRREQ[8], TCC_EA_WRREQ_64B[8], TCC_EA_RDREQ_IO_CREDIT_STALL[9], TCC_EA_RDREQ_LEVEL[9], TCC_EA_WRREQ[9], TCC_EA_WRREQ_64B[9], TCC_EA_RDREQ_IO_CREDIT_STALL[10], TCC_EA_RDREQ_LEVEL[10], TCC_EA_WRREQ[10], TCC_EA_WRREQ_64B[10], TCC_EA_RDREQ_IO_CREDIT_STALL[11], TCC_EA_RDREQ_LEVEL[11], TCC_EA_WRREQ[11], TCC_EA_WRREQ_64B[11], TCC_EA_RDREQ_IO_CREDIT_STALL[12], TCC_EA_RDREQ_LEVEL[12], TCC_EA_WRREQ[12], TCC_EA_WRREQ_64B[12], TCC_EA_RDREQ_IO_CREDIT_STALL[13], TCC_EA_RDREQ_LEVEL[13], TCC_EA_WRREQ[13], TCC_EA_WRREQ_64B[13], TCC_EA_RDREQ_IO_CREDIT_STALL[14], TCC_EA_RDREQ_LEVEL[14], TCC_EA_WRREQ[14], TCC_EA_WRREQ_64B[14], TCC_EA_RDREQ_IO_CREDIT_STALL[15], TCC_EA_RDREQ_LEVEL[15], TCC_EA_WRREQ[15], TCC_EA_WRREQ_64B[15], TCC_EA_RDREQ_IO_CREDIT_STALL[16], TCC_EA_RDREQ_LEVEL[16], TCC_EA_WRREQ[16], TCC_EA_WRREQ_64B[16], TCC_EA_RDREQ_IO_CREDIT_STALL[17], TCC_EA_RDREQ_LEVEL[17], TCC_EA_WRREQ[17], TCC_EA_WRREQ_64B[17], TCC_EA_RDREQ_IO_CREDIT_STALL[18], TCC_EA_RDREQ_LEVEL[18], TCC_EA_WRREQ[18], TCC_EA_WRREQ_64B[18], TCC_EA_RDREQ_IO_CREDIT_STALL[19], TCC_EA_RDREQ_LEVEL[19], TCC_EA_WRREQ[19], TCC_EA_WRREQ_64B[19], TCC_EA_RDREQ_IO_CREDIT_STALL[20], TCC_EA_RDREQ_LEVEL[20], TCC_EA_WRREQ[20], TCC_EA_WRREQ_64B[20], TCC_EA_RDREQ_IO_CREDIT_STALL[21], TCC_EA_RDREQ_LEVEL[21], TCC_EA_WRREQ[21], TCC_EA_WRREQ_64B[21], TCC_EA_RDREQ_IO_CREDIT_STALL[22], TCC_EA_RDREQ_LEVEL[22], TCC_EA_WRREQ[22], TCC_EA_WRREQ_64B[22], TCC_EA_RDREQ_IO_CREDIT_STALL[23], TCC_EA_RDREQ_LEVEL[23], TCC_EA_WRREQ[23], TCC_EA_WRREQ_64B[23], TCC_EA_RDREQ_IO_CREDIT_STALL[24], TCC_EA_RDREQ_LEVEL[24], TCC_EA_WRREQ[24], TCC_EA_WRREQ_64B[24], TCC_EA_RDREQ_IO_CREDIT_STALL[25], TCC_EA_RDREQ_LEVEL[25], TCC_EA_WRREQ[25], TCC_EA_WRREQ_64B[25], TCC_EA_RDREQ_IO_CREDIT_STALL[26], TCC_EA_RDREQ_LEVEL[26], TCC_EA_WRREQ[26], TCC_EA_WRREQ_64B[26], TCC_EA_RDREQ_IO_CREDIT_STALL[27], TCC_EA_RDREQ_LEVEL[27], TCC_EA_WRREQ[27], TCC_EA_WRREQ_64B[27], TCC_EA_RDREQ_IO_CREDIT_STALL[28], TCC_EA_RDREQ_LEVEL[28], TCC_EA_WRREQ[28], TCC_EA_WRREQ_64B[28], TCC_EA_RDREQ_IO_CREDIT_STALL[29], TCC_EA_RDREQ_LEVEL[29], TCC_EA_WRREQ[29], TCC_EA_WRREQ_64B[29], TCC_EA_RDREQ_IO_CREDIT_STALL[30], TCC_EA_RDREQ_LEVEL[30], TCC_EA_WRREQ[30], TCC_EA_WRREQ_64B[30], TCC_EA_RDREQ_IO_CREDIT_STALL[31], TCC_EA_RDREQ_LEVEL[31], TCC_EA_WRREQ[31], TCC_EA_WRREQ_64B[31]
+vcopy testing on GCD 0
+Finished allocating vectors on the CPU
+Finished allocating vectors on the GPU
+Finished copying vectors to the GPU
+sw thinks it moved 0.999755 KB per wave 
+Total threads: 1045876, Grid Size: 4086 block Size:256, Wavefronts:16344:
+Launching the  kernel on the GPU
+Finished executing kernel
+Finished copying the output vector from the GPU to the CPU
+Releasing GPU memory
+Releasing CPU memory
+
+ROCPRofiler: 1 contexts collected, output directory /tmp/rpl_data_231005_124654_185681/input0_results_231005_124654
+File 'Baseline_mi100/pmc_perf_13.csv' is generating
+RPL: on '231005_124654' from '/opt/rocm-5.5.1' in '/home1/josantos/omniperf'
+RPL: profiling '""./sample/vcopy 1045876 256""'
+RPL: input file 'Baseline_mi100/perfmon/pmc_perf_14.txt'
+RPL: output dir '/tmp/rpl_data_231005_124654_185863'
+RPL: result dir '/tmp/rpl_data_231005_124654_185863/input0_results_231005_124654'
+ROCProfiler: input from "/tmp/rpl_data_231005_124654_185863/input0.xml"
+  gpu_index = 
+  kernel = 
+  range = 
+  128 metrics
+    TCC_EA_WRREQ_DRAM_CREDIT_STALL[0], TCC_EA_WRREQ_GMI_CREDIT_STALL[0], TCC_EA_WRREQ_IO_CREDIT_STALL[0], TCC_EA_WRREQ_LEVEL[0], TCC_EA_WRREQ_DRAM_CREDIT_STALL[1], TCC_EA_WRREQ_GMI_CREDIT_STALL[1], TCC_EA_WRREQ_IO_CREDIT_STALL[1], TCC_EA_WRREQ_LEVEL[1], TCC_EA_WRREQ_DRAM_CREDIT_STALL[2], TCC_EA_WRREQ_GMI_CREDIT_STALL[2], TCC_EA_WRREQ_IO_CREDIT_STALL[2], TCC_EA_WRREQ_LEVEL[2], TCC_EA_WRREQ_DRAM_CREDIT_STALL[3], TCC_EA_WRREQ_GMI_CREDIT_STALL[3], TCC_EA_WRREQ_IO_CREDIT_STALL[3], TCC_EA_WRREQ_LEVEL[3], TCC_EA_WRREQ_DRAM_CREDIT_STALL[4], TCC_EA_WRREQ_GMI_CREDIT_STALL[4], TCC_EA_WRREQ_IO_CREDIT_STALL[4], TCC_EA_WRREQ_LEVEL[4], TCC_EA_WRREQ_DRAM_CREDIT_STALL[5], TCC_EA_WRREQ_GMI_CREDIT_STALL[5], TCC_EA_WRREQ_IO_CREDIT_STALL[5], TCC_EA_WRREQ_LEVEL[5], TCC_EA_WRREQ_DRAM_CREDIT_STALL[6], TCC_EA_WRREQ_GMI_CREDIT_STALL[6], TCC_EA_WRREQ_IO_CREDIT_STALL[6], TCC_EA_WRREQ_LEVEL[6], TCC_EA_WRREQ_DRAM_CREDIT_STALL[7], TCC_EA_WRREQ_GMI_CREDIT_STALL[7], TCC_EA_WRREQ_IO_CREDIT_STALL[7], TCC_EA_WRREQ_LEVEL[7], TCC_EA_WRREQ_DRAM_CREDIT_STALL[8], TCC_EA_WRREQ_GMI_CREDIT_STALL[8], TCC_EA_WRREQ_IO_CREDIT_STALL[8], TCC_EA_WRREQ_LEVEL[8], TCC_EA_WRREQ_DRAM_CREDIT_STALL[9], TCC_EA_WRREQ_GMI_CREDIT_STALL[9], TCC_EA_WRREQ_IO_CREDIT_STALL[9], TCC_EA_WRREQ_LEVEL[9], TCC_EA_WRREQ_DRAM_CREDIT_STALL[10], TCC_EA_WRREQ_GMI_CREDIT_STALL[10], TCC_EA_WRREQ_IO_CREDIT_STALL[10], TCC_EA_WRREQ_LEVEL[10], TCC_EA_WRREQ_DRAM_CREDIT_STALL[11], TCC_EA_WRREQ_GMI_CREDIT_STALL[11], TCC_EA_WRREQ_IO_CREDIT_STALL[11], TCC_EA_WRREQ_LEVEL[11], TCC_EA_WRREQ_DRAM_CREDIT_STALL[12], TCC_EA_WRREQ_GMI_CREDIT_STALL[12], TCC_EA_WRREQ_IO_CREDIT_STALL[12], TCC_EA_WRREQ_LEVEL[12], TCC_EA_WRREQ_DRAM_CREDIT_STALL[13], TCC_EA_WRREQ_GMI_CREDIT_STALL[13], TCC_EA_WRREQ_IO_CREDIT_STALL[13], TCC_EA_WRREQ_LEVEL[13], TCC_EA_WRREQ_DRAM_CREDIT_STALL[14], TCC_EA_WRREQ_GMI_CREDIT_STALL[14], TCC_EA_WRREQ_IO_CREDIT_STALL[14], TCC_EA_WRREQ_LEVEL[14], TCC_EA_WRREQ_DRAM_CREDIT_STALL[15], TCC_EA_WRREQ_GMI_CREDIT_STALL[15], TCC_EA_WRREQ_IO_CREDIT_STALL[15], TCC_EA_WRREQ_LEVEL[15], TCC_EA_WRREQ_DRAM_CREDIT_STALL[16], TCC_EA_WRREQ_GMI_CREDIT_STALL[16], TCC_EA_WRREQ_IO_CREDIT_STALL[16], TCC_EA_WRREQ_LEVEL[16], TCC_EA_WRREQ_DRAM_CREDIT_STALL[17], TCC_EA_WRREQ_GMI_CREDIT_STALL[17], TCC_EA_WRREQ_IO_CREDIT_STALL[17], TCC_EA_WRREQ_LEVEL[17], TCC_EA_WRREQ_DRAM_CREDIT_STALL[18], TCC_EA_WRREQ_GMI_CREDIT_STALL[18], TCC_EA_WRREQ_IO_CREDIT_STALL[18], TCC_EA_WRREQ_LEVEL[18], TCC_EA_WRREQ_DRAM_CREDIT_STALL[19], TCC_EA_WRREQ_GMI_CREDIT_STALL[19], TCC_EA_WRREQ_IO_CREDIT_STALL[19], TCC_EA_WRREQ_LEVEL[19], TCC_EA_WRREQ_DRAM_CREDIT_STALL[20], TCC_EA_WRREQ_GMI_CREDIT_STALL[20], TCC_EA_WRREQ_IO_CREDIT_STALL[20], TCC_EA_WRREQ_LEVEL[20], TCC_EA_WRREQ_DRAM_CREDIT_STALL[21], TCC_EA_WRREQ_GMI_CREDIT_STALL[21], TCC_EA_WRREQ_IO_CREDIT_STALL[21], TCC_EA_WRREQ_LEVEL[21], TCC_EA_WRREQ_DRAM_CREDIT_STALL[22], TCC_EA_WRREQ_GMI_CREDIT_STALL[22], TCC_EA_WRREQ_IO_CREDIT_STALL[22], TCC_EA_WRREQ_LEVEL[22], TCC_EA_WRREQ_DRAM_CREDIT_STALL[23], TCC_EA_WRREQ_GMI_CREDIT_STALL[23], TCC_EA_WRREQ_IO_CREDIT_STALL[23], TCC_EA_WRREQ_LEVEL[23], TCC_EA_WRREQ_DRAM_CREDIT_STALL[24], TCC_EA_WRREQ_GMI_CREDIT_STALL[24], TCC_EA_WRREQ_IO_CREDIT_STALL[24], TCC_EA_WRREQ_LEVEL[24], TCC_EA_WRREQ_DRAM_CREDIT_STALL[25], TCC_EA_WRREQ_GMI_CREDIT_STALL[25], TCC_EA_WRREQ_IO_CREDIT_STALL[25], TCC_EA_WRREQ_LEVEL[25], TCC_EA_WRREQ_DRAM_CREDIT_STALL[26], TCC_EA_WRREQ_GMI_CREDIT_STALL[26], TCC_EA_WRREQ_IO_CREDIT_STALL[26], TCC_EA_WRREQ_LEVEL[26], TCC_EA_WRREQ_DRAM_CREDIT_STALL[27], TCC_EA_WRREQ_GMI_CREDIT_STALL[27], TCC_EA_WRREQ_IO_CREDIT_STALL[27], TCC_EA_WRREQ_LEVEL[27], TCC_EA_WRREQ_DRAM_CREDIT_STALL[28], TCC_EA_WRREQ_GMI_CREDIT_STALL[28], TCC_EA_WRREQ_IO_CREDIT_STALL[28], TCC_EA_WRREQ_LEVEL[28], TCC_EA_WRREQ_DRAM_CREDIT_STALL[29], TCC_EA_WRREQ_GMI_CREDIT_STALL[29], TCC_EA_WRREQ_IO_CREDIT_STALL[29], TCC_EA_WRREQ_LEVEL[29], TCC_EA_WRREQ_DRAM_CREDIT_STALL[30], TCC_EA_WRREQ_GMI_CREDIT_STALL[30], TCC_EA_WRREQ_IO_CREDIT_STALL[30], TCC_EA_WRREQ_LEVEL[30], TCC_EA_WRREQ_DRAM_CREDIT_STALL[31], TCC_EA_WRREQ_GMI_CREDIT_STALL[31], TCC_EA_WRREQ_IO_CREDIT_STALL[31], TCC_EA_WRREQ_LEVEL[31]
+vcopy testing on GCD 0
+Finished allocating vectors on the CPU
+Finished allocating vectors on the GPU
+Finished copying vectors to the GPU
+sw thinks it moved 0.999755 KB per wave 
+Total threads: 1045876, Grid Size: 4086 block Size:256, Wavefronts:16344:
+Launching the  kernel on the GPU
+Finished executing kernel
+Finished copying the output vector from the GPU to the CPU
+Releasing GPU memory
+Releasing CPU memory
+
+ROCPRofiler: 1 contexts collected, output directory /tmp/rpl_data_231005_124654_185863/input0_results_231005_124654
+File 'Baseline_mi100/pmc_perf_14.csv' is generating
+RPL: on '231005_124655' from '/opt/rocm-5.5.1' in '/home1/josantos/omniperf'
+RPL: profiling '""./sample/vcopy 1045876 256""'
+RPL: input file 'Baseline_mi100/perfmon/SQ_INST_LEVEL_VMEM.txt'
+RPL: output dir '/tmp/rpl_data_231005_124655_186045'
+RPL: result dir '/tmp/rpl_data_231005_124655_186045/input0_results_231005_124655'
+ROCProfiler: input from "/tmp/rpl_data_231005_124655_186045/input0.xml"
+  gpu_index = 
+  kernel = 
+  range = 
+  3 metrics
+    SQ_INSTS_VMEM, SQ_INST_LEVEL_VMEM, SQ_ACCUM_PREV_HIRES
+vcopy testing on GCD 0
+Finished allocating vectors on the CPU
+Finished allocating vectors on the GPU
+Finished copying vectors to the GPU
+sw thinks it moved 0.999755 KB per wave 
+Total threads: 1045876, Grid Size: 4086 block Size:256, Wavefronts:16344:
+Launching the  kernel on the GPU
+Finished executing kernel
+Finished copying the output vector from the GPU to the CPU
+Releasing GPU memory
+Releasing CPU memory
+
+ROCPRofiler: 1 contexts collected, output directory /tmp/rpl_data_231005_124655_186045/input0_results_231005_124655
+File 'Baseline_mi100/SQ_INST_LEVEL_VMEM.csv' is generating
+RPL: on '231005_124655' from '/opt/rocm-5.5.1' in '/home1/josantos/omniperf'
+RPL: profiling '""./sample/vcopy 1045876 256""'
+RPL: input file 'Baseline_mi100/perfmon/SQ_INST_LEVEL_SMEM.txt'
+RPL: output dir '/tmp/rpl_data_231005_124655_186228'
+RPL: result dir '/tmp/rpl_data_231005_124655_186228/input0_results_231005_124655'
+ROCProfiler: input from "/tmp/rpl_data_231005_124655_186228/input0.xml"
+  gpu_index = 
+  kernel = 
+  range = 
+  3 metrics
+    SQ_INSTS_SMEM, SQ_INST_LEVEL_SMEM, SQ_ACCUM_PREV_HIRES
+vcopy testing on GCD 0
+Finished allocating vectors on the CPU
+Finished allocating vectors on the GPU
+Finished copying vectors to the GPU
+sw thinks it moved 0.999755 KB per wave 
+Total threads: 1045876, Grid Size: 4086 block Size:256, Wavefronts:16344:
+Launching the  kernel on the GPU
+Finished executing kernel
+Finished copying the output vector from the GPU to the CPU
+Releasing GPU memory
+Releasing CPU memory
+
+ROCPRofiler: 1 contexts collected, output directory /tmp/rpl_data_231005_124655_186228/input0_results_231005_124655
+File 'Baseline_mi100/SQ_INST_LEVEL_SMEM.csv' is generating
+RPL: on '231005_124656' from '/opt/rocm-5.5.1' in '/home1/josantos/omniperf'
+RPL: profiling '""./sample/vcopy 1045876 256""'
+RPL: input file 'Baseline_mi100/perfmon/pmc_perf_11.txt'
+RPL: output dir '/tmp/rpl_data_231005_124656_186410'
+RPL: result dir '/tmp/rpl_data_231005_124656_186410/input0_results_231005_124656'
+ROCProfiler: input from "/tmp/rpl_data_231005_124656_186410/input0.xml"
+  gpu_index = 
+  kernel = 
+  range = 
+  128 metrics
+    TCC_ATOMIC[0], TCC_CYCLE[0], TCC_EA_ATOMIC[0], TCC_EA_ATOMIC_LEVEL[0], TCC_ATOMIC[1], TCC_CYCLE[1], TCC_EA_ATOMIC[1], TCC_EA_ATOMIC_LEVEL[1], TCC_ATOMIC[2], TCC_CYCLE[2], TCC_EA_ATOMIC[2], TCC_EA_ATOMIC_LEVEL[2], TCC_ATOMIC[3], TCC_CYCLE[3], TCC_EA_ATOMIC[3], TCC_EA_ATOMIC_LEVEL[3], TCC_ATOMIC[4], TCC_CYCLE[4], TCC_EA_ATOMIC[4], TCC_EA_ATOMIC_LEVEL[4], TCC_ATOMIC[5], TCC_CYCLE[5], TCC_EA_ATOMIC[5], TCC_EA_ATOMIC_LEVEL[5], TCC_ATOMIC[6], TCC_CYCLE[6], TCC_EA_ATOMIC[6], TCC_EA_ATOMIC_LEVEL[6], TCC_ATOMIC[7], TCC_CYCLE[7], TCC_EA_ATOMIC[7], TCC_EA_ATOMIC_LEVEL[7], TCC_ATOMIC[8], TCC_CYCLE[8], TCC_EA_ATOMIC[8], TCC_EA_ATOMIC_LEVEL[8], TCC_ATOMIC[9], TCC_CYCLE[9], TCC_EA_ATOMIC[9], TCC_EA_ATOMIC_LEVEL[9], TCC_ATOMIC[10], TCC_CYCLE[10], TCC_EA_ATOMIC[10], TCC_EA_ATOMIC_LEVEL[10], TCC_ATOMIC[11], TCC_CYCLE[11], TCC_EA_ATOMIC[11], TCC_EA_ATOMIC_LEVEL[11], TCC_ATOMIC[12], TCC_CYCLE[12], TCC_EA_ATOMIC[12], TCC_EA_ATOMIC_LEVEL[12], TCC_ATOMIC[13], TCC_CYCLE[13], TCC_EA_ATOMIC[13], TCC_EA_ATOMIC_LEVEL[13], TCC_ATOMIC[14], TCC_CYCLE[14], TCC_EA_ATOMIC[14], TCC_EA_ATOMIC_LEVEL[14], TCC_ATOMIC[15], TCC_CYCLE[15], TCC_EA_ATOMIC[15], TCC_EA_ATOMIC_LEVEL[15], TCC_ATOMIC[16], TCC_CYCLE[16], TCC_EA_ATOMIC[16], TCC_EA_ATOMIC_LEVEL[16], TCC_ATOMIC[17], TCC_CYCLE[17], TCC_EA_ATOMIC[17], TCC_EA_ATOMIC_LEVEL[17], TCC_ATOMIC[18], TCC_CYCLE[18], TCC_EA_ATOMIC[18], TCC_EA_ATOMIC_LEVEL[18], TCC_ATOMIC[19], TCC_CYCLE[19], TCC_EA_ATOMIC[19], TCC_EA_ATOMIC_LEVEL[19], TCC_ATOMIC[20], TCC_CYCLE[20], TCC_EA_ATOMIC[20], TCC_EA_ATOMIC_LEVEL[20], TCC_ATOMIC[21], TCC_CYCLE[21], TCC_EA_ATOMIC[21], TCC_EA_ATOMIC_LEVEL[21], TCC_ATOMIC[22], TCC_CYCLE[22], TCC_EA_ATOMIC[22], TCC_EA_ATOMIC_LEVEL[22], TCC_ATOMIC[23], TCC_CYCLE[23], TCC_EA_ATOMIC[23], TCC_EA_ATOMIC_LEVEL[23], TCC_ATOMIC[24], TCC_CYCLE[24], TCC_EA_ATOMIC[24], TCC_EA_ATOMIC_LEVEL[24], TCC_ATOMIC[25], TCC_CYCLE[25], TCC_EA_ATOMIC[25], TCC_EA_ATOMIC_LEVEL[25], TCC_ATOMIC[26], TCC_CYCLE[26], TCC_EA_ATOMIC[26], TCC_EA_ATOMIC_LEVEL[26], TCC_ATOMIC[27], TCC_CYCLE[27], TCC_EA_ATOMIC[27], TCC_EA_ATOMIC_LEVEL[27], TCC_ATOMIC[28], TCC_CYCLE[28], TCC_EA_ATOMIC[28], TCC_EA_ATOMIC_LEVEL[28], TCC_ATOMIC[29], TCC_CYCLE[29], TCC_EA_ATOMIC[29], TCC_EA_ATOMIC_LEVEL[29], TCC_ATOMIC[30], TCC_CYCLE[30], TCC_EA_ATOMIC[30], TCC_EA_ATOMIC_LEVEL[30], TCC_ATOMIC[31], TCC_CYCLE[31], TCC_EA_ATOMIC[31], TCC_EA_ATOMIC_LEVEL[31]
+vcopy testing on GCD 0
+Finished allocating vectors on the CPU
+Finished allocating vectors on the GPU
+Finished copying vectors to the GPU
+sw thinks it moved 0.999755 KB per wave 
+Total threads: 1045876, Grid Size: 4086 block Size:256, Wavefronts:16344:
+Launching the  kernel on the GPU
+Finished executing kernel
+Finished copying the output vector from the GPU to the CPU
+Releasing GPU memory
+Releasing CPU memory
+
+ROCPRofiler: 1 contexts collected, output directory /tmp/rpl_data_231005_124656_186410/input0_results_231005_124656
+File 'Baseline_mi100/pmc_perf_11.csv' is generating
+Successfully joined gpu in pmc_perf.csv
+Successfully joined grd in pmc_perf.csv
+Successfully joined Workgroup_Size in pmc_perf.csv
+Successfully joined LDS_Per_Workgroup in pmc_perf.csv
+Successfully joined scr in pmc_perf.csv
+Successfully joined spgr in pmc_perf.csv
+Successfully joined arch_vgpr in pmc_perf.csv
+Successfully joined accum_vgpr in pmc_perf.csv
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/perfmon/SQ_IFETCH_LEVEL.txt b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/perfmon/SQ_IFETCH_LEVEL.txt
new file mode 100644
index 0000000000..293092f641
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/perfmon/SQ_IFETCH_LEVEL.txt
@@ -0,0 +1,5 @@
+pmc: GRBM_COUNT GRBM_GUI_ACTIVE SQ_WAVES SQ_IFETCH SQ_IFETCH_LEVEL  SQ_ACCUM_PREV_HIRES
+
+gpu:
+range:
+kernel:
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/perfmon/SQ_INST_LEVEL_LDS.txt b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/perfmon/SQ_INST_LEVEL_LDS.txt
new file mode 100644
index 0000000000..08439eedce
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/perfmon/SQ_INST_LEVEL_LDS.txt
@@ -0,0 +1,5 @@
+pmc: SQ_INSTS_LDS SQ_INST_LEVEL_LDS  SQ_ACCUM_PREV_HIRES
+
+gpu:
+range:
+kernel:
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/perfmon/SQ_INST_LEVEL_SMEM.txt b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/perfmon/SQ_INST_LEVEL_SMEM.txt
new file mode 100644
index 0000000000..6cca322d4e
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/perfmon/SQ_INST_LEVEL_SMEM.txt
@@ -0,0 +1,5 @@
+pmc: SQ_INSTS_SMEM  SQ_INST_LEVEL_SMEM SQ_ACCUM_PREV_HIRES
+
+gpu:
+range:
+kernel:
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/perfmon/SQ_INST_LEVEL_VMEM.txt b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/perfmon/SQ_INST_LEVEL_VMEM.txt
new file mode 100644
index 0000000000..e527ad31ba
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/perfmon/SQ_INST_LEVEL_VMEM.txt
@@ -0,0 +1,5 @@
+pmc: SQ_INSTS_VMEM  SQ_INST_LEVEL_VMEM SQ_ACCUM_PREV_HIRES
+
+gpu:
+range:
+kernel:
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/perfmon/SQ_LEVEL_WAVES.txt b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/perfmon/SQ_LEVEL_WAVES.txt
new file mode 100644
index 0000000000..3f8e04adb3
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/perfmon/SQ_LEVEL_WAVES.txt
@@ -0,0 +1,5 @@
+pmc: GRBM_COUNT GRBM_GUI_ACTIVE CPC_ME1_BUSY_FOR_PACKET_DECODE SQ_CYCLES SQ_WAVES SQ_WAVE_CYCLES SQ_BUSY_CYCLES SQ_LEVEL_WAVES  SQ_ACCUM_PREV_HIRES
+
+gpu:
+range:
+kernel:
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/perfmon/pmc_perf_0.txt b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/perfmon/pmc_perf_0.txt
new file mode 100644
index 0000000000..95e2e85d3a
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/perfmon/pmc_perf_0.txt
@@ -0,0 +1,5 @@
+pmc:  SQ_CYCLES SQ_BUSY_CYCLES SQ_BUSY_CU_CYCLES SQ_WAVES SQ_WAVE_CYCLES SQ_INSTS_VMEM_WR SQ_INSTS_VMEM_RD SQ_INSTS_VMEM GRBM_COUNT GRBM_GUI_ACTIVE TCP_GATE_EN1_sum TCP_GATE_EN2_sum TCP_TD_TCP_STALL_CYCLES_sum TCP_TCR_TCP_STALL_CYCLES_sum TA_TA_BUSY_sum TA_BUFFER_WAVEFRONTS_sum TD_TD_BUSY_sum TD_TC_STALL_sum SPI_CSN_WINDOW_VALID SPI_CSN_BUSY CPC_CPC_STAT_BUSY CPC_CPC_STAT_IDLE CPF_CPF_STAT_BUSY CPF_CPF_STAT_STALL TCC_CYCLE_sum TCC_BUSY_sum TCC_PROBE_sum TCC_PROBE_ALL_sum
+
+gpu:
+range:
+kernel:
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/perfmon/pmc_perf_1.txt b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/perfmon/pmc_perf_1.txt
new file mode 100644
index 0000000000..a1bd994746
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/perfmon/pmc_perf_1.txt
@@ -0,0 +1,5 @@
+pmc:  SQ_INSTS_SALU SQ_INSTS_VSKIPPED SQ_INSTS_SMEM SQ_INSTS_FLAT SQ_INSTS_LDS SQ_INSTS_GDS SQ_INSTS_EXP_GDS SQ_INSTS_BRANCH GRBM_SPI_BUSY TCP_READ_TAGCONFLICT_STALL_CYCLES_sum TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum TCP_TA_TCP_STATE_READ_sum TA_BUFFER_READ_WAVEFRONTS_sum TA_BUFFER_WRITE_WAVEFRONTS_sum TD_COALESCABLE_WAVEFRONT_sum TD_LOAD_WAVEFRONT_sum SPI_CSN_NUM_THREADGROUPS SPI_CSN_WAVE CPC_CPC_TCIU_BUSY CPC_CPC_TCIU_IDLE CPF_CPF_TCIU_BUSY CPF_CPF_TCIU_STALL TCC_NC_REQ_sum TCC_UC_REQ_sum TCC_CC_REQ_sum TCC_RW_REQ_sum
+
+gpu:
+range:
+kernel:
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/perfmon/pmc_perf_10.txt b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/perfmon/pmc_perf_10.txt
new file mode 100644
index 0000000000..a00555d953
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/perfmon/pmc_perf_10.txt
@@ -0,0 +1,5 @@
+pmc:  TCC_EA_ATOMIC_LEVEL_sum
+
+gpu:
+range:
+kernel:
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/perfmon/pmc_perf_11.txt b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/perfmon/pmc_perf_11.txt
new file mode 100644
index 0000000000..062fc9644a
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/perfmon/pmc_perf_11.txt
@@ -0,0 +1,5 @@
+pmc:  TCC_ATOMIC[0] TCC_CYCLE[0] TCC_EA_ATOMIC[0] TCC_EA_ATOMIC_LEVEL[0] TCC_ATOMIC[1] TCC_CYCLE[1] TCC_EA_ATOMIC[1] TCC_EA_ATOMIC_LEVEL[1] TCC_ATOMIC[2] TCC_CYCLE[2] TCC_EA_ATOMIC[2] TCC_EA_ATOMIC_LEVEL[2] TCC_ATOMIC[3] TCC_CYCLE[3] TCC_EA_ATOMIC[3] TCC_EA_ATOMIC_LEVEL[3] TCC_ATOMIC[4] TCC_CYCLE[4] TCC_EA_ATOMIC[4] TCC_EA_ATOMIC_LEVEL[4] TCC_ATOMIC[5] TCC_CYCLE[5] TCC_EA_ATOMIC[5] TCC_EA_ATOMIC_LEVEL[5] TCC_ATOMIC[6] TCC_CYCLE[6] TCC_EA_ATOMIC[6] TCC_EA_ATOMIC_LEVEL[6] TCC_ATOMIC[7] TCC_CYCLE[7] TCC_EA_ATOMIC[7] TCC_EA_ATOMIC_LEVEL[7] TCC_ATOMIC[8] TCC_CYCLE[8] TCC_EA_ATOMIC[8] TCC_EA_ATOMIC_LEVEL[8] TCC_ATOMIC[9] TCC_CYCLE[9] TCC_EA_ATOMIC[9] TCC_EA_ATOMIC_LEVEL[9] TCC_ATOMIC[10] TCC_CYCLE[10] TCC_EA_ATOMIC[10] TCC_EA_ATOMIC_LEVEL[10] TCC_ATOMIC[11] TCC_CYCLE[11] TCC_EA_ATOMIC[11] TCC_EA_ATOMIC_LEVEL[11] TCC_ATOMIC[12] TCC_CYCLE[12] TCC_EA_ATOMIC[12] TCC_EA_ATOMIC_LEVEL[12] TCC_ATOMIC[13] TCC_CYCLE[13] TCC_EA_ATOMIC[13] TCC_EA_ATOMIC_LEVEL[13] TCC_ATOMIC[14] TCC_CYCLE[14] TCC_EA_ATOMIC[14] TCC_EA_ATOMIC_LEVEL[14] TCC_ATOMIC[15] TCC_CYCLE[15] TCC_EA_ATOMIC[15] TCC_EA_ATOMIC_LEVEL[15] TCC_ATOMIC[16] TCC_CYCLE[16] TCC_EA_ATOMIC[16] TCC_EA_ATOMIC_LEVEL[16] TCC_ATOMIC[17] TCC_CYCLE[17] TCC_EA_ATOMIC[17] TCC_EA_ATOMIC_LEVEL[17] TCC_ATOMIC[18] TCC_CYCLE[18] TCC_EA_ATOMIC[18] TCC_EA_ATOMIC_LEVEL[18] TCC_ATOMIC[19] TCC_CYCLE[19] TCC_EA_ATOMIC[19] TCC_EA_ATOMIC_LEVEL[19] TCC_ATOMIC[20] TCC_CYCLE[20] TCC_EA_ATOMIC[20] TCC_EA_ATOMIC_LEVEL[20] TCC_ATOMIC[21] TCC_CYCLE[21] TCC_EA_ATOMIC[21] TCC_EA_ATOMIC_LEVEL[21] TCC_ATOMIC[22] TCC_CYCLE[22] TCC_EA_ATOMIC[22] TCC_EA_ATOMIC_LEVEL[22] TCC_ATOMIC[23] TCC_CYCLE[23] TCC_EA_ATOMIC[23] TCC_EA_ATOMIC_LEVEL[23] TCC_ATOMIC[24] TCC_CYCLE[24] TCC_EA_ATOMIC[24] TCC_EA_ATOMIC_LEVEL[24] TCC_ATOMIC[25] TCC_CYCLE[25] TCC_EA_ATOMIC[25] TCC_EA_ATOMIC_LEVEL[25] TCC_ATOMIC[26] TCC_CYCLE[26] TCC_EA_ATOMIC[26] TCC_EA_ATOMIC_LEVEL[26] TCC_ATOMIC[27] TCC_CYCLE[27] TCC_EA_ATOMIC[27] TCC_EA_ATOMIC_LEVEL[27] TCC_ATOMIC[28] TCC_CYCLE[28] TCC_EA_ATOMIC[28] TCC_EA_ATOMIC_LEVEL[28] TCC_ATOMIC[29] TCC_CYCLE[29] TCC_EA_ATOMIC[29] TCC_EA_ATOMIC_LEVEL[29] TCC_ATOMIC[30] TCC_CYCLE[30] TCC_EA_ATOMIC[30] TCC_EA_ATOMIC_LEVEL[30] TCC_ATOMIC[31] TCC_CYCLE[31] TCC_EA_ATOMIC[31] TCC_EA_ATOMIC_LEVEL[31]
+
+gpu:
+range:
+kernel:
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/perfmon/pmc_perf_12.txt b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/perfmon/pmc_perf_12.txt
new file mode 100644
index 0000000000..e0698dbf57
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/perfmon/pmc_perf_12.txt
@@ -0,0 +1,5 @@
+pmc:  TCC_EA_RDREQ[0] TCC_EA_RDREQ_32B[0] TCC_EA_RDREQ_DRAM_CREDIT_STALL[0] TCC_EA_RDREQ_GMI_CREDIT_STALL[0] TCC_EA_RDREQ[1] TCC_EA_RDREQ_32B[1] TCC_EA_RDREQ_DRAM_CREDIT_STALL[1] TCC_EA_RDREQ_GMI_CREDIT_STALL[1] TCC_EA_RDREQ[2] TCC_EA_RDREQ_32B[2] TCC_EA_RDREQ_DRAM_CREDIT_STALL[2] TCC_EA_RDREQ_GMI_CREDIT_STALL[2] TCC_EA_RDREQ[3] TCC_EA_RDREQ_32B[3] TCC_EA_RDREQ_DRAM_CREDIT_STALL[3] TCC_EA_RDREQ_GMI_CREDIT_STALL[3] TCC_EA_RDREQ[4] TCC_EA_RDREQ_32B[4] TCC_EA_RDREQ_DRAM_CREDIT_STALL[4] TCC_EA_RDREQ_GMI_CREDIT_STALL[4] TCC_EA_RDREQ[5] TCC_EA_RDREQ_32B[5] TCC_EA_RDREQ_DRAM_CREDIT_STALL[5] TCC_EA_RDREQ_GMI_CREDIT_STALL[5] TCC_EA_RDREQ[6] TCC_EA_RDREQ_32B[6] TCC_EA_RDREQ_DRAM_CREDIT_STALL[6] TCC_EA_RDREQ_GMI_CREDIT_STALL[6] TCC_EA_RDREQ[7] TCC_EA_RDREQ_32B[7] TCC_EA_RDREQ_DRAM_CREDIT_STALL[7] TCC_EA_RDREQ_GMI_CREDIT_STALL[7] TCC_EA_RDREQ[8] TCC_EA_RDREQ_32B[8] TCC_EA_RDREQ_DRAM_CREDIT_STALL[8] TCC_EA_RDREQ_GMI_CREDIT_STALL[8] TCC_EA_RDREQ[9] TCC_EA_RDREQ_32B[9] TCC_EA_RDREQ_DRAM_CREDIT_STALL[9] TCC_EA_RDREQ_GMI_CREDIT_STALL[9] TCC_EA_RDREQ[10] TCC_EA_RDREQ_32B[10] TCC_EA_RDREQ_DRAM_CREDIT_STALL[10] TCC_EA_RDREQ_GMI_CREDIT_STALL[10] TCC_EA_RDREQ[11] TCC_EA_RDREQ_32B[11] TCC_EA_RDREQ_DRAM_CREDIT_STALL[11] TCC_EA_RDREQ_GMI_CREDIT_STALL[11] TCC_EA_RDREQ[12] TCC_EA_RDREQ_32B[12] TCC_EA_RDREQ_DRAM_CREDIT_STALL[12] TCC_EA_RDREQ_GMI_CREDIT_STALL[12] TCC_EA_RDREQ[13] TCC_EA_RDREQ_32B[13] TCC_EA_RDREQ_DRAM_CREDIT_STALL[13] TCC_EA_RDREQ_GMI_CREDIT_STALL[13] TCC_EA_RDREQ[14] TCC_EA_RDREQ_32B[14] TCC_EA_RDREQ_DRAM_CREDIT_STALL[14] TCC_EA_RDREQ_GMI_CREDIT_STALL[14] TCC_EA_RDREQ[15] TCC_EA_RDREQ_32B[15] TCC_EA_RDREQ_DRAM_CREDIT_STALL[15] TCC_EA_RDREQ_GMI_CREDIT_STALL[15] TCC_EA_RDREQ[16] TCC_EA_RDREQ_32B[16] TCC_EA_RDREQ_DRAM_CREDIT_STALL[16] TCC_EA_RDREQ_GMI_CREDIT_STALL[16] TCC_EA_RDREQ[17] TCC_EA_RDREQ_32B[17] TCC_EA_RDREQ_DRAM_CREDIT_STALL[17] TCC_EA_RDREQ_GMI_CREDIT_STALL[17] TCC_EA_RDREQ[18] TCC_EA_RDREQ_32B[18] TCC_EA_RDREQ_DRAM_CREDIT_STALL[18] TCC_EA_RDREQ_GMI_CREDIT_STALL[18] TCC_EA_RDREQ[19] TCC_EA_RDREQ_32B[19] TCC_EA_RDREQ_DRAM_CREDIT_STALL[19] TCC_EA_RDREQ_GMI_CREDIT_STALL[19] TCC_EA_RDREQ[20] TCC_EA_RDREQ_32B[20] TCC_EA_RDREQ_DRAM_CREDIT_STALL[20] TCC_EA_RDREQ_GMI_CREDIT_STALL[20] TCC_EA_RDREQ[21] TCC_EA_RDREQ_32B[21] TCC_EA_RDREQ_DRAM_CREDIT_STALL[21] TCC_EA_RDREQ_GMI_CREDIT_STALL[21] TCC_EA_RDREQ[22] TCC_EA_RDREQ_32B[22] TCC_EA_RDREQ_DRAM_CREDIT_STALL[22] TCC_EA_RDREQ_GMI_CREDIT_STALL[22] TCC_EA_RDREQ[23] TCC_EA_RDREQ_32B[23] TCC_EA_RDREQ_DRAM_CREDIT_STALL[23] TCC_EA_RDREQ_GMI_CREDIT_STALL[23] TCC_EA_RDREQ[24] TCC_EA_RDREQ_32B[24] TCC_EA_RDREQ_DRAM_CREDIT_STALL[24] TCC_EA_RDREQ_GMI_CREDIT_STALL[24] TCC_EA_RDREQ[25] TCC_EA_RDREQ_32B[25] TCC_EA_RDREQ_DRAM_CREDIT_STALL[25] TCC_EA_RDREQ_GMI_CREDIT_STALL[25] TCC_EA_RDREQ[26] TCC_EA_RDREQ_32B[26] TCC_EA_RDREQ_DRAM_CREDIT_STALL[26] TCC_EA_RDREQ_GMI_CREDIT_STALL[26] TCC_EA_RDREQ[27] TCC_EA_RDREQ_32B[27] TCC_EA_RDREQ_DRAM_CREDIT_STALL[27] TCC_EA_RDREQ_GMI_CREDIT_STALL[27] TCC_EA_RDREQ[28] TCC_EA_RDREQ_32B[28] TCC_EA_RDREQ_DRAM_CREDIT_STALL[28] TCC_EA_RDREQ_GMI_CREDIT_STALL[28] TCC_EA_RDREQ[29] TCC_EA_RDREQ_32B[29] TCC_EA_RDREQ_DRAM_CREDIT_STALL[29] TCC_EA_RDREQ_GMI_CREDIT_STALL[29] TCC_EA_RDREQ[30] TCC_EA_RDREQ_32B[30] TCC_EA_RDREQ_DRAM_CREDIT_STALL[30] TCC_EA_RDREQ_GMI_CREDIT_STALL[30] TCC_EA_RDREQ[31] TCC_EA_RDREQ_32B[31] TCC_EA_RDREQ_DRAM_CREDIT_STALL[31] TCC_EA_RDREQ_GMI_CREDIT_STALL[31]
+
+gpu:
+range:
+kernel:
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/perfmon/pmc_perf_13.txt b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/perfmon/pmc_perf_13.txt
new file mode 100644
index 0000000000..77ad088669
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/perfmon/pmc_perf_13.txt
@@ -0,0 +1,5 @@
+pmc:  TCC_EA_RDREQ_IO_CREDIT_STALL[0] TCC_EA_RDREQ_LEVEL[0] TCC_EA_WRREQ[0] TCC_EA_WRREQ_64B[0] TCC_EA_RDREQ_IO_CREDIT_STALL[1] TCC_EA_RDREQ_LEVEL[1] TCC_EA_WRREQ[1] TCC_EA_WRREQ_64B[1] TCC_EA_RDREQ_IO_CREDIT_STALL[2] TCC_EA_RDREQ_LEVEL[2] TCC_EA_WRREQ[2] TCC_EA_WRREQ_64B[2] TCC_EA_RDREQ_IO_CREDIT_STALL[3] TCC_EA_RDREQ_LEVEL[3] TCC_EA_WRREQ[3] TCC_EA_WRREQ_64B[3] TCC_EA_RDREQ_IO_CREDIT_STALL[4] TCC_EA_RDREQ_LEVEL[4] TCC_EA_WRREQ[4] TCC_EA_WRREQ_64B[4] TCC_EA_RDREQ_IO_CREDIT_STALL[5] TCC_EA_RDREQ_LEVEL[5] TCC_EA_WRREQ[5] TCC_EA_WRREQ_64B[5] TCC_EA_RDREQ_IO_CREDIT_STALL[6] TCC_EA_RDREQ_LEVEL[6] TCC_EA_WRREQ[6] TCC_EA_WRREQ_64B[6] TCC_EA_RDREQ_IO_CREDIT_STALL[7] TCC_EA_RDREQ_LEVEL[7] TCC_EA_WRREQ[7] TCC_EA_WRREQ_64B[7] TCC_EA_RDREQ_IO_CREDIT_STALL[8] TCC_EA_RDREQ_LEVEL[8] TCC_EA_WRREQ[8] TCC_EA_WRREQ_64B[8] TCC_EA_RDREQ_IO_CREDIT_STALL[9] TCC_EA_RDREQ_LEVEL[9] TCC_EA_WRREQ[9] TCC_EA_WRREQ_64B[9] TCC_EA_RDREQ_IO_CREDIT_STALL[10] TCC_EA_RDREQ_LEVEL[10] TCC_EA_WRREQ[10] TCC_EA_WRREQ_64B[10] TCC_EA_RDREQ_IO_CREDIT_STALL[11] TCC_EA_RDREQ_LEVEL[11] TCC_EA_WRREQ[11] TCC_EA_WRREQ_64B[11] TCC_EA_RDREQ_IO_CREDIT_STALL[12] TCC_EA_RDREQ_LEVEL[12] TCC_EA_WRREQ[12] TCC_EA_WRREQ_64B[12] TCC_EA_RDREQ_IO_CREDIT_STALL[13] TCC_EA_RDREQ_LEVEL[13] TCC_EA_WRREQ[13] TCC_EA_WRREQ_64B[13] TCC_EA_RDREQ_IO_CREDIT_STALL[14] TCC_EA_RDREQ_LEVEL[14] TCC_EA_WRREQ[14] TCC_EA_WRREQ_64B[14] TCC_EA_RDREQ_IO_CREDIT_STALL[15] TCC_EA_RDREQ_LEVEL[15] TCC_EA_WRREQ[15] TCC_EA_WRREQ_64B[15] TCC_EA_RDREQ_IO_CREDIT_STALL[16] TCC_EA_RDREQ_LEVEL[16] TCC_EA_WRREQ[16] TCC_EA_WRREQ_64B[16] TCC_EA_RDREQ_IO_CREDIT_STALL[17] TCC_EA_RDREQ_LEVEL[17] TCC_EA_WRREQ[17] TCC_EA_WRREQ_64B[17] TCC_EA_RDREQ_IO_CREDIT_STALL[18] TCC_EA_RDREQ_LEVEL[18] TCC_EA_WRREQ[18] TCC_EA_WRREQ_64B[18] TCC_EA_RDREQ_IO_CREDIT_STALL[19] TCC_EA_RDREQ_LEVEL[19] TCC_EA_WRREQ[19] TCC_EA_WRREQ_64B[19] TCC_EA_RDREQ_IO_CREDIT_STALL[20] TCC_EA_RDREQ_LEVEL[20] TCC_EA_WRREQ[20] TCC_EA_WRREQ_64B[20] TCC_EA_RDREQ_IO_CREDIT_STALL[21] TCC_EA_RDREQ_LEVEL[21] TCC_EA_WRREQ[21] TCC_EA_WRREQ_64B[21] TCC_EA_RDREQ_IO_CREDIT_STALL[22] TCC_EA_RDREQ_LEVEL[22] TCC_EA_WRREQ[22] TCC_EA_WRREQ_64B[22] TCC_EA_RDREQ_IO_CREDIT_STALL[23] TCC_EA_RDREQ_LEVEL[23] TCC_EA_WRREQ[23] TCC_EA_WRREQ_64B[23] TCC_EA_RDREQ_IO_CREDIT_STALL[24] TCC_EA_RDREQ_LEVEL[24] TCC_EA_WRREQ[24] TCC_EA_WRREQ_64B[24] TCC_EA_RDREQ_IO_CREDIT_STALL[25] TCC_EA_RDREQ_LEVEL[25] TCC_EA_WRREQ[25] TCC_EA_WRREQ_64B[25] TCC_EA_RDREQ_IO_CREDIT_STALL[26] TCC_EA_RDREQ_LEVEL[26] TCC_EA_WRREQ[26] TCC_EA_WRREQ_64B[26] TCC_EA_RDREQ_IO_CREDIT_STALL[27] TCC_EA_RDREQ_LEVEL[27] TCC_EA_WRREQ[27] TCC_EA_WRREQ_64B[27] TCC_EA_RDREQ_IO_CREDIT_STALL[28] TCC_EA_RDREQ_LEVEL[28] TCC_EA_WRREQ[28] TCC_EA_WRREQ_64B[28] TCC_EA_RDREQ_IO_CREDIT_STALL[29] TCC_EA_RDREQ_LEVEL[29] TCC_EA_WRREQ[29] TCC_EA_WRREQ_64B[29] TCC_EA_RDREQ_IO_CREDIT_STALL[30] TCC_EA_RDREQ_LEVEL[30] TCC_EA_WRREQ[30] TCC_EA_WRREQ_64B[30] TCC_EA_RDREQ_IO_CREDIT_STALL[31] TCC_EA_RDREQ_LEVEL[31] TCC_EA_WRREQ[31] TCC_EA_WRREQ_64B[31]
+
+gpu:
+range:
+kernel:
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/perfmon/pmc_perf_14.txt b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/perfmon/pmc_perf_14.txt
new file mode 100644
index 0000000000..d0628bb948
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/perfmon/pmc_perf_14.txt
@@ -0,0 +1,5 @@
+pmc:  TCC_EA_WRREQ_DRAM_CREDIT_STALL[0] TCC_EA_WRREQ_GMI_CREDIT_STALL[0] TCC_EA_WRREQ_IO_CREDIT_STALL[0] TCC_EA_WRREQ_LEVEL[0] TCC_EA_WRREQ_DRAM_CREDIT_STALL[1] TCC_EA_WRREQ_GMI_CREDIT_STALL[1] TCC_EA_WRREQ_IO_CREDIT_STALL[1] TCC_EA_WRREQ_LEVEL[1] TCC_EA_WRREQ_DRAM_CREDIT_STALL[2] TCC_EA_WRREQ_GMI_CREDIT_STALL[2] TCC_EA_WRREQ_IO_CREDIT_STALL[2] TCC_EA_WRREQ_LEVEL[2] TCC_EA_WRREQ_DRAM_CREDIT_STALL[3] TCC_EA_WRREQ_GMI_CREDIT_STALL[3] TCC_EA_WRREQ_IO_CREDIT_STALL[3] TCC_EA_WRREQ_LEVEL[3] TCC_EA_WRREQ_DRAM_CREDIT_STALL[4] TCC_EA_WRREQ_GMI_CREDIT_STALL[4] TCC_EA_WRREQ_IO_CREDIT_STALL[4] TCC_EA_WRREQ_LEVEL[4] TCC_EA_WRREQ_DRAM_CREDIT_STALL[5] TCC_EA_WRREQ_GMI_CREDIT_STALL[5] TCC_EA_WRREQ_IO_CREDIT_STALL[5] TCC_EA_WRREQ_LEVEL[5] TCC_EA_WRREQ_DRAM_CREDIT_STALL[6] TCC_EA_WRREQ_GMI_CREDIT_STALL[6] TCC_EA_WRREQ_IO_CREDIT_STALL[6] TCC_EA_WRREQ_LEVEL[6] TCC_EA_WRREQ_DRAM_CREDIT_STALL[7] TCC_EA_WRREQ_GMI_CREDIT_STALL[7] TCC_EA_WRREQ_IO_CREDIT_STALL[7] TCC_EA_WRREQ_LEVEL[7] TCC_EA_WRREQ_DRAM_CREDIT_STALL[8] TCC_EA_WRREQ_GMI_CREDIT_STALL[8] TCC_EA_WRREQ_IO_CREDIT_STALL[8] TCC_EA_WRREQ_LEVEL[8] TCC_EA_WRREQ_DRAM_CREDIT_STALL[9] TCC_EA_WRREQ_GMI_CREDIT_STALL[9] TCC_EA_WRREQ_IO_CREDIT_STALL[9] TCC_EA_WRREQ_LEVEL[9] TCC_EA_WRREQ_DRAM_CREDIT_STALL[10] TCC_EA_WRREQ_GMI_CREDIT_STALL[10] TCC_EA_WRREQ_IO_CREDIT_STALL[10] TCC_EA_WRREQ_LEVEL[10] TCC_EA_WRREQ_DRAM_CREDIT_STALL[11] TCC_EA_WRREQ_GMI_CREDIT_STALL[11] TCC_EA_WRREQ_IO_CREDIT_STALL[11] TCC_EA_WRREQ_LEVEL[11] TCC_EA_WRREQ_DRAM_CREDIT_STALL[12] TCC_EA_WRREQ_GMI_CREDIT_STALL[12] TCC_EA_WRREQ_IO_CREDIT_STALL[12] TCC_EA_WRREQ_LEVEL[12] TCC_EA_WRREQ_DRAM_CREDIT_STALL[13] TCC_EA_WRREQ_GMI_CREDIT_STALL[13] TCC_EA_WRREQ_IO_CREDIT_STALL[13] TCC_EA_WRREQ_LEVEL[13] TCC_EA_WRREQ_DRAM_CREDIT_STALL[14] TCC_EA_WRREQ_GMI_CREDIT_STALL[14] TCC_EA_WRREQ_IO_CREDIT_STALL[14] TCC_EA_WRREQ_LEVEL[14] TCC_EA_WRREQ_DRAM_CREDIT_STALL[15] TCC_EA_WRREQ_GMI_CREDIT_STALL[15] TCC_EA_WRREQ_IO_CREDIT_STALL[15] TCC_EA_WRREQ_LEVEL[15] TCC_EA_WRREQ_DRAM_CREDIT_STALL[16] TCC_EA_WRREQ_GMI_CREDIT_STALL[16] TCC_EA_WRREQ_IO_CREDIT_STALL[16] TCC_EA_WRREQ_LEVEL[16] TCC_EA_WRREQ_DRAM_CREDIT_STALL[17] TCC_EA_WRREQ_GMI_CREDIT_STALL[17] TCC_EA_WRREQ_IO_CREDIT_STALL[17] TCC_EA_WRREQ_LEVEL[17] TCC_EA_WRREQ_DRAM_CREDIT_STALL[18] TCC_EA_WRREQ_GMI_CREDIT_STALL[18] TCC_EA_WRREQ_IO_CREDIT_STALL[18] TCC_EA_WRREQ_LEVEL[18] TCC_EA_WRREQ_DRAM_CREDIT_STALL[19] TCC_EA_WRREQ_GMI_CREDIT_STALL[19] TCC_EA_WRREQ_IO_CREDIT_STALL[19] TCC_EA_WRREQ_LEVEL[19] TCC_EA_WRREQ_DRAM_CREDIT_STALL[20] TCC_EA_WRREQ_GMI_CREDIT_STALL[20] TCC_EA_WRREQ_IO_CREDIT_STALL[20] TCC_EA_WRREQ_LEVEL[20] TCC_EA_WRREQ_DRAM_CREDIT_STALL[21] TCC_EA_WRREQ_GMI_CREDIT_STALL[21] TCC_EA_WRREQ_IO_CREDIT_STALL[21] TCC_EA_WRREQ_LEVEL[21] TCC_EA_WRREQ_DRAM_CREDIT_STALL[22] TCC_EA_WRREQ_GMI_CREDIT_STALL[22] TCC_EA_WRREQ_IO_CREDIT_STALL[22] TCC_EA_WRREQ_LEVEL[22] TCC_EA_WRREQ_DRAM_CREDIT_STALL[23] TCC_EA_WRREQ_GMI_CREDIT_STALL[23] TCC_EA_WRREQ_IO_CREDIT_STALL[23] TCC_EA_WRREQ_LEVEL[23] TCC_EA_WRREQ_DRAM_CREDIT_STALL[24] TCC_EA_WRREQ_GMI_CREDIT_STALL[24] TCC_EA_WRREQ_IO_CREDIT_STALL[24] TCC_EA_WRREQ_LEVEL[24] TCC_EA_WRREQ_DRAM_CREDIT_STALL[25] TCC_EA_WRREQ_GMI_CREDIT_STALL[25] TCC_EA_WRREQ_IO_CREDIT_STALL[25] TCC_EA_WRREQ_LEVEL[25] TCC_EA_WRREQ_DRAM_CREDIT_STALL[26] TCC_EA_WRREQ_GMI_CREDIT_STALL[26] TCC_EA_WRREQ_IO_CREDIT_STALL[26] TCC_EA_WRREQ_LEVEL[26] TCC_EA_WRREQ_DRAM_CREDIT_STALL[27] TCC_EA_WRREQ_GMI_CREDIT_STALL[27] TCC_EA_WRREQ_IO_CREDIT_STALL[27] TCC_EA_WRREQ_LEVEL[27] TCC_EA_WRREQ_DRAM_CREDIT_STALL[28] TCC_EA_WRREQ_GMI_CREDIT_STALL[28] TCC_EA_WRREQ_IO_CREDIT_STALL[28] TCC_EA_WRREQ_LEVEL[28] TCC_EA_WRREQ_DRAM_CREDIT_STALL[29] TCC_EA_WRREQ_GMI_CREDIT_STALL[29] TCC_EA_WRREQ_IO_CREDIT_STALL[29] TCC_EA_WRREQ_LEVEL[29] TCC_EA_WRREQ_DRAM_CREDIT_STALL[30] TCC_EA_WRREQ_GMI_CREDIT_STALL[30] TCC_EA_WRREQ_IO_CREDIT_STALL[30] TCC_EA_WRREQ_LEVEL[30] TCC_EA_WRREQ_DRAM_CREDIT_STALL[31] TCC_EA_WRREQ_GMI_CREDIT_STALL[31] TCC_EA_WRREQ_IO_CREDIT_STALL[31] TCC_EA_WRREQ_LEVEL[31]
+
+gpu:
+range:
+kernel:
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/perfmon/pmc_perf_15.txt b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/perfmon/pmc_perf_15.txt
new file mode 100644
index 0000000000..343869c5f1
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/perfmon/pmc_perf_15.txt
@@ -0,0 +1,5 @@
+pmc:  TCC_HIT[0] TCC_MISS[0] TCC_READ[0] TCC_REQ[0] TCC_HIT[1] TCC_MISS[1] TCC_READ[1] TCC_REQ[1] TCC_HIT[2] TCC_MISS[2] TCC_READ[2] TCC_REQ[2] TCC_HIT[3] TCC_MISS[3] TCC_READ[3] TCC_REQ[3] TCC_HIT[4] TCC_MISS[4] TCC_READ[4] TCC_REQ[4] TCC_HIT[5] TCC_MISS[5] TCC_READ[5] TCC_REQ[5] TCC_HIT[6] TCC_MISS[6] TCC_READ[6] TCC_REQ[6] TCC_HIT[7] TCC_MISS[7] TCC_READ[7] TCC_REQ[7] TCC_HIT[8] TCC_MISS[8] TCC_READ[8] TCC_REQ[8] TCC_HIT[9] TCC_MISS[9] TCC_READ[9] TCC_REQ[9] TCC_HIT[10] TCC_MISS[10] TCC_READ[10] TCC_REQ[10] TCC_HIT[11] TCC_MISS[11] TCC_READ[11] TCC_REQ[11] TCC_HIT[12] TCC_MISS[12] TCC_READ[12] TCC_REQ[12] TCC_HIT[13] TCC_MISS[13] TCC_READ[13] TCC_REQ[13] TCC_HIT[14] TCC_MISS[14] TCC_READ[14] TCC_REQ[14] TCC_HIT[15] TCC_MISS[15] TCC_READ[15] TCC_REQ[15] TCC_HIT[16] TCC_MISS[16] TCC_READ[16] TCC_REQ[16] TCC_HIT[17] TCC_MISS[17] TCC_READ[17] TCC_REQ[17] TCC_HIT[18] TCC_MISS[18] TCC_READ[18] TCC_REQ[18] TCC_HIT[19] TCC_MISS[19] TCC_READ[19] TCC_REQ[19] TCC_HIT[20] TCC_MISS[20] TCC_READ[20] TCC_REQ[20] TCC_HIT[21] TCC_MISS[21] TCC_READ[21] TCC_REQ[21] TCC_HIT[22] TCC_MISS[22] TCC_READ[22] TCC_REQ[22] TCC_HIT[23] TCC_MISS[23] TCC_READ[23] TCC_REQ[23] TCC_HIT[24] TCC_MISS[24] TCC_READ[24] TCC_REQ[24] TCC_HIT[25] TCC_MISS[25] TCC_READ[25] TCC_REQ[25] TCC_HIT[26] TCC_MISS[26] TCC_READ[26] TCC_REQ[26] TCC_HIT[27] TCC_MISS[27] TCC_READ[27] TCC_REQ[27] TCC_HIT[28] TCC_MISS[28] TCC_READ[28] TCC_REQ[28] TCC_HIT[29] TCC_MISS[29] TCC_READ[29] TCC_REQ[29] TCC_HIT[30] TCC_MISS[30] TCC_READ[30] TCC_REQ[30] TCC_HIT[31] TCC_MISS[31] TCC_READ[31] TCC_REQ[31]
+
+gpu:
+range:
+kernel:
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/perfmon/pmc_perf_16.txt b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/perfmon/pmc_perf_16.txt
new file mode 100644
index 0000000000..a74cefd281
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/perfmon/pmc_perf_16.txt
@@ -0,0 +1,5 @@
+pmc:  TCC_RW_REQ[0] TCC_TOO_MANY_EA_WRREQS_STALL[0] TCC_WRITE[0] TCC_RW_REQ[1] TCC_TOO_MANY_EA_WRREQS_STALL[1] TCC_WRITE[1] TCC_RW_REQ[2] TCC_TOO_MANY_EA_WRREQS_STALL[2] TCC_WRITE[2] TCC_RW_REQ[3] TCC_TOO_MANY_EA_WRREQS_STALL[3] TCC_WRITE[3] TCC_RW_REQ[4] TCC_TOO_MANY_EA_WRREQS_STALL[4] TCC_WRITE[4] TCC_RW_REQ[5] TCC_TOO_MANY_EA_WRREQS_STALL[5] TCC_WRITE[5] TCC_RW_REQ[6] TCC_TOO_MANY_EA_WRREQS_STALL[6] TCC_WRITE[6] TCC_RW_REQ[7] TCC_TOO_MANY_EA_WRREQS_STALL[7] TCC_WRITE[7] TCC_RW_REQ[8] TCC_TOO_MANY_EA_WRREQS_STALL[8] TCC_WRITE[8] TCC_RW_REQ[9] TCC_TOO_MANY_EA_WRREQS_STALL[9] TCC_WRITE[9] TCC_RW_REQ[10] TCC_TOO_MANY_EA_WRREQS_STALL[10] TCC_WRITE[10] TCC_RW_REQ[11] TCC_TOO_MANY_EA_WRREQS_STALL[11] TCC_WRITE[11] TCC_RW_REQ[12] TCC_TOO_MANY_EA_WRREQS_STALL[12] TCC_WRITE[12] TCC_RW_REQ[13] TCC_TOO_MANY_EA_WRREQS_STALL[13] TCC_WRITE[13] TCC_RW_REQ[14] TCC_TOO_MANY_EA_WRREQS_STALL[14] TCC_WRITE[14] TCC_RW_REQ[15] TCC_TOO_MANY_EA_WRREQS_STALL[15] TCC_WRITE[15] TCC_RW_REQ[16] TCC_TOO_MANY_EA_WRREQS_STALL[16] TCC_WRITE[16] TCC_RW_REQ[17] TCC_TOO_MANY_EA_WRREQS_STALL[17] TCC_WRITE[17] TCC_RW_REQ[18] TCC_TOO_MANY_EA_WRREQS_STALL[18] TCC_WRITE[18] TCC_RW_REQ[19] TCC_TOO_MANY_EA_WRREQS_STALL[19] TCC_WRITE[19] TCC_RW_REQ[20] TCC_TOO_MANY_EA_WRREQS_STALL[20] TCC_WRITE[20] TCC_RW_REQ[21] TCC_TOO_MANY_EA_WRREQS_STALL[21] TCC_WRITE[21] TCC_RW_REQ[22] TCC_TOO_MANY_EA_WRREQS_STALL[22] TCC_WRITE[22] TCC_RW_REQ[23] TCC_TOO_MANY_EA_WRREQS_STALL[23] TCC_WRITE[23] TCC_RW_REQ[24] TCC_TOO_MANY_EA_WRREQS_STALL[24] TCC_WRITE[24] TCC_RW_REQ[25] TCC_TOO_MANY_EA_WRREQS_STALL[25] TCC_WRITE[25] TCC_RW_REQ[26] TCC_TOO_MANY_EA_WRREQS_STALL[26] TCC_WRITE[26] TCC_RW_REQ[27] TCC_TOO_MANY_EA_WRREQS_STALL[27] TCC_WRITE[27] TCC_RW_REQ[28] TCC_TOO_MANY_EA_WRREQS_STALL[28] TCC_WRITE[28] TCC_RW_REQ[29] TCC_TOO_MANY_EA_WRREQS_STALL[29] TCC_WRITE[29] TCC_RW_REQ[30] TCC_TOO_MANY_EA_WRREQS_STALL[30] TCC_WRITE[30] TCC_RW_REQ[31] TCC_TOO_MANY_EA_WRREQS_STALL[31] TCC_WRITE[31]
+
+gpu:
+range:
+kernel:
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/perfmon/pmc_perf_2.txt b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/perfmon/pmc_perf_2.txt
new file mode 100644
index 0000000000..e0bd125c3d
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/perfmon/pmc_perf_2.txt
@@ -0,0 +1,5 @@
+pmc:  SQ_INSTS_SENDMSG SQ_INSTS SQ_WAIT_ANY SQ_WAIT_INST_ANY SQ_ACTIVE_INST_ANY SQ_INSTS_VALU SQ_ACTIVE_INST_VMEM SQ_ACTIVE_INST_LDS TCP_VOLATILE_sum TCP_TOTAL_ACCESSES_sum TCP_TOTAL_READ_sum TCP_TOTAL_WRITE_sum TA_BUFFER_ATOMIC_WAVEFRONTS_sum TA_BUFFER_TOTAL_CYCLES_sum TD_ATOMIC_WAVEFRONT_sum TD_STORE_WAVEFRONT_sum SPI_RA_REQ_NO_ALLOC SPI_RA_REQ_NO_ALLOC_CSN CPC_CPC_STAT_STALL CPC_UTCL1_STALL_ON_TRANSLATION CPF_CPF_STAT_IDLE CPF_CPF_TCIU_IDLE TCC_REQ_sum TCC_STREAMING_REQ_sum TCC_HIT_sum TCC_MISS_sum
+
+gpu:
+range:
+kernel:
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/perfmon/pmc_perf_3.txt b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/perfmon/pmc_perf_3.txt
new file mode 100644
index 0000000000..5119c44312
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/perfmon/pmc_perf_3.txt
@@ -0,0 +1,5 @@
+pmc:  SQ_ACTIVE_INST_VALU SQ_ACTIVE_INST_SCA SQ_ACTIVE_INST_EXP_GDS SQ_ACTIVE_INST_MISC SQ_ACTIVE_INST_FLAT SQ_INST_CYCLES_VMEM_WR SQ_INST_CYCLES_VMEM_RD SQ_INST_CYCLES_SMEM TCP_TOTAL_ATOMIC_WITH_RET_sum TCP_TOTAL_ATOMIC_WITHOUT_RET_sum TCP_TOTAL_WRITEBACK_INVALIDATES_sum TCP_TOTAL_CACHE_ACCESSES_sum TA_BUFFER_COALESCED_READ_CYCLES_sum TA_BUFFER_COALESCED_WRITE_CYCLES_sum SPI_RA_RES_STALL_CSN SPI_RA_TMP_STALL_CSN CPC_CPC_UTCL2IU_BUSY CPC_CPC_UTCL2IU_IDLE CPF_CMP_UTCL1_STALL_ON_TRANSLATION TCC_READ_sum TCC_WRITE_sum TCC_ATOMIC_sum TCC_WRITEBACK_sum
+
+gpu:
+range:
+kernel:
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/perfmon/pmc_perf_4.txt b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/perfmon/pmc_perf_4.txt
new file mode 100644
index 0000000000..968f6afb61
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/perfmon/pmc_perf_4.txt
@@ -0,0 +1,5 @@
+pmc:  SQ_INST_CYCLES_SALU SQ_THREAD_CYCLES_VALU SQ_IFETCH SQ_LDS_BANK_CONFLICT SQ_LDS_ADDR_CONFLICT SQ_LDS_UNALIGNED_STALL SQ_WAVES_EQ_64 SQ_WAVES_LT_64 TCP_UTCL1_TRANSLATION_MISS_sum TCP_UTCL1_TRANSLATION_HIT_sum TCP_UTCL1_PERMISSION_MISS_sum TCP_UTCL1_REQUEST_sum TA_ADDR_STALLED_BY_TC_CYCLES_sum TA_TOTAL_WAVEFRONTS_sum SPI_RA_WAVE_SIMD_FULL_CSN SPI_RA_VGPR_SIMD_FULL_CSN CPC_CPC_UTCL2IU_STALL CPC_ME1_BUSY_FOR_PACKET_DECODE TCC_EA_WRREQ_sum TCC_EA_WRREQ_64B_sum TCC_EA_WR_UNCACHED_32B_sum TCC_EA_WRREQ_STALL_sum
+
+gpu:
+range:
+kernel:
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/perfmon/pmc_perf_5.txt b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/perfmon/pmc_perf_5.txt
new file mode 100644
index 0000000000..f7db083ea0
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/perfmon/pmc_perf_5.txt
@@ -0,0 +1,5 @@
+pmc:  SQ_WAVES_LT_48 SQ_WAVES_LT_32 SQ_WAVES_LT_16 SQ_ITEMS SQ_LDS_MEM_VIOLATIONS SQ_LDS_ATOMIC_RETURN SQ_LDS_IDX_ACTIVE SQ_WAVES_RESTORED TCP_TCP_LATENCY_sum TCP_TCC_READ_REQ_LATENCY_sum TCP_TCC_WRITE_REQ_LATENCY_sum TCP_TCC_READ_REQ_sum TA_ADDR_STALLED_BY_TD_CYCLES_sum TA_DATA_STALLED_BY_TC_CYCLES_sum SPI_RA_SGPR_SIMD_FULL_CSN SPI_RA_LDS_CU_FULL_CSN CPC_ME1_DC0_SPI_BUSY TCC_EA_WRREQ_IO_CREDIT_STALL_sum TCC_EA_WRREQ_GMI_CREDIT_STALL_sum TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum TCC_TOO_MANY_EA_WRREQS_STALL_sum
+
+gpu:
+range:
+kernel:
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/perfmon/pmc_perf_6.txt b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/perfmon/pmc_perf_6.txt
new file mode 100644
index 0000000000..954e2c8a08
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/perfmon/pmc_perf_6.txt
@@ -0,0 +1,5 @@
+pmc:  SQ_WAVES_SAVED SQ_INSTS_SMEM_NORM SQC_TC_INST_REQ SQC_TC_DATA_READ_REQ SQC_TC_DATA_WRITE_REQ SQC_TC_DATA_ATOMIC_REQ SQC_TC_STALL SQC_TC_REQ TCP_TCC_WRITE_REQ_sum TCP_TCC_ATOMIC_WITH_RET_REQ_sum TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum TCP_TCC_NC_READ_REQ_sum TA_FLAT_WAVEFRONTS_sum TA_FLAT_READ_WAVEFRONTS_sum SPI_RA_BAR_CU_FULL_CSN SPI_RA_TGLIM_CU_FULL_CSN TCC_EA_ATOMIC_sum TCC_EA_RDREQ_sum TCC_EA_RDREQ_32B_sum TCC_EA_RD_UNCACHED_32B_sum
+
+gpu:
+range:
+kernel:
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/perfmon/pmc_perf_7.txt b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/perfmon/pmc_perf_7.txt
new file mode 100644
index 0000000000..ee1086ee6f
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/perfmon/pmc_perf_7.txt
@@ -0,0 +1,5 @@
+pmc:  SQC_DCACHE_REQ_READ_16 SQC_ICACHE_REQ SQC_ICACHE_HITS SQC_ICACHE_MISSES SQC_ICACHE_MISSES_DUPLICATE SQC_DCACHE_INPUT_VALID_READYB SQC_DCACHE_ATOMIC SQC_DCACHE_REQ_READ_8 TCP_TCC_NC_WRITE_REQ_sum TCP_TCC_NC_ATOMIC_REQ_sum TCP_TCC_UC_READ_REQ_sum TCP_TCC_UC_WRITE_REQ_sum TA_FLAT_WRITE_WAVEFRONTS_sum TA_FLAT_ATOMIC_WAVEFRONTS_sum SPI_RA_WVLIM_STALL_CSN SPI_SWC_CSC_WR TCC_EA_RDREQ_IO_CREDIT_STALL_sum TCC_EA_RDREQ_GMI_CREDIT_STALL_sum TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum TCC_TAG_STALL_sum
+
+gpu:
+range:
+kernel:
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/perfmon/pmc_perf_8.txt b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/perfmon/pmc_perf_8.txt
new file mode 100644
index 0000000000..db56f1cd33
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/perfmon/pmc_perf_8.txt
@@ -0,0 +1,5 @@
+pmc:  SQC_DCACHE_REQ SQC_DCACHE_HITS SQC_DCACHE_MISSES SQC_DCACHE_MISSES_DUPLICATE SQC_DCACHE_REQ_READ_1 SQC_DCACHE_REQ_READ_2 SQC_DCACHE_REQ_READ_4 TCP_TCC_UC_ATOMIC_REQ_sum TCP_TCC_CC_READ_REQ_sum TCP_TCC_CC_WRITE_REQ_sum TCP_TCC_CC_ATOMIC_REQ_sum SPI_VWC_CSC_WR SPI_RA_BULKY_CU_FULL_CSN TCC_NORMAL_WRITEBACK_sum TCC_ALL_TC_OP_WB_WRITEBACK_sum TCC_NORMAL_EVICT_sum TCC_ALL_TC_OP_INV_EVICT_sum
+
+gpu:
+range:
+kernel:
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/perfmon/pmc_perf_9.txt b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/perfmon/pmc_perf_9.txt
new file mode 100644
index 0000000000..353ccaef82
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/perfmon/pmc_perf_9.txt
@@ -0,0 +1,5 @@
+pmc:  TCP_TCC_RW_READ_REQ_sum TCP_TCC_RW_WRITE_REQ_sum TCP_TCC_RW_ATOMIC_REQ_sum TCP_PENDING_STALL_CYCLES_sum TCC_EA_RDREQ_DRAM_sum TCC_EA_WRREQ_DRAM_sum TCC_EA_RDREQ_LEVEL_sum TCC_EA_WRREQ_LEVEL_sum
+
+gpu:
+range:
+kernel:
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/perfmon/timestamps.txt b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/perfmon/timestamps.txt
new file mode 100644
index 0000000000..676cca1b80
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/perfmon/timestamps.txt
@@ -0,0 +1,5 @@
+pmc:
+
+gpu:
+range:
+kernel:
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/pmc_dispatch_info.csv
new file mode 100644
index 0000000000..e90d72a8cf
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/pmc_dispatch_info.csv
@@ -0,0 +1,2 @@
+Dispatch_ID,Kernel_Name,GPU_ID
+0,"vecCopy(double*, double*, double*, int, int) ",2
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/pmc_perf.csv
new file mode 100644
index 0000000000..a53d80c878
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/pmc_perf.csv
@@ -0,0 +1,2 @@
+Dispatch_ID,Kernel_Name,GPU_ID,grd,Workgroup_Size,LDS_Per_Workgroup,scr,arch_vgpr,accum_vgpr,SGPR,wave_size,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,TA_BUFFER_TOTAL_CYCLES_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,wave_size_1,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],wave_size_2,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,wave_size_3,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],wave_size_4,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,wave_size_5,TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],wave_size_6,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_BUFFER_WAVEFRONTS_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,wave_size_7,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,wave_size_8,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,wave_size_9,TCC_EA_ATOMIC_LEVEL_sum,wave_size_10,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,wave_size_11,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_BUFFER_READ_WAVEFRONTS_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,wave_size_12,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,wave_size_13,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],wave_size_14,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],wave_size_15,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,wave_size_16,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],Start_Timestamp,End_Timestamp
+0,"vecCopy(double*, double*, double*, int, int) ",2,1046016,256,0,0,8,8,16,64,16344,392228,23443110,2018557,359542,163424,0,0,2091776.0,2091776.0,1045888.0,1045888.0,0.0,0.0,0.0,16342.0,14630,30974,9451,588,0,47061,261880.0,0.0,188.0,261692.0,64,0,3474879,4088,4088,0,4534699,4084,4084,0,3793563,4088,4088,0,3425718,4084,4084,0,3253146,4088,4088,0,3910232,4084,4084,0,3053230,4084,4084,0,3711457,4084,4084,0,3362919,4088,4088,0,3164445,4084,4084,0,4516092,4084,4084,0,3402722,4084,4084,0,3380518,4088,4088,0,5150141,4084,4084,0,3536125,4087,4086,0,3662403,4084,4084,0,3410502,4088,4088,0,3233234,4084,4084,0,4012039,4088,4088,0,3806690,4084,4084,0,3266843,4088,4088,0,4114160,4084,4084,0,3773210,4084,4084,0,4001481,4084,4084,0,3625676,4088,4088,0,3952599,4084,4084,0,3104744,4084,4084,0,4602397,4084,4084,0,3620205,4088,4088,0,4505408,4084,4084,0,3264580,4088,4088,0,3821332,4084,4084,64,0,65374,64380,48,1330,201007,0,0,0.0,0.0,0.0,0.0,16342.0,0.0,0,81720,0.0,0.0,46369.0,112735.0,64,4084,0,3830,0,4088,0,484,0,4084,0,583,0,4088,0,904,0,4084,0,262,0,4084,0,515,0,4084,0,1234,0,4088,0,1549,0,4084,0,1637,0,4084,0,728,0,4085,0,1306,0,4088,0,1662,0,4084,0,1111,0,4088,0,2576,0,4084,0,1074,0,4088,0,240,0,4084,0,1957,0,4087,0,2021,0,4324,0,2429,0,4088,0,547,0,4084,0,580,0,4132,0,4119,0,4085,0,1966,0,4088,0,1661,0,4084,0,65,0,4132,0,1785,0,4084,0,1208,0,4088,0,707,0,4084,0,0,0,4088,0,2490,0,4087,0,548,0,4088,0,1872,0,64,179766,114404,0,32688,32684,16342,16342,65372,0.0,0.0,120.0,522938.0,0.0,0.0,0,0,1815,47384,0,131313.0,130735.0,0.0,130767.0,64,8172,0,4088,8172,0,4084,8172,0,4088,8172,0,4084,8172,0,4088,8168,0,4084,8168,0,4084,8172,0,4084,8172,0,4088,8168,0,4084,8168,0,4084,8172,0,4084,8172,0,4088,8172,0,4084,8171,0,4087,8172,0,4084,8172,0,4088,8171,0,4084,8172,0,4088,8172,0,4084,8172,0,4088,8168,0,4084,8168,0,4084,8172,0,4084,8172,0,4088,8168,0,4084,8168,0,4084,8172,0,4084,8172,0,4088,8172,0,4084,8172,0,4088,8316,0,4084,64,394240,243736,3563750,16344,25120901,16342,16342,32684,49279,49279,4008097.0,3095742.0,5118.0,905741.0,2194719.0,0.0,3086745.0,2777815.0,392847,253666,49279,0,49279,0,1576928.0,984381.0,0.0,0.0,64,130735.0,130735.0,0.0,2470076.0,131100.0,130735.0,128055860.0,59601515.0,64,0,0,0,1046016,0,0,0,0,60929458.0,160131054.0,78079506.0,130735.0,0.0,602477.0,0,0,26715,0.0,0.0,140088.0,0.0,64,0.0,64,0,130744,144,48,0,0,0,192,130735.0,0.0,0.0,0.0,32684.0,16342.0,0,0,0.0,131062.0,0.0,646.0,64,49032,0,65372,32684,0,0,0,16344,31572,0.0,0.0,0.0,32684.0,0.0,0.0,0.0,32684.0,4086,16344,512,47418,1751,0,48.0,385.0,0.0,261614.0,64,65372,63884,48,1440,32688,32684,0,0.0,0.0,0.0,0.0,16344,0,86872.0,43863.0,130437.0,0.0,64,0,8459,4371,8459,0,8172,4088,8172,0,8172,4084,8172,0,8172,4088,8172,0,8172,4084,8172,0,8168,4084,8168,0,8168,4084,8168,0,8172,4088,8172,0,8173,4085,8173,0,8168,4084,8168,0,8168,4084,8168,47,8222,4185,8269,0,8172,4084,8172,0,8172,4088,8172,0,8171,4084,8171,0,8172,4088,8172,0,8172,4084,8172,0,8171,4087,8171,0,8172,4084,8172,0,8172,4088,8172,0,8172,4084,8172,0,8168,4084,8168,0,8168,4084,8168,0,8172,4088,8172,0,8172,4084,8172,0,8216,4132,8216,0,8168,4084,8168,0,8172,4088,8172,0,8172,4084,8172,0,8172,4088,8172,0,8172,4084,8172,141,8175,4232,8316,64,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,64,49032,11504916,65374,0,0,0,16344,0,960.0,512577.0,0.0,522938.0,890106.0,32684.0,0,0,0,18371,130735.0,130734.0,0.0,111945.0,64,1543,0,0,1775710,3049,0,0,2012359,2234,0,0,1923221,1897,0,0,1776784,804,0,0,1695337,1099,0,0,1592425,573,0,0,1609050,1265,0,0,1749524,2139,0,0,1910507,2144,0,0,1958065,1555,0,0,1822994,1053,0,0,1638701,4160,0,0,1973109,722,0,0,1767281,1416,0,0,1839198,9128,0,0,2424807,3626,0,0,1954616,1866,0,0,1825681,1068,0,0,1723385,1200,0,0,1755096,949,0,0,1683680,1318,0,0,1776912,2306,0,0,1854211,1169,0,0,1889251,1752,0,0,1708621,635,0,0,1622777,5166,0,0,2191709,3408,0,0,1978738,1896,0,0,1845524,1786,0,0,1747018,1787,0,0,1822316,1660,0,0,1784217,170459569892517.0,170459569917477.0
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/pmc_perf_0.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/pmc_perf_0.csv
new file mode 100644
index 0000000000..5171f7d1d5
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/pmc_perf_0.csv
@@ -0,0 +1,2 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,arch_vgpr,accum_vgpr,SGPR,wave_size,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_BUFFER_WAVEFRONTS_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int) ",2,0,0,184202,184202,1046016,256,0,0,8,8,16,64,0x0,0x7fd01739c900,394240,243736,3563750,16344,25120901,16342,16342,32684,49279,49279,4008097.0,3095742.0,5118.0,905741.0,2194719.0,0.0,3086745.0,2777815.0,392847,253666,49279,0,49279,0,1576928.0,984381.0,0.0,0.0,170462954930304,170459569892517,170459569917477,170462962833305
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/pmc_perf_1.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/pmc_perf_1.csv
new file mode 100644
index 0000000000..008238f966
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/pmc_perf_1.csv
@@ -0,0 +1,2 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,arch_vgpr,accum_vgpr,SGPR,wave_size,sig,obj,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_BUFFER_READ_WAVEFRONTS_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int) ",2,0,0,182745,182745,1046016,256,0,0,8,8,16,64,0x0,0x7fc67c952900,49032,0,65372,32684,0,0,0,16344,31572,0.0,0.0,0.0,32684.0,0.0,0.0,0.0,32684.0,4086,16344,512,47418,1751,0,48.0,385.0,0.0,261614.0,170459144419482,170459569892517,170459569917477,170459152290652
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/pmc_perf_10.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/pmc_perf_10.csv
new file mode 100644
index 0000000000..2d95e46f26
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/pmc_perf_10.csv
@@ -0,0 +1,2 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,arch_vgpr,accum_vgpr,SGPR,wave_size,sig,obj,TCC_EA_ATOMIC_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int) ",2,0,0,185476,185476,1046016,256,0,0,8,8,16,64,0x0,0x7f9648acc900,0.0,170466145856470,170459569892517,170459569917477,170466153429988
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/pmc_perf_11.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/pmc_perf_11.csv
new file mode 100644
index 0000000000..f24400b0c1
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/pmc_perf_11.csv
@@ -0,0 +1,2 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,arch_vgpr,accum_vgpr,SGPR,wave_size,sig,obj,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int) ",2,0,0,186569,186569,1046016,256,0,0,8,8,16,64,0x0,0x7f58b74bc900,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,170469303060323,170459569892517,170459569917477,170469310908370
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/pmc_perf_12.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/pmc_perf_12.csv
new file mode 100644
index 0000000000..c0d0b6b122
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/pmc_perf_12.csv
@@ -0,0 +1,2 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,arch_vgpr,accum_vgpr,SGPR,wave_size,sig,obj,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int) ",2,0,0,183110,183110,1046016,256,0,0,8,8,16,64,0x0,0x7f2e1188c900,4084,0,3830,0,4088,0,484,0,4084,0,583,0,4088,0,904,0,4084,0,262,0,4084,0,515,0,4084,0,1234,0,4088,0,1549,0,4084,0,1637,0,4084,0,728,0,4085,0,1306,0,4088,0,1662,0,4084,0,1111,0,4088,0,2576,0,4084,0,1074,0,4088,0,240,0,4084,0,1957,0,4087,0,2021,0,4324,0,2429,0,4088,0,547,0,4084,0,580,0,4132,0,4119,0,4085,0,1966,0,4088,0,1661,0,4084,0,65,0,4132,0,1785,0,4084,0,1208,0,4088,0,707,0,4084,0,0,0,4088,0,2490,0,4087,0,548,0,4088,0,1872,0,170460168322816,170459569892517,170459569917477,170460176125457
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/pmc_perf_13.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/pmc_perf_13.csv
new file mode 100644
index 0000000000..a3bb3a1767
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/pmc_perf_13.csv
@@ -0,0 +1,2 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,arch_vgpr,accum_vgpr,SGPR,wave_size,sig,obj,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int) ",2,0,0,185840,185840,1046016,256,0,0,8,8,16,64,0x0,0x7f4873c06900,0,3474879,4088,4088,0,4534699,4084,4084,0,3793563,4088,4088,0,3425718,4084,4084,0,3253146,4088,4088,0,3910232,4084,4084,0,3053230,4084,4084,0,3711457,4084,4084,0,3362919,4088,4088,0,3164445,4084,4084,0,4516092,4084,4084,0,3402722,4084,4084,0,3380518,4088,4088,0,5150141,4084,4084,0,3536125,4087,4086,0,3662403,4084,4084,0,3410502,4088,4088,0,3233234,4084,4084,0,4012039,4088,4088,0,3806690,4084,4084,0,3266843,4088,4088,0,4114160,4084,4084,0,3773210,4084,4084,0,4001481,4084,4084,0,3625676,4088,4088,0,3952599,4084,4084,0,3104744,4084,4084,0,4602397,4084,4084,0,3620205,4088,4088,0,4505408,4084,4084,0,3264580,4088,4088,0,3821332,4084,4084,170467199460515,170459569892517,170459569917477,170467207183405
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/pmc_perf_14.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/pmc_perf_14.csv
new file mode 100644
index 0000000000..357557d2bc
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/pmc_perf_14.csv
@@ -0,0 +1,2 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,arch_vgpr,accum_vgpr,SGPR,wave_size,sig,obj,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int) ",2,0,0,186022,186022,1046016,256,0,0,8,8,16,64,0x0,0x7fad31b34900,1543,0,0,1775710,3049,0,0,2012359,2234,0,0,1923221,1897,0,0,1776784,804,0,0,1695337,1099,0,0,1592425,573,0,0,1609050,1265,0,0,1749524,2139,0,0,1910507,2144,0,0,1958065,1555,0,0,1822994,1053,0,0,1638701,4160,0,0,1973109,722,0,0,1767281,1416,0,0,1839198,9128,0,0,2424807,3626,0,0,1954616,1866,0,0,1825681,1068,0,0,1723385,1200,0,0,1755096,949,0,0,1683680,1318,0,0,1776912,2306,0,0,1854211,1169,0,0,1889251,1752,0,0,1708621,635,0,0,1622777,5166,0,0,2191709,3408,0,0,1978738,1896,0,0,1845524,1786,0,0,1747018,1787,0,0,1822316,1660,0,0,1784217,170467815059135,170459569892517,170459569917477,170467822816651
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/pmc_perf_15.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/pmc_perf_15.csv
new file mode 100644
index 0000000000..ea604f8ca3
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/pmc_perf_15.csv
@@ -0,0 +1,2 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,arch_vgpr,accum_vgpr,SGPR,wave_size,sig,obj,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int) ",2,0,0,183292,183292,1046016,256,0,0,8,8,16,64,0x0,0x7fa36b62a900,0,8459,4371,8459,0,8172,4088,8172,0,8172,4084,8172,0,8172,4088,8172,0,8172,4084,8172,0,8168,4084,8168,0,8168,4084,8168,0,8172,4088,8172,0,8173,4085,8173,0,8168,4084,8168,0,8168,4084,8168,47,8222,4185,8269,0,8172,4084,8172,0,8172,4088,8172,0,8171,4084,8171,0,8172,4088,8172,0,8172,4084,8172,0,8171,4087,8171,0,8172,4084,8172,0,8172,4088,8172,0,8172,4084,8172,0,8168,4084,8168,0,8168,4084,8168,0,8172,4088,8172,0,8172,4084,8172,0,8216,4132,8216,0,8168,4084,8168,0,8172,4088,8172,0,8172,4084,8172,0,8172,4088,8172,0,8172,4084,8172,141,8175,4232,8316,170460778506870,170459569892517,170459569917477,170460786131284
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/pmc_perf_16.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/pmc_perf_16.csv
new file mode 100644
index 0000000000..8b6c4a1f50
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/pmc_perf_16.csv
@@ -0,0 +1,2 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,arch_vgpr,accum_vgpr,SGPR,wave_size,sig,obj,TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int) ",2,0,0,184566,184566,1046016,256,0,0,8,8,16,64,0x0,0x7f2a8a808900,8172,0,4088,8172,0,4084,8172,0,4088,8172,0,4084,8172,0,4088,8168,0,4084,8168,0,4084,8172,0,4084,8172,0,4088,8168,0,4084,8168,0,4084,8172,0,4084,8172,0,4088,8172,0,4084,8171,0,4087,8172,0,4084,8172,0,4088,8171,0,4084,8172,0,4088,8172,0,4084,8172,0,4088,8168,0,4084,8168,0,4084,8172,0,4084,8172,0,4088,8168,0,4084,8168,0,4084,8172,0,4084,8172,0,4088,8172,0,4084,8172,0,4088,8316,0,4084,170463959342369,170459569892517,170459569917477,170463967189665
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/pmc_perf_2.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/pmc_perf_2.csv
new file mode 100644
index 0000000000..4892de2d6a
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/pmc_perf_2.csv
@@ -0,0 +1,2 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,arch_vgpr,accum_vgpr,SGPR,wave_size,sig,obj,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,TA_BUFFER_TOTAL_CYCLES_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int) ",2,0,0,185112,185112,1046016,256,0,0,8,8,16,64,0x0,0x7eff4586e900,16344,392228,23443110,2018557,359542,163424,0,0,2091776.0,2091776.0,1045888.0,1045888.0,0.0,0.0,0.0,16342.0,14630,30974,9451,588,0,47061,261880.0,0.0,188.0,261692.0,170465269244275,170459569892517,170459569917477,170465277637692
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/pmc_perf_3.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/pmc_perf_3.csv
new file mode 100644
index 0000000000..f80f729576
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/pmc_perf_3.csv
@@ -0,0 +1,2 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,arch_vgpr,accum_vgpr,SGPR,wave_size,sig,obj,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int) ",2,0,0,185294,185294,1046016,256,0,0,8,8,16,64,0x0,0x7f54299b4900,179766,114404,0,32688,32684,16342,16342,65372,0.0,0.0,120.0,522938.0,0.0,0.0,0,0,1815,47384,0,131313.0,130735.0,0.0,130767.0,170465704653330,170459569892517,170459569917477,170465712329652
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/pmc_perf_4.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/pmc_perf_4.csv
new file mode 100644
index 0000000000..19e93814c8
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/pmc_perf_4.csv
@@ -0,0 +1,2 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,arch_vgpr,accum_vgpr,SGPR,wave_size,sig,obj,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int) ",2,0,0,184748,184748,1046016,256,0,0,8,8,16,64,0x0,0x7f6b1841a900,49032,11504916,65374,0,0,0,16344,0,960.0,512577.0,0.0,522938.0,890106.0,32684.0,0,0,0,18371,130735.0,130734.0,0.0,111945.0,170464397062074,170459569892517,170459569917477,170464404849195
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/pmc_perf_5.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/pmc_perf_5.csv
new file mode 100644
index 0000000000..e42897d89a
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/pmc_perf_5.csv
@@ -0,0 +1,2 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,arch_vgpr,accum_vgpr,SGPR,wave_size,sig,obj,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int) ",2,0,0,185658,185658,1046016,256,0,0,8,8,16,64,0x0,0x7fe05667c900,0,0,0,1046016,0,0,0,0,60929458.0,160131054.0,78079506.0,130735.0,0.0,602477.0,0,0,26715,0.0,0.0,140088.0,0.0,170466583185886,170459569892517,170459569917477,170466590977837
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/pmc_perf_6.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/pmc_perf_6.csv
new file mode 100644
index 0000000000..cb550bb250
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/pmc_perf_6.csv
@@ -0,0 +1,2 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,arch_vgpr,accum_vgpr,SGPR,wave_size,sig,obj,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int) ",2,0,0,184384,184384,1046016,256,0,0,8,8,16,64,0x0,0x7ff903a32900,0,130744,144,48,0,0,0,192,130735.0,0.0,0.0,0.0,32684.0,16342.0,0,0,0.0,131062.0,0.0,646.0,170463392938864,170459569892517,170459569917477,170463400628381
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/pmc_perf_7.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/pmc_perf_7.csv
new file mode 100644
index 0000000000..eb42ad7c62
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/pmc_perf_7.csv
@@ -0,0 +1,2 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,arch_vgpr,accum_vgpr,SGPR,wave_size,sig,obj,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int) ",2,0,0,183474,183474,1046016,256,0,0,8,8,16,64,0x0,0x7fed12eca900,0,65374,64380,48,1330,201007,0,0,0.0,0.0,0.0,0.0,16342.0,0.0,0,81720,0.0,0.0,46369.0,112735.0,170461215610530,170459569892517,170459569917477,170461223524381
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/pmc_perf_8.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/pmc_perf_8.csv
new file mode 100644
index 0000000000..5925b27114
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/pmc_perf_8.csv
@@ -0,0 +1,2 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,arch_vgpr,accum_vgpr,SGPR,wave_size,sig,obj,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int) ",2,0,0,183656,183656,1046016,256,0,0,8,8,16,64,0x0,0x7f45c6d52900,65372,63884,48,1440,32688,32684,0,0.0,0.0,0.0,0.0,16344,0,86872.0,43863.0,130437.0,0.0,170461649490635,170459569892517,170459569917477,170461657210750
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/pmc_perf_9.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/pmc_perf_9.csv
new file mode 100644
index 0000000000..dc3fc8b515
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/pmc_perf_9.csv
@@ -0,0 +1,2 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,arch_vgpr,accum_vgpr,SGPR,wave_size,sig,obj,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int) ",2,0,0,183838,183838,1046016,256,0,0,8,8,16,64,0x0,0x7f7e8ff6e900,130735.0,130735.0,0.0,2470076.0,131100.0,130735.0,128055860.0,59601515.0,170462083294677,170459569892517,170459569917477,170462091025412
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/pmc_perf_error_log.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/pmc_perf_error_log.csv
new file mode 100644
index 0000000000..13996cfa3c
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/pmc_perf_error_log.csv
@@ -0,0 +1,5 @@
+  ,CPC_CPC_STAT_BUSY ,CPC_CPC_STAT_STALL ,CPC_CPC_TCIU_BUSY ,CPC_CPC_UTCL2IU_BUSY ,CPC_ME1_BUSY_FOR_PACKET_DECODE ,CPC_ME1_DC0_SPI_BUSY ,CPF_CPF_STAT_BUSY ,CPF_CPF_TCIU_BUSY ,CPF_CPF_TCIU_IDLE ,GRBM_COUNT ,GRBM_GUI_ACTIVE ,SPI_CSN_BUSY ,SPI_CSN_WINDOW_VALID ,SPI_RA_REQ_NO_ALLOC ,SPI_RA_REQ_NO_ALLOC_CSN ,SQC_DCACHE_INPUT_VALID_READYB ,SQ_BUSY_CU_CYCLES ,SQ_BUSY_CYCLES ,SQ_CYCLES ,SQ_WAIT_ANY ,SQ_WAIT_INST_ANY ,TA_ADDR_STALLED_BY_TC_CYCLES_sum ,TA_DATA_STALLED_BY_TC_CYCLES_sum ,TA_TA_BUSY_sum ,TCC_ALL_TC_OP_WB_WRITEBACK_sum ,TCC_BUSY_sum ,TCC_CYCLE_sum ,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum ,TCC_EA_RDREQ_LEVEL_sum ,TCC_EA_RD_UNCACHED_32B_sum ,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum ,TCC_EA_WRREQ_LEVEL_sum ,TCC_EA_WRREQ_STALL_sum ,TCC_TAG_STALL_sum ,TCC_UC_REQ_sum ,TCP_GATE_EN1_sum ,TCP_GATE_EN2_sum ,TCP_PENDING_STALL_CYCLES_sum ,TCP_TCC_READ_REQ_LATENCY_sum ,TCP_TCC_WRITE_REQ_LATENCY_sum ,TCP_TCP_LATENCY_sum ,TCP_TCR_TCP_STALL_CYCLES_sum ,TCP_TD_TCP_STALL_CYCLES_sum ,TD_TC_STALL_sum ,TD_TD_BUSY_sum ,GPU_ID ,kernel_name                                     ,test_name
+0 ,                  ,                   ,                  ,                     ,                          7.33 ,                     ,                  ,              5.2 ,                  ,           ,                ,             ,                     ,              30.45 ,                  12.23 ,                         7.91 ,                  ,               ,          ,       7.38 ,            10.9 ,                           19.22 ,                                 ,               ,                               ,             ,              ,                             22.45 ,                 25.76 ,                     20.97 ,                            159.25 ,                       ,                       ,            10.42 ,         76.61 ,                 ,                 ,                             ,                       17.49 ,                              ,              16.78 ,                       17.14 ,                      12.51 ,                ,               ,   2.0 ,"vecCopy(double*, double*, double*, int, int) " ,logger
+0 ,             2.35 ,               5.0 ,             4.66 ,                1.17 ,                          7.33 ,                1.71 ,             2.35 ,              5.2 ,             2.57 ,      2.35 ,           2.35 ,        4.26 ,                2.32 ,              30.45 ,                  12.23 ,                         7.91 ,             4.51 ,          4.45 ,     2.35 ,       7.38 ,            10.9 ,                           19.22 ,                            4.14 ,          4.14 ,                          1.21 ,        1.62 ,         2.35 ,                             22.45 ,                 25.76 ,                     20.97 ,                            159.25 ,                  1.57 ,                  4.88 ,            10.42 ,         76.61 ,            4.05 ,            2.82 ,                        4.94 ,                       17.49 ,                         3.11 ,              16.78 ,                       17.14 ,                      12.51 ,            3.2 ,          2.84 ,       ,"vecCopy(double*, double*, double*, int, int) " ,test_path
+0 ,             2.35 ,               5.0 ,             4.66 ,                1.17 ,                          7.33 ,                1.71 ,             2.35 ,              5.2 ,             2.57 ,      2.35 ,           2.35 ,        4.26 ,                2.32 ,              30.45 ,                  12.23 ,                         7.91 ,             4.51 ,          4.45 ,     2.35 ,       7.38 ,            10.9 ,                           19.22 ,                            4.14 ,          4.14 ,                          1.21 ,        1.62 ,         2.35 ,                             22.45 ,                 25.76 ,                     20.97 ,                            159.25 ,                  1.57 ,                  4.88 ,            10.42 ,         76.61 ,            4.05 ,            2.82 ,                        4.94 ,                       17.49 ,                         3.11 ,              16.78 ,                       17.14 ,                      12.51 ,            3.2 ,          2.84 ,       ,"vecCopy(double*, double*, double*, int, int) " ,test_path
+0 ,             2.35 ,               5.0 ,             4.66 ,                1.17 ,                          7.33 ,                1.71 ,             2.35 ,              5.2 ,             2.57 ,      2.35 ,           2.35 ,        4.26 ,                2.32 ,              30.45 ,                  12.23 ,                         7.91 ,             4.51 ,          4.45 ,     2.35 ,       7.38 ,            10.9 ,                           19.22 ,                            4.14 ,          4.14 ,                          1.21 ,        1.62 ,         2.35 ,                             22.45 ,                 25.76 ,                     20.97 ,                            159.25 ,                  1.57 ,                  4.88 ,            10.42 ,         76.61 ,            4.05 ,            2.82 ,                        4.94 ,                       17.49 ,                         3.11 ,              16.78 ,                       17.14 ,                      12.51 ,            3.2 ,          2.84 ,       ,"vecCopy(double*, double*, double*, int, int) " ,test_path
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/sysinfo.csv
new file mode 100644
index 0000000000..a957c8e694
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/sysinfo.csv
@@ -0,0 +1,2 @@
+workload_name,command,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,LDSBanks,name,numSQC,hbmBW,ip_blocks
+Baseline_mi100,"./sample/vcopy 1045876 256",t004-005.hpcfund,AMD EPYC 7V13 64-Core Processor,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,5.5.1-74,Thu Oct  5 12:46:57 2023 (CDT),gfx908,8,120,4,64,40,1024,16,8192,1502,1200,300,1200,32,32,mi100,48,1228.8,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/timestamps.csv
new file mode 100644
index 0000000000..514e94b84e
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi100/timestamps.csv
@@ -0,0 +1,2 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,arch_vgpr,accum_vgpr,SGPR,wave_size,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int) ",2,0,0,182928,182928,1046016,256,0,0,8,8,16,64,0x0,0x7f7d5f2ec900,170459569866514,170459569892517,170459569917477,170459569928641
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/SQ_IFETCH_LEVEL.csv
new file mode 100644
index 0000000000..06fdffd51f
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/SQ_IFETCH_LEVEL.csv
@@ -0,0 +1,2 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,arch_vgpr,accum_vgpr,SGPR,wave_size,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int) ",2,0,0,184020,184020,1046016,256,0,0,8,8,16,64,0x0,0x7f27901dc900,49077,49077,16344,65374,14272,1828056,170462517797539,170459569892517,170459569917477,170462525395574
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/SQ_IFETCH_LEVEL_error_log.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/SQ_IFETCH_LEVEL_error_log.csv
new file mode 100644
index 0000000000..e339a8af09
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/SQ_IFETCH_LEVEL_error_log.csv
@@ -0,0 +1,5 @@
+,SQ_ACCUM_PREV_HIRES,SQ_IFETCH_LEVEL,GPU_ID,kernel_name,test_name
+0,,,2.0,"vecCopy(double*, double*, double*, int, int) ",logger
+0,3.15,2.45,,"vecCopy(double*, double*, double*, int, int) ",test_path
+0,3.15,2.45,,"vecCopy(double*, double*, double*, int, int) ",test_path
+0,3.15,2.45,,"vecCopy(double*, double*, double*, int, int) ",test_path
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/SQ_INST_LEVEL_LDS.csv
new file mode 100644
index 0000000000..114e4c5582
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/SQ_INST_LEVEL_LDS.csv
@@ -0,0 +1,2 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,arch_vgpr,accum_vgpr,SGPR,wave_size,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int) ",2,0,0,182563,182563,1046016,256,0,0,8,8,16,64,0x0,0x7f64e4a14900,0,0,0,170458716982587,170459569892517,170459569917477,170458724553200
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/SQ_INST_LEVEL_LDS_error_log.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/SQ_INST_LEVEL_LDS_error_log.csv
new file mode 100644
index 0000000000..1055d5574f
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/SQ_INST_LEVEL_LDS_error_log.csv
@@ -0,0 +1,5 @@
+,GPU_ID,kernel_name,test_name
+0,2.0,"vecCopy(double*, double*, double*, int, int) ",logger
+0,,"vecCopy(double*, double*, double*, int, int) ",test_path
+0,,"vecCopy(double*, double*, double*, int, int) ",test_path
+0,,"vecCopy(double*, double*, double*, int, int) ",test_path
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/SQ_INST_LEVEL_SMEM.csv
new file mode 100644
index 0000000000..3cfe2f4b7c
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/SQ_INST_LEVEL_SMEM.csv
@@ -0,0 +1,2 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,arch_vgpr,accum_vgpr,SGPR,wave_size,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int) ",2,0,0,186387,186387,1046016,256,0,0,8,8,16,64,0x0,0x7f03fe608900,65372,219514,28018288,170468686919648,170459569892517,170459569917477,170468694691040
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/SQ_INST_LEVEL_SMEM_error_log.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/SQ_INST_LEVEL_SMEM_error_log.csv
new file mode 100644
index 0000000000..fc751af104
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/SQ_INST_LEVEL_SMEM_error_log.csv
@@ -0,0 +1,5 @@
+,SQ_ACCUM_PREV_HIRES,SQ_INST_LEVEL_SMEM,GPU_ID,kernel_name,test_name
+0,9.15,9.24,2.0,"vecCopy(double*, double*, double*, int, int) ",logger
+0,9.15,9.24,,"vecCopy(double*, double*, double*, int, int) ",test_path
+0,9.15,9.24,,"vecCopy(double*, double*, double*, int, int) ",test_path
+0,9.15,9.24,,"vecCopy(double*, double*, double*, int, int) ",test_path
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/SQ_INST_LEVEL_VMEM.csv
new file mode 100644
index 0000000000..1cc5348f4e
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/SQ_INST_LEVEL_VMEM.csv
@@ -0,0 +1,2 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,arch_vgpr,accum_vgpr,SGPR,wave_size,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int) ",2,0,0,186204,186204,1046016,256,0,0,8,8,16,64,0x0,0x7f140af1e900,32684,657046,84111604,170468251325091,170459569892517,170459569917477,170468258841612
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/SQ_INST_LEVEL_VMEM_error_log.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/SQ_INST_LEVEL_VMEM_error_log.csv
new file mode 100644
index 0000000000..ac50ad237e
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/SQ_INST_LEVEL_VMEM_error_log.csv
@@ -0,0 +1,5 @@
+,SQ_ACCUM_PREV_HIRES,SQ_INST_LEVEL_VMEM,GPU_ID,kernel_name,test_name
+0,,,2.0,"vecCopy(double*, double*, double*, int, int) ",logger
+0,3.38,3.38,,"vecCopy(double*, double*, double*, int, int) ",test_path
+0,3.38,3.38,,"vecCopy(double*, double*, double*, int, int) ",test_path
+0,3.38,3.38,,"vecCopy(double*, double*, double*, int, int) ",test_path
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/SQ_LEVEL_WAVES.csv
new file mode 100644
index 0000000000..f2e8f243de
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/SQ_LEVEL_WAVES.csv
@@ -0,0 +1,2 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,arch_vgpr,accum_vgpr,SGPR,wave_size,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int) ",2,0,0,184930,184930,1046016,256,0,0,8,8,16,64,0x0,0x7f4402e88900,49562,49562,17633,396504,16344,26156281,247544,0,105140276,170464833838064,170459569892517,170459569917477,170464841456046
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/SQ_LEVEL_WAVES_error_log.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/SQ_LEVEL_WAVES_error_log.csv
new file mode 100644
index 0000000000..5d9c05d4b5
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/SQ_LEVEL_WAVES_error_log.csv
@@ -0,0 +1,6 @@
+,CPC_ME1_BUSY_FOR_PACKET_DECODE,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_ACCUM_PREV_HIRES,SQ_BUSY_CYCLES,SQ_CYCLES,SQ_WAVE_CYCLES,GPU_ID,kernel_name,test_name
+0,,,,,5.12,,,2.0,"vecCopy(double*, double*, double*, int, int) ",logger
+0,,,,,5.12,,,,"vecCopy(double*, double*, double*, int, int) ",logger
+0,2.6,1.92,1.92,4.42,5.12,1.92,4.47,,"vecCopy(double*, double*, double*, int, int) ",test_path
+0,2.6,1.92,1.92,4.42,5.12,1.92,4.47,,"vecCopy(double*, double*, double*, int, int) ",test_path
+0,2.6,1.92,1.92,4.42,5.12,1.92,4.47,,"vecCopy(double*, double*, double*, int, int) ",test_path
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/log.txt b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/log.txt
new file mode 100644
index 0000000000..435819ae09
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/log.txt
@@ -0,0 +1,582 @@
+RPL: on '231005_124645' from '/opt/rocm-5.5.1' in '/home1/josantos/omniperf'
+RPL: profiling '""./sample/vcopy 1045876 256""'
+RPL: input file 'Baseline_mi100/perfmon/SQ_INST_LEVEL_LDS.txt'
+RPL: output dir '/tmp/rpl_data_231005_124645_182404'
+RPL: result dir '/tmp/rpl_data_231005_124645_182404/input0_results_231005_124645'
+ROCProfiler: input from "/tmp/rpl_data_231005_124645_182404/input0.xml"
+  gpu_index = 
+  kernel = 
+  range = 
+  3 metrics
+    SQ_INSTS_LDS, SQ_INST_LEVEL_LDS, SQ_ACCUM_PREV_HIRES
+vcopy testing on GCD 0
+Finished allocating vectors on the CPU
+Finished allocating vectors on the GPU
+Finished copying vectors to the GPU
+sw thinks it moved 0.999755 KB per wave 
+Total threads: 1045876, Grid Size: 4086 block Size:256, Wavefronts:16344:
+Launching the  kernel on the GPU
+Finished executing kernel
+Finished copying the output vector from the GPU to the CPU
+Releasing GPU memory
+Releasing CPU memory
+
+ROCPRofiler: 1 contexts collected, output directory /tmp/rpl_data_231005_124645_182404/input0_results_231005_124645
+File 'Baseline_mi100/SQ_INST_LEVEL_LDS.csv' is generating
+RPL: on '231005_124646' from '/opt/rocm-5.5.1' in '/home1/josantos/omniperf'
+RPL: profiling '""./sample/vcopy 1045876 256""'
+RPL: input file 'Baseline_mi100/perfmon/pmc_perf_1.txt'
+RPL: output dir '/tmp/rpl_data_231005_124646_182586'
+RPL: result dir '/tmp/rpl_data_231005_124646_182586/input0_results_231005_124646'
+ROCProfiler: input from "/tmp/rpl_data_231005_124646_182586/input0.xml"
+  gpu_index = 
+  kernel = 
+  range = 
+  27 metrics
+    SQ_INSTS_SALU, SQ_INSTS_VSKIPPED, SQ_INSTS_SMEM, SQ_INSTS_FLAT, SQ_INSTS_LDS, SQ_INSTS_GDS, SQ_INSTS_EXP_GDS, SQ_INSTS_BRANCH, GRBM_SPI_BUSY, TCP_READ_TAGCONFLICT_STALL_CYCLES_sum, TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum, TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum, TCP_TA_TCP_STATE_READ_sum, TA_BUFFER_READ_WAVEFRONTS_sum, TA_BUFFER_WRITE_WAVEFRONTS_sum, TD_COALESCABLE_WAVEFRONT_sum, TD_LOAD_WAVEFRONT_sum, SPI_CSN_NUM_THREADGROUPS, SPI_CSN_WAVE, CPC_CPC_TCIU_BUSY, CPC_CPC_TCIU_IDLE, CPF_CPF_TCIU_BUSY, CPF_CPF_TCIU_STALL, TCC_NC_REQ_sum, TCC_UC_REQ_sum, TCC_CC_REQ_sum, TCC_RW_REQ_sum
+vcopy testing on GCD 0
+Finished allocating vectors on the CPU
+Finished allocating vectors on the GPU
+Finished copying vectors to the GPU
+sw thinks it moved 0.999755 KB per wave 
+Total threads: 1045876, Grid Size: 4086 block Size:256, Wavefronts:16344:
+Launching the  kernel on the GPU
+Finished executing kernel
+Finished copying the output vector from the GPU to the CPU
+Releasing GPU memory
+Releasing CPU memory
+
+ROCPRofiler: 1 contexts collected, output directory /tmp/rpl_data_231005_124646_182586/input0_results_231005_124646
+File 'Baseline_mi100/pmc_perf_1.csv' is generating
+RPL: on '231005_124646' from '/opt/rocm-5.5.1' in '/home1/josantos/omniperf'
+RPL: profiling '""./sample/vcopy 1045876 256""'
+RPL: input file 'Baseline_mi100/perfmon/timestamps.txt'
+RPL: output dir '/tmp/rpl_data_231005_124646_182768'
+RPL: result dir '/tmp/rpl_data_231005_124646_182768/input0_results_231005_124646'
+ROCProfiler: input from "/tmp/rpl_data_231005_124646_182768/input0.xml"
+  gpu_index = 
+  kernel = 
+  range = 
+  0 metrics
+vcopy testing on GCD 0
+Finished allocating vectors on the CPU
+Finished allocating vectors on the GPU
+Finished copying vectors to the GPU
+sw thinks it moved 0.999755 KB per wave 
+Total threads: 1045876, Grid Size: 4086 block Size:256, Wavefronts:16344:
+Launching the  kernel on the GPU
+Finished executing kernel
+Finished copying the output vector from the GPU to the CPU
+Releasing GPU memory
+Releasing CPU memory
+
+ROCPRofiler: 1 contexts collected, output directory /tmp/rpl_data_231005_124646_182768/input0_results_231005_124646
+File 'Baseline_mi100/timestamps.csv' is generating
+RPL: on '231005_124647' from '/opt/rocm-5.5.1' in '/home1/josantos/omniperf'
+RPL: profiling '""./sample/vcopy 1045876 256""'
+RPL: input file 'Baseline_mi100/perfmon/pmc_perf_12.txt'
+RPL: output dir '/tmp/rpl_data_231005_124647_182951'
+RPL: result dir '/tmp/rpl_data_231005_124647_182951/input0_results_231005_124647'
+ROCProfiler: input from "/tmp/rpl_data_231005_124647_182951/input0.xml"
+  gpu_index = 
+  kernel = 
+  range = 
+  128 metrics
+    TCC_EA_RDREQ[0], TCC_EA_RDREQ_32B[0], TCC_EA_RDREQ_DRAM_CREDIT_STALL[0], TCC_EA_RDREQ_GMI_CREDIT_STALL[0], TCC_EA_RDREQ[1], TCC_EA_RDREQ_32B[1], TCC_EA_RDREQ_DRAM_CREDIT_STALL[1], TCC_EA_RDREQ_GMI_CREDIT_STALL[1], TCC_EA_RDREQ[2], TCC_EA_RDREQ_32B[2], TCC_EA_RDREQ_DRAM_CREDIT_STALL[2], TCC_EA_RDREQ_GMI_CREDIT_STALL[2], TCC_EA_RDREQ[3], TCC_EA_RDREQ_32B[3], TCC_EA_RDREQ_DRAM_CREDIT_STALL[3], TCC_EA_RDREQ_GMI_CREDIT_STALL[3], TCC_EA_RDREQ[4], TCC_EA_RDREQ_32B[4], TCC_EA_RDREQ_DRAM_CREDIT_STALL[4], TCC_EA_RDREQ_GMI_CREDIT_STALL[4], TCC_EA_RDREQ[5], TCC_EA_RDREQ_32B[5], TCC_EA_RDREQ_DRAM_CREDIT_STALL[5], TCC_EA_RDREQ_GMI_CREDIT_STALL[5], TCC_EA_RDREQ[6], TCC_EA_RDREQ_32B[6], TCC_EA_RDREQ_DRAM_CREDIT_STALL[6], TCC_EA_RDREQ_GMI_CREDIT_STALL[6], TCC_EA_RDREQ[7], TCC_EA_RDREQ_32B[7], TCC_EA_RDREQ_DRAM_CREDIT_STALL[7], TCC_EA_RDREQ_GMI_CREDIT_STALL[7], TCC_EA_RDREQ[8], TCC_EA_RDREQ_32B[8], TCC_EA_RDREQ_DRAM_CREDIT_STALL[8], TCC_EA_RDREQ_GMI_CREDIT_STALL[8], TCC_EA_RDREQ[9], TCC_EA_RDREQ_32B[9], TCC_EA_RDREQ_DRAM_CREDIT_STALL[9], TCC_EA_RDREQ_GMI_CREDIT_STALL[9], TCC_EA_RDREQ[10], TCC_EA_RDREQ_32B[10], TCC_EA_RDREQ_DRAM_CREDIT_STALL[10], TCC_EA_RDREQ_GMI_CREDIT_STALL[10], TCC_EA_RDREQ[11], TCC_EA_RDREQ_32B[11], TCC_EA_RDREQ_DRAM_CREDIT_STALL[11], TCC_EA_RDREQ_GMI_CREDIT_STALL[11], TCC_EA_RDREQ[12], TCC_EA_RDREQ_32B[12], TCC_EA_RDREQ_DRAM_CREDIT_STALL[12], TCC_EA_RDREQ_GMI_CREDIT_STALL[12], TCC_EA_RDREQ[13], TCC_EA_RDREQ_32B[13], TCC_EA_RDREQ_DRAM_CREDIT_STALL[13], TCC_EA_RDREQ_GMI_CREDIT_STALL[13], TCC_EA_RDREQ[14], TCC_EA_RDREQ_32B[14], TCC_EA_RDREQ_DRAM_CREDIT_STALL[14], TCC_EA_RDREQ_GMI_CREDIT_STALL[14], TCC_EA_RDREQ[15], TCC_EA_RDREQ_32B[15], TCC_EA_RDREQ_DRAM_CREDIT_STALL[15], TCC_EA_RDREQ_GMI_CREDIT_STALL[15], TCC_EA_RDREQ[16], TCC_EA_RDREQ_32B[16], TCC_EA_RDREQ_DRAM_CREDIT_STALL[16], TCC_EA_RDREQ_GMI_CREDIT_STALL[16], TCC_EA_RDREQ[17], TCC_EA_RDREQ_32B[17], TCC_EA_RDREQ_DRAM_CREDIT_STALL[17], TCC_EA_RDREQ_GMI_CREDIT_STALL[17], TCC_EA_RDREQ[18], TCC_EA_RDREQ_32B[18], TCC_EA_RDREQ_DRAM_CREDIT_STALL[18], TCC_EA_RDREQ_GMI_CREDIT_STALL[18], TCC_EA_RDREQ[19], TCC_EA_RDREQ_32B[19], TCC_EA_RDREQ_DRAM_CREDIT_STALL[19], TCC_EA_RDREQ_GMI_CREDIT_STALL[19], TCC_EA_RDREQ[20], TCC_EA_RDREQ_32B[20], TCC_EA_RDREQ_DRAM_CREDIT_STALL[20], TCC_EA_RDREQ_GMI_CREDIT_STALL[20], TCC_EA_RDREQ[21], TCC_EA_RDREQ_32B[21], TCC_EA_RDREQ_DRAM_CREDIT_STALL[21], TCC_EA_RDREQ_GMI_CREDIT_STALL[21], TCC_EA_RDREQ[22], TCC_EA_RDREQ_32B[22], TCC_EA_RDREQ_DRAM_CREDIT_STALL[22], TCC_EA_RDREQ_GMI_CREDIT_STALL[22], TCC_EA_RDREQ[23], TCC_EA_RDREQ_32B[23], TCC_EA_RDREQ_DRAM_CREDIT_STALL[23], TCC_EA_RDREQ_GMI_CREDIT_STALL[23], TCC_EA_RDREQ[24], TCC_EA_RDREQ_32B[24], TCC_EA_RDREQ_DRAM_CREDIT_STALL[24], TCC_EA_RDREQ_GMI_CREDIT_STALL[24], TCC_EA_RDREQ[25], TCC_EA_RDREQ_32B[25], TCC_EA_RDREQ_DRAM_CREDIT_STALL[25], TCC_EA_RDREQ_GMI_CREDIT_STALL[25], TCC_EA_RDREQ[26], TCC_EA_RDREQ_32B[26], TCC_EA_RDREQ_DRAM_CREDIT_STALL[26], TCC_EA_RDREQ_GMI_CREDIT_STALL[26], TCC_EA_RDREQ[27], TCC_EA_RDREQ_32B[27], TCC_EA_RDREQ_DRAM_CREDIT_STALL[27], TCC_EA_RDREQ_GMI_CREDIT_STALL[27], TCC_EA_RDREQ[28], TCC_EA_RDREQ_32B[28], TCC_EA_RDREQ_DRAM_CREDIT_STALL[28], TCC_EA_RDREQ_GMI_CREDIT_STALL[28], TCC_EA_RDREQ[29], TCC_EA_RDREQ_32B[29], TCC_EA_RDREQ_DRAM_CREDIT_STALL[29], TCC_EA_RDREQ_GMI_CREDIT_STALL[29], TCC_EA_RDREQ[30], TCC_EA_RDREQ_32B[30], TCC_EA_RDREQ_DRAM_CREDIT_STALL[30], TCC_EA_RDREQ_GMI_CREDIT_STALL[30], TCC_EA_RDREQ[31], TCC_EA_RDREQ_32B[31], TCC_EA_RDREQ_DRAM_CREDIT_STALL[31], TCC_EA_RDREQ_GMI_CREDIT_STALL[31]
+vcopy testing on GCD 0
+Finished allocating vectors on the CPU
+Finished allocating vectors on the GPU
+Finished copying vectors to the GPU
+sw thinks it moved 0.999755 KB per wave 
+Total threads: 1045876, Grid Size: 4086 block Size:256, Wavefronts:16344:
+Launching the  kernel on the GPU
+Finished executing kernel
+Finished copying the output vector from the GPU to the CPU
+Releasing GPU memory
+Releasing CPU memory
+
+ROCPRofiler: 1 contexts collected, output directory /tmp/rpl_data_231005_124647_182951/input0_results_231005_124647
+File 'Baseline_mi100/pmc_perf_12.csv' is generating
+RPL: on '231005_124647' from '/opt/rocm-5.5.1' in '/home1/josantos/omniperf'
+RPL: profiling '""./sample/vcopy 1045876 256""'
+RPL: input file 'Baseline_mi100/perfmon/pmc_perf_15.txt'
+RPL: output dir '/tmp/rpl_data_231005_124647_183133'
+RPL: result dir '/tmp/rpl_data_231005_124647_183133/input0_results_231005_124647'
+ROCProfiler: input from "/tmp/rpl_data_231005_124647_183133/input0.xml"
+  gpu_index = 
+  kernel = 
+  range = 
+  128 metrics
+    TCC_HIT[0], TCC_MISS[0], TCC_READ[0], TCC_REQ[0], TCC_HIT[1], TCC_MISS[1], TCC_READ[1], TCC_REQ[1], TCC_HIT[2], TCC_MISS[2], TCC_READ[2], TCC_REQ[2], TCC_HIT[3], TCC_MISS[3], TCC_READ[3], TCC_REQ[3], TCC_HIT[4], TCC_MISS[4], TCC_READ[4], TCC_REQ[4], TCC_HIT[5], TCC_MISS[5], TCC_READ[5], TCC_REQ[5], TCC_HIT[6], TCC_MISS[6], TCC_READ[6], TCC_REQ[6], TCC_HIT[7], TCC_MISS[7], TCC_READ[7], TCC_REQ[7], TCC_HIT[8], TCC_MISS[8], TCC_READ[8], TCC_REQ[8], TCC_HIT[9], TCC_MISS[9], TCC_READ[9], TCC_REQ[9], TCC_HIT[10], TCC_MISS[10], TCC_READ[10], TCC_REQ[10], TCC_HIT[11], TCC_MISS[11], TCC_READ[11], TCC_REQ[11], TCC_HIT[12], TCC_MISS[12], TCC_READ[12], TCC_REQ[12], TCC_HIT[13], TCC_MISS[13], TCC_READ[13], TCC_REQ[13], TCC_HIT[14], TCC_MISS[14], TCC_READ[14], TCC_REQ[14], TCC_HIT[15], TCC_MISS[15], TCC_READ[15], TCC_REQ[15], TCC_HIT[16], TCC_MISS[16], TCC_READ[16], TCC_REQ[16], TCC_HIT[17], TCC_MISS[17], TCC_READ[17], TCC_REQ[17], TCC_HIT[18], TCC_MISS[18], TCC_READ[18], TCC_REQ[18], TCC_HIT[19], TCC_MISS[19], TCC_READ[19], TCC_REQ[19], TCC_HIT[20], TCC_MISS[20], TCC_READ[20], TCC_REQ[20], TCC_HIT[21], TCC_MISS[21], TCC_READ[21], TCC_REQ[21], TCC_HIT[22], TCC_MISS[22], TCC_READ[22], TCC_REQ[22], TCC_HIT[23], TCC_MISS[23], TCC_READ[23], TCC_REQ[23], TCC_HIT[24], TCC_MISS[24], TCC_READ[24], TCC_REQ[24], TCC_HIT[25], TCC_MISS[25], TCC_READ[25], TCC_REQ[25], TCC_HIT[26], TCC_MISS[26], TCC_READ[26], TCC_REQ[26], TCC_HIT[27], TCC_MISS[27], TCC_READ[27], TCC_REQ[27], TCC_HIT[28], TCC_MISS[28], TCC_READ[28], TCC_REQ[28], TCC_HIT[29], TCC_MISS[29], TCC_READ[29], TCC_REQ[29], TCC_HIT[30], TCC_MISS[30], TCC_READ[30], TCC_REQ[30], TCC_HIT[31], TCC_MISS[31], TCC_READ[31], TCC_REQ[31]
+vcopy testing on GCD 0
+Finished allocating vectors on the CPU
+Finished allocating vectors on the GPU
+Finished copying vectors to the GPU
+sw thinks it moved 0.999755 KB per wave 
+Total threads: 1045876, Grid Size: 4086 block Size:256, Wavefronts:16344:
+Launching the  kernel on the GPU
+Finished executing kernel
+Finished copying the output vector from the GPU to the CPU
+Releasing GPU memory
+Releasing CPU memory
+
+ROCPRofiler: 1 contexts collected, output directory /tmp/rpl_data_231005_124647_183133/input0_results_231005_124647
+File 'Baseline_mi100/pmc_perf_15.csv' is generating
+RPL: on '231005_124648' from '/opt/rocm-5.5.1' in '/home1/josantos/omniperf'
+RPL: profiling '""./sample/vcopy 1045876 256""'
+RPL: input file 'Baseline_mi100/perfmon/pmc_perf_7.txt'
+RPL: output dir '/tmp/rpl_data_231005_124648_183315'
+RPL: result dir '/tmp/rpl_data_231005_124648_183315/input0_results_231005_124648'
+ROCProfiler: input from "/tmp/rpl_data_231005_124648_183315/input0.xml"
+  gpu_index = 
+  kernel = 
+  range = 
+  20 metrics
+    SQC_DCACHE_REQ_READ_16, SQC_ICACHE_REQ, SQC_ICACHE_HITS, SQC_ICACHE_MISSES, SQC_ICACHE_MISSES_DUPLICATE, SQC_DCACHE_INPUT_VALID_READYB, SQC_DCACHE_ATOMIC, SQC_DCACHE_REQ_READ_8, TCP_TCC_NC_WRITE_REQ_sum, TCP_TCC_NC_ATOMIC_REQ_sum, TCP_TCC_UC_READ_REQ_sum, TCP_TCC_UC_WRITE_REQ_sum, TA_FLAT_WRITE_WAVEFRONTS_sum, TA_FLAT_ATOMIC_WAVEFRONTS_sum, SPI_RA_WVLIM_STALL_CSN, SPI_SWC_CSC_WR, TCC_EA_RDREQ_IO_CREDIT_STALL_sum, TCC_EA_RDREQ_GMI_CREDIT_STALL_sum, TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum, TCC_TAG_STALL_sum
+vcopy testing on GCD 0
+Finished allocating vectors on the CPU
+Finished allocating vectors on the GPU
+Finished copying vectors to the GPU
+sw thinks it moved 0.999755 KB per wave 
+Total threads: 1045876, Grid Size: 4086 block Size:256, Wavefronts:16344:
+Launching the  kernel on the GPU
+Finished executing kernel
+Finished copying the output vector from the GPU to the CPU
+Releasing GPU memory
+Releasing CPU memory
+
+ROCPRofiler: 1 contexts collected, output directory /tmp/rpl_data_231005_124648_183315/input0_results_231005_124648
+File 'Baseline_mi100/pmc_perf_7.csv' is generating
+RPL: on '231005_124648' from '/opt/rocm-5.5.1' in '/home1/josantos/omniperf'
+RPL: profiling '""./sample/vcopy 1045876 256""'
+RPL: input file 'Baseline_mi100/perfmon/pmc_perf_8.txt'
+RPL: output dir '/tmp/rpl_data_231005_124648_183497'
+RPL: result dir '/tmp/rpl_data_231005_124648_183497/input0_results_231005_124648'
+ROCProfiler: input from "/tmp/rpl_data_231005_124648_183497/input0.xml"
+  gpu_index = 
+  kernel = 
+  range = 
+  17 metrics
+    SQC_DCACHE_REQ, SQC_DCACHE_HITS, SQC_DCACHE_MISSES, SQC_DCACHE_MISSES_DUPLICATE, SQC_DCACHE_REQ_READ_1, SQC_DCACHE_REQ_READ_2, SQC_DCACHE_REQ_READ_4, TCP_TCC_UC_ATOMIC_REQ_sum, TCP_TCC_CC_READ_REQ_sum, TCP_TCC_CC_WRITE_REQ_sum, TCP_TCC_CC_ATOMIC_REQ_sum, SPI_VWC_CSC_WR, SPI_RA_BULKY_CU_FULL_CSN, TCC_NORMAL_WRITEBACK_sum, TCC_ALL_TC_OP_WB_WRITEBACK_sum, TCC_NORMAL_EVICT_sum, TCC_ALL_TC_OP_INV_EVICT_sum
+vcopy testing on GCD 0
+Finished allocating vectors on the CPU
+Finished allocating vectors on the GPU
+Finished copying vectors to the GPU
+sw thinks it moved 0.999755 KB per wave 
+Total threads: 1045876, Grid Size: 4086 block Size:256, Wavefronts:16344:
+Launching the  kernel on the GPU
+Finished executing kernel
+Finished copying the output vector from the GPU to the CPU
+Releasing GPU memory
+Releasing CPU memory
+
+ROCPRofiler: 1 contexts collected, output directory /tmp/rpl_data_231005_124648_183497/input0_results_231005_124648
+File 'Baseline_mi100/pmc_perf_8.csv' is generating
+RPL: on '231005_124649' from '/opt/rocm-5.5.1' in '/home1/josantos/omniperf'
+RPL: profiling '""./sample/vcopy 1045876 256""'
+RPL: input file 'Baseline_mi100/perfmon/pmc_perf_9.txt'
+RPL: output dir '/tmp/rpl_data_231005_124649_183679'
+RPL: result dir '/tmp/rpl_data_231005_124649_183679/input0_results_231005_124649'
+ROCProfiler: input from "/tmp/rpl_data_231005_124649_183679/input0.xml"
+  gpu_index = 
+  kernel = 
+  range = 
+  8 metrics
+    TCP_TCC_RW_READ_REQ_sum, TCP_TCC_RW_WRITE_REQ_sum, TCP_TCC_RW_ATOMIC_REQ_sum, TCP_PENDING_STALL_CYCLES_sum, TCC_EA_RDREQ_DRAM_sum, TCC_EA_WRREQ_DRAM_sum, TCC_EA_RDREQ_LEVEL_sum, TCC_EA_WRREQ_LEVEL_sum
+vcopy testing on GCD 0
+Finished allocating vectors on the CPU
+Finished allocating vectors on the GPU
+Finished copying vectors to the GPU
+sw thinks it moved 0.999755 KB per wave 
+Total threads: 1045876, Grid Size: 4086 block Size:256, Wavefronts:16344:
+Launching the  kernel on the GPU
+Finished executing kernel
+Finished copying the output vector from the GPU to the CPU
+Releasing GPU memory
+Releasing CPU memory
+
+ROCPRofiler: 1 contexts collected, output directory /tmp/rpl_data_231005_124649_183679/input0_results_231005_124649
+File 'Baseline_mi100/pmc_perf_9.csv' is generating
+RPL: on '231005_124649' from '/opt/rocm-5.5.1' in '/home1/josantos/omniperf'
+RPL: profiling '""./sample/vcopy 1045876 256""'
+RPL: input file 'Baseline_mi100/perfmon/SQ_IFETCH_LEVEL.txt'
+RPL: output dir '/tmp/rpl_data_231005_124649_183861'
+RPL: result dir '/tmp/rpl_data_231005_124649_183861/input0_results_231005_124649'
+ROCProfiler: input from "/tmp/rpl_data_231005_124649_183861/input0.xml"
+  gpu_index = 
+  kernel = 
+  range = 
+  6 metrics
+    GRBM_COUNT, GRBM_GUI_ACTIVE, SQ_WAVES, SQ_IFETCH, SQ_IFETCH_LEVEL, SQ_ACCUM_PREV_HIRES
+vcopy testing on GCD 0
+Finished allocating vectors on the CPU
+Finished allocating vectors on the GPU
+Finished copying vectors to the GPU
+sw thinks it moved 0.999755 KB per wave 
+Total threads: 1045876, Grid Size: 4086 block Size:256, Wavefronts:16344:
+Launching the  kernel on the GPU
+Finished executing kernel
+Finished copying the output vector from the GPU to the CPU
+Releasing GPU memory
+Releasing CPU memory
+
+ROCPRofiler: 1 contexts collected, output directory /tmp/rpl_data_231005_124649_183861/input0_results_231005_124649
+File 'Baseline_mi100/SQ_IFETCH_LEVEL.csv' is generating
+RPL: on '231005_124649' from '/opt/rocm-5.5.1' in '/home1/josantos/omniperf'
+RPL: profiling '""./sample/vcopy 1045876 256""'
+RPL: input file 'Baseline_mi100/perfmon/pmc_perf_0.txt'
+RPL: output dir '/tmp/rpl_data_231005_124649_184043'
+RPL: result dir '/tmp/rpl_data_231005_124649_184043/input0_results_231005_124649'
+ROCProfiler: input from "/tmp/rpl_data_231005_124649_184043/input0.xml"
+  gpu_index = 
+  kernel = 
+  range = 
+  28 metrics
+    SQ_CYCLES, SQ_BUSY_CYCLES, SQ_BUSY_CU_CYCLES, SQ_WAVES, SQ_WAVE_CYCLES, SQ_INSTS_VMEM_WR, SQ_INSTS_VMEM_RD, SQ_INSTS_VMEM, GRBM_COUNT, GRBM_GUI_ACTIVE, TCP_GATE_EN1_sum, TCP_GATE_EN2_sum, TCP_TD_TCP_STALL_CYCLES_sum, TCP_TCR_TCP_STALL_CYCLES_sum, TA_TA_BUSY_sum, TA_BUFFER_WAVEFRONTS_sum, TD_TD_BUSY_sum, TD_TC_STALL_sum, SPI_CSN_WINDOW_VALID, SPI_CSN_BUSY, CPC_CPC_STAT_BUSY, CPC_CPC_STAT_IDLE, CPF_CPF_STAT_BUSY, CPF_CPF_STAT_STALL, TCC_CYCLE_sum, TCC_BUSY_sum, TCC_PROBE_sum, TCC_PROBE_ALL_sum
+vcopy testing on GCD 0
+Finished allocating vectors on the CPU
+Finished allocating vectors on the GPU
+Finished copying vectors to the GPU
+sw thinks it moved 0.999755 KB per wave 
+Total threads: 1045876, Grid Size: 4086 block Size:256, Wavefronts:16344:
+Launching the  kernel on the GPU
+Finished executing kernel
+Finished copying the output vector from the GPU to the CPU
+Releasing GPU memory
+Releasing CPU memory
+
+ROCPRofiler: 1 contexts collected, output directory /tmp/rpl_data_231005_124649_184043/input0_results_231005_124649
+File 'Baseline_mi100/pmc_perf_0.csv' is generating
+RPL: on '231005_124650' from '/opt/rocm-5.5.1' in '/home1/josantos/omniperf'
+RPL: profiling '""./sample/vcopy 1045876 256""'
+RPL: input file 'Baseline_mi100/perfmon/pmc_perf_6.txt'
+RPL: output dir '/tmp/rpl_data_231005_124650_184225'
+RPL: result dir '/tmp/rpl_data_231005_124650_184225/input0_results_231005_124650'
+ROCProfiler: input from "/tmp/rpl_data_231005_124650_184225/input0.xml"
+  gpu_index = 
+  kernel = 
+  range = 
+  20 metrics
+    SQ_WAVES_SAVED, SQ_INSTS_SMEM_NORM, SQC_TC_INST_REQ, SQC_TC_DATA_READ_REQ, SQC_TC_DATA_WRITE_REQ, SQC_TC_DATA_ATOMIC_REQ, SQC_TC_STALL, SQC_TC_REQ, TCP_TCC_WRITE_REQ_sum, TCP_TCC_ATOMIC_WITH_RET_REQ_sum, TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum, TCP_TCC_NC_READ_REQ_sum, TA_FLAT_WAVEFRONTS_sum, TA_FLAT_READ_WAVEFRONTS_sum, SPI_RA_BAR_CU_FULL_CSN, SPI_RA_TGLIM_CU_FULL_CSN, TCC_EA_ATOMIC_sum, TCC_EA_RDREQ_sum, TCC_EA_RDREQ_32B_sum, TCC_EA_RD_UNCACHED_32B_sum
+vcopy testing on GCD 0
+Finished allocating vectors on the CPU
+Finished allocating vectors on the GPU
+Finished copying vectors to the GPU
+sw thinks it moved 0.999755 KB per wave 
+Total threads: 1045876, Grid Size: 4086 block Size:256, Wavefronts:16344:
+Launching the  kernel on the GPU
+Finished executing kernel
+Finished copying the output vector from the GPU to the CPU
+Releasing GPU memory
+Releasing CPU memory
+
+ROCPRofiler: 1 contexts collected, output directory /tmp/rpl_data_231005_124650_184225/input0_results_231005_124650
+File 'Baseline_mi100/pmc_perf_6.csv' is generating
+RPL: on '231005_124650' from '/opt/rocm-5.5.1' in '/home1/josantos/omniperf'
+RPL: profiling '""./sample/vcopy 1045876 256""'
+RPL: input file 'Baseline_mi100/perfmon/pmc_perf_16.txt'
+RPL: output dir '/tmp/rpl_data_231005_124650_184407'
+RPL: result dir '/tmp/rpl_data_231005_124650_184407/input0_results_231005_124650'
+ROCProfiler: input from "/tmp/rpl_data_231005_124650_184407/input0.xml"
+  gpu_index = 
+  kernel = 
+  range = 
+  96 metrics
+    TCC_RW_REQ[0], TCC_TOO_MANY_EA_WRREQS_STALL[0], TCC_WRITE[0], TCC_RW_REQ[1], TCC_TOO_MANY_EA_WRREQS_STALL[1], TCC_WRITE[1], TCC_RW_REQ[2], TCC_TOO_MANY_EA_WRREQS_STALL[2], TCC_WRITE[2], TCC_RW_REQ[3], TCC_TOO_MANY_EA_WRREQS_STALL[3], TCC_WRITE[3], TCC_RW_REQ[4], TCC_TOO_MANY_EA_WRREQS_STALL[4], TCC_WRITE[4], TCC_RW_REQ[5], TCC_TOO_MANY_EA_WRREQS_STALL[5], TCC_WRITE[5], TCC_RW_REQ[6], TCC_TOO_MANY_EA_WRREQS_STALL[6], TCC_WRITE[6], TCC_RW_REQ[7], TCC_TOO_MANY_EA_WRREQS_STALL[7], TCC_WRITE[7], TCC_RW_REQ[8], TCC_TOO_MANY_EA_WRREQS_STALL[8], TCC_WRITE[8], TCC_RW_REQ[9], TCC_TOO_MANY_EA_WRREQS_STALL[9], TCC_WRITE[9], TCC_RW_REQ[10], TCC_TOO_MANY_EA_WRREQS_STALL[10], TCC_WRITE[10], TCC_RW_REQ[11], TCC_TOO_MANY_EA_WRREQS_STALL[11], TCC_WRITE[11], TCC_RW_REQ[12], TCC_TOO_MANY_EA_WRREQS_STALL[12], TCC_WRITE[12], TCC_RW_REQ[13], TCC_TOO_MANY_EA_WRREQS_STALL[13], TCC_WRITE[13], TCC_RW_REQ[14], TCC_TOO_MANY_EA_WRREQS_STALL[14], TCC_WRITE[14], TCC_RW_REQ[15], TCC_TOO_MANY_EA_WRREQS_STALL[15], TCC_WRITE[15], TCC_RW_REQ[16], TCC_TOO_MANY_EA_WRREQS_STALL[16], TCC_WRITE[16], TCC_RW_REQ[17], TCC_TOO_MANY_EA_WRREQS_STALL[17], TCC_WRITE[17], TCC_RW_REQ[18], TCC_TOO_MANY_EA_WRREQS_STALL[18], TCC_WRITE[18], TCC_RW_REQ[19], TCC_TOO_MANY_EA_WRREQS_STALL[19], TCC_WRITE[19], TCC_RW_REQ[20], TCC_TOO_MANY_EA_WRREQS_STALL[20], TCC_WRITE[20], TCC_RW_REQ[21], TCC_TOO_MANY_EA_WRREQS_STALL[21], TCC_WRITE[21], TCC_RW_REQ[22], TCC_TOO_MANY_EA_WRREQS_STALL[22], TCC_WRITE[22], TCC_RW_REQ[23], TCC_TOO_MANY_EA_WRREQS_STALL[23], TCC_WRITE[23], TCC_RW_REQ[24], TCC_TOO_MANY_EA_WRREQS_STALL[24], TCC_WRITE[24], TCC_RW_REQ[25], TCC_TOO_MANY_EA_WRREQS_STALL[25], TCC_WRITE[25], TCC_RW_REQ[26], TCC_TOO_MANY_EA_WRREQS_STALL[26], TCC_WRITE[26], TCC_RW_REQ[27], TCC_TOO_MANY_EA_WRREQS_STALL[27], TCC_WRITE[27], TCC_RW_REQ[28], TCC_TOO_MANY_EA_WRREQS_STALL[28], TCC_WRITE[28], TCC_RW_REQ[29], TCC_TOO_MANY_EA_WRREQS_STALL[29], TCC_WRITE[29], TCC_RW_REQ[30], TCC_TOO_MANY_EA_WRREQS_STALL[30], TCC_WRITE[30], TCC_RW_REQ[31], TCC_TOO_MANY_EA_WRREQS_STALL[31], TCC_WRITE[31]
+vcopy testing on GCD 0
+Finished allocating vectors on the CPU
+Finished allocating vectors on the GPU
+Finished copying vectors to the GPU
+sw thinks it moved 0.999755 KB per wave 
+Total threads: 1045876, Grid Size: 4086 block Size:256, Wavefronts:16344:
+Launching the  kernel on the GPU
+Finished executing kernel
+Finished copying the output vector from the GPU to the CPU
+Releasing GPU memory
+Releasing CPU memory
+
+ROCPRofiler: 1 contexts collected, output directory /tmp/rpl_data_231005_124650_184407/input0_results_231005_124650
+File 'Baseline_mi100/pmc_perf_16.csv' is generating
+RPL: on '231005_124651' from '/opt/rocm-5.5.1' in '/home1/josantos/omniperf'
+RPL: profiling '""./sample/vcopy 1045876 256""'
+RPL: input file 'Baseline_mi100/perfmon/pmc_perf_4.txt'
+RPL: output dir '/tmp/rpl_data_231005_124651_184589'
+RPL: result dir '/tmp/rpl_data_231005_124651_184589/input0_results_231005_124651'
+ROCProfiler: input from "/tmp/rpl_data_231005_124651_184589/input0.xml"
+  gpu_index = 
+  kernel = 
+  range = 
+  22 metrics
+    SQ_INST_CYCLES_SALU, SQ_THREAD_CYCLES_VALU, SQ_IFETCH, SQ_LDS_BANK_CONFLICT, SQ_LDS_ADDR_CONFLICT, SQ_LDS_UNALIGNED_STALL, SQ_WAVES_EQ_64, SQ_WAVES_LT_64, TCP_UTCL1_TRANSLATION_MISS_sum, TCP_UTCL1_TRANSLATION_HIT_sum, TCP_UTCL1_PERMISSION_MISS_sum, TCP_UTCL1_REQUEST_sum, TA_ADDR_STALLED_BY_TC_CYCLES_sum, TA_TOTAL_WAVEFRONTS_sum, SPI_RA_WAVE_SIMD_FULL_CSN, SPI_RA_VGPR_SIMD_FULL_CSN, CPC_CPC_UTCL2IU_STALL, CPC_ME1_BUSY_FOR_PACKET_DECODE, TCC_EA_WRREQ_sum, TCC_EA_WRREQ_64B_sum, TCC_EA_WR_UNCACHED_32B_sum, TCC_EA_WRREQ_STALL_sum
+vcopy testing on GCD 0
+Finished allocating vectors on the CPU
+Finished allocating vectors on the GPU
+Finished copying vectors to the GPU
+sw thinks it moved 0.999755 KB per wave 
+Total threads: 1045876, Grid Size: 4086 block Size:256, Wavefronts:16344:
+Launching the  kernel on the GPU
+Finished executing kernel
+Finished copying the output vector from the GPU to the CPU
+Releasing GPU memory
+Releasing CPU memory
+
+ROCPRofiler: 1 contexts collected, output directory /tmp/rpl_data_231005_124651_184589/input0_results_231005_124651
+File 'Baseline_mi100/pmc_perf_4.csv' is generating
+RPL: on '231005_124651' from '/opt/rocm-5.5.1' in '/home1/josantos/omniperf'
+RPL: profiling '""./sample/vcopy 1045876 256""'
+RPL: input file 'Baseline_mi100/perfmon/SQ_LEVEL_WAVES.txt'
+RPL: output dir '/tmp/rpl_data_231005_124651_184771'
+RPL: result dir '/tmp/rpl_data_231005_124651_184771/input0_results_231005_124651'
+ROCProfiler: input from "/tmp/rpl_data_231005_124651_184771/input0.xml"
+  gpu_index = 
+  kernel = 
+  range = 
+  9 metrics
+    GRBM_COUNT, GRBM_GUI_ACTIVE, CPC_ME1_BUSY_FOR_PACKET_DECODE, SQ_CYCLES, SQ_WAVES, SQ_WAVE_CYCLES, SQ_BUSY_CYCLES, SQ_LEVEL_WAVES, SQ_ACCUM_PREV_HIRES
+vcopy testing on GCD 0
+Finished allocating vectors on the CPU
+Finished allocating vectors on the GPU
+Finished copying vectors to the GPU
+sw thinks it moved 0.999755 KB per wave 
+Total threads: 1045876, Grid Size: 4086 block Size:256, Wavefronts:16344:
+Launching the  kernel on the GPU
+Finished executing kernel
+Finished copying the output vector from the GPU to the CPU
+Releasing GPU memory
+Releasing CPU memory
+
+ROCPRofiler: 1 contexts collected, output directory /tmp/rpl_data_231005_124651_184771/input0_results_231005_124651
+File 'Baseline_mi100/SQ_LEVEL_WAVES.csv' is generating
+RPL: on '231005_124652' from '/opt/rocm-5.5.1' in '/home1/josantos/omniperf'
+RPL: profiling '""./sample/vcopy 1045876 256""'
+RPL: input file 'Baseline_mi100/perfmon/pmc_perf_2.txt'
+RPL: output dir '/tmp/rpl_data_231005_124652_184953'
+RPL: result dir '/tmp/rpl_data_231005_124652_184953/input0_results_231005_124652'
+ROCProfiler: input from "/tmp/rpl_data_231005_124652_184953/input0.xml"
+  gpu_index = 
+  kernel = 
+  range = 
+  26 metrics
+    SQ_INSTS_SENDMSG, SQ_INSTS, SQ_WAIT_ANY, SQ_WAIT_INST_ANY, SQ_ACTIVE_INST_ANY, SQ_INSTS_VALU, SQ_ACTIVE_INST_VMEM, SQ_ACTIVE_INST_LDS, TCP_VOLATILE_sum, TCP_TOTAL_ACCESSES_sum, TCP_TOTAL_READ_sum, TCP_TOTAL_WRITE_sum, TA_BUFFER_ATOMIC_WAVEFRONTS_sum, TA_BUFFER_TOTAL_CYCLES_sum, TD_ATOMIC_WAVEFRONT_sum, TD_STORE_WAVEFRONT_sum, SPI_RA_REQ_NO_ALLOC, SPI_RA_REQ_NO_ALLOC_CSN, CPC_CPC_STAT_STALL, CPC_UTCL1_STALL_ON_TRANSLATION, CPF_CPF_STAT_IDLE, CPF_CPF_TCIU_IDLE, TCC_REQ_sum, TCC_STREAMING_REQ_sum, TCC_HIT_sum, TCC_MISS_sum
+vcopy testing on GCD 0
+Finished allocating vectors on the CPU
+Finished allocating vectors on the GPU
+Finished copying vectors to the GPU
+sw thinks it moved 0.999755 KB per wave 
+Total threads: 1045876, Grid Size: 4086 block Size:256, Wavefronts:16344:
+Launching the  kernel on the GPU
+Finished executing kernel
+Finished copying the output vector from the GPU to the CPU
+Releasing GPU memory
+Releasing CPU memory
+
+ROCPRofiler: 1 contexts collected, output directory /tmp/rpl_data_231005_124652_184953/input0_results_231005_124652
+File 'Baseline_mi100/pmc_perf_2.csv' is generating
+RPL: on '231005_124652' from '/opt/rocm-5.5.1' in '/home1/josantos/omniperf'
+RPL: profiling '""./sample/vcopy 1045876 256""'
+RPL: input file 'Baseline_mi100/perfmon/pmc_perf_3.txt'
+RPL: output dir '/tmp/rpl_data_231005_124652_185135'
+RPL: result dir '/tmp/rpl_data_231005_124652_185135/input0_results_231005_124652'
+ROCProfiler: input from "/tmp/rpl_data_231005_124652_185135/input0.xml"
+  gpu_index = 
+  kernel = 
+  range = 
+  23 metrics
+    SQ_ACTIVE_INST_VALU, SQ_ACTIVE_INST_SCA, SQ_ACTIVE_INST_EXP_GDS, SQ_ACTIVE_INST_MISC, SQ_ACTIVE_INST_FLAT, SQ_INST_CYCLES_VMEM_WR, SQ_INST_CYCLES_VMEM_RD, SQ_INST_CYCLES_SMEM, TCP_TOTAL_ATOMIC_WITH_RET_sum, TCP_TOTAL_ATOMIC_WITHOUT_RET_sum, TCP_TOTAL_WRITEBACK_INVALIDATES_sum, TCP_TOTAL_CACHE_ACCESSES_sum, TA_BUFFER_COALESCED_READ_CYCLES_sum, TA_BUFFER_COALESCED_WRITE_CYCLES_sum, SPI_RA_RES_STALL_CSN, SPI_RA_TMP_STALL_CSN, CPC_CPC_UTCL2IU_BUSY, CPC_CPC_UTCL2IU_IDLE, CPF_CMP_UTCL1_STALL_ON_TRANSLATION, TCC_READ_sum, TCC_WRITE_sum, TCC_ATOMIC_sum, TCC_WRITEBACK_sum
+vcopy testing on GCD 0
+Finished allocating vectors on the CPU
+Finished allocating vectors on the GPU
+Finished copying vectors to the GPU
+sw thinks it moved 0.999755 KB per wave 
+Total threads: 1045876, Grid Size: 4086 block Size:256, Wavefronts:16344:
+Launching the  kernel on the GPU
+Finished executing kernel
+Finished copying the output vector from the GPU to the CPU
+Releasing GPU memory
+Releasing CPU memory
+
+ROCPRofiler: 1 contexts collected, output directory /tmp/rpl_data_231005_124652_185135/input0_results_231005_124652
+File 'Baseline_mi100/pmc_perf_3.csv' is generating
+RPL: on '231005_124653' from '/opt/rocm-5.5.1' in '/home1/josantos/omniperf'
+RPL: profiling '""./sample/vcopy 1045876 256""'
+RPL: input file 'Baseline_mi100/perfmon/pmc_perf_10.txt'
+RPL: output dir '/tmp/rpl_data_231005_124653_185317'
+RPL: result dir '/tmp/rpl_data_231005_124653_185317/input0_results_231005_124653'
+ROCProfiler: input from "/tmp/rpl_data_231005_124653_185317/input0.xml"
+  gpu_index = 
+  kernel = 
+  range = 
+  1 metrics
+    TCC_EA_ATOMIC_LEVEL_sum
+vcopy testing on GCD 0
+Finished allocating vectors on the CPU
+Finished allocating vectors on the GPU
+Finished copying vectors to the GPU
+sw thinks it moved 0.999755 KB per wave 
+Total threads: 1045876, Grid Size: 4086 block Size:256, Wavefronts:16344:
+Launching the  kernel on the GPU
+Finished executing kernel
+Finished copying the output vector from the GPU to the CPU
+Releasing GPU memory
+Releasing CPU memory
+
+ROCPRofiler: 1 contexts collected, output directory /tmp/rpl_data_231005_124653_185317/input0_results_231005_124653
+File 'Baseline_mi100/pmc_perf_10.csv' is generating
+RPL: on '231005_124653' from '/opt/rocm-5.5.1' in '/home1/josantos/omniperf'
+RPL: profiling '""./sample/vcopy 1045876 256""'
+RPL: input file 'Baseline_mi100/perfmon/pmc_perf_5.txt'
+RPL: output dir '/tmp/rpl_data_231005_124653_185499'
+RPL: result dir '/tmp/rpl_data_231005_124653_185499/input0_results_231005_124653'
+ROCProfiler: input from "/tmp/rpl_data_231005_124653_185499/input0.xml"
+  gpu_index = 
+  kernel = 
+  range = 
+  21 metrics
+    SQ_WAVES_LT_48, SQ_WAVES_LT_32, SQ_WAVES_LT_16, SQ_ITEMS, SQ_LDS_MEM_VIOLATIONS, SQ_LDS_ATOMIC_RETURN, SQ_LDS_IDX_ACTIVE, SQ_WAVES_RESTORED, TCP_TCP_LATENCY_sum, TCP_TCC_READ_REQ_LATENCY_sum, TCP_TCC_WRITE_REQ_LATENCY_sum, TCP_TCC_READ_REQ_sum, TA_ADDR_STALLED_BY_TD_CYCLES_sum, TA_DATA_STALLED_BY_TC_CYCLES_sum, SPI_RA_SGPR_SIMD_FULL_CSN, SPI_RA_LDS_CU_FULL_CSN, CPC_ME1_DC0_SPI_BUSY, TCC_EA_WRREQ_IO_CREDIT_STALL_sum, TCC_EA_WRREQ_GMI_CREDIT_STALL_sum, TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum, TCC_TOO_MANY_EA_WRREQS_STALL_sum
+vcopy testing on GCD 0
+Finished allocating vectors on the CPU
+Finished allocating vectors on the GPU
+Finished copying vectors to the GPU
+sw thinks it moved 0.999755 KB per wave 
+Total threads: 1045876, Grid Size: 4086 block Size:256, Wavefronts:16344:
+Launching the  kernel on the GPU
+Finished executing kernel
+Finished copying the output vector from the GPU to the CPU
+Releasing GPU memory
+Releasing CPU memory
+
+ROCPRofiler: 1 contexts collected, output directory /tmp/rpl_data_231005_124653_185499/input0_results_231005_124653
+File 'Baseline_mi100/pmc_perf_5.csv' is generating
+RPL: on '231005_124654' from '/opt/rocm-5.5.1' in '/home1/josantos/omniperf'
+RPL: profiling '""./sample/vcopy 1045876 256""'
+RPL: input file 'Baseline_mi100/perfmon/pmc_perf_13.txt'
+RPL: output dir '/tmp/rpl_data_231005_124654_185681'
+RPL: result dir '/tmp/rpl_data_231005_124654_185681/input0_results_231005_124654'
+ROCProfiler: input from "/tmp/rpl_data_231005_124654_185681/input0.xml"
+  gpu_index = 
+  kernel = 
+  range = 
+  128 metrics
+    TCC_EA_RDREQ_IO_CREDIT_STALL[0], TCC_EA_RDREQ_LEVEL[0], TCC_EA_WRREQ[0], TCC_EA_WRREQ_64B[0], TCC_EA_RDREQ_IO_CREDIT_STALL[1], TCC_EA_RDREQ_LEVEL[1], TCC_EA_WRREQ[1], TCC_EA_WRREQ_64B[1], TCC_EA_RDREQ_IO_CREDIT_STALL[2], TCC_EA_RDREQ_LEVEL[2], TCC_EA_WRREQ[2], TCC_EA_WRREQ_64B[2], TCC_EA_RDREQ_IO_CREDIT_STALL[3], TCC_EA_RDREQ_LEVEL[3], TCC_EA_WRREQ[3], TCC_EA_WRREQ_64B[3], TCC_EA_RDREQ_IO_CREDIT_STALL[4], TCC_EA_RDREQ_LEVEL[4], TCC_EA_WRREQ[4], TCC_EA_WRREQ_64B[4], TCC_EA_RDREQ_IO_CREDIT_STALL[5], TCC_EA_RDREQ_LEVEL[5], TCC_EA_WRREQ[5], TCC_EA_WRREQ_64B[5], TCC_EA_RDREQ_IO_CREDIT_STALL[6], TCC_EA_RDREQ_LEVEL[6], TCC_EA_WRREQ[6], TCC_EA_WRREQ_64B[6], TCC_EA_RDREQ_IO_CREDIT_STALL[7], TCC_EA_RDREQ_LEVEL[7], TCC_EA_WRREQ[7], TCC_EA_WRREQ_64B[7], TCC_EA_RDREQ_IO_CREDIT_STALL[8], TCC_EA_RDREQ_LEVEL[8], TCC_EA_WRREQ[8], TCC_EA_WRREQ_64B[8], TCC_EA_RDREQ_IO_CREDIT_STALL[9], TCC_EA_RDREQ_LEVEL[9], TCC_EA_WRREQ[9], TCC_EA_WRREQ_64B[9], TCC_EA_RDREQ_IO_CREDIT_STALL[10], TCC_EA_RDREQ_LEVEL[10], TCC_EA_WRREQ[10], TCC_EA_WRREQ_64B[10], TCC_EA_RDREQ_IO_CREDIT_STALL[11], TCC_EA_RDREQ_LEVEL[11], TCC_EA_WRREQ[11], TCC_EA_WRREQ_64B[11], TCC_EA_RDREQ_IO_CREDIT_STALL[12], TCC_EA_RDREQ_LEVEL[12], TCC_EA_WRREQ[12], TCC_EA_WRREQ_64B[12], TCC_EA_RDREQ_IO_CREDIT_STALL[13], TCC_EA_RDREQ_LEVEL[13], TCC_EA_WRREQ[13], TCC_EA_WRREQ_64B[13], TCC_EA_RDREQ_IO_CREDIT_STALL[14], TCC_EA_RDREQ_LEVEL[14], TCC_EA_WRREQ[14], TCC_EA_WRREQ_64B[14], TCC_EA_RDREQ_IO_CREDIT_STALL[15], TCC_EA_RDREQ_LEVEL[15], TCC_EA_WRREQ[15], TCC_EA_WRREQ_64B[15], TCC_EA_RDREQ_IO_CREDIT_STALL[16], TCC_EA_RDREQ_LEVEL[16], TCC_EA_WRREQ[16], TCC_EA_WRREQ_64B[16], TCC_EA_RDREQ_IO_CREDIT_STALL[17], TCC_EA_RDREQ_LEVEL[17], TCC_EA_WRREQ[17], TCC_EA_WRREQ_64B[17], TCC_EA_RDREQ_IO_CREDIT_STALL[18], TCC_EA_RDREQ_LEVEL[18], TCC_EA_WRREQ[18], TCC_EA_WRREQ_64B[18], TCC_EA_RDREQ_IO_CREDIT_STALL[19], TCC_EA_RDREQ_LEVEL[19], TCC_EA_WRREQ[19], TCC_EA_WRREQ_64B[19], TCC_EA_RDREQ_IO_CREDIT_STALL[20], TCC_EA_RDREQ_LEVEL[20], TCC_EA_WRREQ[20], TCC_EA_WRREQ_64B[20], TCC_EA_RDREQ_IO_CREDIT_STALL[21], TCC_EA_RDREQ_LEVEL[21], TCC_EA_WRREQ[21], TCC_EA_WRREQ_64B[21], TCC_EA_RDREQ_IO_CREDIT_STALL[22], TCC_EA_RDREQ_LEVEL[22], TCC_EA_WRREQ[22], TCC_EA_WRREQ_64B[22], TCC_EA_RDREQ_IO_CREDIT_STALL[23], TCC_EA_RDREQ_LEVEL[23], TCC_EA_WRREQ[23], TCC_EA_WRREQ_64B[23], TCC_EA_RDREQ_IO_CREDIT_STALL[24], TCC_EA_RDREQ_LEVEL[24], TCC_EA_WRREQ[24], TCC_EA_WRREQ_64B[24], TCC_EA_RDREQ_IO_CREDIT_STALL[25], TCC_EA_RDREQ_LEVEL[25], TCC_EA_WRREQ[25], TCC_EA_WRREQ_64B[25], TCC_EA_RDREQ_IO_CREDIT_STALL[26], TCC_EA_RDREQ_LEVEL[26], TCC_EA_WRREQ[26], TCC_EA_WRREQ_64B[26], TCC_EA_RDREQ_IO_CREDIT_STALL[27], TCC_EA_RDREQ_LEVEL[27], TCC_EA_WRREQ[27], TCC_EA_WRREQ_64B[27], TCC_EA_RDREQ_IO_CREDIT_STALL[28], TCC_EA_RDREQ_LEVEL[28], TCC_EA_WRREQ[28], TCC_EA_WRREQ_64B[28], TCC_EA_RDREQ_IO_CREDIT_STALL[29], TCC_EA_RDREQ_LEVEL[29], TCC_EA_WRREQ[29], TCC_EA_WRREQ_64B[29], TCC_EA_RDREQ_IO_CREDIT_STALL[30], TCC_EA_RDREQ_LEVEL[30], TCC_EA_WRREQ[30], TCC_EA_WRREQ_64B[30], TCC_EA_RDREQ_IO_CREDIT_STALL[31], TCC_EA_RDREQ_LEVEL[31], TCC_EA_WRREQ[31], TCC_EA_WRREQ_64B[31]
+vcopy testing on GCD 0
+Finished allocating vectors on the CPU
+Finished allocating vectors on the GPU
+Finished copying vectors to the GPU
+sw thinks it moved 0.999755 KB per wave 
+Total threads: 1045876, Grid Size: 4086 block Size:256, Wavefronts:16344:
+Launching the  kernel on the GPU
+Finished executing kernel
+Finished copying the output vector from the GPU to the CPU
+Releasing GPU memory
+Releasing CPU memory
+
+ROCPRofiler: 1 contexts collected, output directory /tmp/rpl_data_231005_124654_185681/input0_results_231005_124654
+File 'Baseline_mi100/pmc_perf_13.csv' is generating
+RPL: on '231005_124654' from '/opt/rocm-5.5.1' in '/home1/josantos/omniperf'
+RPL: profiling '""./sample/vcopy 1045876 256""'
+RPL: input file 'Baseline_mi100/perfmon/pmc_perf_14.txt'
+RPL: output dir '/tmp/rpl_data_231005_124654_185863'
+RPL: result dir '/tmp/rpl_data_231005_124654_185863/input0_results_231005_124654'
+ROCProfiler: input from "/tmp/rpl_data_231005_124654_185863/input0.xml"
+  gpu_index = 
+  kernel = 
+  range = 
+  128 metrics
+    TCC_EA_WRREQ_DRAM_CREDIT_STALL[0], TCC_EA_WRREQ_GMI_CREDIT_STALL[0], TCC_EA_WRREQ_IO_CREDIT_STALL[0], TCC_EA_WRREQ_LEVEL[0], TCC_EA_WRREQ_DRAM_CREDIT_STALL[1], TCC_EA_WRREQ_GMI_CREDIT_STALL[1], TCC_EA_WRREQ_IO_CREDIT_STALL[1], TCC_EA_WRREQ_LEVEL[1], TCC_EA_WRREQ_DRAM_CREDIT_STALL[2], TCC_EA_WRREQ_GMI_CREDIT_STALL[2], TCC_EA_WRREQ_IO_CREDIT_STALL[2], TCC_EA_WRREQ_LEVEL[2], TCC_EA_WRREQ_DRAM_CREDIT_STALL[3], TCC_EA_WRREQ_GMI_CREDIT_STALL[3], TCC_EA_WRREQ_IO_CREDIT_STALL[3], TCC_EA_WRREQ_LEVEL[3], TCC_EA_WRREQ_DRAM_CREDIT_STALL[4], TCC_EA_WRREQ_GMI_CREDIT_STALL[4], TCC_EA_WRREQ_IO_CREDIT_STALL[4], TCC_EA_WRREQ_LEVEL[4], TCC_EA_WRREQ_DRAM_CREDIT_STALL[5], TCC_EA_WRREQ_GMI_CREDIT_STALL[5], TCC_EA_WRREQ_IO_CREDIT_STALL[5], TCC_EA_WRREQ_LEVEL[5], TCC_EA_WRREQ_DRAM_CREDIT_STALL[6], TCC_EA_WRREQ_GMI_CREDIT_STALL[6], TCC_EA_WRREQ_IO_CREDIT_STALL[6], TCC_EA_WRREQ_LEVEL[6], TCC_EA_WRREQ_DRAM_CREDIT_STALL[7], TCC_EA_WRREQ_GMI_CREDIT_STALL[7], TCC_EA_WRREQ_IO_CREDIT_STALL[7], TCC_EA_WRREQ_LEVEL[7], TCC_EA_WRREQ_DRAM_CREDIT_STALL[8], TCC_EA_WRREQ_GMI_CREDIT_STALL[8], TCC_EA_WRREQ_IO_CREDIT_STALL[8], TCC_EA_WRREQ_LEVEL[8], TCC_EA_WRREQ_DRAM_CREDIT_STALL[9], TCC_EA_WRREQ_GMI_CREDIT_STALL[9], TCC_EA_WRREQ_IO_CREDIT_STALL[9], TCC_EA_WRREQ_LEVEL[9], TCC_EA_WRREQ_DRAM_CREDIT_STALL[10], TCC_EA_WRREQ_GMI_CREDIT_STALL[10], TCC_EA_WRREQ_IO_CREDIT_STALL[10], TCC_EA_WRREQ_LEVEL[10], TCC_EA_WRREQ_DRAM_CREDIT_STALL[11], TCC_EA_WRREQ_GMI_CREDIT_STALL[11], TCC_EA_WRREQ_IO_CREDIT_STALL[11], TCC_EA_WRREQ_LEVEL[11], TCC_EA_WRREQ_DRAM_CREDIT_STALL[12], TCC_EA_WRREQ_GMI_CREDIT_STALL[12], TCC_EA_WRREQ_IO_CREDIT_STALL[12], TCC_EA_WRREQ_LEVEL[12], TCC_EA_WRREQ_DRAM_CREDIT_STALL[13], TCC_EA_WRREQ_GMI_CREDIT_STALL[13], TCC_EA_WRREQ_IO_CREDIT_STALL[13], TCC_EA_WRREQ_LEVEL[13], TCC_EA_WRREQ_DRAM_CREDIT_STALL[14], TCC_EA_WRREQ_GMI_CREDIT_STALL[14], TCC_EA_WRREQ_IO_CREDIT_STALL[14], TCC_EA_WRREQ_LEVEL[14], TCC_EA_WRREQ_DRAM_CREDIT_STALL[15], TCC_EA_WRREQ_GMI_CREDIT_STALL[15], TCC_EA_WRREQ_IO_CREDIT_STALL[15], TCC_EA_WRREQ_LEVEL[15], TCC_EA_WRREQ_DRAM_CREDIT_STALL[16], TCC_EA_WRREQ_GMI_CREDIT_STALL[16], TCC_EA_WRREQ_IO_CREDIT_STALL[16], TCC_EA_WRREQ_LEVEL[16], TCC_EA_WRREQ_DRAM_CREDIT_STALL[17], TCC_EA_WRREQ_GMI_CREDIT_STALL[17], TCC_EA_WRREQ_IO_CREDIT_STALL[17], TCC_EA_WRREQ_LEVEL[17], TCC_EA_WRREQ_DRAM_CREDIT_STALL[18], TCC_EA_WRREQ_GMI_CREDIT_STALL[18], TCC_EA_WRREQ_IO_CREDIT_STALL[18], TCC_EA_WRREQ_LEVEL[18], TCC_EA_WRREQ_DRAM_CREDIT_STALL[19], TCC_EA_WRREQ_GMI_CREDIT_STALL[19], TCC_EA_WRREQ_IO_CREDIT_STALL[19], TCC_EA_WRREQ_LEVEL[19], TCC_EA_WRREQ_DRAM_CREDIT_STALL[20], TCC_EA_WRREQ_GMI_CREDIT_STALL[20], TCC_EA_WRREQ_IO_CREDIT_STALL[20], TCC_EA_WRREQ_LEVEL[20], TCC_EA_WRREQ_DRAM_CREDIT_STALL[21], TCC_EA_WRREQ_GMI_CREDIT_STALL[21], TCC_EA_WRREQ_IO_CREDIT_STALL[21], TCC_EA_WRREQ_LEVEL[21], TCC_EA_WRREQ_DRAM_CREDIT_STALL[22], TCC_EA_WRREQ_GMI_CREDIT_STALL[22], TCC_EA_WRREQ_IO_CREDIT_STALL[22], TCC_EA_WRREQ_LEVEL[22], TCC_EA_WRREQ_DRAM_CREDIT_STALL[23], TCC_EA_WRREQ_GMI_CREDIT_STALL[23], TCC_EA_WRREQ_IO_CREDIT_STALL[23], TCC_EA_WRREQ_LEVEL[23], TCC_EA_WRREQ_DRAM_CREDIT_STALL[24], TCC_EA_WRREQ_GMI_CREDIT_STALL[24], TCC_EA_WRREQ_IO_CREDIT_STALL[24], TCC_EA_WRREQ_LEVEL[24], TCC_EA_WRREQ_DRAM_CREDIT_STALL[25], TCC_EA_WRREQ_GMI_CREDIT_STALL[25], TCC_EA_WRREQ_IO_CREDIT_STALL[25], TCC_EA_WRREQ_LEVEL[25], TCC_EA_WRREQ_DRAM_CREDIT_STALL[26], TCC_EA_WRREQ_GMI_CREDIT_STALL[26], TCC_EA_WRREQ_IO_CREDIT_STALL[26], TCC_EA_WRREQ_LEVEL[26], TCC_EA_WRREQ_DRAM_CREDIT_STALL[27], TCC_EA_WRREQ_GMI_CREDIT_STALL[27], TCC_EA_WRREQ_IO_CREDIT_STALL[27], TCC_EA_WRREQ_LEVEL[27], TCC_EA_WRREQ_DRAM_CREDIT_STALL[28], TCC_EA_WRREQ_GMI_CREDIT_STALL[28], TCC_EA_WRREQ_IO_CREDIT_STALL[28], TCC_EA_WRREQ_LEVEL[28], TCC_EA_WRREQ_DRAM_CREDIT_STALL[29], TCC_EA_WRREQ_GMI_CREDIT_STALL[29], TCC_EA_WRREQ_IO_CREDIT_STALL[29], TCC_EA_WRREQ_LEVEL[29], TCC_EA_WRREQ_DRAM_CREDIT_STALL[30], TCC_EA_WRREQ_GMI_CREDIT_STALL[30], TCC_EA_WRREQ_IO_CREDIT_STALL[30], TCC_EA_WRREQ_LEVEL[30], TCC_EA_WRREQ_DRAM_CREDIT_STALL[31], TCC_EA_WRREQ_GMI_CREDIT_STALL[31], TCC_EA_WRREQ_IO_CREDIT_STALL[31], TCC_EA_WRREQ_LEVEL[31]
+vcopy testing on GCD 0
+Finished allocating vectors on the CPU
+Finished allocating vectors on the GPU
+Finished copying vectors to the GPU
+sw thinks it moved 0.999755 KB per wave 
+Total threads: 1045876, Grid Size: 4086 block Size:256, Wavefronts:16344:
+Launching the  kernel on the GPU
+Finished executing kernel
+Finished copying the output vector from the GPU to the CPU
+Releasing GPU memory
+Releasing CPU memory
+
+ROCPRofiler: 1 contexts collected, output directory /tmp/rpl_data_231005_124654_185863/input0_results_231005_124654
+File 'Baseline_mi100/pmc_perf_14.csv' is generating
+RPL: on '231005_124655' from '/opt/rocm-5.5.1' in '/home1/josantos/omniperf'
+RPL: profiling '""./sample/vcopy 1045876 256""'
+RPL: input file 'Baseline_mi100/perfmon/SQ_INST_LEVEL_VMEM.txt'
+RPL: output dir '/tmp/rpl_data_231005_124655_186045'
+RPL: result dir '/tmp/rpl_data_231005_124655_186045/input0_results_231005_124655'
+ROCProfiler: input from "/tmp/rpl_data_231005_124655_186045/input0.xml"
+  gpu_index = 
+  kernel = 
+  range = 
+  3 metrics
+    SQ_INSTS_VMEM, SQ_INST_LEVEL_VMEM, SQ_ACCUM_PREV_HIRES
+vcopy testing on GCD 0
+Finished allocating vectors on the CPU
+Finished allocating vectors on the GPU
+Finished copying vectors to the GPU
+sw thinks it moved 0.999755 KB per wave 
+Total threads: 1045876, Grid Size: 4086 block Size:256, Wavefronts:16344:
+Launching the  kernel on the GPU
+Finished executing kernel
+Finished copying the output vector from the GPU to the CPU
+Releasing GPU memory
+Releasing CPU memory
+
+ROCPRofiler: 1 contexts collected, output directory /tmp/rpl_data_231005_124655_186045/input0_results_231005_124655
+File 'Baseline_mi100/SQ_INST_LEVEL_VMEM.csv' is generating
+RPL: on '231005_124655' from '/opt/rocm-5.5.1' in '/home1/josantos/omniperf'
+RPL: profiling '""./sample/vcopy 1045876 256""'
+RPL: input file 'Baseline_mi100/perfmon/SQ_INST_LEVEL_SMEM.txt'
+RPL: output dir '/tmp/rpl_data_231005_124655_186228'
+RPL: result dir '/tmp/rpl_data_231005_124655_186228/input0_results_231005_124655'
+ROCProfiler: input from "/tmp/rpl_data_231005_124655_186228/input0.xml"
+  gpu_index = 
+  kernel = 
+  range = 
+  3 metrics
+    SQ_INSTS_SMEM, SQ_INST_LEVEL_SMEM, SQ_ACCUM_PREV_HIRES
+vcopy testing on GCD 0
+Finished allocating vectors on the CPU
+Finished allocating vectors on the GPU
+Finished copying vectors to the GPU
+sw thinks it moved 0.999755 KB per wave 
+Total threads: 1045876, Grid Size: 4086 block Size:256, Wavefronts:16344:
+Launching the  kernel on the GPU
+Finished executing kernel
+Finished copying the output vector from the GPU to the CPU
+Releasing GPU memory
+Releasing CPU memory
+
+ROCPRofiler: 1 contexts collected, output directory /tmp/rpl_data_231005_124655_186228/input0_results_231005_124655
+File 'Baseline_mi100/SQ_INST_LEVEL_SMEM.csv' is generating
+RPL: on '231005_124656' from '/opt/rocm-5.5.1' in '/home1/josantos/omniperf'
+RPL: profiling '""./sample/vcopy 1045876 256""'
+RPL: input file 'Baseline_mi100/perfmon/pmc_perf_11.txt'
+RPL: output dir '/tmp/rpl_data_231005_124656_186410'
+RPL: result dir '/tmp/rpl_data_231005_124656_186410/input0_results_231005_124656'
+ROCProfiler: input from "/tmp/rpl_data_231005_124656_186410/input0.xml"
+  gpu_index = 
+  kernel = 
+  range = 
+  128 metrics
+    TCC_ATOMIC[0], TCC_CYCLE[0], TCC_EA_ATOMIC[0], TCC_EA_ATOMIC_LEVEL[0], TCC_ATOMIC[1], TCC_CYCLE[1], TCC_EA_ATOMIC[1], TCC_EA_ATOMIC_LEVEL[1], TCC_ATOMIC[2], TCC_CYCLE[2], TCC_EA_ATOMIC[2], TCC_EA_ATOMIC_LEVEL[2], TCC_ATOMIC[3], TCC_CYCLE[3], TCC_EA_ATOMIC[3], TCC_EA_ATOMIC_LEVEL[3], TCC_ATOMIC[4], TCC_CYCLE[4], TCC_EA_ATOMIC[4], TCC_EA_ATOMIC_LEVEL[4], TCC_ATOMIC[5], TCC_CYCLE[5], TCC_EA_ATOMIC[5], TCC_EA_ATOMIC_LEVEL[5], TCC_ATOMIC[6], TCC_CYCLE[6], TCC_EA_ATOMIC[6], TCC_EA_ATOMIC_LEVEL[6], TCC_ATOMIC[7], TCC_CYCLE[7], TCC_EA_ATOMIC[7], TCC_EA_ATOMIC_LEVEL[7], TCC_ATOMIC[8], TCC_CYCLE[8], TCC_EA_ATOMIC[8], TCC_EA_ATOMIC_LEVEL[8], TCC_ATOMIC[9], TCC_CYCLE[9], TCC_EA_ATOMIC[9], TCC_EA_ATOMIC_LEVEL[9], TCC_ATOMIC[10], TCC_CYCLE[10], TCC_EA_ATOMIC[10], TCC_EA_ATOMIC_LEVEL[10], TCC_ATOMIC[11], TCC_CYCLE[11], TCC_EA_ATOMIC[11], TCC_EA_ATOMIC_LEVEL[11], TCC_ATOMIC[12], TCC_CYCLE[12], TCC_EA_ATOMIC[12], TCC_EA_ATOMIC_LEVEL[12], TCC_ATOMIC[13], TCC_CYCLE[13], TCC_EA_ATOMIC[13], TCC_EA_ATOMIC_LEVEL[13], TCC_ATOMIC[14], TCC_CYCLE[14], TCC_EA_ATOMIC[14], TCC_EA_ATOMIC_LEVEL[14], TCC_ATOMIC[15], TCC_CYCLE[15], TCC_EA_ATOMIC[15], TCC_EA_ATOMIC_LEVEL[15], TCC_ATOMIC[16], TCC_CYCLE[16], TCC_EA_ATOMIC[16], TCC_EA_ATOMIC_LEVEL[16], TCC_ATOMIC[17], TCC_CYCLE[17], TCC_EA_ATOMIC[17], TCC_EA_ATOMIC_LEVEL[17], TCC_ATOMIC[18], TCC_CYCLE[18], TCC_EA_ATOMIC[18], TCC_EA_ATOMIC_LEVEL[18], TCC_ATOMIC[19], TCC_CYCLE[19], TCC_EA_ATOMIC[19], TCC_EA_ATOMIC_LEVEL[19], TCC_ATOMIC[20], TCC_CYCLE[20], TCC_EA_ATOMIC[20], TCC_EA_ATOMIC_LEVEL[20], TCC_ATOMIC[21], TCC_CYCLE[21], TCC_EA_ATOMIC[21], TCC_EA_ATOMIC_LEVEL[21], TCC_ATOMIC[22], TCC_CYCLE[22], TCC_EA_ATOMIC[22], TCC_EA_ATOMIC_LEVEL[22], TCC_ATOMIC[23], TCC_CYCLE[23], TCC_EA_ATOMIC[23], TCC_EA_ATOMIC_LEVEL[23], TCC_ATOMIC[24], TCC_CYCLE[24], TCC_EA_ATOMIC[24], TCC_EA_ATOMIC_LEVEL[24], TCC_ATOMIC[25], TCC_CYCLE[25], TCC_EA_ATOMIC[25], TCC_EA_ATOMIC_LEVEL[25], TCC_ATOMIC[26], TCC_CYCLE[26], TCC_EA_ATOMIC[26], TCC_EA_ATOMIC_LEVEL[26], TCC_ATOMIC[27], TCC_CYCLE[27], TCC_EA_ATOMIC[27], TCC_EA_ATOMIC_LEVEL[27], TCC_ATOMIC[28], TCC_CYCLE[28], TCC_EA_ATOMIC[28], TCC_EA_ATOMIC_LEVEL[28], TCC_ATOMIC[29], TCC_CYCLE[29], TCC_EA_ATOMIC[29], TCC_EA_ATOMIC_LEVEL[29], TCC_ATOMIC[30], TCC_CYCLE[30], TCC_EA_ATOMIC[30], TCC_EA_ATOMIC_LEVEL[30], TCC_ATOMIC[31], TCC_CYCLE[31], TCC_EA_ATOMIC[31], TCC_EA_ATOMIC_LEVEL[31]
+vcopy testing on GCD 0
+Finished allocating vectors on the CPU
+Finished allocating vectors on the GPU
+Finished copying vectors to the GPU
+sw thinks it moved 0.999755 KB per wave 
+Total threads: 1045876, Grid Size: 4086 block Size:256, Wavefronts:16344:
+Launching the  kernel on the GPU
+Finished executing kernel
+Finished copying the output vector from the GPU to the CPU
+Releasing GPU memory
+Releasing CPU memory
+
+ROCPRofiler: 1 contexts collected, output directory /tmp/rpl_data_231005_124656_186410/input0_results_231005_124656
+File 'Baseline_mi100/pmc_perf_11.csv' is generating
+Successfully joined gpu in pmc_perf.csv
+Successfully joined grd in pmc_perf.csv
+Successfully joined Workgroup_Size in pmc_perf.csv
+Successfully joined LDS_Per_Workgroup in pmc_perf.csv
+Successfully joined scr in pmc_perf.csv
+Successfully joined spgr in pmc_perf.csv
+Successfully joined arch_vgpr in pmc_perf.csv
+Successfully joined accum_vgpr in pmc_perf.csv
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/perfmon/SQ_IFETCH_LEVEL.txt b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/perfmon/SQ_IFETCH_LEVEL.txt
new file mode 100644
index 0000000000..293092f641
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/perfmon/SQ_IFETCH_LEVEL.txt
@@ -0,0 +1,5 @@
+pmc: GRBM_COUNT GRBM_GUI_ACTIVE SQ_WAVES SQ_IFETCH SQ_IFETCH_LEVEL  SQ_ACCUM_PREV_HIRES
+
+gpu:
+range:
+kernel:
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/perfmon/SQ_INST_LEVEL_LDS.txt b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/perfmon/SQ_INST_LEVEL_LDS.txt
new file mode 100644
index 0000000000..08439eedce
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/perfmon/SQ_INST_LEVEL_LDS.txt
@@ -0,0 +1,5 @@
+pmc: SQ_INSTS_LDS SQ_INST_LEVEL_LDS  SQ_ACCUM_PREV_HIRES
+
+gpu:
+range:
+kernel:
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/perfmon/SQ_INST_LEVEL_SMEM.txt b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/perfmon/SQ_INST_LEVEL_SMEM.txt
new file mode 100644
index 0000000000..6cca322d4e
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/perfmon/SQ_INST_LEVEL_SMEM.txt
@@ -0,0 +1,5 @@
+pmc: SQ_INSTS_SMEM  SQ_INST_LEVEL_SMEM SQ_ACCUM_PREV_HIRES
+
+gpu:
+range:
+kernel:
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/perfmon/SQ_INST_LEVEL_VMEM.txt b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/perfmon/SQ_INST_LEVEL_VMEM.txt
new file mode 100644
index 0000000000..e527ad31ba
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/perfmon/SQ_INST_LEVEL_VMEM.txt
@@ -0,0 +1,5 @@
+pmc: SQ_INSTS_VMEM  SQ_INST_LEVEL_VMEM SQ_ACCUM_PREV_HIRES
+
+gpu:
+range:
+kernel:
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/perfmon/SQ_LEVEL_WAVES.txt b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/perfmon/SQ_LEVEL_WAVES.txt
new file mode 100644
index 0000000000..3f8e04adb3
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/perfmon/SQ_LEVEL_WAVES.txt
@@ -0,0 +1,5 @@
+pmc: GRBM_COUNT GRBM_GUI_ACTIVE CPC_ME1_BUSY_FOR_PACKET_DECODE SQ_CYCLES SQ_WAVES SQ_WAVE_CYCLES SQ_BUSY_CYCLES SQ_LEVEL_WAVES  SQ_ACCUM_PREV_HIRES
+
+gpu:
+range:
+kernel:
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/perfmon/pmc_perf_0.txt b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/perfmon/pmc_perf_0.txt
new file mode 100644
index 0000000000..95e2e85d3a
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/perfmon/pmc_perf_0.txt
@@ -0,0 +1,5 @@
+pmc:  SQ_CYCLES SQ_BUSY_CYCLES SQ_BUSY_CU_CYCLES SQ_WAVES SQ_WAVE_CYCLES SQ_INSTS_VMEM_WR SQ_INSTS_VMEM_RD SQ_INSTS_VMEM GRBM_COUNT GRBM_GUI_ACTIVE TCP_GATE_EN1_sum TCP_GATE_EN2_sum TCP_TD_TCP_STALL_CYCLES_sum TCP_TCR_TCP_STALL_CYCLES_sum TA_TA_BUSY_sum TA_BUFFER_WAVEFRONTS_sum TD_TD_BUSY_sum TD_TC_STALL_sum SPI_CSN_WINDOW_VALID SPI_CSN_BUSY CPC_CPC_STAT_BUSY CPC_CPC_STAT_IDLE CPF_CPF_STAT_BUSY CPF_CPF_STAT_STALL TCC_CYCLE_sum TCC_BUSY_sum TCC_PROBE_sum TCC_PROBE_ALL_sum
+
+gpu:
+range:
+kernel:
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/perfmon/pmc_perf_1.txt b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/perfmon/pmc_perf_1.txt
new file mode 100644
index 0000000000..a1bd994746
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/perfmon/pmc_perf_1.txt
@@ -0,0 +1,5 @@
+pmc:  SQ_INSTS_SALU SQ_INSTS_VSKIPPED SQ_INSTS_SMEM SQ_INSTS_FLAT SQ_INSTS_LDS SQ_INSTS_GDS SQ_INSTS_EXP_GDS SQ_INSTS_BRANCH GRBM_SPI_BUSY TCP_READ_TAGCONFLICT_STALL_CYCLES_sum TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum TCP_TA_TCP_STATE_READ_sum TA_BUFFER_READ_WAVEFRONTS_sum TA_BUFFER_WRITE_WAVEFRONTS_sum TD_COALESCABLE_WAVEFRONT_sum TD_LOAD_WAVEFRONT_sum SPI_CSN_NUM_THREADGROUPS SPI_CSN_WAVE CPC_CPC_TCIU_BUSY CPC_CPC_TCIU_IDLE CPF_CPF_TCIU_BUSY CPF_CPF_TCIU_STALL TCC_NC_REQ_sum TCC_UC_REQ_sum TCC_CC_REQ_sum TCC_RW_REQ_sum
+
+gpu:
+range:
+kernel:
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/perfmon/pmc_perf_10.txt b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/perfmon/pmc_perf_10.txt
new file mode 100644
index 0000000000..a00555d953
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/perfmon/pmc_perf_10.txt
@@ -0,0 +1,5 @@
+pmc:  TCC_EA_ATOMIC_LEVEL_sum
+
+gpu:
+range:
+kernel:
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/perfmon/pmc_perf_11.txt b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/perfmon/pmc_perf_11.txt
new file mode 100644
index 0000000000..062fc9644a
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/perfmon/pmc_perf_11.txt
@@ -0,0 +1,5 @@
+pmc:  TCC_ATOMIC[0] TCC_CYCLE[0] TCC_EA_ATOMIC[0] TCC_EA_ATOMIC_LEVEL[0] TCC_ATOMIC[1] TCC_CYCLE[1] TCC_EA_ATOMIC[1] TCC_EA_ATOMIC_LEVEL[1] TCC_ATOMIC[2] TCC_CYCLE[2] TCC_EA_ATOMIC[2] TCC_EA_ATOMIC_LEVEL[2] TCC_ATOMIC[3] TCC_CYCLE[3] TCC_EA_ATOMIC[3] TCC_EA_ATOMIC_LEVEL[3] TCC_ATOMIC[4] TCC_CYCLE[4] TCC_EA_ATOMIC[4] TCC_EA_ATOMIC_LEVEL[4] TCC_ATOMIC[5] TCC_CYCLE[5] TCC_EA_ATOMIC[5] TCC_EA_ATOMIC_LEVEL[5] TCC_ATOMIC[6] TCC_CYCLE[6] TCC_EA_ATOMIC[6] TCC_EA_ATOMIC_LEVEL[6] TCC_ATOMIC[7] TCC_CYCLE[7] TCC_EA_ATOMIC[7] TCC_EA_ATOMIC_LEVEL[7] TCC_ATOMIC[8] TCC_CYCLE[8] TCC_EA_ATOMIC[8] TCC_EA_ATOMIC_LEVEL[8] TCC_ATOMIC[9] TCC_CYCLE[9] TCC_EA_ATOMIC[9] TCC_EA_ATOMIC_LEVEL[9] TCC_ATOMIC[10] TCC_CYCLE[10] TCC_EA_ATOMIC[10] TCC_EA_ATOMIC_LEVEL[10] TCC_ATOMIC[11] TCC_CYCLE[11] TCC_EA_ATOMIC[11] TCC_EA_ATOMIC_LEVEL[11] TCC_ATOMIC[12] TCC_CYCLE[12] TCC_EA_ATOMIC[12] TCC_EA_ATOMIC_LEVEL[12] TCC_ATOMIC[13] TCC_CYCLE[13] TCC_EA_ATOMIC[13] TCC_EA_ATOMIC_LEVEL[13] TCC_ATOMIC[14] TCC_CYCLE[14] TCC_EA_ATOMIC[14] TCC_EA_ATOMIC_LEVEL[14] TCC_ATOMIC[15] TCC_CYCLE[15] TCC_EA_ATOMIC[15] TCC_EA_ATOMIC_LEVEL[15] TCC_ATOMIC[16] TCC_CYCLE[16] TCC_EA_ATOMIC[16] TCC_EA_ATOMIC_LEVEL[16] TCC_ATOMIC[17] TCC_CYCLE[17] TCC_EA_ATOMIC[17] TCC_EA_ATOMIC_LEVEL[17] TCC_ATOMIC[18] TCC_CYCLE[18] TCC_EA_ATOMIC[18] TCC_EA_ATOMIC_LEVEL[18] TCC_ATOMIC[19] TCC_CYCLE[19] TCC_EA_ATOMIC[19] TCC_EA_ATOMIC_LEVEL[19] TCC_ATOMIC[20] TCC_CYCLE[20] TCC_EA_ATOMIC[20] TCC_EA_ATOMIC_LEVEL[20] TCC_ATOMIC[21] TCC_CYCLE[21] TCC_EA_ATOMIC[21] TCC_EA_ATOMIC_LEVEL[21] TCC_ATOMIC[22] TCC_CYCLE[22] TCC_EA_ATOMIC[22] TCC_EA_ATOMIC_LEVEL[22] TCC_ATOMIC[23] TCC_CYCLE[23] TCC_EA_ATOMIC[23] TCC_EA_ATOMIC_LEVEL[23] TCC_ATOMIC[24] TCC_CYCLE[24] TCC_EA_ATOMIC[24] TCC_EA_ATOMIC_LEVEL[24] TCC_ATOMIC[25] TCC_CYCLE[25] TCC_EA_ATOMIC[25] TCC_EA_ATOMIC_LEVEL[25] TCC_ATOMIC[26] TCC_CYCLE[26] TCC_EA_ATOMIC[26] TCC_EA_ATOMIC_LEVEL[26] TCC_ATOMIC[27] TCC_CYCLE[27] TCC_EA_ATOMIC[27] TCC_EA_ATOMIC_LEVEL[27] TCC_ATOMIC[28] TCC_CYCLE[28] TCC_EA_ATOMIC[28] TCC_EA_ATOMIC_LEVEL[28] TCC_ATOMIC[29] TCC_CYCLE[29] TCC_EA_ATOMIC[29] TCC_EA_ATOMIC_LEVEL[29] TCC_ATOMIC[30] TCC_CYCLE[30] TCC_EA_ATOMIC[30] TCC_EA_ATOMIC_LEVEL[30] TCC_ATOMIC[31] TCC_CYCLE[31] TCC_EA_ATOMIC[31] TCC_EA_ATOMIC_LEVEL[31]
+
+gpu:
+range:
+kernel:
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/perfmon/pmc_perf_12.txt b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/perfmon/pmc_perf_12.txt
new file mode 100644
index 0000000000..e0698dbf57
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/perfmon/pmc_perf_12.txt
@@ -0,0 +1,5 @@
+pmc:  TCC_EA_RDREQ[0] TCC_EA_RDREQ_32B[0] TCC_EA_RDREQ_DRAM_CREDIT_STALL[0] TCC_EA_RDREQ_GMI_CREDIT_STALL[0] TCC_EA_RDREQ[1] TCC_EA_RDREQ_32B[1] TCC_EA_RDREQ_DRAM_CREDIT_STALL[1] TCC_EA_RDREQ_GMI_CREDIT_STALL[1] TCC_EA_RDREQ[2] TCC_EA_RDREQ_32B[2] TCC_EA_RDREQ_DRAM_CREDIT_STALL[2] TCC_EA_RDREQ_GMI_CREDIT_STALL[2] TCC_EA_RDREQ[3] TCC_EA_RDREQ_32B[3] TCC_EA_RDREQ_DRAM_CREDIT_STALL[3] TCC_EA_RDREQ_GMI_CREDIT_STALL[3] TCC_EA_RDREQ[4] TCC_EA_RDREQ_32B[4] TCC_EA_RDREQ_DRAM_CREDIT_STALL[4] TCC_EA_RDREQ_GMI_CREDIT_STALL[4] TCC_EA_RDREQ[5] TCC_EA_RDREQ_32B[5] TCC_EA_RDREQ_DRAM_CREDIT_STALL[5] TCC_EA_RDREQ_GMI_CREDIT_STALL[5] TCC_EA_RDREQ[6] TCC_EA_RDREQ_32B[6] TCC_EA_RDREQ_DRAM_CREDIT_STALL[6] TCC_EA_RDREQ_GMI_CREDIT_STALL[6] TCC_EA_RDREQ[7] TCC_EA_RDREQ_32B[7] TCC_EA_RDREQ_DRAM_CREDIT_STALL[7] TCC_EA_RDREQ_GMI_CREDIT_STALL[7] TCC_EA_RDREQ[8] TCC_EA_RDREQ_32B[8] TCC_EA_RDREQ_DRAM_CREDIT_STALL[8] TCC_EA_RDREQ_GMI_CREDIT_STALL[8] TCC_EA_RDREQ[9] TCC_EA_RDREQ_32B[9] TCC_EA_RDREQ_DRAM_CREDIT_STALL[9] TCC_EA_RDREQ_GMI_CREDIT_STALL[9] TCC_EA_RDREQ[10] TCC_EA_RDREQ_32B[10] TCC_EA_RDREQ_DRAM_CREDIT_STALL[10] TCC_EA_RDREQ_GMI_CREDIT_STALL[10] TCC_EA_RDREQ[11] TCC_EA_RDREQ_32B[11] TCC_EA_RDREQ_DRAM_CREDIT_STALL[11] TCC_EA_RDREQ_GMI_CREDIT_STALL[11] TCC_EA_RDREQ[12] TCC_EA_RDREQ_32B[12] TCC_EA_RDREQ_DRAM_CREDIT_STALL[12] TCC_EA_RDREQ_GMI_CREDIT_STALL[12] TCC_EA_RDREQ[13] TCC_EA_RDREQ_32B[13] TCC_EA_RDREQ_DRAM_CREDIT_STALL[13] TCC_EA_RDREQ_GMI_CREDIT_STALL[13] TCC_EA_RDREQ[14] TCC_EA_RDREQ_32B[14] TCC_EA_RDREQ_DRAM_CREDIT_STALL[14] TCC_EA_RDREQ_GMI_CREDIT_STALL[14] TCC_EA_RDREQ[15] TCC_EA_RDREQ_32B[15] TCC_EA_RDREQ_DRAM_CREDIT_STALL[15] TCC_EA_RDREQ_GMI_CREDIT_STALL[15] TCC_EA_RDREQ[16] TCC_EA_RDREQ_32B[16] TCC_EA_RDREQ_DRAM_CREDIT_STALL[16] TCC_EA_RDREQ_GMI_CREDIT_STALL[16] TCC_EA_RDREQ[17] TCC_EA_RDREQ_32B[17] TCC_EA_RDREQ_DRAM_CREDIT_STALL[17] TCC_EA_RDREQ_GMI_CREDIT_STALL[17] TCC_EA_RDREQ[18] TCC_EA_RDREQ_32B[18] TCC_EA_RDREQ_DRAM_CREDIT_STALL[18] TCC_EA_RDREQ_GMI_CREDIT_STALL[18] TCC_EA_RDREQ[19] TCC_EA_RDREQ_32B[19] TCC_EA_RDREQ_DRAM_CREDIT_STALL[19] TCC_EA_RDREQ_GMI_CREDIT_STALL[19] TCC_EA_RDREQ[20] TCC_EA_RDREQ_32B[20] TCC_EA_RDREQ_DRAM_CREDIT_STALL[20] TCC_EA_RDREQ_GMI_CREDIT_STALL[20] TCC_EA_RDREQ[21] TCC_EA_RDREQ_32B[21] TCC_EA_RDREQ_DRAM_CREDIT_STALL[21] TCC_EA_RDREQ_GMI_CREDIT_STALL[21] TCC_EA_RDREQ[22] TCC_EA_RDREQ_32B[22] TCC_EA_RDREQ_DRAM_CREDIT_STALL[22] TCC_EA_RDREQ_GMI_CREDIT_STALL[22] TCC_EA_RDREQ[23] TCC_EA_RDREQ_32B[23] TCC_EA_RDREQ_DRAM_CREDIT_STALL[23] TCC_EA_RDREQ_GMI_CREDIT_STALL[23] TCC_EA_RDREQ[24] TCC_EA_RDREQ_32B[24] TCC_EA_RDREQ_DRAM_CREDIT_STALL[24] TCC_EA_RDREQ_GMI_CREDIT_STALL[24] TCC_EA_RDREQ[25] TCC_EA_RDREQ_32B[25] TCC_EA_RDREQ_DRAM_CREDIT_STALL[25] TCC_EA_RDREQ_GMI_CREDIT_STALL[25] TCC_EA_RDREQ[26] TCC_EA_RDREQ_32B[26] TCC_EA_RDREQ_DRAM_CREDIT_STALL[26] TCC_EA_RDREQ_GMI_CREDIT_STALL[26] TCC_EA_RDREQ[27] TCC_EA_RDREQ_32B[27] TCC_EA_RDREQ_DRAM_CREDIT_STALL[27] TCC_EA_RDREQ_GMI_CREDIT_STALL[27] TCC_EA_RDREQ[28] TCC_EA_RDREQ_32B[28] TCC_EA_RDREQ_DRAM_CREDIT_STALL[28] TCC_EA_RDREQ_GMI_CREDIT_STALL[28] TCC_EA_RDREQ[29] TCC_EA_RDREQ_32B[29] TCC_EA_RDREQ_DRAM_CREDIT_STALL[29] TCC_EA_RDREQ_GMI_CREDIT_STALL[29] TCC_EA_RDREQ[30] TCC_EA_RDREQ_32B[30] TCC_EA_RDREQ_DRAM_CREDIT_STALL[30] TCC_EA_RDREQ_GMI_CREDIT_STALL[30] TCC_EA_RDREQ[31] TCC_EA_RDREQ_32B[31] TCC_EA_RDREQ_DRAM_CREDIT_STALL[31] TCC_EA_RDREQ_GMI_CREDIT_STALL[31]
+
+gpu:
+range:
+kernel:
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/perfmon/pmc_perf_13.txt b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/perfmon/pmc_perf_13.txt
new file mode 100644
index 0000000000..77ad088669
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/perfmon/pmc_perf_13.txt
@@ -0,0 +1,5 @@
+pmc:  TCC_EA_RDREQ_IO_CREDIT_STALL[0] TCC_EA_RDREQ_LEVEL[0] TCC_EA_WRREQ[0] TCC_EA_WRREQ_64B[0] TCC_EA_RDREQ_IO_CREDIT_STALL[1] TCC_EA_RDREQ_LEVEL[1] TCC_EA_WRREQ[1] TCC_EA_WRREQ_64B[1] TCC_EA_RDREQ_IO_CREDIT_STALL[2] TCC_EA_RDREQ_LEVEL[2] TCC_EA_WRREQ[2] TCC_EA_WRREQ_64B[2] TCC_EA_RDREQ_IO_CREDIT_STALL[3] TCC_EA_RDREQ_LEVEL[3] TCC_EA_WRREQ[3] TCC_EA_WRREQ_64B[3] TCC_EA_RDREQ_IO_CREDIT_STALL[4] TCC_EA_RDREQ_LEVEL[4] TCC_EA_WRREQ[4] TCC_EA_WRREQ_64B[4] TCC_EA_RDREQ_IO_CREDIT_STALL[5] TCC_EA_RDREQ_LEVEL[5] TCC_EA_WRREQ[5] TCC_EA_WRREQ_64B[5] TCC_EA_RDREQ_IO_CREDIT_STALL[6] TCC_EA_RDREQ_LEVEL[6] TCC_EA_WRREQ[6] TCC_EA_WRREQ_64B[6] TCC_EA_RDREQ_IO_CREDIT_STALL[7] TCC_EA_RDREQ_LEVEL[7] TCC_EA_WRREQ[7] TCC_EA_WRREQ_64B[7] TCC_EA_RDREQ_IO_CREDIT_STALL[8] TCC_EA_RDREQ_LEVEL[8] TCC_EA_WRREQ[8] TCC_EA_WRREQ_64B[8] TCC_EA_RDREQ_IO_CREDIT_STALL[9] TCC_EA_RDREQ_LEVEL[9] TCC_EA_WRREQ[9] TCC_EA_WRREQ_64B[9] TCC_EA_RDREQ_IO_CREDIT_STALL[10] TCC_EA_RDREQ_LEVEL[10] TCC_EA_WRREQ[10] TCC_EA_WRREQ_64B[10] TCC_EA_RDREQ_IO_CREDIT_STALL[11] TCC_EA_RDREQ_LEVEL[11] TCC_EA_WRREQ[11] TCC_EA_WRREQ_64B[11] TCC_EA_RDREQ_IO_CREDIT_STALL[12] TCC_EA_RDREQ_LEVEL[12] TCC_EA_WRREQ[12] TCC_EA_WRREQ_64B[12] TCC_EA_RDREQ_IO_CREDIT_STALL[13] TCC_EA_RDREQ_LEVEL[13] TCC_EA_WRREQ[13] TCC_EA_WRREQ_64B[13] TCC_EA_RDREQ_IO_CREDIT_STALL[14] TCC_EA_RDREQ_LEVEL[14] TCC_EA_WRREQ[14] TCC_EA_WRREQ_64B[14] TCC_EA_RDREQ_IO_CREDIT_STALL[15] TCC_EA_RDREQ_LEVEL[15] TCC_EA_WRREQ[15] TCC_EA_WRREQ_64B[15] TCC_EA_RDREQ_IO_CREDIT_STALL[16] TCC_EA_RDREQ_LEVEL[16] TCC_EA_WRREQ[16] TCC_EA_WRREQ_64B[16] TCC_EA_RDREQ_IO_CREDIT_STALL[17] TCC_EA_RDREQ_LEVEL[17] TCC_EA_WRREQ[17] TCC_EA_WRREQ_64B[17] TCC_EA_RDREQ_IO_CREDIT_STALL[18] TCC_EA_RDREQ_LEVEL[18] TCC_EA_WRREQ[18] TCC_EA_WRREQ_64B[18] TCC_EA_RDREQ_IO_CREDIT_STALL[19] TCC_EA_RDREQ_LEVEL[19] TCC_EA_WRREQ[19] TCC_EA_WRREQ_64B[19] TCC_EA_RDREQ_IO_CREDIT_STALL[20] TCC_EA_RDREQ_LEVEL[20] TCC_EA_WRREQ[20] TCC_EA_WRREQ_64B[20] TCC_EA_RDREQ_IO_CREDIT_STALL[21] TCC_EA_RDREQ_LEVEL[21] TCC_EA_WRREQ[21] TCC_EA_WRREQ_64B[21] TCC_EA_RDREQ_IO_CREDIT_STALL[22] TCC_EA_RDREQ_LEVEL[22] TCC_EA_WRREQ[22] TCC_EA_WRREQ_64B[22] TCC_EA_RDREQ_IO_CREDIT_STALL[23] TCC_EA_RDREQ_LEVEL[23] TCC_EA_WRREQ[23] TCC_EA_WRREQ_64B[23] TCC_EA_RDREQ_IO_CREDIT_STALL[24] TCC_EA_RDREQ_LEVEL[24] TCC_EA_WRREQ[24] TCC_EA_WRREQ_64B[24] TCC_EA_RDREQ_IO_CREDIT_STALL[25] TCC_EA_RDREQ_LEVEL[25] TCC_EA_WRREQ[25] TCC_EA_WRREQ_64B[25] TCC_EA_RDREQ_IO_CREDIT_STALL[26] TCC_EA_RDREQ_LEVEL[26] TCC_EA_WRREQ[26] TCC_EA_WRREQ_64B[26] TCC_EA_RDREQ_IO_CREDIT_STALL[27] TCC_EA_RDREQ_LEVEL[27] TCC_EA_WRREQ[27] TCC_EA_WRREQ_64B[27] TCC_EA_RDREQ_IO_CREDIT_STALL[28] TCC_EA_RDREQ_LEVEL[28] TCC_EA_WRREQ[28] TCC_EA_WRREQ_64B[28] TCC_EA_RDREQ_IO_CREDIT_STALL[29] TCC_EA_RDREQ_LEVEL[29] TCC_EA_WRREQ[29] TCC_EA_WRREQ_64B[29] TCC_EA_RDREQ_IO_CREDIT_STALL[30] TCC_EA_RDREQ_LEVEL[30] TCC_EA_WRREQ[30] TCC_EA_WRREQ_64B[30] TCC_EA_RDREQ_IO_CREDIT_STALL[31] TCC_EA_RDREQ_LEVEL[31] TCC_EA_WRREQ[31] TCC_EA_WRREQ_64B[31]
+
+gpu:
+range:
+kernel:
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/perfmon/pmc_perf_14.txt b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/perfmon/pmc_perf_14.txt
new file mode 100644
index 0000000000..d0628bb948
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/perfmon/pmc_perf_14.txt
@@ -0,0 +1,5 @@
+pmc:  TCC_EA_WRREQ_DRAM_CREDIT_STALL[0] TCC_EA_WRREQ_GMI_CREDIT_STALL[0] TCC_EA_WRREQ_IO_CREDIT_STALL[0] TCC_EA_WRREQ_LEVEL[0] TCC_EA_WRREQ_DRAM_CREDIT_STALL[1] TCC_EA_WRREQ_GMI_CREDIT_STALL[1] TCC_EA_WRREQ_IO_CREDIT_STALL[1] TCC_EA_WRREQ_LEVEL[1] TCC_EA_WRREQ_DRAM_CREDIT_STALL[2] TCC_EA_WRREQ_GMI_CREDIT_STALL[2] TCC_EA_WRREQ_IO_CREDIT_STALL[2] TCC_EA_WRREQ_LEVEL[2] TCC_EA_WRREQ_DRAM_CREDIT_STALL[3] TCC_EA_WRREQ_GMI_CREDIT_STALL[3] TCC_EA_WRREQ_IO_CREDIT_STALL[3] TCC_EA_WRREQ_LEVEL[3] TCC_EA_WRREQ_DRAM_CREDIT_STALL[4] TCC_EA_WRREQ_GMI_CREDIT_STALL[4] TCC_EA_WRREQ_IO_CREDIT_STALL[4] TCC_EA_WRREQ_LEVEL[4] TCC_EA_WRREQ_DRAM_CREDIT_STALL[5] TCC_EA_WRREQ_GMI_CREDIT_STALL[5] TCC_EA_WRREQ_IO_CREDIT_STALL[5] TCC_EA_WRREQ_LEVEL[5] TCC_EA_WRREQ_DRAM_CREDIT_STALL[6] TCC_EA_WRREQ_GMI_CREDIT_STALL[6] TCC_EA_WRREQ_IO_CREDIT_STALL[6] TCC_EA_WRREQ_LEVEL[6] TCC_EA_WRREQ_DRAM_CREDIT_STALL[7] TCC_EA_WRREQ_GMI_CREDIT_STALL[7] TCC_EA_WRREQ_IO_CREDIT_STALL[7] TCC_EA_WRREQ_LEVEL[7] TCC_EA_WRREQ_DRAM_CREDIT_STALL[8] TCC_EA_WRREQ_GMI_CREDIT_STALL[8] TCC_EA_WRREQ_IO_CREDIT_STALL[8] TCC_EA_WRREQ_LEVEL[8] TCC_EA_WRREQ_DRAM_CREDIT_STALL[9] TCC_EA_WRREQ_GMI_CREDIT_STALL[9] TCC_EA_WRREQ_IO_CREDIT_STALL[9] TCC_EA_WRREQ_LEVEL[9] TCC_EA_WRREQ_DRAM_CREDIT_STALL[10] TCC_EA_WRREQ_GMI_CREDIT_STALL[10] TCC_EA_WRREQ_IO_CREDIT_STALL[10] TCC_EA_WRREQ_LEVEL[10] TCC_EA_WRREQ_DRAM_CREDIT_STALL[11] TCC_EA_WRREQ_GMI_CREDIT_STALL[11] TCC_EA_WRREQ_IO_CREDIT_STALL[11] TCC_EA_WRREQ_LEVEL[11] TCC_EA_WRREQ_DRAM_CREDIT_STALL[12] TCC_EA_WRREQ_GMI_CREDIT_STALL[12] TCC_EA_WRREQ_IO_CREDIT_STALL[12] TCC_EA_WRREQ_LEVEL[12] TCC_EA_WRREQ_DRAM_CREDIT_STALL[13] TCC_EA_WRREQ_GMI_CREDIT_STALL[13] TCC_EA_WRREQ_IO_CREDIT_STALL[13] TCC_EA_WRREQ_LEVEL[13] TCC_EA_WRREQ_DRAM_CREDIT_STALL[14] TCC_EA_WRREQ_GMI_CREDIT_STALL[14] TCC_EA_WRREQ_IO_CREDIT_STALL[14] TCC_EA_WRREQ_LEVEL[14] TCC_EA_WRREQ_DRAM_CREDIT_STALL[15] TCC_EA_WRREQ_GMI_CREDIT_STALL[15] TCC_EA_WRREQ_IO_CREDIT_STALL[15] TCC_EA_WRREQ_LEVEL[15] TCC_EA_WRREQ_DRAM_CREDIT_STALL[16] TCC_EA_WRREQ_GMI_CREDIT_STALL[16] TCC_EA_WRREQ_IO_CREDIT_STALL[16] TCC_EA_WRREQ_LEVEL[16] TCC_EA_WRREQ_DRAM_CREDIT_STALL[17] TCC_EA_WRREQ_GMI_CREDIT_STALL[17] TCC_EA_WRREQ_IO_CREDIT_STALL[17] TCC_EA_WRREQ_LEVEL[17] TCC_EA_WRREQ_DRAM_CREDIT_STALL[18] TCC_EA_WRREQ_GMI_CREDIT_STALL[18] TCC_EA_WRREQ_IO_CREDIT_STALL[18] TCC_EA_WRREQ_LEVEL[18] TCC_EA_WRREQ_DRAM_CREDIT_STALL[19] TCC_EA_WRREQ_GMI_CREDIT_STALL[19] TCC_EA_WRREQ_IO_CREDIT_STALL[19] TCC_EA_WRREQ_LEVEL[19] TCC_EA_WRREQ_DRAM_CREDIT_STALL[20] TCC_EA_WRREQ_GMI_CREDIT_STALL[20] TCC_EA_WRREQ_IO_CREDIT_STALL[20] TCC_EA_WRREQ_LEVEL[20] TCC_EA_WRREQ_DRAM_CREDIT_STALL[21] TCC_EA_WRREQ_GMI_CREDIT_STALL[21] TCC_EA_WRREQ_IO_CREDIT_STALL[21] TCC_EA_WRREQ_LEVEL[21] TCC_EA_WRREQ_DRAM_CREDIT_STALL[22] TCC_EA_WRREQ_GMI_CREDIT_STALL[22] TCC_EA_WRREQ_IO_CREDIT_STALL[22] TCC_EA_WRREQ_LEVEL[22] TCC_EA_WRREQ_DRAM_CREDIT_STALL[23] TCC_EA_WRREQ_GMI_CREDIT_STALL[23] TCC_EA_WRREQ_IO_CREDIT_STALL[23] TCC_EA_WRREQ_LEVEL[23] TCC_EA_WRREQ_DRAM_CREDIT_STALL[24] TCC_EA_WRREQ_GMI_CREDIT_STALL[24] TCC_EA_WRREQ_IO_CREDIT_STALL[24] TCC_EA_WRREQ_LEVEL[24] TCC_EA_WRREQ_DRAM_CREDIT_STALL[25] TCC_EA_WRREQ_GMI_CREDIT_STALL[25] TCC_EA_WRREQ_IO_CREDIT_STALL[25] TCC_EA_WRREQ_LEVEL[25] TCC_EA_WRREQ_DRAM_CREDIT_STALL[26] TCC_EA_WRREQ_GMI_CREDIT_STALL[26] TCC_EA_WRREQ_IO_CREDIT_STALL[26] TCC_EA_WRREQ_LEVEL[26] TCC_EA_WRREQ_DRAM_CREDIT_STALL[27] TCC_EA_WRREQ_GMI_CREDIT_STALL[27] TCC_EA_WRREQ_IO_CREDIT_STALL[27] TCC_EA_WRREQ_LEVEL[27] TCC_EA_WRREQ_DRAM_CREDIT_STALL[28] TCC_EA_WRREQ_GMI_CREDIT_STALL[28] TCC_EA_WRREQ_IO_CREDIT_STALL[28] TCC_EA_WRREQ_LEVEL[28] TCC_EA_WRREQ_DRAM_CREDIT_STALL[29] TCC_EA_WRREQ_GMI_CREDIT_STALL[29] TCC_EA_WRREQ_IO_CREDIT_STALL[29] TCC_EA_WRREQ_LEVEL[29] TCC_EA_WRREQ_DRAM_CREDIT_STALL[30] TCC_EA_WRREQ_GMI_CREDIT_STALL[30] TCC_EA_WRREQ_IO_CREDIT_STALL[30] TCC_EA_WRREQ_LEVEL[30] TCC_EA_WRREQ_DRAM_CREDIT_STALL[31] TCC_EA_WRREQ_GMI_CREDIT_STALL[31] TCC_EA_WRREQ_IO_CREDIT_STALL[31] TCC_EA_WRREQ_LEVEL[31]
+
+gpu:
+range:
+kernel:
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/perfmon/pmc_perf_15.txt b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/perfmon/pmc_perf_15.txt
new file mode 100644
index 0000000000..343869c5f1
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/perfmon/pmc_perf_15.txt
@@ -0,0 +1,5 @@
+pmc:  TCC_HIT[0] TCC_MISS[0] TCC_READ[0] TCC_REQ[0] TCC_HIT[1] TCC_MISS[1] TCC_READ[1] TCC_REQ[1] TCC_HIT[2] TCC_MISS[2] TCC_READ[2] TCC_REQ[2] TCC_HIT[3] TCC_MISS[3] TCC_READ[3] TCC_REQ[3] TCC_HIT[4] TCC_MISS[4] TCC_READ[4] TCC_REQ[4] TCC_HIT[5] TCC_MISS[5] TCC_READ[5] TCC_REQ[5] TCC_HIT[6] TCC_MISS[6] TCC_READ[6] TCC_REQ[6] TCC_HIT[7] TCC_MISS[7] TCC_READ[7] TCC_REQ[7] TCC_HIT[8] TCC_MISS[8] TCC_READ[8] TCC_REQ[8] TCC_HIT[9] TCC_MISS[9] TCC_READ[9] TCC_REQ[9] TCC_HIT[10] TCC_MISS[10] TCC_READ[10] TCC_REQ[10] TCC_HIT[11] TCC_MISS[11] TCC_READ[11] TCC_REQ[11] TCC_HIT[12] TCC_MISS[12] TCC_READ[12] TCC_REQ[12] TCC_HIT[13] TCC_MISS[13] TCC_READ[13] TCC_REQ[13] TCC_HIT[14] TCC_MISS[14] TCC_READ[14] TCC_REQ[14] TCC_HIT[15] TCC_MISS[15] TCC_READ[15] TCC_REQ[15] TCC_HIT[16] TCC_MISS[16] TCC_READ[16] TCC_REQ[16] TCC_HIT[17] TCC_MISS[17] TCC_READ[17] TCC_REQ[17] TCC_HIT[18] TCC_MISS[18] TCC_READ[18] TCC_REQ[18] TCC_HIT[19] TCC_MISS[19] TCC_READ[19] TCC_REQ[19] TCC_HIT[20] TCC_MISS[20] TCC_READ[20] TCC_REQ[20] TCC_HIT[21] TCC_MISS[21] TCC_READ[21] TCC_REQ[21] TCC_HIT[22] TCC_MISS[22] TCC_READ[22] TCC_REQ[22] TCC_HIT[23] TCC_MISS[23] TCC_READ[23] TCC_REQ[23] TCC_HIT[24] TCC_MISS[24] TCC_READ[24] TCC_REQ[24] TCC_HIT[25] TCC_MISS[25] TCC_READ[25] TCC_REQ[25] TCC_HIT[26] TCC_MISS[26] TCC_READ[26] TCC_REQ[26] TCC_HIT[27] TCC_MISS[27] TCC_READ[27] TCC_REQ[27] TCC_HIT[28] TCC_MISS[28] TCC_READ[28] TCC_REQ[28] TCC_HIT[29] TCC_MISS[29] TCC_READ[29] TCC_REQ[29] TCC_HIT[30] TCC_MISS[30] TCC_READ[30] TCC_REQ[30] TCC_HIT[31] TCC_MISS[31] TCC_READ[31] TCC_REQ[31]
+
+gpu:
+range:
+kernel:
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/perfmon/pmc_perf_16.txt b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/perfmon/pmc_perf_16.txt
new file mode 100644
index 0000000000..a74cefd281
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/perfmon/pmc_perf_16.txt
@@ -0,0 +1,5 @@
+pmc:  TCC_RW_REQ[0] TCC_TOO_MANY_EA_WRREQS_STALL[0] TCC_WRITE[0] TCC_RW_REQ[1] TCC_TOO_MANY_EA_WRREQS_STALL[1] TCC_WRITE[1] TCC_RW_REQ[2] TCC_TOO_MANY_EA_WRREQS_STALL[2] TCC_WRITE[2] TCC_RW_REQ[3] TCC_TOO_MANY_EA_WRREQS_STALL[3] TCC_WRITE[3] TCC_RW_REQ[4] TCC_TOO_MANY_EA_WRREQS_STALL[4] TCC_WRITE[4] TCC_RW_REQ[5] TCC_TOO_MANY_EA_WRREQS_STALL[5] TCC_WRITE[5] TCC_RW_REQ[6] TCC_TOO_MANY_EA_WRREQS_STALL[6] TCC_WRITE[6] TCC_RW_REQ[7] TCC_TOO_MANY_EA_WRREQS_STALL[7] TCC_WRITE[7] TCC_RW_REQ[8] TCC_TOO_MANY_EA_WRREQS_STALL[8] TCC_WRITE[8] TCC_RW_REQ[9] TCC_TOO_MANY_EA_WRREQS_STALL[9] TCC_WRITE[9] TCC_RW_REQ[10] TCC_TOO_MANY_EA_WRREQS_STALL[10] TCC_WRITE[10] TCC_RW_REQ[11] TCC_TOO_MANY_EA_WRREQS_STALL[11] TCC_WRITE[11] TCC_RW_REQ[12] TCC_TOO_MANY_EA_WRREQS_STALL[12] TCC_WRITE[12] TCC_RW_REQ[13] TCC_TOO_MANY_EA_WRREQS_STALL[13] TCC_WRITE[13] TCC_RW_REQ[14] TCC_TOO_MANY_EA_WRREQS_STALL[14] TCC_WRITE[14] TCC_RW_REQ[15] TCC_TOO_MANY_EA_WRREQS_STALL[15] TCC_WRITE[15] TCC_RW_REQ[16] TCC_TOO_MANY_EA_WRREQS_STALL[16] TCC_WRITE[16] TCC_RW_REQ[17] TCC_TOO_MANY_EA_WRREQS_STALL[17] TCC_WRITE[17] TCC_RW_REQ[18] TCC_TOO_MANY_EA_WRREQS_STALL[18] TCC_WRITE[18] TCC_RW_REQ[19] TCC_TOO_MANY_EA_WRREQS_STALL[19] TCC_WRITE[19] TCC_RW_REQ[20] TCC_TOO_MANY_EA_WRREQS_STALL[20] TCC_WRITE[20] TCC_RW_REQ[21] TCC_TOO_MANY_EA_WRREQS_STALL[21] TCC_WRITE[21] TCC_RW_REQ[22] TCC_TOO_MANY_EA_WRREQS_STALL[22] TCC_WRITE[22] TCC_RW_REQ[23] TCC_TOO_MANY_EA_WRREQS_STALL[23] TCC_WRITE[23] TCC_RW_REQ[24] TCC_TOO_MANY_EA_WRREQS_STALL[24] TCC_WRITE[24] TCC_RW_REQ[25] TCC_TOO_MANY_EA_WRREQS_STALL[25] TCC_WRITE[25] TCC_RW_REQ[26] TCC_TOO_MANY_EA_WRREQS_STALL[26] TCC_WRITE[26] TCC_RW_REQ[27] TCC_TOO_MANY_EA_WRREQS_STALL[27] TCC_WRITE[27] TCC_RW_REQ[28] TCC_TOO_MANY_EA_WRREQS_STALL[28] TCC_WRITE[28] TCC_RW_REQ[29] TCC_TOO_MANY_EA_WRREQS_STALL[29] TCC_WRITE[29] TCC_RW_REQ[30] TCC_TOO_MANY_EA_WRREQS_STALL[30] TCC_WRITE[30] TCC_RW_REQ[31] TCC_TOO_MANY_EA_WRREQS_STALL[31] TCC_WRITE[31]
+
+gpu:
+range:
+kernel:
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/perfmon/pmc_perf_2.txt b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/perfmon/pmc_perf_2.txt
new file mode 100644
index 0000000000..e0bd125c3d
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/perfmon/pmc_perf_2.txt
@@ -0,0 +1,5 @@
+pmc:  SQ_INSTS_SENDMSG SQ_INSTS SQ_WAIT_ANY SQ_WAIT_INST_ANY SQ_ACTIVE_INST_ANY SQ_INSTS_VALU SQ_ACTIVE_INST_VMEM SQ_ACTIVE_INST_LDS TCP_VOLATILE_sum TCP_TOTAL_ACCESSES_sum TCP_TOTAL_READ_sum TCP_TOTAL_WRITE_sum TA_BUFFER_ATOMIC_WAVEFRONTS_sum TA_BUFFER_TOTAL_CYCLES_sum TD_ATOMIC_WAVEFRONT_sum TD_STORE_WAVEFRONT_sum SPI_RA_REQ_NO_ALLOC SPI_RA_REQ_NO_ALLOC_CSN CPC_CPC_STAT_STALL CPC_UTCL1_STALL_ON_TRANSLATION CPF_CPF_STAT_IDLE CPF_CPF_TCIU_IDLE TCC_REQ_sum TCC_STREAMING_REQ_sum TCC_HIT_sum TCC_MISS_sum
+
+gpu:
+range:
+kernel:
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/perfmon/pmc_perf_3.txt b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/perfmon/pmc_perf_3.txt
new file mode 100644
index 0000000000..5119c44312
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/perfmon/pmc_perf_3.txt
@@ -0,0 +1,5 @@
+pmc:  SQ_ACTIVE_INST_VALU SQ_ACTIVE_INST_SCA SQ_ACTIVE_INST_EXP_GDS SQ_ACTIVE_INST_MISC SQ_ACTIVE_INST_FLAT SQ_INST_CYCLES_VMEM_WR SQ_INST_CYCLES_VMEM_RD SQ_INST_CYCLES_SMEM TCP_TOTAL_ATOMIC_WITH_RET_sum TCP_TOTAL_ATOMIC_WITHOUT_RET_sum TCP_TOTAL_WRITEBACK_INVALIDATES_sum TCP_TOTAL_CACHE_ACCESSES_sum TA_BUFFER_COALESCED_READ_CYCLES_sum TA_BUFFER_COALESCED_WRITE_CYCLES_sum SPI_RA_RES_STALL_CSN SPI_RA_TMP_STALL_CSN CPC_CPC_UTCL2IU_BUSY CPC_CPC_UTCL2IU_IDLE CPF_CMP_UTCL1_STALL_ON_TRANSLATION TCC_READ_sum TCC_WRITE_sum TCC_ATOMIC_sum TCC_WRITEBACK_sum
+
+gpu:
+range:
+kernel:
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/perfmon/pmc_perf_4.txt b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/perfmon/pmc_perf_4.txt
new file mode 100644
index 0000000000..968f6afb61
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/perfmon/pmc_perf_4.txt
@@ -0,0 +1,5 @@
+pmc:  SQ_INST_CYCLES_SALU SQ_THREAD_CYCLES_VALU SQ_IFETCH SQ_LDS_BANK_CONFLICT SQ_LDS_ADDR_CONFLICT SQ_LDS_UNALIGNED_STALL SQ_WAVES_EQ_64 SQ_WAVES_LT_64 TCP_UTCL1_TRANSLATION_MISS_sum TCP_UTCL1_TRANSLATION_HIT_sum TCP_UTCL1_PERMISSION_MISS_sum TCP_UTCL1_REQUEST_sum TA_ADDR_STALLED_BY_TC_CYCLES_sum TA_TOTAL_WAVEFRONTS_sum SPI_RA_WAVE_SIMD_FULL_CSN SPI_RA_VGPR_SIMD_FULL_CSN CPC_CPC_UTCL2IU_STALL CPC_ME1_BUSY_FOR_PACKET_DECODE TCC_EA_WRREQ_sum TCC_EA_WRREQ_64B_sum TCC_EA_WR_UNCACHED_32B_sum TCC_EA_WRREQ_STALL_sum
+
+gpu:
+range:
+kernel:
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/perfmon/pmc_perf_5.txt b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/perfmon/pmc_perf_5.txt
new file mode 100644
index 0000000000..f7db083ea0
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/perfmon/pmc_perf_5.txt
@@ -0,0 +1,5 @@
+pmc:  SQ_WAVES_LT_48 SQ_WAVES_LT_32 SQ_WAVES_LT_16 SQ_ITEMS SQ_LDS_MEM_VIOLATIONS SQ_LDS_ATOMIC_RETURN SQ_LDS_IDX_ACTIVE SQ_WAVES_RESTORED TCP_TCP_LATENCY_sum TCP_TCC_READ_REQ_LATENCY_sum TCP_TCC_WRITE_REQ_LATENCY_sum TCP_TCC_READ_REQ_sum TA_ADDR_STALLED_BY_TD_CYCLES_sum TA_DATA_STALLED_BY_TC_CYCLES_sum SPI_RA_SGPR_SIMD_FULL_CSN SPI_RA_LDS_CU_FULL_CSN CPC_ME1_DC0_SPI_BUSY TCC_EA_WRREQ_IO_CREDIT_STALL_sum TCC_EA_WRREQ_GMI_CREDIT_STALL_sum TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum TCC_TOO_MANY_EA_WRREQS_STALL_sum
+
+gpu:
+range:
+kernel:
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/perfmon/pmc_perf_6.txt b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/perfmon/pmc_perf_6.txt
new file mode 100644
index 0000000000..954e2c8a08
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/perfmon/pmc_perf_6.txt
@@ -0,0 +1,5 @@
+pmc:  SQ_WAVES_SAVED SQ_INSTS_SMEM_NORM SQC_TC_INST_REQ SQC_TC_DATA_READ_REQ SQC_TC_DATA_WRITE_REQ SQC_TC_DATA_ATOMIC_REQ SQC_TC_STALL SQC_TC_REQ TCP_TCC_WRITE_REQ_sum TCP_TCC_ATOMIC_WITH_RET_REQ_sum TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum TCP_TCC_NC_READ_REQ_sum TA_FLAT_WAVEFRONTS_sum TA_FLAT_READ_WAVEFRONTS_sum SPI_RA_BAR_CU_FULL_CSN SPI_RA_TGLIM_CU_FULL_CSN TCC_EA_ATOMIC_sum TCC_EA_RDREQ_sum TCC_EA_RDREQ_32B_sum TCC_EA_RD_UNCACHED_32B_sum
+
+gpu:
+range:
+kernel:
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/perfmon/pmc_perf_7.txt b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/perfmon/pmc_perf_7.txt
new file mode 100644
index 0000000000..ee1086ee6f
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/perfmon/pmc_perf_7.txt
@@ -0,0 +1,5 @@
+pmc:  SQC_DCACHE_REQ_READ_16 SQC_ICACHE_REQ SQC_ICACHE_HITS SQC_ICACHE_MISSES SQC_ICACHE_MISSES_DUPLICATE SQC_DCACHE_INPUT_VALID_READYB SQC_DCACHE_ATOMIC SQC_DCACHE_REQ_READ_8 TCP_TCC_NC_WRITE_REQ_sum TCP_TCC_NC_ATOMIC_REQ_sum TCP_TCC_UC_READ_REQ_sum TCP_TCC_UC_WRITE_REQ_sum TA_FLAT_WRITE_WAVEFRONTS_sum TA_FLAT_ATOMIC_WAVEFRONTS_sum SPI_RA_WVLIM_STALL_CSN SPI_SWC_CSC_WR TCC_EA_RDREQ_IO_CREDIT_STALL_sum TCC_EA_RDREQ_GMI_CREDIT_STALL_sum TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum TCC_TAG_STALL_sum
+
+gpu:
+range:
+kernel:
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/perfmon/pmc_perf_8.txt b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/perfmon/pmc_perf_8.txt
new file mode 100644
index 0000000000..db56f1cd33
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/perfmon/pmc_perf_8.txt
@@ -0,0 +1,5 @@
+pmc:  SQC_DCACHE_REQ SQC_DCACHE_HITS SQC_DCACHE_MISSES SQC_DCACHE_MISSES_DUPLICATE SQC_DCACHE_REQ_READ_1 SQC_DCACHE_REQ_READ_2 SQC_DCACHE_REQ_READ_4 TCP_TCC_UC_ATOMIC_REQ_sum TCP_TCC_CC_READ_REQ_sum TCP_TCC_CC_WRITE_REQ_sum TCP_TCC_CC_ATOMIC_REQ_sum SPI_VWC_CSC_WR SPI_RA_BULKY_CU_FULL_CSN TCC_NORMAL_WRITEBACK_sum TCC_ALL_TC_OP_WB_WRITEBACK_sum TCC_NORMAL_EVICT_sum TCC_ALL_TC_OP_INV_EVICT_sum
+
+gpu:
+range:
+kernel:
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/perfmon/pmc_perf_9.txt b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/perfmon/pmc_perf_9.txt
new file mode 100644
index 0000000000..353ccaef82
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/perfmon/pmc_perf_9.txt
@@ -0,0 +1,5 @@
+pmc:  TCP_TCC_RW_READ_REQ_sum TCP_TCC_RW_WRITE_REQ_sum TCP_TCC_RW_ATOMIC_REQ_sum TCP_PENDING_STALL_CYCLES_sum TCC_EA_RDREQ_DRAM_sum TCC_EA_WRREQ_DRAM_sum TCC_EA_RDREQ_LEVEL_sum TCC_EA_WRREQ_LEVEL_sum
+
+gpu:
+range:
+kernel:
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/perfmon/timestamps.txt b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/perfmon/timestamps.txt
new file mode 100644
index 0000000000..676cca1b80
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/perfmon/timestamps.txt
@@ -0,0 +1,5 @@
+pmc:
+
+gpu:
+range:
+kernel:
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/pmc_dispatch_info.csv
new file mode 100644
index 0000000000..e90d72a8cf
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/pmc_dispatch_info.csv
@@ -0,0 +1,2 @@
+Dispatch_ID,Kernel_Name,GPU_ID
+0,"vecCopy(double*, double*, double*, int, int) ",2
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/pmc_perf.csv
new file mode 100644
index 0000000000..a53d80c878
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/pmc_perf.csv
@@ -0,0 +1,2 @@
+Dispatch_ID,Kernel_Name,GPU_ID,grd,Workgroup_Size,LDS_Per_Workgroup,scr,arch_vgpr,accum_vgpr,SGPR,wave_size,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,TA_BUFFER_TOTAL_CYCLES_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,wave_size_1,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],wave_size_2,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,wave_size_3,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],wave_size_4,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,wave_size_5,TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],wave_size_6,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_BUFFER_WAVEFRONTS_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,wave_size_7,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,wave_size_8,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,wave_size_9,TCC_EA_ATOMIC_LEVEL_sum,wave_size_10,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,wave_size_11,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_BUFFER_READ_WAVEFRONTS_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,wave_size_12,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,wave_size_13,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],wave_size_14,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],wave_size_15,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,wave_size_16,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],Start_Timestamp,End_Timestamp
+0,"vecCopy(double*, double*, double*, int, int) ",2,1046016,256,0,0,8,8,16,64,16344,392228,23443110,2018557,359542,163424,0,0,2091776.0,2091776.0,1045888.0,1045888.0,0.0,0.0,0.0,16342.0,14630,30974,9451,588,0,47061,261880.0,0.0,188.0,261692.0,64,0,3474879,4088,4088,0,4534699,4084,4084,0,3793563,4088,4088,0,3425718,4084,4084,0,3253146,4088,4088,0,3910232,4084,4084,0,3053230,4084,4084,0,3711457,4084,4084,0,3362919,4088,4088,0,3164445,4084,4084,0,4516092,4084,4084,0,3402722,4084,4084,0,3380518,4088,4088,0,5150141,4084,4084,0,3536125,4087,4086,0,3662403,4084,4084,0,3410502,4088,4088,0,3233234,4084,4084,0,4012039,4088,4088,0,3806690,4084,4084,0,3266843,4088,4088,0,4114160,4084,4084,0,3773210,4084,4084,0,4001481,4084,4084,0,3625676,4088,4088,0,3952599,4084,4084,0,3104744,4084,4084,0,4602397,4084,4084,0,3620205,4088,4088,0,4505408,4084,4084,0,3264580,4088,4088,0,3821332,4084,4084,64,0,65374,64380,48,1330,201007,0,0,0.0,0.0,0.0,0.0,16342.0,0.0,0,81720,0.0,0.0,46369.0,112735.0,64,4084,0,3830,0,4088,0,484,0,4084,0,583,0,4088,0,904,0,4084,0,262,0,4084,0,515,0,4084,0,1234,0,4088,0,1549,0,4084,0,1637,0,4084,0,728,0,4085,0,1306,0,4088,0,1662,0,4084,0,1111,0,4088,0,2576,0,4084,0,1074,0,4088,0,240,0,4084,0,1957,0,4087,0,2021,0,4324,0,2429,0,4088,0,547,0,4084,0,580,0,4132,0,4119,0,4085,0,1966,0,4088,0,1661,0,4084,0,65,0,4132,0,1785,0,4084,0,1208,0,4088,0,707,0,4084,0,0,0,4088,0,2490,0,4087,0,548,0,4088,0,1872,0,64,179766,114404,0,32688,32684,16342,16342,65372,0.0,0.0,120.0,522938.0,0.0,0.0,0,0,1815,47384,0,131313.0,130735.0,0.0,130767.0,64,8172,0,4088,8172,0,4084,8172,0,4088,8172,0,4084,8172,0,4088,8168,0,4084,8168,0,4084,8172,0,4084,8172,0,4088,8168,0,4084,8168,0,4084,8172,0,4084,8172,0,4088,8172,0,4084,8171,0,4087,8172,0,4084,8172,0,4088,8171,0,4084,8172,0,4088,8172,0,4084,8172,0,4088,8168,0,4084,8168,0,4084,8172,0,4084,8172,0,4088,8168,0,4084,8168,0,4084,8172,0,4084,8172,0,4088,8172,0,4084,8172,0,4088,8316,0,4084,64,394240,243736,3563750,16344,25120901,16342,16342,32684,49279,49279,4008097.0,3095742.0,5118.0,905741.0,2194719.0,0.0,3086745.0,2777815.0,392847,253666,49279,0,49279,0,1576928.0,984381.0,0.0,0.0,64,130735.0,130735.0,0.0,2470076.0,131100.0,130735.0,128055860.0,59601515.0,64,0,0,0,1046016,0,0,0,0,60929458.0,160131054.0,78079506.0,130735.0,0.0,602477.0,0,0,26715,0.0,0.0,140088.0,0.0,64,0.0,64,0,130744,144,48,0,0,0,192,130735.0,0.0,0.0,0.0,32684.0,16342.0,0,0,0.0,131062.0,0.0,646.0,64,49032,0,65372,32684,0,0,0,16344,31572,0.0,0.0,0.0,32684.0,0.0,0.0,0.0,32684.0,4086,16344,512,47418,1751,0,48.0,385.0,0.0,261614.0,64,65372,63884,48,1440,32688,32684,0,0.0,0.0,0.0,0.0,16344,0,86872.0,43863.0,130437.0,0.0,64,0,8459,4371,8459,0,8172,4088,8172,0,8172,4084,8172,0,8172,4088,8172,0,8172,4084,8172,0,8168,4084,8168,0,8168,4084,8168,0,8172,4088,8172,0,8173,4085,8173,0,8168,4084,8168,0,8168,4084,8168,47,8222,4185,8269,0,8172,4084,8172,0,8172,4088,8172,0,8171,4084,8171,0,8172,4088,8172,0,8172,4084,8172,0,8171,4087,8171,0,8172,4084,8172,0,8172,4088,8172,0,8172,4084,8172,0,8168,4084,8168,0,8168,4084,8168,0,8172,4088,8172,0,8172,4084,8172,0,8216,4132,8216,0,8168,4084,8168,0,8172,4088,8172,0,8172,4084,8172,0,8172,4088,8172,0,8172,4084,8172,141,8175,4232,8316,64,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,64,49032,11504916,65374,0,0,0,16344,0,960.0,512577.0,0.0,522938.0,890106.0,32684.0,0,0,0,18371,130735.0,130734.0,0.0,111945.0,64,1543,0,0,1775710,3049,0,0,2012359,2234,0,0,1923221,1897,0,0,1776784,804,0,0,1695337,1099,0,0,1592425,573,0,0,1609050,1265,0,0,1749524,2139,0,0,1910507,2144,0,0,1958065,1555,0,0,1822994,1053,0,0,1638701,4160,0,0,1973109,722,0,0,1767281,1416,0,0,1839198,9128,0,0,2424807,3626,0,0,1954616,1866,0,0,1825681,1068,0,0,1723385,1200,0,0,1755096,949,0,0,1683680,1318,0,0,1776912,2306,0,0,1854211,1169,0,0,1889251,1752,0,0,1708621,635,0,0,1622777,5166,0,0,2191709,3408,0,0,1978738,1896,0,0,1845524,1786,0,0,1747018,1787,0,0,1822316,1660,0,0,1784217,170459569892517.0,170459569917477.0
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/pmc_perf_0.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/pmc_perf_0.csv
new file mode 100644
index 0000000000..5171f7d1d5
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/pmc_perf_0.csv
@@ -0,0 +1,2 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,arch_vgpr,accum_vgpr,SGPR,wave_size,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_BUFFER_WAVEFRONTS_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int) ",2,0,0,184202,184202,1046016,256,0,0,8,8,16,64,0x0,0x7fd01739c900,394240,243736,3563750,16344,25120901,16342,16342,32684,49279,49279,4008097.0,3095742.0,5118.0,905741.0,2194719.0,0.0,3086745.0,2777815.0,392847,253666,49279,0,49279,0,1576928.0,984381.0,0.0,0.0,170462954930304,170459569892517,170459569917477,170462962833305
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/pmc_perf_1.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/pmc_perf_1.csv
new file mode 100644
index 0000000000..008238f966
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/pmc_perf_1.csv
@@ -0,0 +1,2 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,arch_vgpr,accum_vgpr,SGPR,wave_size,sig,obj,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_BUFFER_READ_WAVEFRONTS_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int) ",2,0,0,182745,182745,1046016,256,0,0,8,8,16,64,0x0,0x7fc67c952900,49032,0,65372,32684,0,0,0,16344,31572,0.0,0.0,0.0,32684.0,0.0,0.0,0.0,32684.0,4086,16344,512,47418,1751,0,48.0,385.0,0.0,261614.0,170459144419482,170459569892517,170459569917477,170459152290652
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/pmc_perf_10.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/pmc_perf_10.csv
new file mode 100644
index 0000000000..2d95e46f26
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/pmc_perf_10.csv
@@ -0,0 +1,2 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,arch_vgpr,accum_vgpr,SGPR,wave_size,sig,obj,TCC_EA_ATOMIC_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int) ",2,0,0,185476,185476,1046016,256,0,0,8,8,16,64,0x0,0x7f9648acc900,0.0,170466145856470,170459569892517,170459569917477,170466153429988
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/pmc_perf_11.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/pmc_perf_11.csv
new file mode 100644
index 0000000000..f24400b0c1
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/pmc_perf_11.csv
@@ -0,0 +1,2 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,arch_vgpr,accum_vgpr,SGPR,wave_size,sig,obj,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int) ",2,0,0,186569,186569,1046016,256,0,0,8,8,16,64,0x0,0x7f58b74bc900,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,0,48063,0,0,170469303060323,170459569892517,170459569917477,170469310908370
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/pmc_perf_12.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/pmc_perf_12.csv
new file mode 100644
index 0000000000..c0d0b6b122
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/pmc_perf_12.csv
@@ -0,0 +1,2 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,arch_vgpr,accum_vgpr,SGPR,wave_size,sig,obj,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int) ",2,0,0,183110,183110,1046016,256,0,0,8,8,16,64,0x0,0x7f2e1188c900,4084,0,3830,0,4088,0,484,0,4084,0,583,0,4088,0,904,0,4084,0,262,0,4084,0,515,0,4084,0,1234,0,4088,0,1549,0,4084,0,1637,0,4084,0,728,0,4085,0,1306,0,4088,0,1662,0,4084,0,1111,0,4088,0,2576,0,4084,0,1074,0,4088,0,240,0,4084,0,1957,0,4087,0,2021,0,4324,0,2429,0,4088,0,547,0,4084,0,580,0,4132,0,4119,0,4085,0,1966,0,4088,0,1661,0,4084,0,65,0,4132,0,1785,0,4084,0,1208,0,4088,0,707,0,4084,0,0,0,4088,0,2490,0,4087,0,548,0,4088,0,1872,0,170460168322816,170459569892517,170459569917477,170460176125457
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/pmc_perf_13.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/pmc_perf_13.csv
new file mode 100644
index 0000000000..a3bb3a1767
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/pmc_perf_13.csv
@@ -0,0 +1,2 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,arch_vgpr,accum_vgpr,SGPR,wave_size,sig,obj,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20],TCC_EA_RDREQ_IO_CREDIT_STALL[21],TCC_EA_RDREQ_LEVEL[21],TCC_EA_WRREQ[21],TCC_EA_WRREQ_64B[21],TCC_EA_RDREQ_IO_CREDIT_STALL[22],TCC_EA_RDREQ_LEVEL[22],TCC_EA_WRREQ[22],TCC_EA_WRREQ_64B[22],TCC_EA_RDREQ_IO_CREDIT_STALL[23],TCC_EA_RDREQ_LEVEL[23],TCC_EA_WRREQ[23],TCC_EA_WRREQ_64B[23],TCC_EA_RDREQ_IO_CREDIT_STALL[24],TCC_EA_RDREQ_LEVEL[24],TCC_EA_WRREQ[24],TCC_EA_WRREQ_64B[24],TCC_EA_RDREQ_IO_CREDIT_STALL[25],TCC_EA_RDREQ_LEVEL[25],TCC_EA_WRREQ[25],TCC_EA_WRREQ_64B[25],TCC_EA_RDREQ_IO_CREDIT_STALL[26],TCC_EA_RDREQ_LEVEL[26],TCC_EA_WRREQ[26],TCC_EA_WRREQ_64B[26],TCC_EA_RDREQ_IO_CREDIT_STALL[27],TCC_EA_RDREQ_LEVEL[27],TCC_EA_WRREQ[27],TCC_EA_WRREQ_64B[27],TCC_EA_RDREQ_IO_CREDIT_STALL[28],TCC_EA_RDREQ_LEVEL[28],TCC_EA_WRREQ[28],TCC_EA_WRREQ_64B[28],TCC_EA_RDREQ_IO_CREDIT_STALL[29],TCC_EA_RDREQ_LEVEL[29],TCC_EA_WRREQ[29],TCC_EA_WRREQ_64B[29],TCC_EA_RDREQ_IO_CREDIT_STALL[30],TCC_EA_RDREQ_LEVEL[30],TCC_EA_WRREQ[30],TCC_EA_WRREQ_64B[30],TCC_EA_RDREQ_IO_CREDIT_STALL[31],TCC_EA_RDREQ_LEVEL[31],TCC_EA_WRREQ[31],TCC_EA_WRREQ_64B[31],DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int) ",2,0,0,185840,185840,1046016,256,0,0,8,8,16,64,0x0,0x7f4873c06900,0,3474879,4088,4088,0,4534699,4084,4084,0,3793563,4088,4088,0,3425718,4084,4084,0,3253146,4088,4088,0,3910232,4084,4084,0,3053230,4084,4084,0,3711457,4084,4084,0,3362919,4088,4088,0,3164445,4084,4084,0,4516092,4084,4084,0,3402722,4084,4084,0,3380518,4088,4088,0,5150141,4084,4084,0,3536125,4087,4086,0,3662403,4084,4084,0,3410502,4088,4088,0,3233234,4084,4084,0,4012039,4088,4088,0,3806690,4084,4084,0,3266843,4088,4088,0,4114160,4084,4084,0,3773210,4084,4084,0,4001481,4084,4084,0,3625676,4088,4088,0,3952599,4084,4084,0,3104744,4084,4084,0,4602397,4084,4084,0,3620205,4088,4088,0,4505408,4084,4084,0,3264580,4088,4088,0,3821332,4084,4084,170467199460515,170459569892517,170459569917477,170467207183405
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/pmc_perf_14.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/pmc_perf_14.csv
new file mode 100644
index 0000000000..357557d2bc
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/pmc_perf_14.csv
@@ -0,0 +1,2 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,arch_vgpr,accum_vgpr,SGPR,wave_size,sig,obj,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_WRREQ_IO_CREDIT_STALL[26],TCC_EA_WRREQ_LEVEL[26],TCC_EA_WRREQ_DRAM_CREDIT_STALL[27],TCC_EA_WRREQ_GMI_CREDIT_STALL[27],TCC_EA_WRREQ_IO_CREDIT_STALL[27],TCC_EA_WRREQ_LEVEL[27],TCC_EA_WRREQ_DRAM_CREDIT_STALL[28],TCC_EA_WRREQ_GMI_CREDIT_STALL[28],TCC_EA_WRREQ_IO_CREDIT_STALL[28],TCC_EA_WRREQ_LEVEL[28],TCC_EA_WRREQ_DRAM_CREDIT_STALL[29],TCC_EA_WRREQ_GMI_CREDIT_STALL[29],TCC_EA_WRREQ_IO_CREDIT_STALL[29],TCC_EA_WRREQ_LEVEL[29],TCC_EA_WRREQ_DRAM_CREDIT_STALL[30],TCC_EA_WRREQ_GMI_CREDIT_STALL[30],TCC_EA_WRREQ_IO_CREDIT_STALL[30],TCC_EA_WRREQ_LEVEL[30],TCC_EA_WRREQ_DRAM_CREDIT_STALL[31],TCC_EA_WRREQ_GMI_CREDIT_STALL[31],TCC_EA_WRREQ_IO_CREDIT_STALL[31],TCC_EA_WRREQ_LEVEL[31],DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int) ",2,0,0,186022,186022,1046016,256,0,0,8,8,16,64,0x0,0x7fad31b34900,1543,0,0,1775710,3049,0,0,2012359,2234,0,0,1923221,1897,0,0,1776784,804,0,0,1695337,1099,0,0,1592425,573,0,0,1609050,1265,0,0,1749524,2139,0,0,1910507,2144,0,0,1958065,1555,0,0,1822994,1053,0,0,1638701,4160,0,0,1973109,722,0,0,1767281,1416,0,0,1839198,9128,0,0,2424807,3626,0,0,1954616,1866,0,0,1825681,1068,0,0,1723385,1200,0,0,1755096,949,0,0,1683680,1318,0,0,1776912,2306,0,0,1854211,1169,0,0,1889251,1752,0,0,1708621,635,0,0,1622777,5166,0,0,2191709,3408,0,0,1978738,1896,0,0,1845524,1786,0,0,1747018,1787,0,0,1822316,1660,0,0,1784217,170467815059135,170459569892517,170459569917477,170467822816651
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/pmc_perf_15.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/pmc_perf_15.csv
new file mode 100644
index 0000000000..ea604f8ca3
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/pmc_perf_15.csv
@@ -0,0 +1,2 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,arch_vgpr,accum_vgpr,SGPR,wave_size,sig,obj,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int) ",2,0,0,183292,183292,1046016,256,0,0,8,8,16,64,0x0,0x7fa36b62a900,0,8459,4371,8459,0,8172,4088,8172,0,8172,4084,8172,0,8172,4088,8172,0,8172,4084,8172,0,8168,4084,8168,0,8168,4084,8168,0,8172,4088,8172,0,8173,4085,8173,0,8168,4084,8168,0,8168,4084,8168,47,8222,4185,8269,0,8172,4084,8172,0,8172,4088,8172,0,8171,4084,8171,0,8172,4088,8172,0,8172,4084,8172,0,8171,4087,8171,0,8172,4084,8172,0,8172,4088,8172,0,8172,4084,8172,0,8168,4084,8168,0,8168,4084,8168,0,8172,4088,8172,0,8172,4084,8172,0,8216,4132,8216,0,8168,4084,8168,0,8172,4088,8172,0,8172,4084,8172,0,8172,4088,8172,0,8172,4084,8172,141,8175,4232,8316,170460778506870,170459569892517,170459569917477,170460786131284
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/pmc_perf_16.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/pmc_perf_16.csv
new file mode 100644
index 0000000000..8b6c4a1f50
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/pmc_perf_16.csv
@@ -0,0 +1,2 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,arch_vgpr,accum_vgpr,SGPR,wave_size,sig,obj,TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int) ",2,0,0,184566,184566,1046016,256,0,0,8,8,16,64,0x0,0x7f2a8a808900,8172,0,4088,8172,0,4084,8172,0,4088,8172,0,4084,8172,0,4088,8168,0,4084,8168,0,4084,8172,0,4084,8172,0,4088,8168,0,4084,8168,0,4084,8172,0,4084,8172,0,4088,8172,0,4084,8171,0,4087,8172,0,4084,8172,0,4088,8171,0,4084,8172,0,4088,8172,0,4084,8172,0,4088,8168,0,4084,8168,0,4084,8172,0,4084,8172,0,4088,8168,0,4084,8168,0,4084,8172,0,4084,8172,0,4088,8172,0,4084,8172,0,4088,8316,0,4084,170463959342369,170459569892517,170459569917477,170463967189665
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/pmc_perf_2.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/pmc_perf_2.csv
new file mode 100644
index 0000000000..4892de2d6a
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/pmc_perf_2.csv
@@ -0,0 +1,2 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,arch_vgpr,accum_vgpr,SGPR,wave_size,sig,obj,SQ_INSTS_SENDMSG,SQ_INSTS,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_INSTS_VALU,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,TA_BUFFER_TOTAL_CYCLES_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int) ",2,0,0,185112,185112,1046016,256,0,0,8,8,16,64,0x0,0x7eff4586e900,16344,392228,23443110,2018557,359542,163424,0,0,2091776.0,2091776.0,1045888.0,1045888.0,0.0,0.0,0.0,16342.0,14630,30974,9451,588,0,47061,261880.0,0.0,188.0,261692.0,170465269244275,170459569892517,170459569917477,170465277637692
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/pmc_perf_3.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/pmc_perf_3.csv
new file mode 100644
index 0000000000..f80f729576
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/pmc_perf_3.csv
@@ -0,0 +1,2 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,arch_vgpr,accum_vgpr,SGPR,wave_size,sig,obj,SQ_ACTIVE_INST_VALU,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int) ",2,0,0,185294,185294,1046016,256,0,0,8,8,16,64,0x0,0x7f54299b4900,179766,114404,0,32688,32684,16342,16342,65372,0.0,0.0,120.0,522938.0,0.0,0.0,0,0,1815,47384,0,131313.0,130735.0,0.0,130767.0,170465704653330,170459569892517,170459569917477,170465712329652
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/pmc_perf_4.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/pmc_perf_4.csv
new file mode 100644
index 0000000000..19e93814c8
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/pmc_perf_4.csv
@@ -0,0 +1,2 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,arch_vgpr,accum_vgpr,SGPR,wave_size,sig,obj,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_STALL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int) ",2,0,0,184748,184748,1046016,256,0,0,8,8,16,64,0x0,0x7f6b1841a900,49032,11504916,65374,0,0,0,16344,0,960.0,512577.0,0.0,522938.0,890106.0,32684.0,0,0,0,18371,130735.0,130734.0,0.0,111945.0,170464397062074,170459569892517,170459569917477,170464404849195
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/pmc_perf_5.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/pmc_perf_5.csv
new file mode 100644
index 0000000000..e42897d89a
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/pmc_perf_5.csv
@@ -0,0 +1,2 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,arch_vgpr,accum_vgpr,SGPR,wave_size,sig,obj,SQ_WAVES_LT_48,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_IO_CREDIT_STALL_sum,TCC_EA_WRREQ_GMI_CREDIT_STALL_sum,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int) ",2,0,0,185658,185658,1046016,256,0,0,8,8,16,64,0x0,0x7fe05667c900,0,0,0,1046016,0,0,0,0,60929458.0,160131054.0,78079506.0,130735.0,0.0,602477.0,0,0,26715,0.0,0.0,140088.0,0.0,170466583185886,170459569892517,170459569917477,170466590977837
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/pmc_perf_6.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/pmc_perf_6.csv
new file mode 100644
index 0000000000..cb550bb250
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/pmc_perf_6.csv
@@ -0,0 +1,2 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,arch_vgpr,accum_vgpr,SGPR,wave_size,sig,obj,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int) ",2,0,0,184384,184384,1046016,256,0,0,8,8,16,64,0x0,0x7ff903a32900,0,130744,144,48,0,0,0,192,130735.0,0.0,0.0,0.0,32684.0,16342.0,0,0,0.0,131062.0,0.0,646.0,170463392938864,170459569892517,170459569917477,170463400628381
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/pmc_perf_7.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/pmc_perf_7.csv
new file mode 100644
index 0000000000..eb42ad7c62
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/pmc_perf_7.csv
@@ -0,0 +1,2 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,arch_vgpr,accum_vgpr,SGPR,wave_size,sig,obj,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_EA_RDREQ_IO_CREDIT_STALL_sum,TCC_EA_RDREQ_GMI_CREDIT_STALL_sum,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum,TCC_TAG_STALL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int) ",2,0,0,183474,183474,1046016,256,0,0,8,8,16,64,0x0,0x7fed12eca900,0,65374,64380,48,1330,201007,0,0,0.0,0.0,0.0,0.0,16342.0,0.0,0,81720,0.0,0.0,46369.0,112735.0,170461215610530,170459569892517,170459569917477,170461223524381
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/pmc_perf_8.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/pmc_perf_8.csv
new file mode 100644
index 0000000000..5925b27114
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/pmc_perf_8.csv
@@ -0,0 +1,2 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,arch_vgpr,accum_vgpr,SGPR,wave_size,sig,obj,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int) ",2,0,0,183656,183656,1046016,256,0,0,8,8,16,64,0x0,0x7f45c6d52900,65372,63884,48,1440,32688,32684,0,0.0,0.0,0.0,0.0,16344,0,86872.0,43863.0,130437.0,0.0,170461649490635,170459569892517,170459569917477,170461657210750
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/pmc_perf_9.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/pmc_perf_9.csv
new file mode 100644
index 0000000000..dc3fc8b515
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/pmc_perf_9.csv
@@ -0,0 +1,2 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,arch_vgpr,accum_vgpr,SGPR,wave_size,sig,obj,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TCC_EA_RDREQ_DRAM_sum,TCC_EA_WRREQ_DRAM_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int) ",2,0,0,183838,183838,1046016,256,0,0,8,8,16,64,0x0,0x7f7e8ff6e900,130735.0,130735.0,0.0,2470076.0,131100.0,130735.0,128055860.0,59601515.0,170462083294677,170459569892517,170459569917477,170462091025412
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/pmc_perf_error_log.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/pmc_perf_error_log.csv
new file mode 100644
index 0000000000..13996cfa3c
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/pmc_perf_error_log.csv
@@ -0,0 +1,5 @@
+  ,CPC_CPC_STAT_BUSY ,CPC_CPC_STAT_STALL ,CPC_CPC_TCIU_BUSY ,CPC_CPC_UTCL2IU_BUSY ,CPC_ME1_BUSY_FOR_PACKET_DECODE ,CPC_ME1_DC0_SPI_BUSY ,CPF_CPF_STAT_BUSY ,CPF_CPF_TCIU_BUSY ,CPF_CPF_TCIU_IDLE ,GRBM_COUNT ,GRBM_GUI_ACTIVE ,SPI_CSN_BUSY ,SPI_CSN_WINDOW_VALID ,SPI_RA_REQ_NO_ALLOC ,SPI_RA_REQ_NO_ALLOC_CSN ,SQC_DCACHE_INPUT_VALID_READYB ,SQ_BUSY_CU_CYCLES ,SQ_BUSY_CYCLES ,SQ_CYCLES ,SQ_WAIT_ANY ,SQ_WAIT_INST_ANY ,TA_ADDR_STALLED_BY_TC_CYCLES_sum ,TA_DATA_STALLED_BY_TC_CYCLES_sum ,TA_TA_BUSY_sum ,TCC_ALL_TC_OP_WB_WRITEBACK_sum ,TCC_BUSY_sum ,TCC_CYCLE_sum ,TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum ,TCC_EA_RDREQ_LEVEL_sum ,TCC_EA_RD_UNCACHED_32B_sum ,TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum ,TCC_EA_WRREQ_LEVEL_sum ,TCC_EA_WRREQ_STALL_sum ,TCC_TAG_STALL_sum ,TCC_UC_REQ_sum ,TCP_GATE_EN1_sum ,TCP_GATE_EN2_sum ,TCP_PENDING_STALL_CYCLES_sum ,TCP_TCC_READ_REQ_LATENCY_sum ,TCP_TCC_WRITE_REQ_LATENCY_sum ,TCP_TCP_LATENCY_sum ,TCP_TCR_TCP_STALL_CYCLES_sum ,TCP_TD_TCP_STALL_CYCLES_sum ,TD_TC_STALL_sum ,TD_TD_BUSY_sum ,GPU_ID ,kernel_name                                     ,test_name
+0 ,                  ,                   ,                  ,                     ,                          7.33 ,                     ,                  ,              5.2 ,                  ,           ,                ,             ,                     ,              30.45 ,                  12.23 ,                         7.91 ,                  ,               ,          ,       7.38 ,            10.9 ,                           19.22 ,                                 ,               ,                               ,             ,              ,                             22.45 ,                 25.76 ,                     20.97 ,                            159.25 ,                       ,                       ,            10.42 ,         76.61 ,                 ,                 ,                             ,                       17.49 ,                              ,              16.78 ,                       17.14 ,                      12.51 ,                ,               ,   2.0 ,"vecCopy(double*, double*, double*, int, int) " ,logger
+0 ,             2.35 ,               5.0 ,             4.66 ,                1.17 ,                          7.33 ,                1.71 ,             2.35 ,              5.2 ,             2.57 ,      2.35 ,           2.35 ,        4.26 ,                2.32 ,              30.45 ,                  12.23 ,                         7.91 ,             4.51 ,          4.45 ,     2.35 ,       7.38 ,            10.9 ,                           19.22 ,                            4.14 ,          4.14 ,                          1.21 ,        1.62 ,         2.35 ,                             22.45 ,                 25.76 ,                     20.97 ,                            159.25 ,                  1.57 ,                  4.88 ,            10.42 ,         76.61 ,            4.05 ,            2.82 ,                        4.94 ,                       17.49 ,                         3.11 ,              16.78 ,                       17.14 ,                      12.51 ,            3.2 ,          2.84 ,       ,"vecCopy(double*, double*, double*, int, int) " ,test_path
+0 ,             2.35 ,               5.0 ,             4.66 ,                1.17 ,                          7.33 ,                1.71 ,             2.35 ,              5.2 ,             2.57 ,      2.35 ,           2.35 ,        4.26 ,                2.32 ,              30.45 ,                  12.23 ,                         7.91 ,             4.51 ,          4.45 ,     2.35 ,       7.38 ,            10.9 ,                           19.22 ,                            4.14 ,          4.14 ,                          1.21 ,        1.62 ,         2.35 ,                             22.45 ,                 25.76 ,                     20.97 ,                            159.25 ,                  1.57 ,                  4.88 ,            10.42 ,         76.61 ,            4.05 ,            2.82 ,                        4.94 ,                       17.49 ,                         3.11 ,              16.78 ,                       17.14 ,                      12.51 ,            3.2 ,          2.84 ,       ,"vecCopy(double*, double*, double*, int, int) " ,test_path
+0 ,             2.35 ,               5.0 ,             4.66 ,                1.17 ,                          7.33 ,                1.71 ,             2.35 ,              5.2 ,             2.57 ,      2.35 ,           2.35 ,        4.26 ,                2.32 ,              30.45 ,                  12.23 ,                         7.91 ,             4.51 ,          4.45 ,     2.35 ,       7.38 ,            10.9 ,                           19.22 ,                            4.14 ,          4.14 ,                          1.21 ,        1.62 ,         2.35 ,                             22.45 ,                 25.76 ,                     20.97 ,                            159.25 ,                  1.57 ,                  4.88 ,            10.42 ,         76.61 ,            4.05 ,            2.82 ,                        4.94 ,                       17.49 ,                         3.11 ,              16.78 ,                       17.14 ,                      12.51 ,            3.2 ,          2.84 ,       ,"vecCopy(double*, double*, double*, int, int) " ,test_path
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/sysinfo.csv
new file mode 100644
index 0000000000..a957c8e694
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/sysinfo.csv
@@ -0,0 +1,2 @@
+workload_name,command,host_name,host_cpu,host_distro,host_kernel,host_rocmver,date,gpu_soc,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,LDSBanks,name,numSQC,hbmBW,ip_blocks
+Baseline_mi100,"./sample/vcopy 1045876 256",t004-005.hpcfund,AMD EPYC 7V13 64-Core Processor,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,5.5.1-74,Thu Oct  5 12:46:57 2023 (CDT),gfx908,8,120,4,64,40,1024,16,8192,1502,1200,300,1200,32,32,mi100,48,1228.8,SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
\ No newline at end of file
diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/timestamps.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/timestamps.csv
new file mode 100644
index 0000000000..514e94b84e
--- /dev/null
+++ b/projects/rocprofiler-compute/tests/workloads/vcopy/mi200/timestamps.csv
@@ -0,0 +1,2 @@
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,arch_vgpr,accum_vgpr,SGPR,wave_size,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
+0,"vecCopy(double*, double*, double*, int, int) ",2,0,0,182928,182928,1046016,256,0,0,8,8,16,64,0x0,0x7f7d5f2ec900,170459569866514,170459569892517,170459569917477,170459569928641