Make SDMA engine availability status queryable.

Report the availability of SDMA engines for memory copies.

Change-Id: Ie31b02d6b65355122bb8c98bc73700a59bee166e

runtime/hsa-runtime/core/runtime/amd_gpu_agent.cpp

@@ -775,6 +775,43 @@ hsa_status_t GpuAgent::DmaCopy(void* dst, core::Agent& dst_agent,
   return stat;
 }
 
+hsa_status_t GpuAgent::DmaCopyStatus(core::Agent& dst_agent, core::Agent& src_agent,
+                                     uint32_t *engine_ids_mask) {
+  assert(((src_agent.device_type() == core::Agent::kAmdGpuDevice) ||
+          (dst_agent.device_type() == core::Agent::kAmdGpuDevice)) &&
+         ("Both devices are CPU agents which is not expected"));
+
+  *engine_ids_mask = 0;
+  if (src_agent.device_type() == core::Agent::kAmdGpuDevice &&
+                   dst_agent.device_type() == core::Agent::kAmdGpuDevice &&
+                     dst_agent.HiveId() && src_agent.HiveId() == dst_agent.HiveId() &&
+                       properties_.NumSdmaXgmiEngines) {
+    // Find a free xGMI SDMA engine
+    for (int i = 0; i < properties_.NumSdmaXgmiEngines; i++) {
+      if (!!!blits_[DefaultBlitCount + i]->PendingBytes()) {
+         *engine_ids_mask |= (HSA_AMD_SDMA_ENGINE_2 << i);
+      }
+    }
+  } else {
+    bool is_h2d_blit = (src_agent.device_type() == core::Agent::kAmdCpuDevice &&
+      dst_agent.device_type() == core::Agent::kAmdGpuDevice);
+    // Due to a RAS issue, GFX90a can only support H2D copies on SDMA0
+    bool limit_h2d_blit = isa_->GetVersion() == core::Isa::Version(9, 0, 10);
+
+    if (!!!blits_[BlitHostToDev]->PendingBytes()) {
+      if (is_h2d_blit || !limit_h2d_blit) {
+        *engine_ids_mask |= HSA_AMD_SDMA_ENGINE_0;
+      }
+    }
+
+    if (!!!blits_[BlitDevToHost]->PendingBytes()) {
+      *engine_ids_mask |= HSA_AMD_SDMA_ENGINE_1;
+    }
+  }
+
+  return !!(*engine_ids_mask) ? HSA_STATUS_SUCCESS : HSA_STATUS_ERROR_OUT_OF_RESOURCES;
+}
+
 hsa_status_t GpuAgent::DmaCopyRect(const hsa_pitched_ptr_t* dst, const hsa_dim3_t* dst_offset,
                                    const hsa_pitched_ptr_t* src, const hsa_dim3_t* src_offset,
                                    const hsa_dim3_t* range, hsa_amd_copy_direction_t dir,

runtime/hsa-runtime/core/runtime/hsa_api_trace.cpp

@@ -365,6 +365,7 @@ void HsaApiTable::UpdateAmdExts() {
   amd_ext_api.hsa_amd_memory_pool_allocate_fn = AMD::hsa_amd_memory_pool_allocate;
   amd_ext_api.hsa_amd_memory_pool_free_fn = AMD::hsa_amd_memory_pool_free;
   amd_ext_api.hsa_amd_memory_async_copy_fn = AMD::hsa_amd_memory_async_copy;
+  amd_ext_api.hsa_amd_memory_copy_engine_status_fn = AMD::hsa_amd_memory_copy_engine_status;
   amd_ext_api.hsa_amd_agent_memory_pool_get_info_fn = AMD::hsa_amd_agent_memory_pool_get_info;
   amd_ext_api.hsa_amd_agents_allow_access_fn = AMD::hsa_amd_agents_allow_access;
   amd_ext_api.hsa_amd_memory_pool_can_migrate_fn = AMD::hsa_amd_memory_pool_can_migrate;

runtime/hsa-runtime/core/runtime/hsa_ext_amd.cpp

@@ -276,6 +276,17 @@ hsa_status_t hsa_amd_memory_async_copy(void* dst, hsa_agent_t dst_agent_handle,
   CATCH;
 }
 
+hsa_status_t hsa_amd_memory_copy_engine_status(hsa_agent_t dst_agent_handle, hsa_agent_t src_agent_handle,
+                                               uint32_t *engine_ids_mask) {
+  core::Agent* dst_agent = core::Agent::Convert(dst_agent_handle);
+  IS_VALID(dst_agent);
+
+  core::Agent* src_agent = core::Agent::Convert(src_agent_handle);
+  IS_VALID(src_agent);
+
+  return core::Runtime::runtime_singleton_->CopyMemoryStatus(dst_agent, src_agent, engine_ids_mask);
+}
+
 hsa_status_t hsa_amd_memory_async_copy_rect(
     const hsa_pitched_ptr_t* dst, const hsa_dim3_t* dst_offset, const hsa_pitched_ptr_t* src,
     const hsa_dim3_t* src_offset, const hsa_dim3_t* range, hsa_agent_t copy_agent,

runtime/hsa-runtime/core/runtime/runtime.cpp

@@ -459,7 +459,7 @@ hsa_status_t Runtime::CopyMemory(void* dst, const void* src, size_t size) {
 
   /*
   GPU-GPU - functional support, not a performance path.
-  
+
   This goes through system memory because we have to support copying between non-peer GPUs
   and we can't use P2P pointers even if the GPUs are peers.  Because hsa_amd_agents_allow_access
   requires the caller to specify all allowed agents we can't assume that a peer mapped pointer
@@ -501,6 +501,18 @@ hsa_status_t Runtime::CopyMemory(void* dst, core::Agent* dst_agent, const void*
                              completion_signal);
 }
 
+hsa_status_t Runtime::CopyMemoryStatus(core::Agent* dst_agent, core::Agent* src_agent,
+                                       uint32_t *engine_ids_mask) {
+  const bool src_gpu = (src_agent->device_type() == core::Agent::DeviceType::kAmdGpuDevice);
+  core::Agent* copy_agent = (src_gpu) ? src_agent : dst_agent;
+
+  if (dst_agent == src_agent) {
+    return HSA_STATUS_ERROR_INVALID_AGENT;
+  }
+
+  return copy_agent->DmaCopyStatus(*dst_agent, *src_agent, engine_ids_mask);
+}
+
 hsa_status_t Runtime::FillMemory(void* ptr, uint32_t value, size_t count) {
   // Choose blit agent from pointer info
   hsa_amd_pointer_info_t info;