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P4 to Git Change 1065597 by gandryey@gera-dev-w7 on 2014/08/12 18:38:45

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ECR #304775 - Device enqueuing
	- Provide scratch buffer offset for generic address space
	- Use single scratch buffer for all available queues. Each queue will have a unique subbuffer in the global buffer

Affected files ...

... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpudevice.cpp#454 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpudevice.hpp#129 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpusched.hpp#11 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpuschedcl.cpp#24 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpuvirtual.cpp#329 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpuvirtual.hpp#120 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gslbe/src/rt/GSLContext.cpp#63 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gslbe/src/rt/GSLContext.h#37 edit
This commit is contained in:
foreman
2014-08-12 18:49:08 -04:00
parent 7e43e18d8c
commit 8fa184db38
8 changed files with 93 additions and 44 deletions
Download Patch File Download Diff File Expand all files Collapse all files
rocclr/runtime/device/gpu/gpuschedcl.cpp
+11 -9
View File
@@ -92,7 +92,7 @@ typedef struct _SchedulerParam {
uint releaseHostCP; //!< Releases CP on the host queue
ulong parentAQL; //!< Host parent AmdAqlWrap packet
uint dedicatedQueue; //!< Scheduler uses a dedicated queue
uint reserved; //!< Reserved field
uint scratchOffset; //!< Scratch buffer offset
} SchedulerParam;
typedef struct _HwDispatch {
@@ -152,7 +152,7 @@ typedef struct _HwDispatch {
uint shPrivateHi; // 0x00000000 ---- dstAddressHi
uint user4; // 0xC0027602 -- TYPE 3, SET_SH_REG, TYPE:COMPUTE (2 values)
uint offsUser4; // 0x00000248 ---- OFFSET
uint privOffs; // 0x00000000 ---- COMPUTE_USER_DATA_10: DATA = 0x0
uint scratchOffs; // 0x00000000 ---- COMPUTE_USER_DATA_10: DATA = 0x0
uint privSize; // 0x00000030 ---- COMPUTE_USER_DATA_11: DATA = 0x30
uint packet4; // 0xC0031502 -- TYPE 3, DISPATCH_DIRECT, TYPE:COMPUTE
uint glbSizeX; // 0x00000000
@@ -170,10 +170,11 @@ static inline void
dispatch(
volatile __global HwDispatch* dispatch,
__global HsaAqlDispatchPacket* aqlPkt,
uint scratchSize,
uint numMaxWaves,
ulong scratch,
ulong hsaQueue)
ulong scratch,
ulong hsaQueue,
uint scratchSize,
uint scratchOffset,
uint numMaxWaves)
{
const uint UsrRegOffset = 0x240;
const uint Pm4Nop = 0xC0001002;
@@ -258,8 +259,9 @@ dispatch(
// flatScratchEna = (flags & 0x20);
if (flags & 0x20) {
dispatch->copyData = Pm4CopyReg;
dispatch->scratchAddrLo = (uint)(scratch >> 16);
dispatch->scratchAddrLo = (uint)((scratch - scratchOffset) >> 16);
dispatch->offsUser4 = UsrRegOffset + usrRegCnt;
dispatch->scratchOffs = scratchOffset;
dispatch->privSize = privateSize;
}
else {
@@ -421,8 +423,8 @@ scheduler(
(__hsail_get_clock() * (ulong)param->eng_clk) >> 10;
}
// Launch child kernel ....
dispatch(hwDisp, &disp->aql, param->scratchSize, param->numMaxWaves,
param->scratch, param->hsa_queue);
dispatch(hwDisp, &disp->aql, param->scratch, param->hsa_queue,
param->scratchSize, param->scratchOffset, param->numMaxWaves);
disp->state = AQL_WRAP_BUSY;
releaseWaitEvents((__global AmdEvent**)(disp->wait_list),
disp->wait_num, (__global uint*)queue->event_slot_mask,