Update code object handling for GSL, PAL and ROCm

- Correct GSL path to report targets using the TargetID syntax.

- Correct GSL path to check compatibility of code objects when
  loading.

- Add concept of an device isa and create a registery used by ROCm,
  PAL and GSL.

- Support XNACK and SRAMECC target features consistently for PAL and ROCm.

- Correct logic for NullDevices and asserts to avoid memory coruption.

- Allow all NullDevices to be created for HIP.

- Numerous other code improvements.

Change-Id: I40abf3d2b22249c1492d1af5919665f8184f4e0e


[ROCm/clr commit: c7e8d91e14]
This commit is contained in:
Tony Tye committed 2021-01-14 11:11:51 -05:00
1 parent b43d61e48f
commit 902cf1a239
30 files changed
+1020 -969

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@@ -1166,7 +1166,7 @@ bool Kernel::SetAvailableSgprVgpr() {
bool hasVgprMeta = false;
amd_comgr_status_t status = amd::Comgr::get_isa_metadata(
prog().device().info().targetId_, &isaMeta);
prog().device().isa().isaName().c_str(), &isaMeta);
if (status == AMD_COMGR_STATUS_SUCCESS) {
hasIsaMeta = true;