From 90938b804ff2ecd7982df8db4877c43477a1ab07 Mon Sep 17 00:00:00 2001
From: Aditya Atluri <Aditya.Atluri@amd.com>
Date: Mon, 12 Dec 2016 10:16:58 -0600
Subject: [PATCH] Changed threadfences to match target parsing by hcc

Change-Id: I28fcabbaacd13495b707f263fd09afaead0665fa


[ROCm/hip commit: 765947aaf52caf329f4b60608580e7ca06a24dc0]
---
 projects/hip/src/hip_ir.ll | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/projects/hip/src/hip_ir.ll b/projects/hip/src/hip_ir.ll
index d0e2a879a3..21123dd7c0 100644
--- a/projects/hip/src/hip_ir.ll
+++ b/projects/hip/src/hip_ir.ll
@@ -2,12 +2,12 @@ target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:
 target triple = "amdgcn--amdhsa"
 
 
-define void @__threadfence() #1 {
+define linkonce_odr spir_func void @__threadfence() #1 {
     fence syncscope(2) seq_cst
     ret void
 }
 
-define void @__threadfence_block()  #1 {
+define linkonce_odr spir_func void @__threadfence_block()  #1 {
     fence syncscope(3) seq_cst
     ret void
 }