From 96640b24ff2f4750edd31b3b9bc52f7b2fc9016a Mon Sep 17 00:00:00 2001
From: sdashmiz <shadi.dashmiz@amd.com>
Date: Fri, 12 Aug 2022 09:46:07 -0400
Subject: [PATCH] SWDEV-350569 - add proper indexing for attribute

- rocr attribute needs to be updated after each iteration

Signed-off-by: sdashmiz <shadi.dashmiz@amd.com>
Change-Id: I3afb2d7954ef3de37f5f5f9d3cc7757fdacffcec


[ROCm/clr commit: 50e0ddb0559a5e1e7001a2d94dba5f86bf939ff3]
---
 projects/clr/rocclr/device/rocm/rocdevice.cpp | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/projects/clr/rocclr/device/rocm/rocdevice.cpp b/projects/clr/rocclr/device/rocm/rocdevice.cpp
index dfe64f8dd5..9aaca7c774 100644
--- a/projects/clr/rocclr/device/rocm/rocdevice.cpp
+++ b/projects/clr/rocclr/device/rocm/rocdevice.cpp
@@ -2479,6 +2479,7 @@ bool Device::GetSvmAttributes(void** data, size_t* data_sizes, int* attributes,
           // Cast ROCr value into the hip format
           *reinterpret_cast<uint32_t*>(data[idx]) =
               (static_cast<uint32_t>(it.value) > 0) ? true : false;
+          ++rocr_attr;
           break;
         // The logic should be identical for the both queries
         case amd::MemRangeAttribute::PreferredLocation:
@@ -2499,6 +2500,7 @@ bool Device::GetSvmAttributes(void** data, size_t* data_sizes, int* attributes,
               *reinterpret_cast<int32_t*>(data[idx]) = static_cast<int32_t>(amd::CpuDeviceId);
             }
           }
+          ++rocr_attr;
           break;
         case amd::MemRangeAttribute::AccessedBy: {
           uint32_t entry = 0;
@@ -2557,6 +2559,7 @@ bool Device::GetSvmAttributes(void** data, size_t* data_sizes, int* attributes,
             // Cast ROCr value into the hip format
             *reinterpret_cast<uint32_t*>(data[idx]) = static_cast<uint32_t>(it.value);
           }
+          ++rocr_attr;
           break;
         default:
           return false;