SWDEV-240803 - add hipFuncSetSharedMemConfig

Change-Id: I160b04677b3e7b99b3981ae7ecc84a0e3811d5e8

include/hip/hcc_detail/hip_runtime_api.h

@@ -312,7 +312,6 @@ typedef enum hipFuncCache_t {
     hipFuncCachePreferEqual,   ///< prefer equal size L1 cache and shared memory
 } hipFuncCache_t;
 
-
 /**
  * @warning On AMD devices and some Nvidia devices, these hints and controls are ignored.
  */
@@ -566,6 +565,20 @@ hipError_t hipFuncSetAttribute(const void* func, hipFuncAttribute attr, int valu
  */
 hipError_t hipFuncSetCacheConfig(const void* func, hipFuncCache_t config);
 
+/**
+ * @brief Set shared memory configuation for a specific function
+ *
+ * @param [in] func
+ * @param [in] config
+ *
+ * @returns #hipSuccess, #hipErrorInvalidDeviceFunction, #hipErrorInvalidValue
+ *
+ * Note: AMD devices and some Nvidia GPUS do not support shared cache banking, and the hint is
+ * ignored on those architectures.
+ *
+ */
+hipError_t hipFuncSetSharedMemConfig(const void* func, hipSharedMemConfig config);
+
 /**
  * @brief Returns bank width of shared memory for current device
  *

include/hip/nvcc_detail/hip_runtime_api.h

@@ -1016,6 +1016,10 @@ inline static hipError_t hipDeviceSetCacheConfig(hipFuncCache_t cacheConfig) {
     return hipCUDAErrorTohipError(cudaDeviceSetCacheConfig(cacheConfig));
 }
 
+inline static hipError_t hipFuncSetSharedMemConfig(const void* func, hipSharedMemConfig config) {
+    return hipCUDAErrorTohipError(cudaFuncSetSharedMemConfig(func, config));
+}
+
 inline static const char* hipGetErrorString(hipError_t error) {
     return cudaGetErrorString(hipErrorToCudaError(error));
 }