From 9aca622a926239eb58e3feb29104767a0c81b1f5 Mon Sep 17 00:00:00 2001 From: foreman Date: Fri, 20 Jul 2018 19:34:45 -0400 Subject: [PATCH] P4 to Git Change 1583633 by vsytchen@vsytchen-win10 on 2018/07/20 18:09:50 SWDEV-79445 - OCL generic changes and code clean-up 1. Purge reduntant SVM alignment. The size will always get correctly aligned inside of PAL/GSL. ReviewBoardURL = http://ocltc.amd.com/reviews/r/15454/diff/ Affected files ... ... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpudevice.cpp#596 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpuresource.cpp#245 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/pal/paldevice.cpp#98 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/pal/palresource.cpp#70 edit --- rocclr/runtime/device/gpu/gpudevice.cpp | 5 ----- rocclr/runtime/device/gpu/gpuresource.cpp | 3 +++ rocclr/runtime/device/pal/paldevice.cpp | 5 ----- rocclr/runtime/device/pal/palresource.cpp | 3 ++- 4 files changed, 5 insertions(+), 11 deletions(-) diff --git a/rocclr/runtime/device/gpu/gpudevice.cpp b/rocclr/runtime/device/gpu/gpudevice.cpp index 6c9821eef9..53185f9106 100644 --- a/rocclr/runtime/device/gpu/gpudevice.cpp +++ b/rocclr/runtime/device/gpu/gpudevice.cpp @@ -2089,11 +2089,6 @@ void* Device::svmAlloc(amd::Context& context, size_t size, size_t alignment, cl_ void* svmPtr) const { alignment = std::max(alignment, static_cast(info_.memBaseAddrAlign_)); - // VAM for GPU needs 64K alignment for Tahiti and CI+, will pull idnfo from gsl later - size_t vmBigK = 64 * Ki; - alignment = (alignment < vmBigK) ? vmBigK : alignment; - - size = amd::alignUp(size, alignment); amd::Memory* mem = NULL; if (NULL == svmPtr) { if (isFineGrainedSystem()) { diff --git a/rocclr/runtime/device/gpu/gpuresource.cpp b/rocclr/runtime/device/gpu/gpuresource.cpp index bdf8c28cbd..4cb76c53a3 100644 --- a/rocclr/runtime/device/gpu/gpuresource.cpp +++ b/rocclr/runtime/device/gpu/gpuresource.cpp @@ -415,6 +415,9 @@ bool Resource::create(MemoryType memType, CreateParams* params) { //! @todo Remove alignment. //! GSL asserts in mem copy with an unaligned size cal_.width_ = amd::alignUp(cal_.width_, 64); + if ((desc.section == GSL_SECTION_SVM || desc.section == GSL_SECTION_SVM_ATOMICS)) { + cal_.width_ = amd::alignUp(cal_.width_, 64 * Ki / sizeof(uint32_t)); + } } desc.dimension = cal()->dimension_; diff --git a/rocclr/runtime/device/pal/paldevice.cpp b/rocclr/runtime/device/pal/paldevice.cpp index 8a01000cca..3a8bb5388a 100644 --- a/rocclr/runtime/device/pal/paldevice.cpp +++ b/rocclr/runtime/device/pal/paldevice.cpp @@ -1985,11 +1985,6 @@ void* Device::svmAlloc(amd::Context& context, size_t size, size_t alignment, cl_ void* svmPtr) const { alignment = std::max(alignment, static_cast(info_.memBaseAddrAlign_)); - // VAM for GPU needs 64K alignment for Tahiti and CI+, will pull idnfo from gsl later - size_t vmBigK = 64 * Ki; - alignment = (alignment < vmBigK) ? vmBigK : alignment; - - size = amd::alignUp(size, alignment); amd::Memory* mem = nullptr; freeCPUMem_ = false; if (nullptr == svmPtr) { diff --git a/rocclr/runtime/device/pal/palresource.cpp b/rocclr/runtime/device/pal/palresource.cpp index 78d86aca75..334193fc09 100644 --- a/rocclr/runtime/device/pal/palresource.cpp +++ b/rocclr/runtime/device/pal/palresource.cpp @@ -972,7 +972,8 @@ bool Resource::CreatePinned(CreateParams* params) bool Resource::CreateSvm(CreateParams* params, Pal::gpusize svmPtr) { const bool isFineGrain = (memoryType() == RemoteUSWC) || (memoryType() == Remote); - size_t allocSize = amd::alignUp(desc().width_ * elementSize_, MaxGpuAlignment); + size_t allocSize = amd::alignUp(desc().width_ * elementSize_, + dev().properties().gpuMemoryProperties.fragmentSize); if (isFineGrain) { Pal::SvmGpuMemoryCreateInfo createInfo = {}; createInfo.isUsedForKernel = desc_.isAllocExecute_;