From 9ccbdb863011ec8e563595624778acc249f35f0d Mon Sep 17 00:00:00 2001 From: Giovanni Baraldi Date: Fri, 22 Nov 2024 13:24:57 -0600 Subject: [PATCH] Fix for cache invalidation in stitch.py Change-Id: I81fa7bd7006feb20fead5eca2003886f58e3ca53 [ROCm/rocprofiler commit: 3f437a9c4178fa41ab5a9b73f49bf1c33e880472] --- projects/rocprofiler/plugin/att/stitch.py | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/projects/rocprofiler/plugin/att/stitch.py b/projects/rocprofiler/plugin/att/stitch.py index 9a8509bf8a..546f0786ec 100644 --- a/projects/rocprofiler/plugin/att/stitch.py +++ b/projects/rocprofiler/plugin/att/stitch.py @@ -423,17 +423,16 @@ def stitch(insts, raw_code, jumps, gfxv, bIsAuto, codeservice): if "flat_" in as_line[0]: inc_ordering = True - if not "buffer_" in as_line[0] or not ("_inv" in as_line[0] or "_wb" in as_line[0]): - if not bGFX9 and "store" in as_line[0]: - VSMEM_INST.append([reverse_map[line], num_inflight]) - NUM_VSMEM += 1 - if inc_ordering: - vsmem_ordering = 1 - else: - VLMEM_INST.append([reverse_map[line], num_inflight]) - NUM_VLMEM += 1 - if inc_ordering: - vlmem_ordering = 1 + if not bGFX9 and "store" in as_line[0]: + VSMEM_INST.append([reverse_map[line], num_inflight]) + NUM_VSMEM += 1 + if inc_ordering: + vsmem_ordering = 1 + else: + VLMEM_INST.append([reverse_map[line], num_inflight]) + NUM_VLMEM += 1 + if inc_ordering: + vlmem_ordering = 1 elif inst.type == FLAT: smem_ordering = 1 vlmem_ordering = 1