Replace __HIP_PLATFORM_HCC__ with __HIP_PLATFORM_AMD__ (#1154)
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@@ -48,7 +48,7 @@ extern __shared__ struct mscclShmemData mscclShmem;
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#endif
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inline __device__ static void barrier(int nthreads) {
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#if defined(__HIP_PLATFORM_HCC__) || defined(__HCC__) || defined(__HIPCC__)
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#if defined(__HIP_PLATFORM_AMD__) || defined(__HCC__) || defined(__HIPCC__)
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assert(nthreads == NCCL_MAX_NTHREADS);
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__asm__ __volatile__("s_waitcnt vmcnt(0) lgkmcnt(0)\ns_barrier");
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#else
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@@ -81,7 +81,7 @@ private:
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uint64_t* barrier_next;
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inline __device__ void barrier() {
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#if defined(__HIP_PLATFORM_HCC__) || defined(__HCC__) || defined(__HIPCC__)
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#if defined(__HIP_PLATFORM_AMD__) || defined(__HCC__) || defined(__HIPCC__)
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if (nthreads != WARP_SIZE)
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barrier_by_group();
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#else
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@@ -159,7 +159,7 @@ private:
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}
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#endif
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#if defined(__HIP_PLATFORM_HCC__) || defined(__HCC__) || defined(__HIPCC__)
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#if defined(__HIP_PLATFORM_AMD__) || defined(__HCC__) || defined(__HIPCC__)
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union ncclLLFifoLine i4;
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do {
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i4.v[0] = LL_LOAD(src->v);
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@@ -197,7 +197,7 @@ private:
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for (int i=BeginIx; i < MaxRecv; i++) {
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if (i < fan.nrecv()) {
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union ncclLLFifoLine* src = recvPtr(i) + offset;
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#if defined(__HIP_PLATFORM_HCC__) || defined(__HCC__) || defined(__HIPCC__)
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#if defined(__HIP_PLATFORM_AMD__) || defined(__HCC__) || defined(__HIPCC__)
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line[i].v[0] = LL_LOAD(src->v);
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line[i].v[1] = LL_LOAD(src->v+1);
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#else
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@@ -219,7 +219,7 @@ private:
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#endif
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do {
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#if defined(__HIP_PLATFORM_HCC__) || defined(__HCC__) || defined(__HIPCC__)
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#if defined(__HIP_PLATFORM_AMD__) || defined(__HCC__) || defined(__HIPCC__)
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line[i].v[0] = LL_LOAD(src->v);
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line[i].v[1] = LL_LOAD(src->v+1);
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#else
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@@ -243,7 +243,7 @@ private:
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}
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__device__ void storeLL(union ncclLLFifoLine* dst, uint64_t val, uint32_t flag) {
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#if defined(__HIP_PLATFORM_HCC__) || defined(__HCC__) || defined(__HIPCC__)
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#if defined(__HIP_PLATFORM_AMD__) || defined(__HCC__) || defined(__HIPCC__)
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union ncclLLFifoLine i4;
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i4.data1 = val & 0xffffffff;
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i4.flag1 = flag;
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@@ -267,7 +267,7 @@ private:
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uint32_t u4;
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uint64_t u8;
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};
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#if defined(__HIP_PLATFORM_HCC__) || defined(__HCC__) || defined(__HIPCC__)
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#if defined(__HIP_PLATFORM_AMD__) || defined(__HCC__) || defined(__HIPCC__)
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if(sizeof(U) == 1)
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u1 = LL_LOAD((uint8_t*)src);
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else if(sizeof(U) == 2)
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@@ -299,7 +299,7 @@ private:
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uint64_t u8;
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};
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elt = val;
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#if defined(__HIP_PLATFORM_HCC__) || defined(__HCC__) || defined(__HIPCC__)
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#if defined(__HIP_PLATFORM_AMD__) || defined(__HCC__) || defined(__HIPCC__)
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if(sizeof(U) == 1)
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LL_STORE(u1, (uint8_t*)dst);
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else if(sizeof(U) == 2)
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@@ -74,7 +74,7 @@ private:
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#endif
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inline __device__ void barrier() {
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#if defined(__HIP_PLATFORM_HCC__) || defined(__HCC__) || defined(__HIPCC__)
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#if defined(__HIP_PLATFORM_AMD__) || defined(__HCC__) || defined(__HIPCC__)
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if (nthreads != WARP_SIZE)
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barrier_by_group();
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#else
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