diff --git a/example/amd_smi_drm_example.cc b/example/amd_smi_drm_example.cc
index 09ae1144ee..1ac45844b6 100644
--- a/example/amd_smi_drm_example.cc
+++ b/example/amd_smi_drm_example.cc
@@ -380,8 +380,9 @@ int main() {
             CHK_AMDSMI_RET(ret)
             printf("    Output of amdsmi_get_pcie_link_status:\n");
             printf("\tPCIe lanes: %d\n", pcie_info.pcie_lanes);
-            printf("\tPCIe speed: %d\n\n", pcie_info.pcie_speed);
-            printf("\tPCIe Interface Version: %d\n\n", pcie_info.pcie_interface_version);
+            printf("\tPCIe speed: %d\n", pcie_info.pcie_speed);
+            printf("\tPCIe Interface Version: %d\n", pcie_info.pcie_interface_version);
+            printf("\tPCIe slot type: %d\n\n", pcie_info.pcie_slot_type);
 
             // Get PCIe caps
             amdsmi_pcie_info_t pcie_caps_info = {};
@@ -389,7 +390,7 @@ int main() {
             CHK_AMDSMI_RET(ret)
             printf("    Output of amdsmi_get_pcie_link_caps:\n");
             printf("\tPCIe max lanes: %d\n", pcie_caps_info.pcie_lanes);
-            printf("\tPCIe max speed: %d\n\n", pcie_caps_info.pcie_speed);
+            printf("\tPCIe max speed: %d\n", pcie_caps_info.pcie_speed);
             printf("\tPCIe Interface Version: %d\n\n", pcie_caps_info.pcie_interface_version);
 
             // Get VRAM temperature limit
diff --git a/include/amd_smi/amdsmi.h b/include/amd_smi/amdsmi.h
index 4f8f2536f1..66ec6dae2d 100644
--- a/include/amd_smi/amdsmi.h
+++ b/include/amd_smi/amdsmi.h
@@ -1157,6 +1157,7 @@ typedef struct {
 	uint16_t pcie_lanes;
 	uint32_t pcie_speed;
 	uint32_t pcie_interface_version;
+  uint32_t pcie_slot_type;   // 0: PCIE, 1: CEM, 2: OAM, 3: Reserved
 	uint32_t reserved[5];
 } amdsmi_pcie_info_t;
 /**
diff --git a/py-interface/amdsmi_interface.py b/py-interface/amdsmi_interface.py
index 9731bf6c65..74a8e23aeb 100644
--- a/py-interface/amdsmi_interface.py
+++ b/py-interface/amdsmi_interface.py
@@ -1061,7 +1061,8 @@ def amdsmi_get_pcie_link_status(
 
     return {"pcie_speed": pcie_info.pcie_speed,
             "pcie_lanes": pcie_info.pcie_lanes,
-            "pcie_interface_version": pcie_info.pcie_interface_version}
+            "pcie_interface_version": pcie_info.pcie_interface_version,
+            "pcie_slot_type": pcie_info.pcie_slot_type}
 
 def amdsmi_get_pcie_link_caps(
     processor_handle: amdsmi_wrapper.amdsmi_processor_handle,
@@ -1079,7 +1080,8 @@ def amdsmi_get_pcie_link_caps(
 
     return {"max_pcie_speed": pcie_info.pcie_speed,
             "max_pcie_lanes": pcie_info.pcie_lanes,
-            "pcie_interface_version": pcie_info.pcie_interface_version}
+            "pcie_interface_version": pcie_info.pcie_interface_version,
+            "pcie_slot_type": pcie_info.pcie_slot_type}
 
 
 def amdsmi_get_processor_handle_from_bdf(bdf):
diff --git a/py-interface/amdsmi_wrapper.py b/py-interface/amdsmi_wrapper.py
index 2c0fcfe1ab..a948f31c3d 100644
--- a/py-interface/amdsmi_wrapper.py
+++ b/py-interface/amdsmi_wrapper.py
@@ -1433,6 +1433,7 @@ struct_amdsmi_pcie_info_t._fields_ = [
     ('PADDING_0', ctypes.c_ubyte * 2),
     ('pcie_speed', ctypes.c_uint32),
     ('pcie_interface_version', ctypes.c_uint32),
+    ('pcie_slot_type', ctypes.c_uint32),
     ('reserved', ctypes.c_uint32 * 5),
 ]
 
diff --git a/src/amd_smi/amd_smi.cc b/src/amd_smi/amd_smi.cc
index f6a3fbef4c..66daf32be0 100644
--- a/src/amd_smi/amd_smi.cc
+++ b/src/amd_smi/amd_smi.cc
@@ -1813,6 +1813,23 @@ amdsmi_get_pcie_link_status(amdsmi_processor_handle processor_handle, amdsmi_pci
         info->pcie_interface_version = 0;
     }
 
+    // default to PCIe
+    info->pcie_slot_type = 0;
+    amd::smi::AMDSmiGPUDevice* gpu_device = nullptr;
+    status = get_gpu_device_from_handle(
+            processor_handle, &gpu_device);
+    if (status == AMDSMI_STATUS_SUCCESS
+            && gpu_device->check_if_drm_is_supported()) {
+        struct drm_amdgpu_info_device dev_info = {};
+        status = gpu_device->amdgpu_query_info(AMDGPU_INFO_DEV_INFO,
+                sizeof(struct drm_amdgpu_memory_info), &dev_info);
+        // bits [16:17] in ids_flags field as slot type
+        if (status == AMDSMI_STATUS_SUCCESS) {
+            // two bits starts with index 16
+            info->pcie_slot_type = (dev_info.ids_flags >> 16) & 0x03;
+        }
+    }
+
     return status;
 }
 
@@ -1887,6 +1904,19 @@ amdsmi_status_t amdsmi_get_pcie_link_caps(amdsmi_processor_handle processor_hand
         info->pcie_interface_version = 0;
     }
 
+    // default to PCIe
+    info->pcie_slot_type = 0;
+    if (gpu_device->check_if_drm_is_supported()) {
+        struct drm_amdgpu_info_device dev_info = {};
+        status = gpu_device->amdgpu_query_info(AMDGPU_INFO_DEV_INFO,
+                sizeof(struct drm_amdgpu_memory_info), &dev_info);
+        // bits [16:17] in ids_flags field as slot type
+        if (status == AMDSMI_STATUS_SUCCESS) {
+            // two bits starts with index 16
+            info->pcie_slot_type = (dev_info.ids_flags >> 16) & 0x03;
+        }
+    }
+
     return status;
 }