Added dispatch time, async copy and test template rocrtst tests
Change-Id: I57a844ee65c36bd61616ee6d60d358303f51db56
This commit is contained in:
@@ -50,11 +50,9 @@
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namespace rocrtst {
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BaseRocR::BaseRocR(void) {
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num_iteration_ = 100;
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signal_.handle = 0;
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num_iteration_ = 1;
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cpu_device_.handle = -1;
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gpu_device1_.handle = -1;
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region_.handle = 0;
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device_pool_.handle = 0;
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kern_arg_pool_.handle = 0;
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main_queue_ = nullptr;
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@@ -66,6 +64,7 @@ BaseRocR::BaseRocR(void) {
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orig_hsa_enable_interrupt_ = GetEnv("HSA_ENABLE_INTERRUPT");
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set_kernel_file_name("");
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set_verbosity(0);
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set_title("unset_title");
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}
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BaseRocR::~BaseRocR() {
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Regular → Executable
-17
@@ -105,13 +105,6 @@ class BaseRocR {
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return kernel_object_;
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}
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void set_signal(hsa_signal_t sig) {
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signal_.handle = sig.handle;
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}
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const hsa_signal_t& signal(void) const {
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return signal_;
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}
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void set_profile(hsa_profile_t in_prof) {
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profile_ = in_prof;
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}
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@@ -151,10 +144,6 @@ class BaseRocR {
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return aql_;
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}
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hsa_region_t& region(void) {
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return region_;
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}
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void set_num_iteration(int num) {
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num_iteration_ = num;
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}
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@@ -237,16 +226,12 @@ class BaseRocR {
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private:
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uint64_t num_iteration_; ///< Number of times to execute test
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hsa_signal_t signal_; ///< Completion signal used for kernel execution
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hsa_queue_t* main_queue_; ///< AQL queue used for packets
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hsa_agent_t gpu_device1_; ///< Handle to first GPU found
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hsa_agent_t cpu_device_; ///< Handle to CPU
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hsa_region_t region_; ///< TODO(cfreehil): delete this
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hsa_amd_memory_pool_t device_pool_; ///< Memory pool on gpu pool list
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hsa_amd_memory_pool_t cpu_pool_; ///< Memory pool on cpu pool list
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@@ -255,8 +240,6 @@ class BaseRocR {
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uint64_t kernel_object_; ///< Handle to kernel code
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std::string brig_file_; // TODO(cfreehil): delete this
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std::string kernel_file_name_; ///< Code object file name
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std::string kernel_name_; ///< Kernel name
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@@ -70,6 +70,8 @@ namespace rocrtst {
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} \
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}
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// Clean up some of the common handles and memory used by BaseRocR code, then
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// shut down hsa. Restore HSA_ENABLE_INTERRUPT to original value, if necessary
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hsa_status_t CommonCleanUp(BaseRocR* test) {
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hsa_status_t err;
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@@ -87,13 +89,9 @@ hsa_status_t CommonCleanUp(BaseRocR* test) {
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test->set_main_queue(nullptr);
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}
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if (0 != test->signal().handle) {
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hsa_signal_t sig;
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sig.handle = 0;
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err = hsa_signal_destroy(test->signal());
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if (test->aql().completion_signal.handle != 0) {
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err = hsa_signal_destroy(test->aql().completion_signal);
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RET_IF_HSA_UTILS_ERR(err);
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test->set_signal(sig);
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}
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err = hsa_shut_down();
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@@ -122,7 +120,7 @@ static const char* PROFILE_STR[] = {"HSA_PROFILE_BASE", "HSA_PROFILE_FULL", };
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/// \returns bool
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/// - true Machine meets test requirements
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/// - false Machine does not meet test requirements
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static bool CheckProfileAndInform(BaseRocR* test) {
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bool CheckProfileAndInform(BaseRocR* test) {
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if (test->verbosity() > 0) {
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std::cout << "Target HW Profile is "
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<< PROFILE_STR[test->profile()] << std::endl;
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@@ -162,6 +160,10 @@ static hsa_status_t ProcessIterateError(hsa_status_t err) {
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return err;
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}
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// Find pools for cpu, gpu and for kernel arguments. These pools have
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// common basic requirements, but are not suitable for all cases. In
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// that case, set cpu_pool(), device_pool() and/or kern_arg_pool()
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// yourself instead of using this function.
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hsa_status_t SetPoolsTypical(BaseRocR* test) {
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hsa_status_t err;
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@@ -180,11 +182,9 @@ hsa_status_t SetPoolsTypical(BaseRocR* test) {
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return HSA_STATUS_SUCCESS;
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}
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// Enable interrupts if necessary, and call hsa_init()
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hsa_status_t InitAndSetupHSA(BaseRocR* test) {
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hsa_agent_t gpu_device1;
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hsa_agent_t cpu_device;
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hsa_status_t err;
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hsa_signal_t sig;
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if (test->enable_interrupt()) {
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SetEnv("HSA_ENABLE_INTERRUPT", "1");
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@@ -193,6 +193,15 @@ hsa_status_t InitAndSetupHSA(BaseRocR* test) {
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err = hsa_init();
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RET_IF_HSA_UTILS_ERR(err);
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return HSA_STATUS_SUCCESS;
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}
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// Attempt to find and set test->cpu_device and test->gpu_device1
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hsa_status_t SetDefaultAgents(BaseRocR* test) {
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hsa_agent_t gpu_device1;
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hsa_agent_t cpu_device;
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hsa_status_t err;
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gpu_device1.handle = 0;
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err = hsa_iterate_agents(FindGPUDevice, &gpu_device1);
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RET_IF_HSA_UTILS_ERR(rocrtst::ProcessIterateError(err));
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@@ -217,7 +226,7 @@ hsa_status_t InitAndSetupHSA(BaseRocR* test) {
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char name[64] = {0};
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err = hsa_agent_get_info(gpu_device1, HSA_AGENT_INFO_NAME, name);
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RET_IF_HSA_UTILS_ERR(err);
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std::cout << "The device name is " << name << std::endl;
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std::cout << "The gpu device name is " << name << std::endl;
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}
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hsa_profile_t profile;
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@@ -228,14 +237,11 @@ hsa_status_t InitAndSetupHSA(BaseRocR* test) {
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if (!CheckProfileAndInform(test)) {
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return HSA_STATUS_ERROR;
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}
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err = hsa_signal_create(1, 0, NULL, &sig);
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RET_IF_HSA_UTILS_ERR(err);
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test->set_signal(sig);
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return HSA_STATUS_SUCCESS;
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}
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// See if the profile of the target matches any required profile by the
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// test program.
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bool CheckProfile(BaseRocR const* test) {
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if (test->requires_profile() == -1) {
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return true;
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@@ -243,6 +249,19 @@ bool CheckProfile(BaseRocR const* test) {
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return (test->requires_profile() == test->profile());
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}
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}
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// Load the specified kernel code from the specified file, inspect and fill
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// in BaseRocR member variables related to the kernel and executable.
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// Required Input BaseRocR member variables:
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// - gpu_device1()
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// - kernel_file_name()
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// - kernel_name()
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//
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// Written BaseRocR member variables:
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// -kernel_object()
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// -private_segment_size()
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// -group_segment_size()
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// -kernarg_size()
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// -kernarg_align()
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hsa_status_t LoadKernelFromObjFile(BaseRocR* test) {
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hsa_status_t err;
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hsa_code_object_reader_t code_obj_rdr = {0};
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@@ -334,13 +353,16 @@ hsa_status_t CreateQueue(hsa_agent_t device, hsa_queue_t** queue,
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return HSA_STATUS_SUCCESS;
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}
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void InitializeAQLPacket(const BaseRocR* test,
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// Initialize the provided aql packet with standard default values, and
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// values from provided BaseRocR object.
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hsa_status_t InitializeAQLPacket(const BaseRocR* test,
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hsa_kernel_dispatch_packet_t* aql) {
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hsa_status_t err;
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assert(aql != nullptr);
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if (aql == nullptr) {
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return;
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return HSA_STATUS_ERROR;
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}
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aql->header = 0; // Set this right before doorbell ring
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@@ -361,19 +383,25 @@ void InitializeAQLPacket(const BaseRocR* test,
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// Pin kernel code and the kernel argument buffer to the aql packet->
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aql->kernel_object = test->kernel_object();
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aql->kernarg_address = NULL;
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aql->completion_signal.handle = test->signal().handle;
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// aql->kernarg_address may be filled in by AllocAndSetKernArgs() if it is
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// called before this function, so we don't want overwrite it, therefore
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// we ignore it in this function.
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return;
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err = hsa_signal_create(1, 0, NULL, &aql->completion_signal);
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return err;
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}
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void WriteAQLToQueue(BaseRocR* test) {
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// Copy BaseRocR aql object values to the BaseRocR object queue in the
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// specified queue position (ind)
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hsa_kernel_dispatch_packet_t * WriteAQLToQueue(BaseRocR* test, uint64_t *ind) {
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assert(test);
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assert(test->main_queue());
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void *queue_base = test->main_queue()->base_address;
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const uint32_t queue_mask = test->main_queue()->size - 1;
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uint64_t que_idx = hsa_queue_add_write_index_relaxed(test->main_queue(), 1);
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*ind = que_idx;
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hsa_kernel_dispatch_packet_t* staging_aql_packet = &test->aql();
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hsa_kernel_dispatch_packet_t* queue_aql_packet;
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@@ -395,8 +423,12 @@ void WriteAQLToQueue(BaseRocR* test) {
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queue_aql_packet->kernel_object = staging_aql_packet->kernel_object;
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queue_aql_packet->kernarg_address = staging_aql_packet->kernarg_address;
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queue_aql_packet->completion_signal = staging_aql_packet->completion_signal;
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return queue_aql_packet;
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}
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// Allocate a buffer in the kern_arg_pool for the kernel arguments and write
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// the arguments to buffer
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hsa_status_t AllocAndSetKernArgs(BaseRocR* test, void* args, size_t arg_size) {
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void* kern_arg_buf = nullptr;
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hsa_status_t err;
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@@ -421,56 +453,18 @@ hsa_status_t AllocAndSetKernArgs(BaseRocR* test, void* args, size_t arg_size) {
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assert(((uintptr_t)adj_kern_arg_buf + arg_size) <
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((uintptr_t)kern_arg_buf + buf_size));
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err = hsa_memory_copy_workaround_cpu(adj_kern_arg_buf, args, arg_size);
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RET_IF_HSA_UTILS_ERR(err);
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hsa_agent_t ag_list[2] = {*test->gpu_device1(), *test->cpu_device()};
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err = hsa_amd_agents_allow_access(2, ag_list, NULL, kern_arg_buf);
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RET_IF_HSA_UTILS_ERR(err);
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err = hsa_memory_copy(adj_kern_arg_buf, args, arg_size);
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RET_IF_HSA_UTILS_ERR(err);
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test->aql().kernarg_address = adj_kern_arg_buf;
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return HSA_STATUS_SUCCESS;
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}
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hsa_status_t AllocAndAllowAccess(BaseRocR* test, size_t len,
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hsa_amd_memory_pool_t pool, void**buffer) {
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hsa_status_t err;
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err = hsa_amd_memory_pool_allocate(pool, len, 0, buffer);
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RET_IF_HSA_UTILS_ERR(err);
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hsa_agent_t ag_list[2] = {*test->gpu_device1(), *test->cpu_device()};
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err = hsa_amd_agents_allow_access(2, ag_list, NULL, *buffer);
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RET_IF_HSA_UTILS_ERR(err);
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return err;
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}
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hsa_status_t hsa_memory_fill_workaround_gen(void* ptr, uint32_t value,
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size_t count, hsa_agent_t dst_ag, hsa_agent_t src_ag, BaseRocR* test) {
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hsa_status_t err;
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void *tmp_mem;
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err = hsa_amd_memory_pool_allocate(test->cpu_pool(), count, 0, &tmp_mem);
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RET_IF_HSA_UTILS_ERR(err);
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hsa_agent_t ag_list[2] = {*test->gpu_device1(), *test->cpu_device()};
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err = hsa_amd_agents_allow_access(2, ag_list, NULL, tmp_mem);
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RET_IF_HSA_UTILS_ERR(err);
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(void)memset(tmp_mem, value, count);
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err = hsa_memory_copy_workaround_gen(ptr, tmp_mem, count, dst_ag, src_ag);
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RET_IF_HSA_UTILS_ERR(err);
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hsa_amd_memory_pool_free(tmp_mem);
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return HSA_STATUS_SUCCESS;
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}
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#undef RET_IF_HSA_UTILS_ERR
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} // namespace rocrtst
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@@ -60,14 +60,16 @@ namespace rocrtst {
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/// \param[in] test Test for which the kernel will be loaded.
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/// \returns HSA_STATUS_SUCCESS if no errors
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hsa_status_t LoadKernelFromObjFile(BaseRocR* test);
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/// Do initialization tasks for HSA test program. This includes calling
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/// hsa_init(), finding and setting the cpu and gpu agent member variables,
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/// creating the signal needed for queueing AQL packets and checking
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/// HW requirements.
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/// Do initialization tasks for HSA test program.
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/// \param[in] test Test to initialize
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/// \returns HSA_STATUS_SUCCESS if no errors
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hsa_status_t InitAndSetupHSA(BaseRocR* test);
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/// Find and set the cpu and gpu agent member variables. Also checks that
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/// gpu agent meets test requirements (e.g., FULL profile vs. BASE profile).
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hsa_status_t SetDefaultAgents(BaseRocR* test);
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/// For the provided device agent, create an AQL queue
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/// \param[in] device Device for which a queue is to be created
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/// \param[out] queue Address to which created queue pointer will be written
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@@ -84,16 +86,16 @@ hsa_status_t CreateQueue(hsa_agent_t device, hsa_queue_t** queue,
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/// be drawn.
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/// \param[inout] aql Caller provided pointer to aql packet that will be
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/// populated
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/// \returns void
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void InitializeAQLPacket(const BaseRocR* test,
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/// \returns Appropriate hsa_status_t
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hsa_status_t InitializeAQLPacket(const BaseRocR* test,
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hsa_kernel_dispatch_packet_t* aql);
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/// This function writes all of the aql packet fields to the queue besides
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/// "setup" and "header". This assumes all the aql fields have be set
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/// appropriately.
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/// \param[in] test Test containing the queue and aql packet to be written.
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/// \returns void
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void WriteAQLToQueue(BaseRocR* test);
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/// \returns Pointer to dispatch packet in queue that was written to
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hsa_kernel_dispatch_packet_t* WriteAQLToQueue(BaseRocR* test, uint64_t *ind);
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/// This function writes the first 32 bits of an aql packet to the provided
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/// aql packet. This function is meant to be called immediately before
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@@ -139,6 +141,15 @@ bool CheckProfile(BaseRocR const* test);
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hsa_status_t AllocAndSetKernArgs(BaseRocR* test, void* args,
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size_t arg_size);
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/// Verify that the machine running the test has the required profile.
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/// This function will verify that the execution machine meets any specific
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/// test requirement for a profile (HSA_PROFILE_BASE or HSA_PROFILE_FULL).
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/// \param[in] test Test that provides profile requirements.
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/// \returns bool
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/// - true Machine meets test requirements
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/// - false Machine does not meet test requirements
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bool CheckProfileAndInform(BaseRocR* test);
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/// This function will set the cpu and gpu memory pools to the type used in
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/// many applications.
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/// \param[in] test Test that provides profile requirements.
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@@ -146,17 +157,6 @@ hsa_status_t AllocAndSetKernArgs(BaseRocR* test, void* args,
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/// error code otherwise.
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hsa_status_t SetPoolsTypical(BaseRocR* test);
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/// Allocate memory from a specified pool and grant both standard BaseRocR
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/// agents access
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/// \param[in] test Test having the agents to which access is granted
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/// \param[in] len Size of the memory buffer to allocate
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/// \pool[in] Pool from which to allocate memory
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/// \buffer[out] Address of pointer which will point to newly allocated memory
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/// upon return
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/// \returns HSA_STATUS_OK if no errors
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hsa_status_t AllocAndAllowAccess(BaseRocR* test, size_t len,
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hsa_amd_memory_pool_t pool, void**buffer);
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/// Work-around for hsa_amd_memory_fill, which is currently broken.
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/// \param[in] ptr Pointer to start of memory location to be filled
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/// \param[in] value Value to write to each byte of input buffer
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@@ -341,45 +341,6 @@ hsa_status_t DumpPointerInfo(void* ptr) {
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return HSA_STATUS_SUCCESS;
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}
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hsa_status_t hsa_memory_fill_workaround_cpu(void* ptr, uint32_t value,
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size_t count) {
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(void)memset(ptr, value, count);
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return HSA_STATUS_SUCCESS;
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}
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hsa_status_t hsa_memory_copy_workaround_cpu(void* dst, const void *src,
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size_t size) {
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(void)memcpy(dst, src, size);
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return HSA_STATUS_SUCCESS;
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}
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hsa_status_t hsa_memory_copy_workaround_gen(void* dst, const void *src,
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size_t size, hsa_agent_t dst_ag, hsa_agent_t src_ag) {
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hsa_signal_t s;
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hsa_status_t err;
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err = hsa_signal_create(1, 0, NULL, &s);
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RET_IF_HSA_COMMON_ERR(err);
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err = hsa_amd_memory_async_copy(dst, dst_ag, src, src_ag, size, 0, NULL, s);
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RET_IF_HSA_COMMON_ERR(err);
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if (hsa_signal_wait_scacquire(s, HSA_SIGNAL_CONDITION_LT, 1,
|
||||
UINT64_MAX, HSA_WAIT_STATE_BLOCKED) != 0) {
|
||||
err = HSA_STATUS_ERROR;
|
||||
std::cout << "Async copy signal error" << std::endl;
|
||||
|
||||
RET_IF_HSA_COMMON_ERR(err);
|
||||
}
|
||||
|
||||
err = hsa_signal_destroy(s);
|
||||
|
||||
RET_IF_HSA_COMMON_ERR(err);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
/*! \brief Writes to the buffer and increments the write pointer to the
|
||||
* buffer. Also, ensures that the argument is written to an
|
||||
|
||||
@@ -140,35 +140,5 @@ hsa_status_t DumpMemoryPoolInfo(const hsa_amd_memory_pool_t pool,
|
||||
/// \returns HSA_STATUS_SUCCESS if there are no errors
|
||||
hsa_status_t DumpPointerInfo(void* ptr);
|
||||
|
||||
/// This is a work-around for filling cpu-memory to be used until
|
||||
/// hsa_amd_memory_fill is fixed. Should only be used for cpu memory.
|
||||
/// \param[in] ptr Start address of memory to be filled.
|
||||
/// \param[in] value Value to fill buffer with
|
||||
/// \param[in] count Size of buffer to fill
|
||||
/// \returns HSA_STATUS_SUCCESS if there are no errors
|
||||
hsa_status_t hsa_memory_fill_workaround_cpu(void* ptr, uint32_t value,
|
||||
size_t count);
|
||||
|
||||
/// This is a work-around for copying cpu-memory to be used until
|
||||
/// hsa_amd_memory_copy is fixed. Should only be used for cpu memory.
|
||||
/// \param[in] dst Destination address of memory to be copied
|
||||
/// \param[in] src Source address of memory to be copied
|
||||
/// \param[in] size Size of buffer to fill
|
||||
/// \returns HSA_STATUS_SUCCESS if there are no errors
|
||||
hsa_status_t hsa_memory_copy_workaround_cpu(void* dst, const void *src,
|
||||
size_t size);
|
||||
|
||||
/// This is a work-around for copying memory to be used until
|
||||
/// hsa_amd_memory_copy is fixed. Should be used when gpu local memory is
|
||||
/// involved.
|
||||
/// \param[in] dst Destination address of memory to be copied
|
||||
/// \param[in] src Source address of memory to be copied
|
||||
/// \param[in] size Size of buffer to fill
|
||||
/// \param[in] dst_ag Destination agent handle
|
||||
/// \param[in] src_ag Source agent handle
|
||||
/// \returns HSA_STATUS_SUCCESS if there are no errors
|
||||
hsa_status_t hsa_memory_copy_workaround_gen(void* dst, const void *src,
|
||||
size_t size, hsa_agent_t dst_ag, hsa_agent_t src_ag);
|
||||
|
||||
} // namespace rocrtst
|
||||
#endif // ROCRTST_COMMON_COMMON_H_
|
||||
|
||||
@@ -52,10 +52,10 @@
|
||||
#include <iostream>
|
||||
#include <string>
|
||||
#include <vector>
|
||||
#include <numeric>
|
||||
|
||||
namespace rocrtst {
|
||||
|
||||
|
||||
template<typename T>
|
||||
void PrintArray(const std::string header, const T* data, const int width,
|
||||
const int height) {
|
||||
@@ -191,7 +191,7 @@ AlignUp(void* value, size_t alignment) {
|
||||
alignment));
|
||||
}
|
||||
|
||||
double CalcMedian(std::vector<double> scores) {
|
||||
double CalcMedian(const std::vector<double> &scores) {
|
||||
double median;
|
||||
size_t size = scores.size();
|
||||
|
||||
@@ -204,15 +204,11 @@ double CalcMedian(std::vector<double> scores) {
|
||||
return median;
|
||||
}
|
||||
|
||||
double CalcMean(std::vector<double> scores) {
|
||||
double mean = 0;
|
||||
size_t size = scores.size();
|
||||
double CalcMean(const std::vector<double> &scores) {
|
||||
double mean;
|
||||
|
||||
for (size_t i = 0; i < size; ++i) {
|
||||
mean += scores[i];
|
||||
}
|
||||
|
||||
return mean / size;
|
||||
mean = std::accumulate(scores.begin(), scores.end(), 0.0);
|
||||
return mean/scores.size();
|
||||
}
|
||||
|
||||
double CalcMean(const std::vector<double>& v1, const std::vector<double>& v2) {
|
||||
|
||||
@@ -60,7 +60,7 @@ bool Compare(const double* refData, const double* data,
|
||||
const int length, const double epsilon = 1e-6);
|
||||
|
||||
/// Calculate the mean number of the vector
|
||||
double CalcMean(std::vector<double> scores);
|
||||
double CalcMean(const std::vector<double> &scores);
|
||||
|
||||
/// Calculate the mean time of difference of the two vectors
|
||||
double CalcMean(const std::vector<double>& v1, const std::vector<double>& v2);
|
||||
@@ -68,7 +68,7 @@ double CalcMean(const std::vector<double>& v1, const std::vector<double>& v2);
|
||||
/// Return the median value of a vector of doubles
|
||||
/// \param[in] scores Vector of doubles
|
||||
/// \returns double Median value of provided vector
|
||||
double CalcMedian(std::vector<double> scores);
|
||||
double CalcMedian(const std::vector<double> &scores);
|
||||
|
||||
/// Calculate the standard deviation of the vector
|
||||
double CalcStdDeviation(std::vector<double> scores, int score_mean);
|
||||
|
||||
@@ -70,6 +70,7 @@ PreDispatchCallback(const hsa_dispatch_callback_t* dispParam, void* usrArg) {
|
||||
dispParam->aql_translation_handle, true);
|
||||
assert((status == HSA_STATUS_SUCCESS) &&
|
||||
"Error in beginning Perf Cntr Session");
|
||||
(void)status; // Avoid warning
|
||||
}
|
||||
|
||||
static void
|
||||
@@ -82,6 +83,7 @@ PostDispatchCallback(const hsa_dispatch_callback_t* dispParam, void* usrArg) {
|
||||
dispParam->aql_translation_handle);
|
||||
assert((status == HSA_STATUS_SUCCESS) &&
|
||||
"Error in endning Perf Cntr Session");
|
||||
(void)status; // Avoid warning
|
||||
}
|
||||
|
||||
/// Constructor of the class
|
||||
@@ -192,6 +194,8 @@ void RocrPerfCntrApp::RegisterCallbacks(hsa_queue_t* queue) {
|
||||
status = hsa_ext_tools_set_callback_arguments(queue, &perfMgr_, &perfMgr_);
|
||||
assert((status == HSA_STATUS_SUCCESS) &&
|
||||
"Error in registering Pre & Post Dispatch Callback Params");
|
||||
|
||||
(void)status; // Avoid warning
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
@@ -176,8 +176,7 @@ uint64_t PerfTimer::MeasureTSCFreqHz() {
|
||||
|
||||
do {
|
||||
tscTicksEnd = __rdtscp(&unused);
|
||||
}
|
||||
while (tscTicksEnd - tscTicksBegin < 1000000000);
|
||||
} while (tscTicksEnd - tscTicksBegin < 1000000000);
|
||||
|
||||
uint64_t coarseEndUs = CoarseTimestampUs();
|
||||
|
||||
|
||||
@@ -91,6 +91,7 @@ class PerfTimer {
|
||||
void ResetTimer(int index);
|
||||
|
||||
/// Read the time value of the timer associated with the provided index.
|
||||
/// Units are seconds
|
||||
/// \param[in] index Index of the timer to read
|
||||
/// \returns double Value of the timer
|
||||
double ReadTimer(int index);
|
||||
|
||||
Reference in New Issue
Block a user