P4 to Git Change 1288106 by jsjodin@jsjodin-git2p4-llvm on 2016/07/06 18:17:28
SWDEV-3 - AMDGPU: Improve load/store of illegal types. There was a combine before to handle the simple copy case. Split this into handling loads and stores separately. We might want to change how this handles some of the vector extloads, since this can result in large code size increases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274394 91177308-0d34-0410-b5e6-96231b3b80d8 GitHash: df587174ebb04a30c8b55aef601121c25af11986 Affected files ... ... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/lib/Target/AMDGPU/AMDGPUISelLowering.cpp#2 edit ... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/lib/Target/AMDGPU/AMDGPUISelLowering.h#2 edit ... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/lib/Target/AMDGPU/SIISelLowering.cpp#6 edit ... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/test/CodeGen/AMDGPU/add.ll#2 edit ... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/test/CodeGen/AMDGPU/copy-illegal-type.ll#2 edit ... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/test/CodeGen/AMDGPU/ctpop64.ll#2 edit ... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll#2 edit ... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/test/CodeGen/AMDGPU/half.ll#2 edit ... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/test/CodeGen/AMDGPU/insert_vector_elt.ll#2 edit ... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/test/CodeGen/AMDGPU/load-constant-i16.ll#2 edit ... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/test/CodeGen/AMDGPU/load-constant-i32.ll#2 edit ... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/test/CodeGen/AMDGPU/load-constant-i64.ll#2 edit ... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/test/CodeGen/AMDGPU/load-constant-i8.ll#2 edit ... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/test/CodeGen/AMDGPU/load-global-f64.ll#2 edit ... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/test/CodeGen/AMDGPU/load-global-i16.ll#2 edit ... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/test/CodeGen/AMDGPU/load-global-i32.ll#2 edit ... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/test/CodeGen/AMDGPU/load-global-i64.ll#2 edit ... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/test/CodeGen/AMDGPU/load-global-i8.ll#2 edit ... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/test/CodeGen/AMDGPU/load-local-f32.ll#2 edit ... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/test/CodeGen/AMDGPU/load-local-i16.ll#2 edit ... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/test/CodeGen/AMDGPU/load-local-i8.ll#2 edit ... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/test/CodeGen/AMDGPU/load-weird-sizes.ll#1 add ... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/test/CodeGen/AMDGPU/scalar_to_vector.ll#2 edit ... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/test/CodeGen/AMDGPU/sext-in-reg.ll#2 edit ... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/test/CodeGen/AMDGPU/shift-and-i128-ubfe.ll#2 edit ... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/test/CodeGen/AMDGPU/store-barrier.ll#2 edit ... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/test/CodeGen/AMDGPU/store.ll#2 edit ... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/test/CodeGen/AMDGPU/sub.ll#2 edit ... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/test/CodeGen/AMDGPU/trunc-bitcast-vector.ll#2 edit ... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/test/CodeGen/AMDGPU/trunc-store.ll#2 edit
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@@ -155,11 +155,11 @@ VirtualGPU::Queue::removeCmdMemRef(Pal::IGpuMemory* iMem)
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}
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uint
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VirtualGPU::Queue::submit(bool forceFlush)
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VirtualGPU::Queue::submit()
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{
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cmdCnt_++;
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uint id = cmdBufIdCurrent_;
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if ((cmdCnt_ > MaxCommands) || forceFlush) {
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if ((cmdCnt_ > MaxCommands) || GPU_FLUSH_ON_EXECUTION) {
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if (!flush()) {
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return GpuEvent::InvalidID;
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}
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@@ -238,11 +238,6 @@ VirtualGPU::Queue::flush()
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return false;
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}
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// Reset command buffer, so CB chunks could be reused
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if (Pal::Result::Success != iCmdBuffs_[cmdBufIdSlot_]->Reset(nullptr, false)) {
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LogError("PAL failed CB reset!");
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return false;
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}
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// Start command buffer building
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Pal::CmdBufferBuildInfo cmdBuildInfo = {};
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if (Pal::Result::Success != iCmdBuffs_[cmdBufIdSlot_]->Begin(cmdBuildInfo)) {
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@@ -596,44 +591,41 @@ VirtualGPU::createVirtualQueue(uint deviceQueueSize)
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if ((virtualQueue_ == nullptr) || !virtualQueue_->create(type)) {
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return false;
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}
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if (GPU_PRINT_CHILD_KERNEL != 0) {
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address ptr = reinterpret_cast<address>(
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virtualQueue_->map(this, Resource::WriteOnly));
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if (nullptr == ptr) {
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return false;
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}
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address ptr = reinterpret_cast<address>(
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virtualQueue_->map(this, Resource::WriteOnly));
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if (nullptr == ptr) {
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return false;
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}
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// Clear memory
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memset(ptr, 0, allocSize);
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uint64_t vaBase = virtualQueue_->vmAddress();
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AmdVQueueHeader* header = reinterpret_cast<AmdVQueueHeader*>(ptr);
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uint64_t vaBase = virtualQueue_->vmAddress();
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AmdVQueueHeader header = {};
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// Initialize the virtual queue header
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header.aql_slot_num = numSlots;
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header.event_slot_num = dev().settings().numDeviceEvents_;
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header.event_slot_mask = vaBase + eventMaskOffs;
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header.event_slots = vaBase + eventsOffs;
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header.aql_slot_mask = vaBase + slotMaskOffs;
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header.wait_size = dev().settings().numWaitEvents_;
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header.arg_size = dev().info().maxParameterSize_ + 64;
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header.mask_groups = maskGroups_;
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header->aql_slot_num = numSlots;
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header->event_slot_num = dev().settings().numDeviceEvents_;
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header->event_slot_mask = vaBase + eventMaskOffs;
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header->event_slots = vaBase + eventsOffs;
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header->aql_slot_mask = vaBase + slotMaskOffs;
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header->wait_size = dev().settings().numWaitEvents_;
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header->arg_size = dev().info().maxParameterSize_ + 64;
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header->mask_groups = maskGroups_;
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vqHeader_ = new AmdVQueueHeader;
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if (nullptr == vqHeader_) {
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return false;
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}
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*vqHeader_ = header;
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virtualQueue_->writeRawData(*this, 0, sizeof(AmdVQueueHeader), &header, false);
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*vqHeader_ = *header;
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// Go over all slots and perform initialization
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AmdAqlWrap slot = {};
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size_t offset = sizeof(AmdVQueueHeader);
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AmdAqlWrap* slots = reinterpret_cast<AmdAqlWrap*>(&header[1]);
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for (uint i = 0; i < numSlots; ++i) {
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uint64_t argStart = vaBase + argOffs + i * singleArgSize;
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slot.aql.kernarg_address = reinterpret_cast<void*>(argStart);
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slot.wait_list = argStart + dev().info().maxParameterSize_ + 64;
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virtualQueue_->writeRawData(*this, offset, sizeof(AmdAqlWrap), &slot, false);
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offset += sizeof(AmdAqlWrap);
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slots[i].aql.kernarg_address = reinterpret_cast<void*>(argStart);
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slots[i].wait_list = argStart + dev().info().maxParameterSize_ + 64;
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}
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// Upload data back to local memory
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if (GPU_PRINT_CHILD_KERNEL == 0) {
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virtualQueue_->unmap(this);
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}
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schedParams_ = new Memory(dev(), 64 * Ki);
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@@ -641,7 +633,7 @@ VirtualGPU::createVirtualQueue(uint deviceQueueSize)
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return false;
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}
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address ptr = reinterpret_cast<address>(schedParams_->map(this));
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ptr = reinterpret_cast<address>(schedParams_->map(this));
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deviceQueueSize_ = deviceQueueSize;
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@@ -697,9 +689,9 @@ VirtualGPU::create(bool profiling, uint deviceQueueSize)
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state_.profiling_ = profiling;
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Pal::CmdAllocatorCreateInfo createInfo = {};
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createInfo.flags.threadSafe = true;
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// \todo forces PAL to reuse CBs, but requires postamble
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createInfo.flags.autoMemoryReuse = false;
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createInfo.flags.autoMemoryReuse = true;
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createInfo.flags.threadSafe = false;
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createInfo.allocInfo[Pal::CommandDataAlloc].allocHeap =
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Pal::GpuHeapGartCacheable;
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createInfo.allocInfo[Pal::CommandDataAlloc].allocSize = 128 * Ki;
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@@ -2108,28 +2100,34 @@ VirtualGPU::submitKernelInternal(
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}
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if (!dev().settings().useDeviceQueue_) {
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Unimplemented();
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/*
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// Add the termination handshake to the host queue
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eventBegin(MainEngine);
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//iCmd()->CmdVirtualQueueHandshake(*gpuDefQueue->schedParams_->iMem(),
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// vmParentWrap + offsetof(AmdAqlWrap, state), AQL_WRAP_DONE,
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// vmParentWrap + offsetof(AmdAqlWrap, child_counter),
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// 0, dev().settings().useDeviceQueue_);
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cs()->VirtualQueueHandshake(gpuDefQueue->schedParams_->iMem(),
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vmParentWrap + offsetof(AmdAqlWrap, state), AQL_WRAP_DONE,
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vmParentWrap + offsetof(AmdAqlWrap, child_counter),
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0, dev().settings().useDeviceQueue_);
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eventEnd(MainEngine, gpuEvent);
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*/
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}
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// Get the global loop start before the scheduler
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//Pal::gpusize loopStart = gpuDefQueue->iCmd()->CmdVirtualQueueDispatcherStart();
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//static_cast<KernelBlitManager&>(gpuDefQueue->blitMgr()).runScheduler(
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// *gpuDefQueue->virtualQueue_,
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// *gpuDefQueue->schedParams_, gpuDefQueue->schedParamIdx_,
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// gpuDefQueue->vqHeader_->aql_slot_num / (DeviceQueueMaskSize * maskGroups_));
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Unimplemented();
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/*
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mcaddr loopStart = gpuDefQueue->cs()->VirtualQueueDispatcherStart();
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static_cast<KernelBlitManager&>(gpuDefQueue->blitMgr()).runScheduler(
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*gpuDefQueue->virtualQueue_,
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*gpuDefQueue->schedParams_, gpuDefQueue->schedParamIdx_,
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gpuDefQueue->vqHeader_->aql_slot_num / (DeviceQueueMaskSize * maskGroups_));
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const static bool FlushL2 = true;
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gpuDefQueue->flushCUCaches(FlushL2);
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// Get the address of PM4 template and add write it to params
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//! @note DMA flush must not occur between patch and the scheduler
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mcaddr patchStart = gpuDefQueue->cs()->VirtualQueueDispatcherStart();
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*/
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Pal::gpusize patchStart = 0;
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//Pal::gpusize patchStart = gpuDefQueue->iCmd()->CmdVirtualQueueDispatcherStart();
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// Program parameters for the scheduler
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SchedulerParam* param = &reinterpret_cast<SchedulerParam*>
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(gpuDefQueue->schedParams_->data())[gpuDefQueue->schedParamIdx_];
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@@ -2170,28 +2168,31 @@ VirtualGPU::submitKernelInternal(
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Pal::gpusize signalAddr = gpuDefQueue->schedParams_->vmAddress() +
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gpuDefQueue->schedParamIdx_ * sizeof(SchedulerParam);
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Unimplemented();
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/*
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gpuDefQueue->eventBegin(MainEngine);
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//gpuDefQueue->iCmd()->CmdVirtualQueueDispatcherEnd(
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// signalAddr, loopStart, gpuDefQueue->vqHeader_->aql_slot_num /
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// (DeviceQueueMaskSize * maskGroups_));
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// Note: Device enqueue can't have extra commands after INDIRECT_BUFFER call.
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// Thus TS command for profiling has to follow in the next CB.
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constexpr bool ForceSubmitFirst = true;
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gpuDefQueue->eventEnd(MainEngine, gpuEvent, ForceSubmitFirst);
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gpuDefQueue->cs()->VirtualQueueDispatcherEnd(
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gpuDefQueue->vmMems(), gpuDefQueue->cal_.memCount_,
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signalAddr, loopStart, gpuDefQueue->vqHeader_->aql_slot_num /
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(DeviceQueueMaskSize * maskGroups_));
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gpuDefQueue->eventEnd(MainEngine, gpuEvent);
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*/
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// Set GPU event for the used resources
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for (uint i = 0; i < memList.size(); ++i) {
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memList[i]->setBusy(*gpuDefQueue, gpuEvent);
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}
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if (dev().settings().useDeviceQueue_) {
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Unimplemented();
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/*
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// Add the termination handshake to the host queue
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eventBegin(MainEngine);
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//iCmd()->CmdVirtualQueueHandshake(*gpuDefQueue->schedParams_->iMem(),
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// vmParentWrap + offsetof(AmdAqlWrap, state), AQL_WRAP_DONE,
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// vmParentWrap + offsetof(AmdAqlWrap, child_counter),
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// signalAddr, dev().settings().useDeviceQueue_);
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cs()->VirtualQueueHandshake(gpuDefQueue->schedParams_->iMem(),
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vmParentWrap + offsetof(AmdAqlWrap, state), AQL_WRAP_DONE,
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vmParentWrap + offsetof(AmdAqlWrap, child_counter),
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signalAddr, dev().settings().useDeviceQueue_);
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eventEnd(MainEngine, gpuEvent);
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*/
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}
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++gpuDefQueue->schedParamIdx_ %=
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@@ -3249,7 +3250,7 @@ VirtualGPU::writeVQueueHeader(VirtualGPU& hostQ, uint64_t kernelTable)
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{
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const static bool Wait = true;
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vqHeader_->kernel_table = kernelTable;
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virtualQueue_->writeRawData(hostQ, 0, sizeof(AmdVQueueHeader), vqHeader_, Wait);
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virtualQueue_->writeRawData(hostQ, sizeof(AmdVQueueHeader), vqHeader_, !Wait);
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}
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void
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