From a5aa5566a79c7bee10517d1d67efe9e61316ca3e Mon Sep 17 00:00:00 2001 From: foreman Date: Tue, 14 Mar 2017 16:20:13 -0400 Subject: [PATCH] P4 to Git Change 1385569 by wchau@wchau_brahma on 2017/03/14 16:12:25 SWDEV-115692 - Remove Lexa and Polaris 22 support from Linux Pro Affected files ... ... //depot/stg/opencl/drivers/opencl/compiler/legacy-lib/utils/v0_8/target_mappings.h#18 edit ... //depot/stg/opencl/drivers/opencl/compiler/legacy-lib/utils/v0_8/target_mappings_amdil.h#17 edit ... //depot/stg/opencl/drivers/opencl/compiler/legacy-lib/utils/v0_8/target_mappings_amdil64.h#16 edit ... //depot/stg/opencl/drivers/opencl/compiler/legacy-lib/utils/v0_8/target_mappings_hsail.h#17 edit ... //depot/stg/opencl/drivers/opencl/compiler/legacy-lib/utils/v0_8/target_mappings_hsail64.h#17 edit ... //depot/stg/opencl/drivers/opencl/compiler/lib/utils/v0_8/target_mappings.h#50 edit ... //depot/stg/opencl/drivers/opencl/compiler/lib/utils/v0_8/target_mappings_amdil.h#43 edit ... //depot/stg/opencl/drivers/opencl/compiler/lib/utils/v0_8/target_mappings_amdil64.h#39 edit ... //depot/stg/opencl/drivers/opencl/compiler/lib/utils/v0_8/target_mappings_hsail.h#42 edit ... //depot/stg/opencl/drivers/opencl/compiler/lib/utils/v0_8/target_mappings_hsail64.h#37 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpudefs.hpp#146 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpudevice.cpp#564 edit [ROCm/clr commit: 598d635fc4951fc1a4b032139b1e960f34377f63] --- .../rocclr/compiler/lib/utils/v0_8/target_mappings.h | 5 ++++- .../compiler/lib/utils/v0_8/target_mappings_amdil.h | 6 +++++- .../compiler/lib/utils/v0_8/target_mappings_amdil64.h | 4 ++++ .../compiler/lib/utils/v0_8/target_mappings_hsail.h | 6 ++++++ .../compiler/lib/utils/v0_8/target_mappings_hsail64.h | 6 ++++++ projects/clr/rocclr/runtime/device/gpu/gpudefs.hpp | 8 ++++---- projects/clr/rocclr/runtime/device/gpu/gpudevice.cpp | 11 ++++++++++- 7 files changed, 39 insertions(+), 7 deletions(-) diff --git a/projects/clr/rocclr/compiler/lib/utils/v0_8/target_mappings.h b/projects/clr/rocclr/compiler/lib/utils/v0_8/target_mappings.h index 5b86ccd4de..14341e958a 100644 --- a/projects/clr/rocclr/compiler/lib/utils/v0_8/target_mappings.h +++ b/projects/clr/rocclr/compiler/lib/utils/v0_8/target_mappings.h @@ -206,7 +206,10 @@ static const char* calTargetMapping[] = { "Hainan", "Hawaii", "Iceland", "Tonga", "Mullins", "Fiji", "Carrizo", "Ellesmere", "Baffin", - "gfx900", "Stoney", "gfx804", "gfx901", + IF(IS_BRAHMA,"","gfx900"), + "Stoney", + IF(IS_BRAHMA,"","gfx804"), + IF(IS_BRAHMA,"","gfx901"), }; #include "utils/v0_8/target_mappings_amdil.h" diff --git a/projects/clr/rocclr/compiler/lib/utils/v0_8/target_mappings_amdil.h b/projects/clr/rocclr/compiler/lib/utils/v0_8/target_mappings_amdil.h index d97037c89e..29cd571a8b 100644 --- a/projects/clr/rocclr/compiler/lib/utils/v0_8/target_mappings_amdil.h +++ b/projects/clr/rocclr/compiler/lib/utils/v0_8/target_mappings_amdil.h @@ -52,7 +52,7 @@ static const TargetMapping AMDILTargetMapping_0_8[] = { { "Sumo", "Loveland", "cedar", amd::GPU_Library_Evergreen, WRESTLER_A1, F_REDWOOD, false , false, FAMILY_SUMO }, { "Sumo", "Loveland", "cedar", amd::GPU_Library_Evergreen, WRESTLER_B0, F_REDWOOD, false , false, FAMILY_SUMO }, { "Sumo", "Loveland", "cedar", amd::GPU_Library_Evergreen, WRESTLER_C0, F_REDWOOD, false , true , FAMILY_SUMO }, - { "Sumo", "Bheem", "cedar", amd::GPU_Library_Evergreen, BHEEM_A0, F_REDWOOD, false , true , FAMILY_SUMO }, + { "Sumo", "Bheem", "cedar", amd::GPU_Library_Evergreen, BHEEM_A0, F_REDWOOD, false , true , FAMILY_SUMO }, { "SI", "Tahiti", "tahiti", amd::GPU_Library_SI, SI_TAHITI_P_A11, F_SI_BASE, true ,false, FAMILY_SI }, { "SI", "Tahiti", "tahiti", amd::GPU_Library_SI, SI_TAHITI_P_A0, F_SI_BASE, true ,false, FAMILY_SI }, { "SI", "Tahiti", "tahiti", amd::GPU_Library_SI, SI_TAHITI_P_A21, F_SI_BASE, true ,false, FAMILY_SI }, @@ -100,7 +100,11 @@ static const TargetMapping AMDILTargetMapping_0_8[] = { { "CZ", "Stoney", "stoney", amd::GPU_Library_CI, STONEY_A0, F_SI_BASE, true, true, FAMILY_CZ }, { "VI", "Baffin", "baffin", amd::GPU_Library_CI, VI_BAFFIN_M_A0, F_SI_BASE, true, true, FAMILY_VI }, { "VI", "Ellesmere", "ellesmere", amd::GPU_Library_CI, VI_ELLESMERE_P_A0, F_SI_BASE, true, true, FAMILY_VI }, +#ifndef BRAHMA { "VI", "gfx804", "gfx804", amd::GPU_Library_CI, VI_LEXA_V_A0, F_SI_BASE, true, true, FAMILY_VI }, +#else + UnknownTarget, +#endif InvalidTarget }; diff --git a/projects/clr/rocclr/compiler/lib/utils/v0_8/target_mappings_amdil64.h b/projects/clr/rocclr/compiler/lib/utils/v0_8/target_mappings_amdil64.h index ad354b868e..d85cafe89c 100644 --- a/projects/clr/rocclr/compiler/lib/utils/v0_8/target_mappings_amdil64.h +++ b/projects/clr/rocclr/compiler/lib/utils/v0_8/target_mappings_amdil64.h @@ -46,7 +46,11 @@ static const TargetMapping AMDIL64TargetMapping_0_8[] = { { "CZ", "Stoney", "stoney", amd::GPU64_Library_CI, STONEY_A0, F_SI_64BIT_PTR, true, true, FAMILY_CZ }, { "VI", "Baffin", "baffin", amd::GPU64_Library_CI, VI_BAFFIN_M_A0, F_SI_64BIT_PTR, true, true, FAMILY_VI }, { "VI", "Ellesmere", "ellesmere", amd::GPU64_Library_CI, VI_ELLESMERE_P_A0, F_SI_64BIT_PTR, true, true, FAMILY_VI }, +#ifndef BRAHMA { "VI", "gfx804", "gfx804", amd::GPU64_Library_CI, VI_LEXA_V_A0, F_SI_64BIT_PTR, true, true, FAMILY_VI }, +#else + UnknownTarget, +#endif InvalidTarget }; diff --git a/projects/clr/rocclr/compiler/lib/utils/v0_8/target_mappings_hsail.h b/projects/clr/rocclr/compiler/lib/utils/v0_8/target_mappings_hsail.h index 39a661c6e9..45e9c2cc68 100644 --- a/projects/clr/rocclr/compiler/lib/utils/v0_8/target_mappings_hsail.h +++ b/projects/clr/rocclr/compiler/lib/utils/v0_8/target_mappings_hsail.h @@ -31,9 +31,15 @@ static const TargetMapping HSAILTargetMapping_0_8[] = { { "CZ", "Stoney", "GFX8", amd::GPU_Library_HSAIL, STONEY_A0, F_VI_BASE, true, true, FAMILY_CZ }, { "VI", "Baffin", "GFX8", amd::GPU_Library_HSAIL, VI_BAFFIN_M_A0, F_VI_BASE, true, true, FAMILY_VI }, { "VI", "Ellesmere", "GFX8", amd::GPU_Library_HSAIL, VI_ELLESMERE_P_A0, F_VI_BASE, true, true, FAMILY_VI }, +#ifndef BRAHMA { "AI", "gfx900", "GFX9", amd::GPU_Library_HSAIL, AI_GREENLAND_P_A0, F_AI_BASE, true, true, FAMILY_AI }, { "VI", "gfx804", "GFX8", amd::GPU_Library_HSAIL, VI_LEXA_V_A0, F_VI_BASE, true, true, FAMILY_VI }, { "RV", "gfx901", "GFX9", amd::GPU_Library_HSAIL, RAVEN_A0, F_AI_BASE, true, true, FAMILY_RV }, +#else + UnknownTarget, + UnknownTarget, + UnknownTarget, +#endif InvalidTarget }; diff --git a/projects/clr/rocclr/compiler/lib/utils/v0_8/target_mappings_hsail64.h b/projects/clr/rocclr/compiler/lib/utils/v0_8/target_mappings_hsail64.h index d4aa755715..cef5f2bc4a 100644 --- a/projects/clr/rocclr/compiler/lib/utils/v0_8/target_mappings_hsail64.h +++ b/projects/clr/rocclr/compiler/lib/utils/v0_8/target_mappings_hsail64.h @@ -30,9 +30,15 @@ static const TargetMapping HSAIL64TargetMapping_0_8[] = { { "CZ", "Stoney", "GFX8", amd::GPU_Library_HSAIL, STONEY_A0, F_VI_BASE, true, true, FAMILY_CZ }, { "VI", "Baffin", "GFX8", amd::GPU_Library_HSAIL, VI_BAFFIN_M_A0, F_VI_BASE, true, true, FAMILY_VI }, { "VI", "Ellesmere", "GFX8", amd::GPU_Library_HSAIL, VI_ELLESMERE_P_A0, F_VI_BASE, true, true, FAMILY_VI }, +#ifndef BRAHMA { "AI", "gfx900", "GFX9", amd::GPU_Library_HSAIL, AI_GREENLAND_P_A0, F_AI_BASE, true, true, FAMILY_AI }, { "VI", "gfx804", "GFX8", amd::GPU_Library_HSAIL, VI_LEXA_V_A0, F_VI_BASE, true, true, FAMILY_VI }, { "RV", "gfx901", "GFX9", amd::GPU_Library_HSAIL, RAVEN_A0, F_AI_BASE, true, true, FAMILY_RV }, +#else + UnknownTarget, + UnknownTarget, + UnknownTarget, +#endif InvalidTarget }; diff --git a/projects/clr/rocclr/runtime/device/gpu/gpudefs.hpp b/projects/clr/rocclr/runtime/device/gpu/gpudefs.hpp index 9bdbd0b5b7..db1bb016c6 100644 --- a/projects/clr/rocclr/runtime/device/gpu/gpudefs.hpp +++ b/projects/clr/rocclr/runtime/device/gpu/gpudefs.hpp @@ -125,11 +125,11 @@ static const AMDDeviceInfo DeviceInfo[] = { /* CAL_TARGET_CARRIZO */ { ED_ATI_CAL_MACHINE_CARRIZO_ISA, "Carrizo" , "carrizo", 4, 16, 1, 256, 64 * Ki, 32, 800 }, /* CAL_TARGET_ELLESMERE */ { ED_ATI_CAL_MACHINE_ELLESMERE_ISA, "Ellesmere", "ellesmere", 4, 16, 1, 256, 64 * Ki, 32, 800 }, /* CAL_TARGET_BAFFIN */ { ED_ATI_CAL_MACHINE_BAFFIN_ISA, "Baffin", "baffin", 4, 16, 1, 256, 64 * Ki, 32, 800 }, -/* CAL_TARGET_GREENLAND */ { ED_ATI_CAL_MACHINE_GREENLAND_ISA, "gfx900", "gfx900", 4, 16, 1, 256, 64 * Ki, 32, 900 }, +/* CAL_TARGET_GREENLAND */ { ED_ATI_CAL_MACHINE_GREENLAND_ISA, IF(IS_BRAHMA,"","gfx900"), IF(IS_BRAHMA,"","gfx900"), 4, 16, 1, 256, 64 * Ki, 32, 900 }, /* CAL_TARGET_STONEY */ { ED_ATI_CAL_MACHINE_STONEY_ISA, "Stoney", "stoney", 4, 16, 1, 256, 64 * Ki, 32, 800 }, -/* CAL_TARGET_LEXA */ { ED_ATI_CAL_MACHINE_LEXA_ISA, "gfx804", "gfx804", 4, 16, 1, 256, 64 * Ki, 32, 800 }, -/* CAL_TARGET_RAVEN */ { ED_ATI_CAL_MACHINE_RAVEN_ISA, "gfx901", "gfx901", 4, 16, 1, 256, 64 * Ki, 32, 900 }, -/* CAL_TARGET_POLARIS22 */ { ED_ATI_CAL_MACHINE_POLARIS22_ISA, "gfx804", "gfx804", 4, 16, 1, 256, 64 * Ki, 32, 800 }, +/* CAL_TARGET_LEXA */ { ED_ATI_CAL_MACHINE_LEXA_ISA, IF(IS_BRAHMA,"","gfx804"), IF(IS_BRAHMA,"","gfx804"), 4, 16, 1, 256, 64 * Ki, 32, 800 }, +/* CAL_TARGET_RAVEN */ { ED_ATI_CAL_MACHINE_RAVEN_ISA, IF(IS_BRAHMA,"","gfx901"), IF(IS_BRAHMA,"","gfx901"), 4, 16, 1, 256, 64 * Ki, 32, 900 }, +/* CAL_TARGET_POLARIS22 */ { ED_ATI_CAL_MACHINE_POLARIS22_ISA, IF(IS_BRAHMA,"","gfx804"), IF(IS_BRAHMA,"","gfx804"), 4, 16, 1, 256, 64 * Ki, 32, 800 }, }; enum gfx_handle { diff --git a/projects/clr/rocclr/runtime/device/gpu/gpudevice.cpp b/projects/clr/rocclr/runtime/device/gpu/gpudevice.cpp index d98e3464b2..b061ae9df2 100644 --- a/projects/clr/rocclr/runtime/device/gpu/gpudevice.cpp +++ b/projects/clr/rocclr/runtime/device/gpu/gpudevice.cpp @@ -884,6 +884,15 @@ Device::create(CALuint ordinal, CALuint numOfDevices) return false; } +#if defined(BRAHMA) + if (calTarget_ == CAL_TARGET_GREENLAND || + calTarget_ == CAL_TARGET_LEXA || + calTarget_ == CAL_TARGET_RAVEN || + calTarget_ == CAL_TARGET_POLARIS22) { + return false; + } +#endif + // Creates device settings settings_ = new gpu::Settings(); gpu::Settings* gpuSettings = reinterpret_cast(settings_); @@ -2086,7 +2095,7 @@ Device::allocScratch(uint regNum, const VirtualGPU* vgpu) // Serialize the scratch buffer allocation code amd::ScopedLock lk(*scratchAlloc_); uint sb = vgpu->hwRing(); - + static const uint WaveSizeLimit = ((1 << 21) - 256); const uint threadSizeLimit = WaveSizeLimit / getAttribs().wavefrontSize; if (regNum > threadSizeLimit) {