From a5cb2d40ec2e8684ee57faa709b293d84eef4459 Mon Sep 17 00:00:00 2001 From: Aditya Atluri Date: Fri, 28 Apr 2017 11:53:11 -0500 Subject: [PATCH] fixed hipFuncSetCacheConfig on rocm path Change-Id: I937a3afbf115edc94a753a0beb2230ed60a6f021 --- include/hip/hcc_detail/hip_runtime_api.h | 2 +- src/hip_device.cpp | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/include/hip/hcc_detail/hip_runtime_api.h b/include/hip/hcc_detail/hip_runtime_api.h index 7a99ff0810..6917f04f96 100644 --- a/include/hip/hcc_detail/hip_runtime_api.h +++ b/include/hip/hcc_detail/hip_runtime_api.h @@ -385,7 +385,7 @@ hipError_t hipDeviceGetLimit(size_t *pValue, enum hipLimit_t limit); * Note: AMD devices and recent Nvidia GPUS do not support reconfigurable cache. This hint is ignored on those architectures. * */ -hipError_t hipFuncSetCacheConfig ( hipFuncCache_t config ); +hipError_t hipFuncSetCacheConfig (const void* func, hipFuncCache_t config ); /** * @brief Returns bank width of shared memory for current device diff --git a/src/hip_device.cpp b/src/hip_device.cpp index 88d94411e8..01a213190f 100644 --- a/src/hip_device.cpp +++ b/src/hip_device.cpp @@ -112,7 +112,7 @@ hipError_t hipDeviceGetLimit (size_t *pValue, hipLimit_t limit) } } -hipError_t hipFuncSetCacheConfig (hipFuncCache_t cacheConfig) +hipError_t hipFuncSetCacheConfig (const void* func, hipFuncCache_t cacheConfig) { HIP_INIT_API(cacheConfig);