SWDEV-292408 - Disable cache coherency tracking for HIP

Cache coherency layer is OCL feature to support multiple devices in
single OCL context.

Change-Id: Ic66df9551fad5b0c4df95ab3e1db1da259919f25


[ROCm/clr commit: 6da9d18140]

projects/clr/rocclr/platform/memory.cpp

@@ -457,13 +457,16 @@ bool Memory::setDestructorCallback(DestructorCallBackFunction callback, void* da
 }
 
 void Memory::signalWrite(const Device* writer) {
-  // (the potential race condition below doesn't matter, no critical
-  // section needed)
-  ++version_;
-  lastWriter_ = writer;
-  // Update all subbuffers for this object
-  for (auto buf : subBuffers_) {
-    buf->signalWrite(writer);
+  // Disable cache coherency layer for HIP
+  if (!amd::IS_HIP) {
+    // (the potential race condition below doesn't matter, no critical
+    // section needed)
+    ++version_;
+    lastWriter_ = writer;
+    // Update all subbuffers for this object
+    for (auto buf : subBuffers_) {
+      buf->signalWrite(writer);
+    }
   }
 }