diff --git a/projects/rdc/common/rdc_field.data b/projects/rdc/common/rdc_field.data index c01e44a4f4..3fbb0b5710 100644 --- a/projects/rdc/common/rdc_field.data +++ b/projects/rdc/common/rdc_field.data @@ -137,6 +137,7 @@ FLD_DESC_ENT(RDC_FI_PROF_EVAL_MEM_W_BW, "Written to video memory kb / ms FLD_DESC_ENT(RDC_FI_PROF_EVAL_FLOPS_16, "Number of fp16 OPS / ms", "FLOPS_16", false) FLD_DESC_ENT(RDC_FI_PROF_EVAL_FLOPS_32, "Number of fp32 OPS / ms", "FLOPS_32", false) FLD_DESC_ENT(RDC_FI_PROF_EVAL_FLOPS_64, "Number of fp64 OPS / ms", "FLOPS_64", false) +FLD_DESC_ENT(RDC_FI_PROF_VALU_PIPE_ISSUE_UTIL, "Percent of Active Pipe VALU", "VALU_UTILIZATION", false) // Events FLD_DESC_ENT(RDC_EVNT_XGMI_0_NOP_TX, "NOPs sent to neighbor 0", "XGMI_NOP_0", false) diff --git a/projects/rdc/include/rdc/rdc.h b/projects/rdc/include/rdc/rdc.h index a0d84d33ea..237a2535e5 100644 --- a/projects/rdc/include/rdc/rdc.h +++ b/projects/rdc/include/rdc/rdc.h @@ -277,6 +277,7 @@ typedef enum { RDC_FI_PROF_EVAL_FLOPS_16, RDC_FI_PROF_EVAL_FLOPS_32, RDC_FI_PROF_EVAL_FLOPS_64, + RDC_FI_PROF_VALU_PIPE_ISSUE_UTIL, /** * @brief Raw XGMI counter events diff --git a/projects/rdc/python_binding/rdc_bootstrap.py b/projects/rdc/python_binding/rdc_bootstrap.py index fc631b1579..fb23470bf7 100644 --- a/projects/rdc/python_binding/rdc_bootstrap.py +++ b/projects/rdc/python_binding/rdc_bootstrap.py @@ -138,16 +138,18 @@ class rdc_field_t(c_int): RDC_FI_XGMI_7_WRITE_KB = 715 RDC_FI_XGMI_TOTAL_READ_KB = 716 RDC_FI_XGMI_TOTAL_WRITE_KB = 717 - RDC_FI_PROF_MEAN_OCCUPANCY_PER_CU = 800 - RDC_FI_PROF_MEAN_OCCUPANCY_PER_ACTIVE_CU = 801 - RDC_FI_PROF_ACTIVE_CYCLES = 802 - RDC_FI_PROF_ACTIVE_WAVES = 803 - RDC_FI_PROF_ELAPSED_CYCLES = 804 - RDC_FI_PROF_EVAL_MEM_R_BW = 805 - RDC_FI_PROF_EVAL_MEM_W_BW = 806 - RDC_FI_PROF_EVAL_FLOPS_16 = 807 - RDC_FI_PROF_EVAL_FLOPS_32 = 808 - RDC_FI_PROF_EVAL_FLOPS_64 = 809 + RDC_FI_PROF_OCCUPANCY_PERCENT = 800 + RDC_FI_PROF_ACTIVE_CYCLES = 801 + RDC_FI_PROF_ACTIVE_WAVES = 802 + RDC_FI_PROF_ELAPSED_CYCLES = 803 + RDC_FI_PROF_TENSOR_ACTIVE_PERCENT = 804 + RDC_FI_PROF_GPU_UTIL_PERCENT = 805 + RDC_FI_PROF_EVAL_MEM_R_BW = 806 + RDC_FI_PROF_EVAL_MEM_W_BW = 807 + RDC_FI_PROF_EVAL_FLOPS_16 = 808 + RDC_FI_PROF_EVAL_FLOPS_32 = 809 + RDC_FI_PROF_EVAL_FLOPS_64 = 810 + RDC_FI_PROF_VALU_PIPE_ISSUE_UTIL = 811 RDC_EVNT_XGMI_0_NOP_TX = 1000 RDC_EVNT_XGMI_0_REQ_TX = 1001 RDC_EVNT_XGMI_0_RESP_TX = 1002 diff --git a/projects/rdc/rdc_libs/rdc_modules/rdc_rocp/RdcRocpBase.cc b/projects/rdc/rdc_libs/rdc_modules/rdc_rocp/RdcRocpBase.cc index 9cc61a70ac..af00cfbbbb 100644 --- a/projects/rdc/rdc_libs/rdc_modules/rdc_rocp/RdcRocpBase.cc +++ b/projects/rdc/rdc_libs/rdc_modules/rdc_rocp/RdcRocpBase.cc @@ -258,6 +258,7 @@ RdcRocpBase::RdcRocpBase() { {RDC_FI_PROF_EVAL_FLOPS_16, "TOTAL_16_OPS"}, {RDC_FI_PROF_EVAL_FLOPS_32, "TOTAL_32_OPS"}, {RDC_FI_PROF_EVAL_FLOPS_64, "FP64_ACTIVE"}, + {RDC_FI_PROF_VALU_PIPE_ISSUE_UTIL, "ValuPipeIssueUtil"}, }; std::vector all_fields;