From a87782e9414072938f34eb30e5d9eaadd7fc387d Mon Sep 17 00:00:00 2001 From: Saleel Kudchadker Date: Wed, 10 Jan 2024 07:04:49 +0000 Subject: [PATCH] SWDEV-439242 - Fix perf regression This issue is due to the fact that we set fence_dirty_ flag for every kernel launch. Whenever any next HIP API is caused, the stream logic assumes fence is dirty and queues a marker, when its not needed. Change-Id: I10a49ee951daa92221aa6be75e2334849579a45d [ROCm/clr commit: d6b4892600268a013c8e51e2d69c7d6766642878] --- projects/clr/rocclr/device/rocm/rocvirtual.cpp | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/projects/clr/rocclr/device/rocm/rocvirtual.cpp b/projects/clr/rocclr/device/rocm/rocvirtual.cpp index ea14273015..400b791a81 100644 --- a/projects/clr/rocclr/device/rocm/rocvirtual.cpp +++ b/projects/clr/rocclr/device/rocm/rocvirtual.cpp @@ -859,10 +859,6 @@ bool VirtualGPU::dispatchGenericAqlPacket( fence_state_ = static_cast(expected_fence_state); - if (expected_fence_state != amd::Device::kCacheStateSystem) { - fence_dirty_ = true; - } - if (timestamp_ != nullptr) { // Get active signal for current dispatch if profiling is necessary packet->completion_signal = Barriers().ActiveSignal(kInitSignalValueOne, timestamp_); @@ -3476,6 +3472,11 @@ void VirtualGPU::submitAccumulate(amd::AccumulateCommand& vcmd) { constexpr size_t kPacketSize = 1; auto packet = reinterpret_cast(aqlPacket); dispatchGenericAqlPacket(packet, packet->header, packet->setup, false, kPacketSize); + // We need to set fence_dirty_ flag as we would use a dispatch packet with a completion signal + // to track graph finish for the last. The sync logic assumes HW event to a barrier packet that + // has a system scope release. This would cause isFenceDirty() check at top level to insert + // barrier packet wherever needed + fence_dirty_ = true; } else { const Settings& settings = dev().settings(); if (settings.barrier_value_packet_) {