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P4 to Git Change 1732168 by jatang@jatang_win_pal_lc on 2019/01/17 17:58:53

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SWDEV-172202 - Workaround the scheduler for systems don't support PCIe 3 atomics properly.

	The idea is the scheduler uses a device side global as write_index, and only write the write_index back to the hsa queue when the last thread of the scheduler leaves.

	This change along with the library side change have been tested on systems with or without proper PCIe 3 atomics support.

Affected files ...

... //depot/stg/opencl/drivers/opencl/runtime/device/rocm/rocblit.cpp#29 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/rocm/rocsched.hpp#2 edit
This commit is contained in:
foreman
2019-01-17 18:20:24 -05:00
parent dc3e9a916d
commit aa3989dcd0
2 changed files with 4 additions and 3 deletions
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rocclr/runtime/device/rocm/rocblit.cpp
+3
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@@ -2214,6 +2214,9 @@ bool KernelBlitManager::runScheduler(uint64_t vqVM, amd::Memory* schedulerParam,
sp->parentAQL = sp->kernarg_address + sizeof(SchedulerParam);
sp->eng_clk = (1000 * 1024) / dev().info().maxEngineClockFrequency_;
// Use a device side global atomics to workaround the reliance of PCIe 3 atomics
sp->write_index = hsa_queue_load_write_index_relaxed(schedulerQueue);
cl_mem mem = as_cl<amd::Memory>(schedulerParam);
setArgument(kernels_[Scheduler], 0, sizeof(cl_mem), &mem);