[aqlprofile] Misc formatting (#810)
* Remove dupicated code segment and apply formatting to some code regions
This commit is contained in:
Mythreya Kuricheti
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GitHub
GitHub
parent
b6ffa43226
commit
aa90a83e42
@@ -301,9 +301,10 @@ class GpuPmcBuilder : public PmcBuilder, protected Primitives {
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// TODO: In order to get different event for different instance with WGP counter blocks, we
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// need to loop through WGP instead of blindly broadcast instance. Fortunately, this
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// is not a common practice
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const uint32_t grbm_value = (block_info->instance_count > 1 && !(block_info->attr & CounterBlockWgpAttr))
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? Primitives::grbm_inst_index_value(block_des.index)
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: Primitives::grbm_broadcast_value();
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const uint32_t grbm_value =
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(block_info->instance_count > 1 && !(block_info->attr & CounterBlockWgpAttr))
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? Primitives::grbm_inst_index_value(block_des.index)
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: Primitives::grbm_broadcast_value();
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SetGrbmGfxIndex(cmd_buffer, grbm_value, block_info->attr);
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// Reset counters
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if (block_info->attr & CounterBlockMcAttr) {
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@@ -592,41 +593,44 @@ class GpuPmcBuilder : public PmcBuilder, protected Primitives {
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grbm_value = Primitives::grbm_se_index_value(se_index);
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}
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bool bIsWGPcounter11 = Primitives::GFXIP_LEVEL == 11 && (block_info->attr & CounterBlockSqAttr);
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bool bIsWGPcounter12 = Primitives::GFXIP_LEVEL >= 12 && (block_info->attr & CounterBlockWgpAttr);
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bool bIsWGPcounter11 =
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Primitives::GFXIP_LEVEL == 11 && (block_info->attr & CounterBlockSqAttr);
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bool bIsWGPcounter12 =
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Primitives::GFXIP_LEVEL >= 12 && (block_info->attr & CounterBlockWgpAttr);
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if (bIsWGPcounter11) {
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for (int wgp=0; wgp<wgp_per_sa; wgp++) {
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grbm_value = Primitives::grbm_se_sh_wgp_index_value(se_index, sarray, wgp);
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SetGrbmGfxIndex(cmd_buffer, grbm_value);
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builder.BuildCopyCounterDataPacket(
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cmd_buffer, reg_info.register_addr_lo, reg_info.register_addr_hi,
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reinterpret_cast<uint32_t*>(data_buffer) + read_counter, 1);
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read_counter += 2;
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}
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} else if (bIsWGPcounter12) {
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for (int wgp=0; wgp<wgp_per_sa; wgp++) {
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if (block_info->instance_count > 1)
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grbm_value = Primitives::grbm_inst_se_sh_wgp_index_value(block_des.index, se_index, sarray, wgp);
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else
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if (bIsWGPcounter11) {
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for (int wgp = 0; wgp < wgp_per_sa; wgp++) {
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grbm_value = Primitives::grbm_se_sh_wgp_index_value(se_index, sarray, wgp);
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SetGrbmGfxIndex(cmd_buffer, grbm_value);
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uint32_t dw_mask = reg_info.register_addr_hi.offset ? 3 : 1;
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SetGrbmGfxIndex(cmd_buffer, grbm_value);
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builder.BuildCopyCounterDataPacket(
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cmd_buffer, reg_info.register_addr_lo, reg_info.register_addr_hi,
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reinterpret_cast<uint32_t*>(data_buffer) + read_counter, 1);
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read_counter += 2;
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}
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} else if (bIsWGPcounter12) {
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for (int wgp = 0; wgp < wgp_per_sa; wgp++) {
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if (block_info->instance_count > 1)
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grbm_value = Primitives::grbm_inst_se_sh_wgp_index_value(block_des.index,
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se_index, sarray, wgp);
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else
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grbm_value = Primitives::grbm_se_sh_wgp_index_value(se_index, sarray, wgp);
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SetGrbmGfxIndex(cmd_buffer, grbm_value);
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uint32_t dw_mask = reg_info.register_addr_hi.offset ? 3 : 1;
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builder.BuildCopyCounterDataPacket(
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cmd_buffer, reg_info.register_addr_lo, reg_info.register_addr_hi,
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reinterpret_cast<uint32_t*>(data_buffer) + read_counter, dw_mask);
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if (data_buffer && (dw_mask == 1))
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*(reinterpret_cast<uint32_t*>(data_buffer) + read_counter + 1) = 0;
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read_counter += 2;
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}
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} else {
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SetGrbmGfxIndex(cmd_buffer, grbm_value, block_info->attr);
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builder.BuildCopyCounterDataPacket(
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cmd_buffer, reg_info.register_addr_lo, reg_info.register_addr_hi,
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reinterpret_cast<uint32_t*>(data_buffer) + read_counter, dw_mask);
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if (data_buffer && (dw_mask == 1))
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*(reinterpret_cast<uint32_t*>(data_buffer) + read_counter + 1) = 0;
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reinterpret_cast<uint32_t*>(data_buffer) + read_counter, 3);
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read_counter += 2;
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}
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} else {
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SetGrbmGfxIndex(cmd_buffer, grbm_value, block_info->attr);
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builder.BuildCopyCounterDataPacket(
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cmd_buffer, reg_info.register_addr_lo, reg_info.register_addr_hi,
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reinterpret_cast<uint32_t*>(data_buffer) + read_counter, 3);
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read_counter += 2;
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}
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}
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}
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}
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// Reset Grbm to its default state - broadcast
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@@ -641,54 +645,7 @@ class GpuPmcBuilder : public PmcBuilder, protected Primitives {
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SetGrbmBroadcast(cmd_buffer, counters_vec.get_attr());
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uint32_t sdma_mask = 0;
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if (counters_vec.get_attr() & CounterBlockAidAttr)
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for (const auto& counter_des : counters_vec) {
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const auto* block_info = counter_des.block_info;
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const auto& block_des = counter_des.block_des;
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const auto* reg_table = get_reg_table(counter_des);
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const auto& reg_info = reg_table[counter_des.index];
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if (!(block_info->attr & CounterBlockAidAttr))
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// skip all non-AID blocks
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continue;
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// MI300 AID blocks: UMC/RPB/ATC/SDMA event insert master XCC PRED_EXEC packet here
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PrecExecBuilder<Builder> prec_exec_builder(builder, cmd_buffer, VIRTUALXCCID_SELECT,
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xcc_number_ > 1);
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const auto target_aid_index = GetTargetAid(counter_des);
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uint64_t smn_control_addr = get_smn_addr(reg_info.control_addr, target_aid_index);
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if (block_info->attr & CounterBlockUmcAttr) {
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// Stop UMC
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} else if (block_info->attr & (CounterBlockRpbAttr | CounterBlockAtcAttr)) {
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// Stop RPB/ATC
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builder.BuildWritePConfigRegPacket(cmd_buffer, smn_control_addr, 0);
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} else if (block_info->attr & CounterBlockSdmaAttr) {
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// Stop SDMA
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if (reg_info.control_addr.offset == 0) {
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// MI100: stopped per instance
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const uint32_t mask = 1u << counter_des.block_des.index;
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if ((sdma_mask & mask) == 0) {
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sdma_mask |= mask;
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auto control_addr = (reg_info.control_addr.offset == 0) ? reg_info.select_addr
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: reg_info.control_addr;
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builder.BuildWritePConfigRegPacket(cmd_buffer, control_addr,
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Primitives::sdma_stop_value(counter_des));
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}
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} else if (xcc_number_ > 1) {
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// MI300 SDMA event: insert master XCC PRED_EXEC packet here
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builder.BuildWritePConfigRegPacket(cmd_buffer, smn_control_addr,
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Primitives::sdma_stop_value(counter_des));
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} else {
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// MI200: stopped per counter to choose which counter to read
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builder.BuildWritePConfigRegPacket(cmd_buffer, reg_info.control_addr,
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Primitives::sdma_stop_value(counter_des));
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}
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}
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}
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sdma_mask = 0;
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if (counters_vec.get_attr() & CounterBlockAidAttr)
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if (counters_vec.get_attr() & CounterBlockAidAttr) {
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for (const auto& counter_des : counters_vec) {
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const auto* block_info = counter_des.block_info;
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const auto& block_des = counter_des.block_des;
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@@ -734,6 +691,7 @@ class GpuPmcBuilder : public PmcBuilder, protected Primitives {
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}
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}
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}
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}
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// Issue barrier command to wait commands to complete
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SetPerfmonCntl(cmd_buffer, Primitives::cp_perfmon_cntl_stop_value(), counters_vec.get_attr());
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@@ -755,7 +713,7 @@ class GpuPmcBuilder : public PmcBuilder, protected Primitives {
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SetPerfmonCntl(cmd_buffer, Primitives::cp_perfmon_cntl_read_value(), counters_vec.get_attr());
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// counters have UMC events: MI300 Loop over MI300 XCCs for each counter_des
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if (counters_attr & CounterBlockAidAttr)
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if (counters_attr & CounterBlockAidAttr) {
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for (const auto& counter_des : counters_vec) {
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const auto* block_info = counter_des.block_info;
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const auto& block_des = counter_des.block_des;
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@@ -809,6 +767,7 @@ class GpuPmcBuilder : public PmcBuilder, protected Primitives {
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read_counter += 2;
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}
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}
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}
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for (size_t xcc_selected = 0; xcc_selected < xcc_number_; ++xcc_selected) {
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PrecExecBuilder<Builder> prec_exec_builder(builder, cmd_buffer, xcc_selected,
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xcc_number_ > 1);
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