Adjust how we read ECC block counter status

This change corresponds to kernel changes.

Change-Id: Ibd977e8b3338349036cb16e55fb0b2c9c187726d

include/rocm_smi/rocm_smi.h

@@ -361,10 +361,19 @@ typedef enum {
   RSMI_GPU_BLOCK_UMC = RSMI_GPU_BLOCK_FIRST,      //!< UMC block
   RSMI_GPU_BLOCK_SDMA =      0x0000000000000002,  //!< SDMA block
   RSMI_GPU_BLOCK_GFX =       0x0000000000000004,  //!< GFX block
+  RSMI_GPU_BLOCK_MMHUB =     0x0000000000000008,  //!< MMHUB block
+  RSMI_GPU_BLOCK_ATHUB =     0x0000000000000010,  //!< ATHUB block
+  RSMI_GPU_BLOCK_PCIE_BIF =  0x0000000000000020,  //!< PCIE_BIF block
+  RSMI_GPU_BLOCK_HDP =       0x0000000000000040,  //!< HDP block
+  RSMI_GPU_BLOCK_XGMI_WAFL = 0x0000000000000080,  //!< XGMI block
+  RSMI_GPU_BLOCK_DF =        0x0000000000000100,  //!< DF block
+  RSMI_GPU_BLOCK_SMN =       0x0000000000000200,  //!< SMN block
+  RSMI_GPU_BLOCK_SEM =       0x0000000000000400,  //!< SEM block
+  RSMI_GPU_BLOCK_MP0 =       0x0000000000000800,  //!< MP0 block
+  RSMI_GPU_BLOCK_MP1 =       0x0000000000001000,  //!< MP1 block
+  RSMI_GPU_BLOCK_FUSE =      0x0000000000002000,  //!< Fuse block
 
-  // New enum elements will be added as support is added for other blocks
-
-  RSMI_GPU_BLOCK_LAST = RSMI_GPU_BLOCK_GFX,       //!< The highest bit position
+  RSMI_GPU_BLOCK_LAST = RSMI_GPU_BLOCK_FUSE,       //!< The highest bit position
                                                   //!< for supported blocks
   RSMI_GPU_BLOCK_RESERVED =  0x8000000000000000
 } rsmi_gpu_block_t;
@@ -1818,6 +1827,10 @@ rsmi_dev_firmware_version_get(uint32_t dv_ind, rsmi_fw_block_t block,
  *
  * @retval ::RSMI_STATUS_SUCCESS is returned upon successful call.
  *
+ * ::RSMI_NOT_SUPPORTED will be returned if either ECC is not enabled for the
+ * specified block @p block, or if there is no kernel support for ECC for
+ * that block.
+ *
  */
 rsmi_status_t rsmi_dev_ecc_count_get(uint32_t dv_ind,
                               rsmi_gpu_block_t block, rsmi_error_count_t *ec);
@@ -1826,22 +1839,25 @@ rsmi_status_t rsmi_dev_ecc_count_get(uint32_t dv_ind,
  * @brief Retrieve the enabled ECC bit-mask
  *
  * @details Given a device index @p dv_ind, and a pointer to a uint64_t @p
- * enabled_mask, this function will write a bit_mask to memory pointed to by
- * @p enabled_mask. Upon a successful call, the bitmask can then be AND'd with
- * elements of the ::rsmi_gpu_block_t ennumeration to determine if the
- * corresponding block has ECC enabled. Note that the bits above
- * ::RSMI_GPU_BLOCK_LAST correspond to blocks that do not yet have ECC support.
+ * enabled_mask, this function will write bits to memory pointed to by
+ * @p enabled_blocks. Upon a successful call, @p enabled_blocks can then be
+ * AND'd with elements of the ::rsmi_gpu_block_t ennumeration to determine if
+ * the corresponding block has ECC enabled. Note that whether a block has ECC
+ * enabled or not in the device is independent of whether there is kernel
+ * support for error counting for that block. Although a block may be enabled,
+ * but there may not be kernel support for reading error counters for that
+ * block.
  *
  * @param[in] dv_ind a device index
  *
- * @param[inout] enabled_mask A pointer to a uint64_t to which the enabled
- * mask will be written
+ * @param[inout] enabled_blocks A pointer to a uint64_t to which the enabled
+ * blocks bits will be written
  *
  * @retval ::RSMI_STATUS_SUCCESS is returned upon successful call.
  *
  */
 rsmi_status_t rsmi_dev_ecc_enabled_get(uint32_t dv_ind,
-                                                      uint64_t *enabled_mask);
+                                                    uint64_t *enabled_blocks);
 
 /**
  * @brief Retrieve the ECC status for a GPU block