From bb01b4c3b45cd85d4cf355e735ec93c2fc4b8160 Mon Sep 17 00:00:00 2001
From: Saleel Kudchadker <Saleel.Kudchadker@amd.com>
Date: Tue, 14 May 2024 00:13:22 +0000
Subject: [PATCH] SWDEV-461717 - Increase CB alignment and size

- Gfx12 TCC cacheline size is 256B, Increase to have alignment
compatible. Eventually this needs to be replaced with what the query
returns.

Change-Id: I545929446c4faa3f26872a6290b3a89657888596
---
 rocclr/device/rocm/rocblit.hpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/rocclr/device/rocm/rocblit.hpp b/rocclr/device/rocm/rocblit.hpp
index f8b4c1a28b..35035cbb76 100644
--- a/rocclr/device/rocm/rocblit.hpp
+++ b/rocclr/device/rocm/rocblit.hpp
@@ -576,8 +576,8 @@ class KernelBlitManager : public DmaBlitManager {
                           const device::Memory* dev_mem = nullptr,
                           bool writeVAImmediate = false) const;
 
-  static constexpr uint32_t kCBSize = 0x80;
-  static constexpr size_t   kCBAlignment = 0x80;
+  static constexpr uint32_t kCBSize = 0x100;
+  static constexpr size_t   kCBAlignment = 0x100;
 
   inline uint32_t NumBlitKernels() {
     return (dev().info().imageSupport_) ? BlitTotal : BlitLinearTotal;