GFX12: Update addrlib

Updated address lib to mesa amd-temp-gfx12 branch.
Commit: 6e5244bd3184f0720197270a10e031b5ecd5fe75

Signed-off-by: David Belanger <david.belanger@amd.com>
Change-Id: Icaead4f38c5f3019c375116070b1f97a927f09b0
Signed-off-by: Chris Freehill <cfreehil@amd.com>


[ROCm/ROCR-Runtime commit: bb02f4e9a7]
This commit is contained in:
David Belanger
2024-02-02 11:06:06 -05:00
committed by Chris Freehill
parent 1b5596a7f2
commit bb0a28b8c5
41 changed files with 5329 additions and 1159 deletions
@@ -2,24 +2,7 @@
************************************************************************************************************************
*
* Copyright (C) 2007-2022 Advanced Micro Devices, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE
* SPDX-License-Identifier: MIT
*
***********************************************************************************************************************/
@@ -2,24 +2,7 @@
************************************************************************************************************************
*
* Copyright (C) 2007-2022 Advanced Micro Devices, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE
* SPDX-License-Identifier: MIT
*
***********************************************************************************************************************/
@@ -74,3 +57,4 @@ union GB_ADDR_CONFIG_GFX11
};
#endif
@@ -0,0 +1,57 @@
/*
************************************************************************************************************************
*
* Copyright (C) 2007-2023 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*
***********************************************************************************************************************/
#if !defined (__GFX12_GB_REG_H__)
#define __GFX12_GB_REG_H__
/*
* gfx12_gb_reg.h
*
* Register Spec Release: 1.0
*
*/
//
// Make sure the necessary endian defines are there.
//
#if defined(LITTLEENDIAN_CPU)
#elif defined(BIGENDIAN_CPU)
#else
#error "BIGENDIAN_CPU or LITTLEENDIAN_CPU must be defined"
#endif
union GB_ADDR_CONFIG_GFX12 {
struct {
#if defined(LITTLEENDIAN_CPU)
unsigned int NUM_PIPES : 3;
unsigned int PIPE_INTERLEAVE_SIZE : 3;
unsigned int MAX_COMPRESSED_FRAGS : 2;
unsigned int NUM_PKRS : 3;
unsigned int : 8;
unsigned int NUM_SHADER_ENGINES : 4;
unsigned int : 3;
unsigned int NUM_RB_PER_SE : 2;
unsigned int : 4;
#elif defined(BIGENDIAN_CPU)
unsigned int : 4;
unsigned int NUM_RB_PER_SE : 2;
unsigned int : 3;
unsigned int NUM_SHADER_ENGINES : 4;
unsigned int : 8;
unsigned int NUM_PKRS : 3;
unsigned int MAX_COMPRESSED_FRAGS : 2;
unsigned int PIPE_INTERLEAVE_SIZE : 3;
unsigned int NUM_PIPES : 3;
#endif
} bitfields, bits;
unsigned int u32All;
int i32All;
float f32All;
};
#endif
@@ -2,24 +2,7 @@
************************************************************************************************************************
*
* Copyright (C) 2007-2022 Advanced Micro Devices, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE
* SPDX-License-Identifier: MIT
*
***********************************************************************************************************************/
@@ -2,24 +2,7 @@
************************************************************************************************************************
*
* Copyright (C) 2007-2022 Advanced Micro Devices, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE
* SPDX-License-Identifier: MIT
*
***********************************************************************************************************************/
@@ -93,9 +76,52 @@
#endif
#if defined(LITTLEENDIAN_CPU)
typedef struct _GB_ADDR_CONFIG_N {
unsigned int num_pipes : 3;
unsigned int pipe_interleave_size : 3;
unsigned int max_compressed_frags : 2;
unsigned int bank_interleave_size : 3;
unsigned int : 1;
unsigned int num_banks : 3;
unsigned int : 1;
unsigned int shader_engine_tile_size : 3;
unsigned int num_shader_engines : 2;
unsigned int num_gpus : 3;
unsigned int multi_gpu_tile_size : 2;
unsigned int num_rb_per_se : 2;
unsigned int row_size : 2;
unsigned int num_lower_pipes : 1;
unsigned int se_enable : 1;
} GB_ADDR_CONFIG_N;
#elif defined(BIGENDIAN_CPU)
typedef struct _GB_ADDR_CONFIG_N {
unsigned int se_enable : 1;
unsigned int num_lower_pipes : 1;
unsigned int row_size : 2;
unsigned int num_rb_per_se : 2;
unsigned int multi_gpu_tile_size : 2;
unsigned int num_gpus : 3;
unsigned int num_shader_engines : 2;
unsigned int shader_engine_tile_size : 3;
unsigned int : 1;
unsigned int num_banks : 3;
unsigned int : 1;
unsigned int bank_interleave_size : 3;
unsigned int max_compressed_frags : 2;
unsigned int pipe_interleave_size : 3;
unsigned int num_pipes : 3;
} GB_ADDR_CONFIG_N;
#endif
typedef union {
unsigned int val : 32;
GB_ADDR_CONFIG_T f;
GB_ADDR_CONFIG_N n;
} GB_ADDR_CONFIG;
#if defined(LITTLEENDIAN_CPU)