SWDEV-464475 - Add linting and spellcheck

- Markdown fixes
- Fix spellcheck
- Clean up
- Supress etoc warning
- Remove folder before clone if it's exist
- Change liniting.yml to use develop
- Trailing white space fix

Change-Id: Ib3bb2cdd0abebeb21071b5d2e2d3b57fe41666e0

docs/understand/glossary.md

@@ -1,23 +1,24 @@
 # Glossary of terms
 
-- **host**, **host cpu** : Executes the HIP runtime API and is capable of initiating kernel launches to one or more devices.
-- **default device** : Each host thread maintains a default device.
+* **host**, **host CPU** : Executes the HIP runtime API and is capable of initiating kernel launches to one or more devices.
+* **default device** : Each host thread maintains a default device.
 Most HIP runtime APIs (including memory allocation, copy commands, kernel launches) do not accept an explicit device
 argument but instead implicitly use the default device.
-The default device can be set with ```hipSetDevice```.
+The default device can be set with `hipSetDevice`.
 
-- **active host thread** - the thread which is running the HIP APIs.
+* **active host thread** - the thread which is running the HIP APIs.
 
-- **HIP-Clang** - Heterogeneous AMDGPU Compiler, with its capability to compile HIP programs on AMD platform (https://github.com/RadeonOpenCompute/llvm-project).
+* **HIP-Clang** - Heterogeneous AMDGPU Compiler, with its capability to compile HIP programs on AMD platform (https://github.com/RadeonOpenCompute/llvm-project).
 
-- **clr** - a repository for AMD Common Language Runtime, contains source codes for AMD's compute languages runtimes: HIP and OpenCL.
+* **clr** - a repository for AMD Common Language Runtime, contains source codes for AMD's compute languages runtimes: HIP and OpenCL.
 clr (https://github.com/ROCm/clr) contains the following three parts,
-    - ```hipamd```: contains implementation of HIP language on AMD platform.
-    - ```rocclr```: contains common runtime used in HIP and OpenCL, which provides virtual device interfaces that compute runtimes interact with different backends such as ROCr on Linux or PAL on Windows.
-    - ```opencl```: contains implementation of OpenCL on AMD platform.
 
-- **hipify tools** - tools to convert CUDA code to portable C++ code (https://github.com/ROCm/HIPIFY).
+  * `hipamd`: contains implementation of HIP language on AMD platform.
+  * `rocclr`: contains common runtime used in HIP and OpenCL, which provides virtual device interfaces that compute runtimes interact with different backends such as ROCr on Linux or PAL on Windows.
+  * `opencl`: contains implementation of OpenCL on AMD platform.
 
-- **hipconfig** - tool to report various configuration properties of the target platform.
+* **hipify tools** - tools to convert CUDA code to portable C++ code (https://github.com/ROCm/HIPIFY).
 
-- **nvcc** - NVIDIA CUDA ```nvcc``` compiler, do not capitalize.
+* **`hipconfig`** - tool to report various configuration properties of the target platform.
+
+* **`nvcc`** - NVIDIA CUDA `nvcc` compiler, do not capitalize.

docs/understand/programming_model.rst

@@ -9,17 +9,17 @@ Understanding the HIP programming model
 *******************************************************************************
 
 The HIP programming model makes it easy to map data-parallel C/C++ algorithms to
-massively parallel, wide single instruction, multiple data (SIMD) architectures, 
-such as GPUs. A basic understanding of the underlying device architecture helps you 
-make efficient use of HIP and general purpose graphics processing unit (GPGPU) 
+massively parallel, wide single instruction, multiple data (SIMD) architectures,
+such as GPUs. A basic understanding of the underlying device architecture helps you
+make efficient use of HIP and general purpose graphics processing unit (GPGPU)
 programming in general.
 
 RDNA & CDNA Architecture Summary
 ================================
 
 Most GPU architectures, like RDNA and CDNA, have a hierarchical structure.
-The innermost piece is a SIMD-enabled vector Arithmetic Logical Unit (ALU). 
-In addition to the vector ALUs, most recent GPUs also house matrix ALUs for 
+The innermost piece is a SIMD-enabled vector Arithmetic Logical Unit (ALU).
+In addition to the vector ALUs, most recent GPUs also house matrix ALUs for
 accelerating algorithms involving matrix multiply-accumulate operations.
 AMD GPUs also contain scalar ALUs, that can be used to reduce the load on the
 vector ALU by performing operations which are uniform for all threads of a warp.
@@ -71,8 +71,8 @@ memory subsystem resources.
 Single Instruction Multiple Threads
 ===================================
 
-The single instruction, multiple threads (SIMT) programming model behind the 
-HIP device-side execution is a middle-ground between SMT (Simultaneous Multi-Threading) 
+The single instruction, multiple threads (SIMT) programming model behind the
+HIP device-side execution is a middle-ground between SMT (Simultaneous Multi-Threading)
 programming known from multicore CPUs, and SIMD (Single Instruction, Multiple Data) programming
 mostly known from exploiting relevant instruction sets on CPUs (for example SSE/AVX/Neon).
 
@@ -84,7 +84,7 @@ identical instructions over the available SIMD engines.
 
 Consider the following kernel:
 
-.. code:: cu
+.. code-block:: cpp
 
   __global__ void k(float4* a, const float4* b)
   {
@@ -153,4 +153,4 @@ a few key differences between the two:
   execute asynchronously with respect to the host, and it is the user's responsibility to
   synchronize their data dispatch/fetch with computations on the device. HIP
   does perform implicit synchronization on occasions, more advanced than other APIs such as
-  OpenCL or SYCL, in which the responsibility of synchronization mostly depends on the user. 
+  OpenCL or SYCL, in which the responsibility of synchronization mostly depends on the user.

docs/understand/programming_model_reference.rst

@@ -8,9 +8,9 @@
 Programming model reference
 *******************************************************************************
 
-HIP defines a model for mapping single instruction, multiple threads (SIMT) programs 
-onto various architectures, primarily GPUs. While the model may be expressed 
-in most imperative languages, (eg. Python via PyHIP) this document will focus on 
+HIP defines a model for mapping single instruction, multiple threads (SIMT) programs
+onto various architectures, primarily GPUs. While the model may be expressed
+in most imperative languages, (for example Python via PyHIP) this document will focus on
 the original C/C++ API of HIP.
 
 Threading Model
@@ -20,8 +20,8 @@ The SIMT nature of HIP is captured by the ability to execute user-provided
 device programs, expressed as single-source C/C++ functions or sources compiled
 online/offline to binaries in bulk.
 
-Multiple instances of the device program (or kernel) are called threads and may 
-execute in parallel. All uniquely identified by a set of integral values, or thread IDs. 
+Multiple instances of the device program (or kernel) are called threads and may
+execute in parallel. All uniquely identified by a set of integral values, or thread IDs.
 The set of integers identifying a thread relate to the hierarchy in which threads execute.
 
 .. _inherent_thread_model:
@@ -53,10 +53,10 @@ Warp
   multidimensional as the user interprets the calculated values to be.
 
   The size of a warp is architecture dependent and always fixed. Warps are
-  signified by the set of communication primitives at their disposal, as 
+  signified by the set of communication primitives at their disposal, as
   discussed in :ref:`warp-cross-lane`.
 
-Block 
+Block
   The middle grouping is called a block or thread block. The defining feature
   of a block is that all threads in a block will share an instance of memory
   which they may use to share data or synchronize with one another.
@@ -67,7 +67,7 @@ Block
   within a block, assume the "fast index" being dimension ``x``, followed by
   the ``y`` and ``z`` dimensions.
 
-Grid 
+Grid
   The outermost grouping is called a grid. A grid manifests as a single
   dispatch of kernels for execution. The unique ID of each block within a grid
   is 3-dimensional, as provided by the API and is queryable by every thread