diff --git a/projects/rdc/include/rdc_lib/impl/RdcConfigSettingsImpl.h b/projects/rdc/include/rdc_lib/impl/RdcConfigSettingsImpl.h
index a58017edb4..f492bdf77b 100644
--- a/projects/rdc/include/rdc_lib/impl/RdcConfigSettingsImpl.h
+++ b/projects/rdc/include/rdc_lib/impl/RdcConfigSettingsImpl.h
@@ -64,6 +64,7 @@ class RdcConfigSettingsImpl : public RdcConfigSettings {
   void monitorSettings();
   uint64_t wattsToMicrowatts(uint64_t watts) const;
   uint64_t microwattsToWatts(int microwatts) const;
+  uint64_t mHzToHz(uint64_t mhz) const;
   rdc_status_t get_group_info(rdc_gpu_group_t group_id, rdc_group_info_t* rdc_group_info);
 };
 
diff --git a/projects/rdc/rdc_libs/rdc/src/RdcConfigSettingsImpl.cc b/projects/rdc/rdc_libs/rdc/src/RdcConfigSettingsImpl.cc
index a126884ea7..ba763bd485 100644
--- a/projects/rdc/rdc_libs/rdc/src/RdcConfigSettingsImpl.cc
+++ b/projects/rdc/rdc_libs/rdc/src/RdcConfigSettingsImpl.cc
@@ -44,7 +44,7 @@ void RdcConfigSettingsImpl::monitorSettings() {
   rdc_status_t rdc_status;
   rdc_group_info_t rdc_group_info = {};
   amdsmi_power_cap_info_t cap_info = {};
-  amdsmi_frequencies_t freqs = {};
+  amdsmi_clk_info_t info = {};
   uint64_t cached_value;
 
   while (true) {
@@ -102,18 +102,18 @@ void RdcConfigSettingsImpl::monitorSettings() {
           }
 
           // Mem clock
-          status = amdsmi_get_clk_freq(processor_handle, AMDSMI_CLK_TYPE_MEM, &freqs);
+          status = amdsmi_get_clock_info(processor_handle, AMDSMI_CLK_TYPE_MEM, &info);
           if (status != AMDSMI_STATUS_SUCCESS) {
-            RDC_LOG(
-                RDC_ERROR,
-                "RdcConfigSettingsImpl::monitorSettings(); amdsmi_get_clk_freq failed: " << status);
+            RDC_LOG(RDC_ERROR,
+                    "RdcConfigSettingsImpl::monitorSettings(); amdsmi_get_clk_freq for mem failed: "
+                        << status);
             continue;
           }
 
           auto mem_clk_it = cached_settings.find(RDC_CFG_MEMORY_CLOCK_LIMIT);
           if (mem_clk_it != cached_settings.end()) {
             cached_value = mem_clk_it->second.target_value;
-            if (freqs.frequency[freqs.current] == cached_value) {
+            if (info.max_clk != cached_value) {
               status = amdsmi_set_gpu_clk_limit(processor_handle, AMDSMI_CLK_TYPE_MEM,
                                                 CLK_LIMIT_MAX, cached_value);
               if (status != AMDSMI_STATUS_SUCCESS) {
@@ -127,18 +127,18 @@ void RdcConfigSettingsImpl::monitorSettings() {
           }
 
           // GFX clock
-          status = amdsmi_get_clk_freq(processor_handle, AMDSMI_CLK_TYPE_GFX, &freqs);
+          status = amdsmi_get_clock_info(processor_handle, AMDSMI_CLK_TYPE_GFX, &info);
           if (status != AMDSMI_STATUS_SUCCESS) {
-            RDC_LOG(
-                RDC_ERROR,
-                "RdcConfigSettingsImpl::monitorSettings(); amdsmi_get_clk_freq failed: " << status);
+            RDC_LOG(RDC_ERROR,
+                    "RdcConfigSettingsImpl::monitorSettings(); amdsmi_get_clk_freq for gfx failed: "
+                        << status);
             continue;
           }
 
           auto gfx_clk_it = cached_settings.find(RDC_CFG_GFX_CLOCK_LIMIT);
           if (gfx_clk_it != cached_settings.end()) {
             cached_value = gfx_clk_it->second.target_value;
-            if (freqs.frequency[freqs.current] == cached_value) {
+            if (info.max_clk != cached_value) {
               status = amdsmi_set_gpu_clk_limit(processor_handle, AMDSMI_CLK_TYPE_GFX,
                                                 CLK_LIMIT_MAX, cached_value);
               if (status != AMDSMI_STATUS_SUCCESS) {
@@ -165,6 +165,8 @@ uint64_t RdcConfigSettingsImpl::microwattsToWatts(int microwatts) const {
   return microwatts / 1'000'000;
 }
 
+uint64_t RdcConfigSettingsImpl::mHzToHz(uint64_t mhz) const { return mhz * 1000000ULL; }
+
 rdc_status_t RdcConfigSettingsImpl::get_group_info(rdc_gpu_group_t group_id,
                                                    rdc_group_info_t* rdc_group_info) {
   rdc_status_t status = group_settings_->rdc_group_gpu_get_info(group_id, rdc_group_info);
@@ -312,19 +314,31 @@ rdc_status_t RdcConfigSettingsImpl::rdc_config_clear(rdc_gpu_group_t group_id) {
     // Reset GFX clock limit if it was set
     if (group_iter->second.find(RDC_CFG_GFX_CLOCK_LIMIT) != group_iter->second.end()) {
       amdsmi_frequencies_t freqs = {};
+      amdsmi_clk_info_t info = {};
+
       amd_ret = amdsmi_get_clk_freq(processor_handle, AMDSMI_CLK_TYPE_GFX, &freqs);
-      if (amd_ret == AMDSMI_STATUS_SUCCESS) {
-        uint64_t curr = freqs.frequency[freqs.current];
-        uint64_t maxf = freqs.frequency[freqs.num_supported - 1];
-        if (curr != maxf) {
-          amd_ret = amdsmi_set_gpu_clk_limit(processor_handle, AMDSMI_CLK_TYPE_GFX, CLK_LIMIT_MAX,
-                                             AMDSMI_DEV_PERF_LEVEL_AUTO);
-          if (amd_ret != AMDSMI_STATUS_SUCCESS) {
-            RDC_LOG(RDC_ERROR,
-                    "RdcConfigSettingsImpl::rdc_config_clear: Failed to reset GFX clock limit : "
-                        << amd_ret);
-            break;
-          }
+      if (amd_ret != AMDSMI_STATUS_SUCCESS) {
+        RDC_LOG(RDC_ERROR,
+                "RdcConfigSettingsImpl::rdc_config_clear: Failed to get GFX freq: " << amd_ret);
+        break;
+      }
+
+      amd_ret = amdsmi_get_clock_info(processor_handle, AMDSMI_CLK_TYPE_GFX, &info);
+      if (amd_ret != AMDSMI_STATUS_SUCCESS) {
+        RDC_LOG(RDC_ERROR,
+                "RdcConfigSettingsImpl::rdc_config_clear: Failed to get GFX info: " << amd_ret);
+        break;
+      }
+
+      uint64_t curr = mHzToHz(info.max_clk);
+      uint64_t maxf = freqs.frequency[freqs.num_supported - 1];
+      if (curr != maxf) {
+        amd_ret = amdsmi_set_gpu_perf_level(processor_handle, AMDSMI_DEV_PERF_LEVEL_AUTO);
+        if (amd_ret != AMDSMI_STATUS_SUCCESS) {
+          RDC_LOG(RDC_ERROR,
+                  "RdcConfigSettingsImpl::rdc_config_clear: Failed to reset GFX clock limit : "
+                      << amd_ret);
+          break;
         }
       }
     }
@@ -332,19 +346,31 @@ rdc_status_t RdcConfigSettingsImpl::rdc_config_clear(rdc_gpu_group_t group_id) {
     // Reset memory clock limit if it was set
     if (group_iter->second.find(RDC_CFG_MEMORY_CLOCK_LIMIT) != group_iter->second.end()) {
       amdsmi_frequencies_t freqs = {};
+      amdsmi_clk_info_t info = {};
+
       amd_ret = amdsmi_get_clk_freq(processor_handle, AMDSMI_CLK_TYPE_MEM, &freqs);
-      if (amd_ret == AMDSMI_STATUS_SUCCESS) {
-        uint64_t curr = freqs.frequency[freqs.current];
-        uint64_t maxf = freqs.frequency[freqs.num_supported - 1];
-        if (curr != maxf) {
-          amd_ret =
-              amdsmi_set_gpu_clk_limit(processor_handle, AMDSMI_CLK_TYPE_MEM, CLK_LIMIT_MAX, 0);
-          if (amd_ret != AMDSMI_STATUS_SUCCESS) {
-            RDC_LOG(RDC_ERROR,
-                    "RdcConfigSettingsImpl::rdc_config_clear: Failed to reset memory clock limit:"
-                        << amd_ret);
-            break;
-          }
+      if (amd_ret != AMDSMI_STATUS_SUCCESS) {
+        RDC_LOG(RDC_ERROR,
+                "RdcConfigSettingsImpl::rdc_config_clear: Failed to get MEM freq: " << amd_ret);
+        break;
+      }
+
+      amd_ret = amdsmi_get_clock_info(processor_handle, AMDSMI_CLK_TYPE_MEM, &info);
+      if (amd_ret != AMDSMI_STATUS_SUCCESS) {
+        RDC_LOG(RDC_ERROR,
+                "RdcConfigSettingsImpl::rdc_config_clear: Failed to get MEM info: " << amd_ret);
+        break;
+      }
+
+      uint64_t curr = mHzToHz(info.max_clk);
+      uint64_t maxf = freqs.frequency[freqs.num_supported - 1];
+      if (curr != maxf) {
+        amd_ret = amdsmi_set_gpu_perf_level(processor_handle, AMDSMI_DEV_PERF_LEVEL_AUTO);
+        if (amd_ret != AMDSMI_STATUS_SUCCESS) {
+          RDC_LOG(RDC_ERROR,
+                  "RdcConfigSettingsImpl::rdc_config_clear: Failed to reset memory clock limit:"
+                      << amd_ret);
+          break;
         }
       }
     }