From bfefbd1dc03745dc1281312f6da3be15cd443b7e Mon Sep 17 00:00:00 2001
From: foreman <dl.swbuild@amd.com>
Date: Wed, 1 May 2019 11:44:42 -0400
Subject: [PATCH] P4 to Git Change 1776874 by jatang@jatang_win_pal_lc on
 2019/05/01 10:56:52

	SWDEV-174198 - Add support for MI100.

Affected files ...

... //depot/stg/opencl/drivers/opencl/compiler/lib/backends/common/linker.cpp#160 edit
... //depot/stg/opencl/drivers/opencl/compiler/lib/utils/v0_8/libUtils.cpp#38 edit
... //depot/stg/opencl/drivers/opencl/compiler/lib/utils/v0_8/target_mappings.h#57 edit
... //depot/stg/opencl/drivers/opencl/compiler/lib/utils/v0_8/target_mappings_hsail.h#53 edit
... //depot/stg/opencl/drivers/opencl/compiler/lib/utils/v0_8/target_mappings_hsail64.h#48 edit
... //depot/stg/opencl/drivers/opencl/compiler/tools/driver/driver.cpp#70 edit


[ROCm/clr commit: c8d38859e07e2fe179794f28e49a4007d49e38f3]
---
 projects/clr/rocclr/compiler/lib/backends/common/linker.cpp    | 1 +
 projects/clr/rocclr/compiler/lib/utils/v0_8/libUtils.cpp       | 3 +++
 projects/clr/rocclr/compiler/lib/utils/v0_8/target_mappings.h  | 1 +
 .../clr/rocclr/compiler/lib/utils/v0_8/target_mappings_hsail.h | 1 +
 .../rocclr/compiler/lib/utils/v0_8/target_mappings_hsail64.h   | 1 +
 5 files changed, 7 insertions(+)

diff --git a/projects/clr/rocclr/compiler/lib/backends/common/linker.cpp b/projects/clr/rocclr/compiler/lib/backends/common/linker.cpp
index c2295e6e86..bad7455318 100644
--- a/projects/clr/rocclr/compiler/lib/backends/common/linker.cpp
+++ b/projects/clr/rocclr/compiler/lib/backends/common/linker.cpp
@@ -590,6 +590,7 @@ amdcl::OCLLinker::link(llvm::Module* input, std::vector<std::unique_ptr<llvm::Mo
                 || chip == "gfx905"
                 || chip == "gfx906"
                 || chip == "gfx907"
+                || chip == "gfx908"
                 || chip == "gfx1000"
                 || chip == "gfx1010"
                 || chip == "gfx1011"
diff --git a/projects/clr/rocclr/compiler/lib/utils/v0_8/libUtils.cpp b/projects/clr/rocclr/compiler/lib/utils/v0_8/libUtils.cpp
index 6e0289fa87..699a0d015b 100644
--- a/projects/clr/rocclr/compiler/lib/utils/v0_8/libUtils.cpp
+++ b/projects/clr/rocclr/compiler/lib/utils/v0_8/libUtils.cpp
@@ -30,6 +30,7 @@ static const std::string sgfx904 = "AMD:AMDGPU:9:0:4";
 static const std::string sgfx905 = "AMD:AMDGPU:9:0:5";
 static const std::string sgfx906 = "AMD:AMDGPU:9:0:6";
 static const std::string sgfx907 = "AMD:AMDGPU:9:0:7";
+static const std::string sgfx908 = "AMD:AMDGPU:9:0:8";
 static const std::string sgfx1000 = "AMD:AMDGPU:10:0:0";
 static const std::string sgfx1010 = "AMD:AMDGPU:10:1:0";
 static const std::string sgfx1011 = "AMD:AMDGPU:10:1:1";
@@ -547,6 +548,7 @@ const std::string &getIsaTypeName(const aclTargetInfo *target)
   case 905: return sgfx905;
   case 906: return sgfx906;
   case 907: return sgfx907;
+  case 908: return sgfx908;
   case 1000: return sgfx1000;
   case 1010: return sgfx1010;
   case 1011: return sgfx1011;
@@ -616,6 +618,7 @@ int getIsaType(const aclTargetInfo *target)
         case AI_GREENLAND_P_A1: return Mapping.xnack_supported ? 901 : 900;
         case AI_VEGA12_P_A0:    return Mapping.xnack_supported ? 905 : 904;
         case AI_VEGA20_P_A0:    return Mapping.xnack_supported ? 907 : 906;
+        case AI_MI100_P_A0:     return 908;
       }
     case FAMILY_RV:
       switch (Mapping.chip_enum) {
diff --git a/projects/clr/rocclr/compiler/lib/utils/v0_8/target_mappings.h b/projects/clr/rocclr/compiler/lib/utils/v0_8/target_mappings.h
index 6ce3b6edba..4271a59a77 100644
--- a/projects/clr/rocclr/compiler/lib/utils/v0_8/target_mappings.h
+++ b/projects/clr/rocclr/compiler/lib/utils/v0_8/target_mappings.h
@@ -217,6 +217,7 @@ static const char* calTargetMapping[] = {
       IF(IS_BRAHMA,"","gfx905"),
       IF(IS_BRAHMA,"","gfx906"),
       IF(IS_BRAHMA,"","gfx907"),
+      IF(IS_BRAHMA,"","gfx908"),
       IF(IS_BRAHMA,"","gfx1000"),
       IF(IS_BRAHMA,"","gfx1010"),
       IF(IS_BRAHMA,"","gfx1011"),
diff --git a/projects/clr/rocclr/compiler/lib/utils/v0_8/target_mappings_hsail.h b/projects/clr/rocclr/compiler/lib/utils/v0_8/target_mappings_hsail.h
index 02000cef5b..bbc4fc7b3e 100644
--- a/projects/clr/rocclr/compiler/lib/utils/v0_8/target_mappings_hsail.h
+++ b/projects/clr/rocclr/compiler/lib/utils/v0_8/target_mappings_hsail.h
@@ -51,6 +51,7 @@ static const TargetMapping HSAILTargetMapping_0_8[] = {
   { "AI", "gfx905",    "GFX9",  amd::GPU_Library_HSAIL, AI_VEGA12_P_A0,     F_AI_BASE, true, true,  FAMILY_AI, true },
   { "AI", "gfx906",    "GFX9",  amd::GPU_Library_HSAIL, AI_VEGA20_P_A0,     F_AI_BASE, true, true,  FAMILY_AI, false },
   { "AI", "gfx907",    "GFX9",  amd::GPU_Library_HSAIL, AI_VEGA20_P_A0,     F_AI_BASE, true, true,  FAMILY_AI, true },
+  { "AI", "gfx908",    "GFX9",  amd::GPU_Library_HSAIL, AI_MI100_P_A0,      F_AI_BASE, true, true,  FAMILY_AI, true },
   { "NV", "gfx1000",   "GFX10", amd::GPU_Library_HSAIL, NV_NAVI10_LITE_P_A0,     F_AI_BASE, true, true,  FAMILY_NV, false },
   { "NV", "gfx1010",   "GFX10", amd::GPU_Library_HSAIL, NV_NAVI10_P_A0,     F_AI_BASE, true, true,  FAMILY_NV, false },
   { "NV", "gfx1011",   "GFX10", amd::GPU_Library_HSAIL, NV_NAVI12_P_A0,     F_AI_BASE, true, true,  FAMILY_NV, false },
diff --git a/projects/clr/rocclr/compiler/lib/utils/v0_8/target_mappings_hsail64.h b/projects/clr/rocclr/compiler/lib/utils/v0_8/target_mappings_hsail64.h
index dfd6ef0653..c8cea64a4c 100644
--- a/projects/clr/rocclr/compiler/lib/utils/v0_8/target_mappings_hsail64.h
+++ b/projects/clr/rocclr/compiler/lib/utils/v0_8/target_mappings_hsail64.h
@@ -50,6 +50,7 @@ static const TargetMapping HSAIL64TargetMapping_0_8[] = {
   { "AI", "gfx905",    "GFX9",  amd::GPU_Library_HSAIL, AI_VEGA12_P_A0,     F_AI_BASE, true, true,  FAMILY_AI, true },
   { "AI", "gfx906",    "GFX9",  amd::GPU_Library_HSAIL, AI_VEGA20_P_A0,     F_AI_BASE, true, true,  FAMILY_AI, false },
   { "AI", "gfx907",    "GFX9",  amd::GPU_Library_HSAIL, AI_VEGA20_P_A0,     F_AI_BASE, true, true,  FAMILY_AI, true },
+  { "AI", "gfx908",    "GFX9",  amd::GPU_Library_HSAIL, AI_MI100_P_A0,      F_AI_BASE, true, true,  FAMILY_AI, true },
   { "NV", "gfx1000",   "GFX10", amd::GPU_Library_HSAIL, NV_NAVI10_LITE_P_A0,     F_AI_BASE, true, true,  FAMILY_NV, false },
   { "NV", "gfx1010",   "GFX10", amd::GPU_Library_HSAIL, NV_NAVI10_P_A0,     F_AI_BASE, true, true,  FAMILY_NV, false },
   { "NV", "gfx1011",   "GFX10", amd::GPU_Library_HSAIL, NV_NAVI12_P_A0,     F_AI_BASE, true, true,  FAMILY_NV, false },