diff --git a/docs/doxygen/Doxyfile b/docs/doxygen/Doxyfile index 892855e79d..e2c08b77c0 100644 --- a/docs/doxygen/Doxyfile +++ b/docs/doxygen/Doxyfile @@ -2238,7 +2238,7 @@ ENABLE_PREPROCESSING = YES # The default value is: NO. # This tag requires that the tag ENABLE_PREPROCESSING is set to YES. -MACRO_EXPANSION = NO +MACRO_EXPANSION = YES # If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES then # the macro expansion is limited to the macros specified with the PREDEFINED and @@ -2246,7 +2246,7 @@ MACRO_EXPANSION = NO # The default value is: NO. # This tag requires that the tag ENABLE_PREPROCESSING is set to YES. -EXPAND_ONLY_PREDEF = NO +EXPAND_ONLY_PREDEF = YES # If the SEARCH_INCLUDES tag is set to YES, the include files in the # INCLUDE_PATH will be searched if a #include is found. @@ -2279,7 +2279,8 @@ INCLUDE_FILE_PATTERNS = # recursively expanded use the := operator instead of the = operator. # This tag requires that the tag ENABLE_PREPROCESSING is set to YES. -PREDEFINED = ENABLE_ESMI_LIB +PREDEFINED = ENABLE_ESMI_LIB \ + __attribute__(x)= # If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then this # tag can be used to specify a list of macro names that should be expanded. The diff --git a/include/amd_smi/amdsmi.h b/include/amd_smi/amdsmi.h index 8517ceb30b..ff0c30a448 100644 --- a/include/amd_smi/amdsmi.h +++ b/include/amd_smi/amdsmi.h @@ -47,11 +47,12 @@ extern "C" { */ typedef enum { AMDSMI_INIT_ALL_PROCESSORS = 0xFFFFFFFF, //!< Initialize all processors - AMDSMI_INIT_AMD_CPUS = (1 << 0), - AMDSMI_INIT_AMD_GPUS = (1 << 1), - AMDSMI_INIT_NON_AMD_CPUS = (1 << 2), - AMDSMI_INIT_NON_AMD_GPUS = (1 << 3), - AMDSMI_INIT_AMD_APUS = (AMDSMI_INIT_AMD_CPUS | AMDSMI_INIT_AMD_GPUS) // Default option + AMDSMI_INIT_AMD_CPUS = (1 << 0), //!< Initialize AMD CPUS + AMDSMI_INIT_AMD_GPUS = (1 << 1), //!< Initialize AMD GPUS + AMDSMI_INIT_NON_AMD_CPUS = (1 << 2), //!< Initialize Non-AMD CPUS + AMDSMI_INIT_NON_AMD_GPUS = (1 << 3), //!< Initialize Non-AMD GPUS + AMDSMI_INIT_AMD_APUS = (AMDSMI_INIT_AMD_CPUS | AMDSMI_INIT_AMD_GPUS) /**< Initialize AMD CPUS and GPUS + (Default option) */ } amdsmi_init_flags_t; /** @@ -221,9 +222,9 @@ typedef enum { * @cond @tag{gpu_bm_linux} @tag{host} @endcond */ typedef enum { - AMDSMI_MM_UVD, - AMDSMI_MM_VCE, - AMDSMI_MM_VCN, + AMDSMI_MM_UVD, //!< Multi-Media Unified Video Decoder + AMDSMI_MM_VCE, //!< Multi-Media Video Coding Engine + AMDSMI_MM_VCN, //!< Multi-Media Video Core Next AMDSMI_MM__MAX } amdsmi_mm_ip_t; @@ -233,8 +234,8 @@ typedef enum { * @cond @tag{gpu_bm_linux} @endcond */ typedef enum { - AMDSMI_CONTAINER_LXC, - AMDSMI_CONTAINER_DOCKER, + AMDSMI_CONTAINER_LXC, //!< Linux containers + AMDSMI_CONTAINER_DOCKER //!< Docker containers } amdsmi_container_types_t; /** @@ -276,13 +277,13 @@ typedef struct { * @cond @tag{gpu_bm_linux} @tag{host} @tag{cpu_bm} @tag{guest_windows} @endcond */ typedef enum { - AMDSMI_PROCESSOR_TYPE_UNKNOWN = 0, - AMDSMI_PROCESSOR_TYPE_AMD_GPU, - AMDSMI_PROCESSOR_TYPE_AMD_CPU, - AMDSMI_PROCESSOR_TYPE_NON_AMD_GPU, - AMDSMI_PROCESSOR_TYPE_NON_AMD_CPU, - AMDSMI_PROCESSOR_TYPE_AMD_CPU_CORE, - AMDSMI_PROCESSOR_TYPE_AMD_APU + AMDSMI_PROCESSOR_TYPE_UNKNOWN = 0, //!< Unknown processor type + AMDSMI_PROCESSOR_TYPE_AMD_GPU, //!< AMD Graphics processor type + AMDSMI_PROCESSOR_TYPE_AMD_CPU, //!< AMD CPU processor type + AMDSMI_PROCESSOR_TYPE_NON_AMD_GPU, //!< Non-AMD Graphics processor type + AMDSMI_PROCESSOR_TYPE_NON_AMD_CPU, //!< Non-AMD CPU processor type + AMDSMI_PROCESSOR_TYPE_AMD_CPU_CORE, //!< AMD CPU-Core processor type + AMDSMI_PROCESSOR_TYPE_AMD_APU //!< AMD Accelerated processor type (GPU and CPU) } processor_type_t; /** @@ -343,7 +344,7 @@ typedef enum { AMDSMI_STATUS_CORRUPTED_EEPROM = 56, //!< EEPROM is corrupted // General errors AMDSMI_STATUS_MAP_ERROR = 0xFFFFFFFE, //!< The internal library error did not map to a status code - AMDSMI_STATUS_UNKNOWN_ERROR = 0xFFFFFFFF, //!< An unknown error occurred + AMDSMI_STATUS_UNKNOWN_ERROR = 0xFFFFFFFF //!< An unknown error occurred } amdsmi_status_t; /** @@ -376,16 +377,16 @@ typedef enum { */ typedef enum { AMDSMI_ACCELERATOR_PARTITION_INVALID = 0, - AMDSMI_ACCELERATOR_PARTITION_SPX, //!< Single GPU mode (SPX)- All XCCs work - //!< together with shared memory - AMDSMI_ACCELERATOR_PARTITION_DPX, //!< Dual GPU mode (DPX)- Half XCCs work - //!< together with shared memory - AMDSMI_ACCELERATOR_PARTITION_TPX, //!< Triple GPU mode (TPX)- One-third XCCs - //!< work together with shared memory - AMDSMI_ACCELERATOR_PARTITION_QPX, //!< Quad GPU mode (QPX)- Quarter XCCs - //!< work together with shared memory - AMDSMI_ACCELERATOR_PARTITION_CPX, //!< Core mode (CPX)- Per-chip XCC with - //!< shared memory + AMDSMI_ACCELERATOR_PARTITION_SPX, /**< Single GPU mode (SPX)- All XCCs work + together with shared memory */ + AMDSMI_ACCELERATOR_PARTITION_DPX, /**< Dual GPU mode (DPX)- Half XCCs work + together with shared memory */ + AMDSMI_ACCELERATOR_PARTITION_TPX, /**< Triple GPU mode (TPX)- One-third XCCs + work together with shared memory */ + AMDSMI_ACCELERATOR_PARTITION_QPX, /**< Quad GPU mode (QPX)- Quarter XCCs + work together with shared memory */ + AMDSMI_ACCELERATOR_PARTITION_CPX, /**< Core mode (CPX)- Per-chip XCC with + shared memory */ AMDSMI_ACCELERATOR_PARTITION_MAX } amdsmi_accelerator_partition_type_t; @@ -395,11 +396,11 @@ typedef enum { * @cond @tag{gpu_bm_linux} @tag{host} @tag{guest_windows} @endcond */ typedef enum { - AMDSMI_ACCELERATOR_XCC, - AMDSMI_ACCELERATOR_ENCODER, - AMDSMI_ACCELERATOR_DECODER, - AMDSMI_ACCELERATOR_DMA, - AMDSMI_ACCELERATOR_JPEG, + AMDSMI_ACCELERATOR_XCC, //!< Compute complex or stream processors + AMDSMI_ACCELERATOR_ENCODER, //!< Video encoding + AMDSMI_ACCELERATOR_DECODER, //!< Video decoding + AMDSMI_ACCELERATOR_DMA, //!< Direct Memory Access, high speed data transfers + AMDSMI_ACCELERATOR_JPEG, //!< Encoding and Decoding jpeg engines AMDSMI_ACCELERATOR_MAX } amdsmi_accelerator_partition_resource_type_t; @@ -410,17 +411,17 @@ typedef enum { * @cond @tag{gpu_bm_linux} @tag{host} @tag{guest_windows} @endcond */ typedef enum { - AMDSMI_COMPUTE_PARTITION_INVALID = 0, - AMDSMI_COMPUTE_PARTITION_SPX, //!< Single GPU mode (SPX)- All XCCs work - //!< together with shared memory - AMDSMI_COMPUTE_PARTITION_DPX, //!< Dual GPU mode (DPX)- Half XCCs work - //!< together with shared memory - AMDSMI_COMPUTE_PARTITION_TPX, //!< Triple GPU mode (TPX)- One-third XCCs - //!< work together with shared memory - AMDSMI_COMPUTE_PARTITION_QPX, //!< Quad GPU mode (QPX)- Quarter XCCs - //!< work together with shared memory - AMDSMI_COMPUTE_PARTITION_CPX //!< Core mode (CPX)- Per-chip XCC with - //!< shared memory + AMDSMI_COMPUTE_PARTITION_INVALID = 0, //!< Invalid compute partition type + AMDSMI_COMPUTE_PARTITION_SPX, /**< Single GPU mode (SPX)- All XCCs work + together with shared memory */ + AMDSMI_COMPUTE_PARTITION_DPX, /**< Dual GPU mode (DPX)- Half XCCs work + together with shared memory */ + AMDSMI_COMPUTE_PARTITION_TPX, /**< Triple GPU mode (TPX)- One-third XCCs + work together with shared memory */ + AMDSMI_COMPUTE_PARTITION_QPX, /**< Quad GPU mode (QPX)- Quarter XCCs + work together with shared memory */ + AMDSMI_COMPUTE_PARTITION_CPX /**< Core mode (CPX)- Per-chip XCC with + shared memory */ } amdsmi_compute_partition_type_t; /** @@ -430,19 +431,19 @@ typedef enum { */ typedef enum { AMDSMI_MEMORY_PARTITION_UNKNOWN = 0, - AMDSMI_MEMORY_PARTITION_NPS1 = 1, //!< NPS1 - All CCD & XCD data is interleaved - //!< across all 8 HBM stacks (all stacks/1). - AMDSMI_MEMORY_PARTITION_NPS2 = 2, //!< NPS2 - 2 sets of CCDs or 4 XCD interleaved - //!< across the 4 HBM stacks per AID pair - //!< (8 stacks/2). - AMDSMI_MEMORY_PARTITION_NPS4 = 4, //!< NPS4 - Each XCD data is interleaved - //!< across 2 (or single) HBM stacks - //!< (8 stacks/8 or 8 stacks/4). - AMDSMI_MEMORY_PARTITION_NPS8 = 8, //!< NPS8 - Each XCD uses a single HBM stack - //!< (8 stacks/8). Or each XCD uses a single - //!< HBM stack & CCDs share 2 non-interleaved - //!< HBM stacks on its AID - //!< (AID[1,2,3] = 6 stacks/6). + AMDSMI_MEMORY_PARTITION_NPS1 = 1, /**< NPS1 - All CCD & XCD data is interleaved + across all 8 HBM stacks (all stacks/1) */ + AMDSMI_MEMORY_PARTITION_NPS2 = 2, /**< NPS2 - 2 sets of CCDs or 4 XCD interleaved + across the 4 HBM stacks per AID pair + (8 stacks/2) */ + AMDSMI_MEMORY_PARTITION_NPS4 = 4, /**< NPS4 - Each XCD data is interleaved + across 2 (or single) HBM stacks + (8 stacks/8 or 8 stacks/4) */ + AMDSMI_MEMORY_PARTITION_NPS8 = 8, /**< NPS8 - Each XCD uses a single HBM stack + (8 stacks/8). Or each XCD uses a single + HBM stack & CCDs share 2 non-interleaved + HBM stacks on its AID + (AID[1,2,3] = 6 stacks/6) */ } amdsmi_memory_partition_type_t; /** @@ -452,16 +453,16 @@ typedef enum { * @cond @tag{gpu_bm_linux} @tag{host} @tag{guest_windows} @endcond */ typedef enum { - AMDSMI_TEMPERATURE_TYPE_EDGE, + AMDSMI_TEMPERATURE_TYPE_EDGE, //!< Edge temperature AMDSMI_TEMPERATURE_TYPE_FIRST = AMDSMI_TEMPERATURE_TYPE_EDGE, - AMDSMI_TEMPERATURE_TYPE_HOTSPOT, - AMDSMI_TEMPERATURE_TYPE_JUNCTION = AMDSMI_TEMPERATURE_TYPE_HOTSPOT, - AMDSMI_TEMPERATURE_TYPE_VRAM, - AMDSMI_TEMPERATURE_TYPE_HBM_0, - AMDSMI_TEMPERATURE_TYPE_HBM_1, - AMDSMI_TEMPERATURE_TYPE_HBM_2, - AMDSMI_TEMPERATURE_TYPE_HBM_3, - AMDSMI_TEMPERATURE_TYPE_PLX, + AMDSMI_TEMPERATURE_TYPE_HOTSPOT, //!< Hottest temperature reported for entire die + AMDSMI_TEMPERATURE_TYPE_JUNCTION = AMDSMI_TEMPERATURE_TYPE_HOTSPOT, //!< Synonymous with HOTSPOT + AMDSMI_TEMPERATURE_TYPE_VRAM, //!< VRAM temperature on graphics card + AMDSMI_TEMPERATURE_TYPE_HBM_0, //!< High Bandwidth 0 temperature per stack + AMDSMI_TEMPERATURE_TYPE_HBM_1, //!< High Bandwidth 1 temperature per stack + AMDSMI_TEMPERATURE_TYPE_HBM_2, //!< High Bandwidth 2 temperature per stack + AMDSMI_TEMPERATURE_TYPE_HBM_3, //!< High Bandwidth 3 temperature per stack + AMDSMI_TEMPERATURE_TYPE_PLX, //!< PCIe switch temperature AMDSMI_TEMPERATURE_TYPE__MAX = AMDSMI_TEMPERATURE_TYPE_PLX } amdsmi_temperature_type_t; @@ -472,86 +473,87 @@ typedef enum { * @cond @tag{gpu_bm_linux} @tag{guest_windows} @tag{host} @endcond */ typedef enum { - AMDSMI_FW_ID_SMU = 1, + AMDSMI_FW_ID_SMU = 1, /**< System Management Unit (power management, + clock control, thermal monitoring, etc...) */ AMDSMI_FW_ID_FIRST = AMDSMI_FW_ID_SMU, - AMDSMI_FW_ID_CP_CE, - AMDSMI_FW_ID_CP_PFP, - AMDSMI_FW_ID_CP_ME, - AMDSMI_FW_ID_CP_MEC_JT1, - AMDSMI_FW_ID_CP_MEC_JT2, - AMDSMI_FW_ID_CP_MEC1, - AMDSMI_FW_ID_CP_MEC2, - AMDSMI_FW_ID_RLC, - AMDSMI_FW_ID_SDMA0, - AMDSMI_FW_ID_SDMA1, - AMDSMI_FW_ID_SDMA2, - AMDSMI_FW_ID_SDMA3, - AMDSMI_FW_ID_SDMA4, - AMDSMI_FW_ID_SDMA5, - AMDSMI_FW_ID_SDMA6, - AMDSMI_FW_ID_SDMA7, - AMDSMI_FW_ID_VCN, - AMDSMI_FW_ID_UVD, - AMDSMI_FW_ID_VCE, - AMDSMI_FW_ID_ISP, - AMDSMI_FW_ID_DMCU_ERAM, /*eRAM*/ - AMDSMI_FW_ID_DMCU_ISR, /*ISR*/ - AMDSMI_FW_ID_RLC_RESTORE_LIST_GPM_MEM, - AMDSMI_FW_ID_RLC_RESTORE_LIST_SRM_MEM, - AMDSMI_FW_ID_RLC_RESTORE_LIST_CNTL, - AMDSMI_FW_ID_RLC_V, - AMDSMI_FW_ID_MMSCH, - AMDSMI_FW_ID_PSP_SYSDRV, - AMDSMI_FW_ID_PSP_SOSDRV, - AMDSMI_FW_ID_PSP_TOC, - AMDSMI_FW_ID_PSP_KEYDB, - AMDSMI_FW_ID_DFC, - AMDSMI_FW_ID_PSP_SPL, - AMDSMI_FW_ID_DRV_CAP, - AMDSMI_FW_ID_MC, - AMDSMI_FW_ID_PSP_BL, - AMDSMI_FW_ID_CP_PM4, - AMDSMI_FW_ID_RLC_P, - AMDSMI_FW_ID_SEC_POLICY_STAGE2, - AMDSMI_FW_ID_REG_ACCESS_WHITELIST, - AMDSMI_FW_ID_IMU_DRAM, - AMDSMI_FW_ID_IMU_IRAM, - AMDSMI_FW_ID_SDMA_TH0, - AMDSMI_FW_ID_SDMA_TH1, - AMDSMI_FW_ID_CP_MES, - AMDSMI_FW_ID_MES_KIQ, - AMDSMI_FW_ID_MES_STACK, - AMDSMI_FW_ID_MES_THREAD1, - AMDSMI_FW_ID_MES_THREAD1_STACK, - AMDSMI_FW_ID_RLX6, - AMDSMI_FW_ID_RLX6_DRAM_BOOT, - AMDSMI_FW_ID_RS64_ME, - AMDSMI_FW_ID_RS64_ME_P0_DATA, - AMDSMI_FW_ID_RS64_ME_P1_DATA, - AMDSMI_FW_ID_RS64_PFP, - AMDSMI_FW_ID_RS64_PFP_P0_DATA, - AMDSMI_FW_ID_RS64_PFP_P1_DATA, - AMDSMI_FW_ID_RS64_MEC, - AMDSMI_FW_ID_RS64_MEC_P0_DATA, - AMDSMI_FW_ID_RS64_MEC_P1_DATA, - AMDSMI_FW_ID_RS64_MEC_P2_DATA, - AMDSMI_FW_ID_RS64_MEC_P3_DATA, - AMDSMI_FW_ID_PPTABLE, - AMDSMI_FW_ID_PSP_SOC, - AMDSMI_FW_ID_PSP_DBG, - AMDSMI_FW_ID_PSP_INTF, - AMDSMI_FW_ID_RLX6_CORE1, - AMDSMI_FW_ID_RLX6_DRAM_BOOT_CORE1, - AMDSMI_FW_ID_RLCV_LX7, - AMDSMI_FW_ID_RLC_SAVE_RESTORE_LIST, - AMDSMI_FW_ID_ASD, - AMDSMI_FW_ID_TA_RAS, - AMDSMI_FW_ID_TA_XGMI, - AMDSMI_FW_ID_RLC_SRLG, - AMDSMI_FW_ID_RLC_SRLS, - AMDSMI_FW_ID_PM, - AMDSMI_FW_ID_DMCU, - AMDSMI_FW_ID_PLDM, + AMDSMI_FW_ID_CP_CE, //!< Compute Processor - Command_Engine (fetch, decode, dispatch) + AMDSMI_FW_ID_CP_PFP, //!< Compute Processor - Pixel Front End Processor (pixelating process) + AMDSMI_FW_ID_CP_ME, //!< Compute Processor - Micro Engine (specialize processing) + AMDSMI_FW_ID_CP_MEC_JT1, //!< Compute Processor - Micro Engine Controler Job Table 1 (queues, scheduling) + AMDSMI_FW_ID_CP_MEC_JT2, //!< Compute Processor - Micro Engine Controler Job Table 2 (queues, scheduling) + AMDSMI_FW_ID_CP_MEC1, //!< Compute Processor - Micro Engine Controler 1 (scheduling, managing resources) + AMDSMI_FW_ID_CP_MEC2, //!< Compute Processor - Micro Engine Controler 2 (scheduling, managing resources) + AMDSMI_FW_ID_RLC, //!< Rasterizer and L2 Cache (rasterization processs) + AMDSMI_FW_ID_SDMA0, //!< System Direct Memory Access 0 (high speed data transfers) + AMDSMI_FW_ID_SDMA1, //!< System Direct Memory Access 1 (high speed data transfers) + AMDSMI_FW_ID_SDMA2, //!< System Direct Memory Access 2 (high speed data transfers) + AMDSMI_FW_ID_SDMA3, //!< System Direct Memory Access 3 (high speed data transfers) + AMDSMI_FW_ID_SDMA4, //!< System Direct Memory Access 4 (high speed data transfers) + AMDSMI_FW_ID_SDMA5, //!< System Direct Memory Access 5 (high speed data transfers) + AMDSMI_FW_ID_SDMA6, //!< System Direct Memory Access 6 (high speed data transfers) + AMDSMI_FW_ID_SDMA7, //!< System Direct Memory Access 7 (high speed data transfers) + AMDSMI_FW_ID_VCN, //!< Video Core Next (encoding and decoding) + AMDSMI_FW_ID_UVD, //!< Unified Video Decoder (decode specific video formats) + AMDSMI_FW_ID_VCE, //!< Video Coding Engine (Encoding video) + AMDSMI_FW_ID_ISP, //!< Image Signal Processor (processing raw image data from sensors) + AMDSMI_FW_ID_DMCU_ERAM, //!< Digital Micro Controller Unit - Embedded RAM (memory used by DMU) + AMDSMI_FW_ID_DMCU_ISR, //!< Digital Micro Controller Unit - Interrupt Service Routine (interrupt handlers) + AMDSMI_FW_ID_RLC_RESTORE_LIST_GPM_MEM, //!< Rasterizier and L2 Cache Restore List Graphics Processor Memory + AMDSMI_FW_ID_RLC_RESTORE_LIST_SRM_MEM, //!< Rasterizier and L2 Cache Restore List System RAM Memory + AMDSMI_FW_ID_RLC_RESTORE_LIST_CNTL, //!< Rasterizier and L2 Cache Restore List Control + AMDSMI_FW_ID_RLC_V, //!< Rasterizier and L2 Cache Virtual memory + AMDSMI_FW_ID_MMSCH, //!< Multi-Media Shader Hardware Scheduler + AMDSMI_FW_ID_PSP_SYSDRV, //!< Platform Security Processor System Driver + AMDSMI_FW_ID_PSP_SOSDRV, //!< Platform Security Processor Secure Operating System Driver + AMDSMI_FW_ID_PSP_TOC, //!< Platform Security Processor Table of Contents + AMDSMI_FW_ID_PSP_KEYDB, //!< Platform Security Processor Table of Contents + AMDSMI_FW_ID_DFC, //!< Data Fabric Controler (bandwidth and coherency) + AMDSMI_FW_ID_PSP_SPL, //!< Platform Security Processor Secure Program Loader + AMDSMI_FW_ID_DRV_CAP, //!< Driver Capabilities (capabilities, features) + AMDSMI_FW_ID_MC, //!< Memory Contoller (RAM and VRAM) + AMDSMI_FW_ID_PSP_BL, //!< Platform Security Processor Bootloader (initial firmware) + AMDSMI_FW_ID_CP_PM4, //!< Compute Processor Packet Processor 4 (processing command packets) + AMDSMI_FW_ID_RLC_P, //!< Rasterizier and L2 Cache Partition + AMDSMI_FW_ID_SEC_POLICY_STAGE2, //!< Security Policy Stage 2 (security features) + AMDSMI_FW_ID_REG_ACCESS_WHITELIST, //!< Register Access Whitelist (Prevent unathorizied access) + AMDSMI_FW_ID_IMU_DRAM, //!< Input/Output Memory Management Unit - Dynamic RAM + AMDSMI_FW_ID_IMU_IRAM, //!< Input/Output Memory Management Unit - Instruction RAM + AMDSMI_FW_ID_SDMA_TH0, //!< System Direct Memory Access - Thread Handler 0 + AMDSMI_FW_ID_SDMA_TH1, //!< System Direct Memory Access - Thread Handler 0 + AMDSMI_FW_ID_CP_MES, //!< Compute Processor - Micro Engine Scheduler + AMDSMI_FW_ID_MES_KIQ, //!< Micro Engine Scheduler - Kernel Indirect Queue + AMDSMI_FW_ID_MES_STACK, //!< Micro Engine Scheduler - Stack + AMDSMI_FW_ID_MES_THREAD1, //!< Micro Engine Scheduler - Thread 1 + AMDSMI_FW_ID_MES_THREAD1_STACK, //!< Micro Engine Scheduler - Thread 1 Stack + AMDSMI_FW_ID_RLX6, //!< Hardware Block RLX6 + AMDSMI_FW_ID_RLX6_DRAM_BOOT, //!< Hardware Block RLX6 - Dynamic Ram Boot + AMDSMI_FW_ID_RS64_ME, //!< Hardware Block RS64 - Micro Engine + AMDSMI_FW_ID_RS64_ME_P0_DATA, //!< Hardware Block RS64 - Micro Engine Partition 0 Data + AMDSMI_FW_ID_RS64_ME_P1_DATA, //!< Hardware Block RS64 - Micro Engine Partition 1 Data + AMDSMI_FW_ID_RS64_PFP, //!< Hardware Block RS64 - Pixel Front End Processor + AMDSMI_FW_ID_RS64_PFP_P0_DATA, //!< Hardware Block RS64 - Pixel Front End Processor Partition 0 Data + AMDSMI_FW_ID_RS64_PFP_P1_DATA, //!< Hardware Block RS64 - Pixel Front End Processor Partition 1 Data + AMDSMI_FW_ID_RS64_MEC, //!< Hardware Block RS64 - Micro Engine Controller + AMDSMI_FW_ID_RS64_MEC_P0_DATA, //!< Hardware Block RS64 - Micro Engine Controller Partition 0 Data + AMDSMI_FW_ID_RS64_MEC_P1_DATA, //!< Hardware Block RS64 - Micro Engine Controller Partition 1 Data + AMDSMI_FW_ID_RS64_MEC_P2_DATA, //!< Hardware Block RS64 - Micro Engine Controller Partition 2 Data + AMDSMI_FW_ID_RS64_MEC_P3_DATA, //!< Hardware Block RS64 - Micro Engine Controller Partition 3 Data + AMDSMI_FW_ID_PPTABLE, //!< Power Policy Table (power management policies) + AMDSMI_FW_ID_PSP_SOC, //!< Platform Security Processor - System On a Chip + AMDSMI_FW_ID_PSP_DBG, //!< Platform Security Processor - Debug + AMDSMI_FW_ID_PSP_INTF, //!< Platform Security Processor - Interface + AMDSMI_FW_ID_RLX6_CORE1, //!< Hardware Block RLX6 - Core 1 + AMDSMI_FW_ID_RLX6_DRAM_BOOT_CORE1, //!< Hardware Block RLX6 Core 1 - Dynamic RAM Boot + AMDSMI_FW_ID_RLCV_LX7, //!< Hardware Block RLCV - Subsystem LX7 + AMDSMI_FW_ID_RLC_SAVE_RESTORE_LIST, //!< Rasterizier and L2 Cache - Save Restore List + AMDSMI_FW_ID_ASD, //!< Asynchronous Shader Dispatcher + AMDSMI_FW_ID_TA_RAS, //!< Trusted Applications - Reliablity Availability and Serviceability + AMDSMI_FW_ID_TA_XGMI, //!< Trusted Applications - Reliablity XGMI + AMDSMI_FW_ID_RLC_SRLG, //!< Rasterizier and L2 Cache - Shared Resource Local Group + AMDSMI_FW_ID_RLC_SRLS, //!< Rasterizier and L2 Cache - Shared Resource Local Segment + AMDSMI_FW_ID_PM, //!< Power Management Firmware + AMDSMI_FW_ID_DMCU, //!< Display Micro-Controller Unit + AMDSMI_FW_ID_PLDM, //!< Platform Level Data Model AMDSMI_FW_ID__MAX } amdsmi_fw_block_t; @@ -561,24 +563,24 @@ typedef enum { * @cond @tag{gpu_bm_linux} @tag{host} @endcond */ typedef enum { - AMDSMI_VRAM_TYPE_UNKNOWN = 0, + AMDSMI_VRAM_TYPE_UNKNOWN = 0, //!< Unknown memory type // HBM - AMDSMI_VRAM_TYPE_HBM = 1, - AMDSMI_VRAM_TYPE_HBM2 = 2, - AMDSMI_VRAM_TYPE_HBM2E = 3, - AMDSMI_VRAM_TYPE_HBM3 = 4, + AMDSMI_VRAM_TYPE_HBM = 1, //!< High Bandwidth Memory + AMDSMI_VRAM_TYPE_HBM2 = 2, //!< High Bandwidth Memory, Generation 2 + AMDSMI_VRAM_TYPE_HBM2E = 3, //!< High Bandwidth Memory, Generation 2 Enhanced + AMDSMI_VRAM_TYPE_HBM3 = 4, //!< High Bandwidth Memory, Generation 3 // DDR - AMDSMI_VRAM_TYPE_DDR2 = 10, - AMDSMI_VRAM_TYPE_DDR3 = 11, - AMDSMI_VRAM_TYPE_DDR4 = 12, + AMDSMI_VRAM_TYPE_DDR2 = 10, //!< Double Data Rate, Generation 2 + AMDSMI_VRAM_TYPE_DDR3 = 11, //!< Double Data Rate, Generation 3 + AMDSMI_VRAM_TYPE_DDR4 = 12, //!< Double Data Rate, Generation 4 // GDDR - AMDSMI_VRAM_TYPE_GDDR1 = 17, - AMDSMI_VRAM_TYPE_GDDR2 = 18, - AMDSMI_VRAM_TYPE_GDDR3 = 19, - AMDSMI_VRAM_TYPE_GDDR4 = 20, - AMDSMI_VRAM_TYPE_GDDR5 = 21, - AMDSMI_VRAM_TYPE_GDDR6 = 22, - AMDSMI_VRAM_TYPE_GDDR7 = 23, + AMDSMI_VRAM_TYPE_GDDR1 = 17, //!< Graphics Double Data Rate, Generation 1 + AMDSMI_VRAM_TYPE_GDDR2 = 18, //!< Graphics Double Data Rate, Generation 2 + AMDSMI_VRAM_TYPE_GDDR3 = 19, //!< Graphics Double Data Rate, Generation 3 + AMDSMI_VRAM_TYPE_GDDR4 = 20, //!< Graphics Double Data Rate, Generation 4 + AMDSMI_VRAM_TYPE_GDDR5 = 21, //!< Graphics Double Data Rate, Generation 5 + AMDSMI_VRAM_TYPE_GDDR6 = 22, //!< Graphics Double Data Rate, Generation 6 + AMDSMI_VRAM_TYPE_GDDR7 = 23, //!< Graphics Double Data Rate, Generation 7 AMDSMI_VRAM_TYPE__MAX = AMDSMI_VRAM_TYPE_GDDR7 } amdsmi_vram_type_t; @@ -708,11 +710,11 @@ typedef union { * @cond @tag{gpu_bm_linux} @tag{guest_windows} @tag{guest_1vf} @tag{guest_mvf} @endcond */ typedef struct { - uint32_t drm_render; // the render node under /sys/class/drm/renderD* - uint32_t drm_card; // the graphic card device under /sys/class/drm/card* - uint32_t hsa_id; // the HSA enumeration ID - uint32_t hip_id; // the HIP enumeration ID - char hip_uuid[AMDSMI_MAX_STRING_LENGTH]; // the HIP unique identifer + uint32_t drm_render; //!< the render node under /sys/class/drm/renderD* + uint32_t drm_card; //!< the graphic card device under /sys/class/drm/card* + uint32_t hsa_id; //!< the HSA enumeration ID + uint32_t hip_id; //!< the HIP enumeration ID + char hip_uuid[AMDSMI_MAX_STRING_LENGTH]; //!< the HIP unique identifer } amdsmi_enumeration_info_t; /** @@ -721,10 +723,10 @@ typedef struct { * @cond @tag{gpu_bm_linux} @tag{host} @endcond */ typedef enum { - AMDSMI_CARD_FORM_FACTOR_PCIE, - AMDSMI_CARD_FORM_FACTOR_OAM, - AMDSMI_CARD_FORM_FACTOR_CEM, - AMDSMI_CARD_FORM_FACTOR_UNKNOWN + AMDSMI_CARD_FORM_FACTOR_PCIE, //!< PCIE card form factor + AMDSMI_CARD_FORM_FACTOR_OAM, //!< OAM form factor + AMDSMI_CARD_FORM_FACTOR_CEM, //!< CEM form factor + AMDSMI_CARD_FORM_FACTOR_UNKNOWN //!< Unknown Form factor } amdsmi_card_form_factor_t; /** @@ -789,11 +791,11 @@ typedef struct { * @cond @tag{gpu_bm_linux} @tag{host} @endcond */ typedef enum { - AMDSMI_CACHE_PROPERTY_ENABLED = 0x00000001, - AMDSMI_CACHE_PROPERTY_DATA_CACHE = 0x00000002, - AMDSMI_CACHE_PROPERTY_INST_CACHE = 0x00000004, - AMDSMI_CACHE_PROPERTY_CPU_CACHE = 0x00000008, - AMDSMI_CACHE_PROPERTY_SIMD_CACHE = 0x00000010, + AMDSMI_CACHE_PROPERTY_ENABLED = 0x00000001, //!< Cache enabled + AMDSMI_CACHE_PROPERTY_DATA_CACHE = 0x00000002, //!< Data cache + AMDSMI_CACHE_PROPERTY_INST_CACHE = 0x00000004, //!< Instruction cache + AMDSMI_CACHE_PROPERTY_CPU_CACHE = 0x00000008, //!< CPU cache + AMDSMI_CACHE_PROPERTY_SIMD_CACHE = 0x00000010 //!< Single Instruction, Multiple Data Cache } amdsmi_cache_property_type_t; /** @@ -855,9 +857,9 @@ typedef struct { * @cond @tag{gpu_bm_linux} @tag{guest_windows} @endcond */ typedef struct { - uint64_t kfd_id; //< 0xFFFFFFFFFFFFFFFF if not supported - uint32_t node_id; //< 0xFFFFFFFF if not supported - uint32_t current_partition_id; //< 0xFFFFFFFF if not supported + uint64_t kfd_id; //!< 0xFFFFFFFFFFFFFFFF if not supported + uint32_t node_id; //!< 0xFFFFFFFF if not supported + uint32_t current_partition_id; //!< 0xFFFFFFFF if not supported uint32_t reserved[12]; } amdsmi_kfd_info_t; @@ -944,11 +946,11 @@ typedef struct { * @cond @tag{gpu_bm_linux} @tag{host} @endcond */ typedef enum { - AMDSMI_LINK_TYPE_INTERNAL, - AMDSMI_LINK_TYPE_XGMI, - AMDSMI_LINK_TYPE_PCIE, - AMDSMI_LINK_TYPE_NOT_APPLICABLE, - AMDSMI_LINK_TYPE_UNKNOWN + AMDSMI_LINK_TYPE_INTERNAL, //!< Internal Link Type, within chip + AMDSMI_LINK_TYPE_XGMI, //!< GPU Memory Interconnect (multi GPU communication) + AMDSMI_LINK_TYPE_PCIE, //!< Peripheral Component Interconnect Express Link Type + AMDSMI_LINK_TYPE_NOT_APPLICABLE, //!< Not Applicatble Link Type + AMDSMI_LINK_TYPE_UNKNOWN //!< Unknown Link Type } amdsmi_link_type_t; /** @@ -1135,8 +1137,8 @@ typedef enum { AMDSMI_DEV_PERF_LEVEL_FIRST = AMDSMI_DEV_PERF_LEVEL_AUTO, AMDSMI_DEV_PERF_LEVEL_LOW, //!< Keep PowerPlay levels "low", regardless of workload AMDSMI_DEV_PERF_LEVEL_HIGH, //!< Keep PowerPlay levels "high", regardless of workload - AMDSMI_DEV_PERF_LEVEL_MANUAL, //!< Only use values defined by manually - //!< setting the AMDSMI_CLK_TYPE_SYS speed + AMDSMI_DEV_PERF_LEVEL_MANUAL, /**< Only use values defined by manually + setting the AMDSMI_CLK_TYPE_SYS speed */ AMDSMI_DEV_PERF_LEVEL_STABLE_STD, //!< Stable power state with profiling clocks AMDSMI_DEV_PERF_LEVEL_STABLE_PEAK, //!< Stable power state with peak clocks AMDSMI_DEV_PERF_LEVEL_STABLE_MIN_MCLK, //!< Stable power state with minimum memory clock @@ -1161,9 +1163,9 @@ typedef uintptr_t amdsmi_event_handle_t; * @cond @tag{gpu_bm_linux} @endcond */ typedef enum { - AMDSMI_EVNT_GRP_XGMI = 0, //!< Data Fabric (XGMI) related events + AMDSMI_EVNT_GRP_XGMI = 0, //!< Data Fabric (XGMI) related events AMDSMI_EVNT_GRP_XGMI_DATA_OUT = 10, //!< XGMI Outbound data - AMDSMI_EVNT_GRP_INVALID = 0xFFFFFFFF + AMDSMI_EVNT_GRP_INVALID = 0xFFFFFFFF //!< Unknown Event Group } amdsmi_event_group_t; /** @@ -1210,14 +1212,14 @@ typedef enum { AMDSMI_EVNT_XGMI_1_BEATS_TX, //!< Data beats sent to neighbor 1; Each beat represents 32 bytes AMDSMI_EVNT_XGMI_LAST = AMDSMI_EVNT_XGMI_1_BEATS_TX, AMDSMI_EVNT_XGMI_DATA_OUT_FIRST = AMDSMI_EVNT_GRP_XGMI_DATA_OUT, - AMDSMI_EVNT_XGMI_DATA_OUT_0 = AMDSMI_EVNT_XGMI_DATA_OUT_FIRST, - AMDSMI_EVNT_XGMI_DATA_OUT_1, //!< Outbound beats to neighbor 1 - AMDSMI_EVNT_XGMI_DATA_OUT_2, //!< Outbound beats to neighbor 2 - AMDSMI_EVNT_XGMI_DATA_OUT_3, //!< Outbound beats to neighbor 3 - AMDSMI_EVNT_XGMI_DATA_OUT_4, //!< Outbound beats to neighbor 4 - AMDSMI_EVNT_XGMI_DATA_OUT_5, //!< Outbound beats to neighbor 5 + AMDSMI_EVNT_XGMI_DATA_OUT_0 = AMDSMI_EVNT_XGMI_DATA_OUT_FIRST, //!< Outbound beats to neighbor 0 + AMDSMI_EVNT_XGMI_DATA_OUT_1, //!< Outbound beats to neighbor 1 + AMDSMI_EVNT_XGMI_DATA_OUT_2, //!< Outbound beats to neighbor 2 + AMDSMI_EVNT_XGMI_DATA_OUT_3, //!< Outbound beats to neighbor 3 + AMDSMI_EVNT_XGMI_DATA_OUT_4, //!< Outbound beats to neighbor 4 + AMDSMI_EVNT_XGMI_DATA_OUT_5, //!< Outbound beats to neighbor 5 AMDSMI_EVNT_XGMI_DATA_OUT_LAST = AMDSMI_EVNT_XGMI_DATA_OUT_5, - AMDSMI_EVNT_LAST = AMDSMI_EVNT_XGMI_DATA_OUT_LAST, + AMDSMI_EVNT_LAST = AMDSMI_EVNT_XGMI_DATA_OUT_LAST } amdsmi_event_type_t; /** @@ -1227,8 +1229,8 @@ typedef enum { */ typedef enum { AMDSMI_CNTR_CMD_START = 0, //!< Start the counter - AMDSMI_CNTR_CMD_STOP, //!< Stop the counter; note that this should not - //!< be used before reading. + AMDSMI_CNTR_CMD_STOP, /**< Stop the counter; note that this should not + be used before reading */ } amdsmi_counter_command_t; /** @@ -1248,8 +1250,8 @@ typedef struct { * @cond @tag{gpu_bm_linux} @endcond */ typedef enum { - AMDSMI_EVT_NOTIF_NONE = 0, //!< Not used - AMDSMI_EVT_NOTIF_VMFAULT = 1, //!< VM page fault + AMDSMI_EVT_NOTIF_NONE = 0, //!< No events + AMDSMI_EVT_NOTIF_VMFAULT = 1, //!< Virtual Memory Page Fault Event AMDSMI_EVT_NOTIF_FIRST = AMDSMI_EVT_NOTIF_VMFAULT, AMDSMI_EVT_NOTIF_THERMAL_THROTTLE = 2, //!< thermal throttle AMDSMI_EVT_NOTIF_GPU_PRE_RESET = 3, //!< pre-reset @@ -1293,40 +1295,34 @@ typedef struct { * @cond @tag{gpu_bm_linux} @tag{host} @endcond */ typedef enum { - AMDSMI_TEMP_CURRENT = 0x0, //!< Temperature current value. + AMDSMI_TEMP_CURRENT = 0x0, //!< Current temperature AMDSMI_TEMP_FIRST = AMDSMI_TEMP_CURRENT, - AMDSMI_TEMP_MAX, //!< Temperature max value. - AMDSMI_TEMP_MIN, //!< Temperature min value. - AMDSMI_TEMP_MAX_HYST, //!< Temperature hysteresis value for max limit. - //!< (This is an absolute temperature, not a - //!< delta). - AMDSMI_TEMP_MIN_HYST, //!< Temperature hysteresis value for min limit. - //!< (This is an absolute temperature, - //!< not a delta). - AMDSMI_TEMP_CRITICAL, //!< Temperature critical max value, typically - //!< greater than corresponding temp_max values. - AMDSMI_TEMP_CRITICAL_HYST, //!< Temperature hysteresis value for critical - //!< limit. (This is an absolute temperature, - //!< not a delta). - AMDSMI_TEMP_EMERGENCY, //!< Temperature emergency max value, for chips - //!< supporting more than two upper temperature - //!< limits. Must be equal or greater than - //!< corresponding temp_crit values. - AMDSMI_TEMP_EMERGENCY_HYST, //!< Temperature hysteresis value for emergency - //!< limit. (This is an absolute temperature, - //!< not a delta). - AMDSMI_TEMP_CRIT_MIN, //!< Temperature critical min value, typically - //!< lower than corresponding temperature - //!< minimum values. - AMDSMI_TEMP_CRIT_MIN_HYST, //!< Temperature hysteresis value for critical - //!< minimum limit. (This is an absolute - //!< temperature, not a delta). - AMDSMI_TEMP_OFFSET, //!< Temperature offset which is added to the - //!< temperature reading by the chip. - AMDSMI_TEMP_LOWEST, //!< Historical minimum temperature. - AMDSMI_TEMP_HIGHEST, //!< Historical maximum temperature. - AMDSMI_TEMP_SHUTDOWN, //!< Shutdown temperature. + AMDSMI_TEMP_MAX, //!< Max temperature + AMDSMI_TEMP_MIN, //!< Min temperature + AMDSMI_TEMP_MAX_HYST, /**< Max limit hysteresis temperature + (Absolute temperature, not a delta) */ + AMDSMI_TEMP_MIN_HYST, /**< Min limit hysteresis temperature + (Absolute temperature, not a delta) */ + AMDSMI_TEMP_CRITICAL, /**< Critical max limit temperature, typically + greater than max temperatures */ + AMDSMI_TEMP_CRITICAL_HYST, /**< Critical hysteresis limit temperature + (Absolute temperature, not a delta) */ + AMDSMI_TEMP_EMERGENCY, /**< Emergency max temperature, for chips + supporting more than two upper temperature + limits. Must be equal or greater than + corresponding temp_crit values */ + AMDSMI_TEMP_EMERGENCY_HYST, /**< Emergency hysteresis limit temperature + (Absolute temperature, not a delta) */ + AMDSMI_TEMP_CRIT_MIN, /**< Critical min temperature, typically + lower than minimum temperatures */ + AMDSMI_TEMP_CRIT_MIN_HYST, /**< Min Hysteresis critical limit temperature + (Absolute temperature, not a delta) */ + AMDSMI_TEMP_OFFSET, /**< Temperature offset which is added to the + temperature reading by the chip */ + AMDSMI_TEMP_LOWEST, //!< Historical min temperature + AMDSMI_TEMP_HIGHEST, //!< Historical max temperature + AMDSMI_TEMP_SHUTDOWN, //!< Shutdown temperature AMDSMI_TEMP_LAST = AMDSMI_TEMP_SHUTDOWN } amdsmi_temperature_metric_t; @@ -1337,16 +1333,16 @@ typedef enum { * @cond @tag{gpu_bm_linux} @endcond */ typedef enum { - AMDSMI_VOLT_CURRENT = 0x0, //!< Voltage current value. + AMDSMI_VOLT_CURRENT = 0x0, //!< Voltage current value. AMDSMI_VOLT_FIRST = AMDSMI_VOLT_CURRENT, - AMDSMI_VOLT_MAX, //!< Voltage max value. - AMDSMI_VOLT_MIN_CRIT, //!< Voltage critical min value. - AMDSMI_VOLT_MIN, //!< Voltage min value. - AMDSMI_VOLT_MAX_CRIT, //!< Voltage critical max value. - AMDSMI_VOLT_AVERAGE, //!< Average voltage. - AMDSMI_VOLT_LOWEST, //!< Historical minimum voltage. - AMDSMI_VOLT_HIGHEST, //!< Historical maximum voltage. + AMDSMI_VOLT_MAX, //!< Voltage max value. + AMDSMI_VOLT_MIN_CRIT, //!< Voltage critical min value. + AMDSMI_VOLT_MIN, //!< Voltage min value. + AMDSMI_VOLT_MAX_CRIT, //!< Voltage critical max value. + AMDSMI_VOLT_AVERAGE, //!< Average voltage. + AMDSMI_VOLT_LOWEST, //!< Historical minimum voltage. + AMDSMI_VOLT_HIGHEST, //!< Historical maximum voltage. AMDSMI_VOLT_LAST = AMDSMI_VOLT_HIGHEST } amdsmi_voltage_metric_t; @@ -1381,13 +1377,13 @@ typedef enum { AMDSMI_PWR_PROF_PRST_COMPUTE_MASK = 0x8, //!< Compute Saving Profile AMDSMI_PWR_PROF_PRST_VR_MASK = 0x10, //!< VR Power Profile - //!< 3D Full Screen Power Profile - AMDSMI_PWR_PROF_PRST_3D_FULL_SCR_MASK = 0x20, + // 3D Full Screen Power Profile + AMDSMI_PWR_PROF_PRST_3D_FULL_SCR_MASK = 0x20, //!< 3D Full Screen Profile AMDSMI_PWR_PROF_PRST_BOOTUP_DEFAULT = 0x40, //!< Default Boot Up Profile AMDSMI_PWR_PROF_PRST_LAST = AMDSMI_PWR_PROF_PRST_BOOTUP_DEFAULT, - //!< Invalid power profile - AMDSMI_PWR_PROF_PRST_INVALID = 0xFFFFFFFFFFFFFFFF + // Invalid power profile + AMDSMI_PWR_PROF_PRST_INVALID = 0xFFFFFFFFFFFFFFFF //!< Invalid Power Profile } amdsmi_power_profile_preset_masks_t; /** @@ -1427,8 +1423,8 @@ typedef enum { * @cond @tag{gpu_bm_linux} @endcond */ typedef enum { - CLK_LIMIT_MIN, //!< Clock values in MHz - CLK_LIMIT_MAX //!< Clock values in MHz + CLK_LIMIT_MIN, //!< Min Clock value in MHz + CLK_LIMIT_MAX //!< Max Clock value in MHz } amdsmi_clk_limit_type_t; /** @@ -1437,11 +1433,11 @@ typedef enum { * @cond @tag{gpu_bm_linux} @tag{host} @endcond */ typedef enum { - AMDSMI_CPER_SEV_NON_FATAL_UNCORRECTED = 0, - AMDSMI_CPER_SEV_FATAL = 1, - AMDSMI_CPER_SEV_NON_FATAL_CORRECTED = 2, - AMDSMI_CPER_SEV_NUM = 3, - AMDSMI_CPER_SEV_UNUSED = 10, + AMDSMI_CPER_SEV_NON_FATAL_UNCORRECTED = 0, //!< CPER Non-Fatal Uncorrected severity + AMDSMI_CPER_SEV_FATAL = 1, //!< CPER Fatal severity + AMDSMI_CPER_SEV_NON_FATAL_CORRECTED = 2, //!< CPER Non-Fatal Corrected severity + AMDSMI_CPER_SEV_NUM = 3, //!< CPER severity Number + AMDSMI_CPER_SEV_UNUSED = 10 //!< CPER Unused severity } amdsmi_cper_sev_t; /** @@ -1450,18 +1446,18 @@ typedef enum { * @cond @tag{gpu_bm_linux} @endcond */ typedef enum { - AMDSMI_CPER_NOTIFY_TYPE_CMC = 0x450eBDD72DCE8BB1, - AMDSMI_CPER_NOTIFY_TYPE_CPE = 0x4a55D8434E292F96, - AMDSMI_CPER_NOTIFY_TYPE_MCE = 0x4cc5919CE8F56FFE, - AMDSMI_CPER_NOTIFY_TYPE_PCIE = 0x4dfc1A16CF93C01F, - AMDSMI_CPER_NOTIFY_TYPE_INIT = 0x454a9308CC5263E8, - AMDSMI_CPER_NOTIFY_TYPE_NMI = 0x42c9B7E65BAD89FF, - AMDSMI_CPER_NOTIFY_TYPE_BOOT = 0x409aAB403D61A466, - AMDSMI_CPER_NOTIFY_TYPE_DMAR = 0x4c27C6B3667DD791, - AMDSMI_CPER_NOTIFY_TYPE_SEA = 0x11E4BBE89A78788A, - AMDSMI_CPER_NOTIFY_TYPE_SEI = 0x4E87B0AE5C284C81, - AMDSMI_CPER_NOTIFY_TYPE_PEI = 0x4214520409A9D5AC, - AMDSMI_CPER_NOTIFY_TYPE_CXL_COMPONENT = 0x49A341DF69293BC9, + AMDSMI_CPER_NOTIFY_TYPE_CMC = 0x450eBDD72DCE8BB1, //!< Corrected Memory Check + AMDSMI_CPER_NOTIFY_TYPE_CPE = 0x4a55D8434E292F96, //!< Corrected Platform Error + AMDSMI_CPER_NOTIFY_TYPE_MCE = 0x4cc5919CE8F56FFE, //!< Machine Check Exception + AMDSMI_CPER_NOTIFY_TYPE_PCIE = 0x4dfc1A16CF93C01F, //!< PCI Express Error + AMDSMI_CPER_NOTIFY_TYPE_INIT = 0x454a9308CC5263E8, //!< Initialization Error + AMDSMI_CPER_NOTIFY_TYPE_NMI = 0x42c9B7E65BAD89FF, //!< Non_Maskable Interrupt + AMDSMI_CPER_NOTIFY_TYPE_BOOT = 0x409aAB403D61A466, //!< Boot Error + AMDSMI_CPER_NOTIFY_TYPE_DMAR = 0x4c27C6B3667DD791, //!< Direct Memory Access Remapping Error + AMDSMI_CPER_NOTIFY_TYPE_SEA = 0x11E4BBE89A78788A, //!< System Error Architecture + AMDSMI_CPER_NOTIFY_TYPE_SEI = 0x4E87B0AE5C284C81, //!< System Error Interface + AMDSMI_CPER_NOTIFY_TYPE_PEI = 0x4214520409A9D5AC, //!< Platform Error Interface + AMDSMI_CPER_NOTIFY_TYPE_CXL_COMPONENT = 0x49A341DF69293BC9 //!< Compute Express Link Component Error } amdsmi_cper_notify_type_t; /** @@ -1475,8 +1471,8 @@ typedef enum { AMDSMI_RAS_ERR_STATE_PARITY, //!< ECC errors present, but type unknown AMDSMI_RAS_ERR_STATE_SING_C, //!< Single correctable error AMDSMI_RAS_ERR_STATE_MULT_UC, //!< Multiple uncorrectable errors - AMDSMI_RAS_ERR_STATE_POISON, //!< Firmware detected error and isolated - //!< page. Treat as uncorrectable. + AMDSMI_RAS_ERR_STATE_POISON, /**< Firmware detected error and isolated + page. Treat as uncorrectable */ AMDSMI_RAS_ERR_STATE_ENABLED, //!< ECC is enabled AMDSMI_RAS_ERR_STATE_LAST = AMDSMI_RAS_ERR_STATE_ENABLED, @@ -1515,9 +1511,9 @@ typedef enum { * @cond @tag{gpu_bm_linux} @endcond */ typedef enum { - AMDSMI_XGMI_STATUS_NO_ERRORS = 0, - AMDSMI_XGMI_STATUS_ERROR, - AMDSMI_XGMI_STATUS_MULTIPLE_ERRORS, + AMDSMI_XGMI_STATUS_NO_ERRORS = 0, //!< XGMI No Errors + AMDSMI_XGMI_STATUS_ERROR, //!< XGMI Errors + AMDSMI_XGMI_STATUS_MULTIPLE_ERRORS //!< XGMI Multiple Errors } amdsmi_xgmi_status_t; /** @@ -1534,8 +1530,8 @@ typedef uint64_t amdsmi_bit_field_t; */ typedef enum { AMDSMI_MEM_PAGE_STATUS_RESERVED = 0, //!< Reserved. This gpu page is reserved and not available for use - AMDSMI_MEM_PAGE_STATUS_PENDING, //!< Pending. This gpu page is marked as bad and will be marked - //!< reserved at the next window. + AMDSMI_MEM_PAGE_STATUS_PENDING, /**< Pending. This gpu page is marked as bad and will be marked + reserved at the next window */ AMDSMI_MEM_PAGE_STATUS_UNRESERVABLE //!< Unable to reserve this page } amdsmi_memory_page_status_t; @@ -1546,20 +1542,15 @@ typedef enum { */ typedef enum { AMDSMI_UTILIZATION_COUNTER_FIRST = 0, - //! Corse grain activity counters - AMDSMI_COARSE_GRAIN_GFX_ACTIVITY = AMDSMI_UTILIZATION_COUNTER_FIRST, - AMDSMI_COARSE_GRAIN_MEM_ACTIVITY, //!< Memory Activity - AMDSMI_COARSE_DECODER_ACTIVITY, //!< Decoder Activity - //! Fine grain activity counters - AMDSMI_FINE_GRAIN_GFX_ACTIVITY = 100, - AMDSMI_FINE_GRAIN_MEM_ACTIVITY = 101, - AMDSMI_FINE_DECODER_ACTIVITY = 102, + // Course grain activity counters + AMDSMI_COARSE_GRAIN_GFX_ACTIVITY = AMDSMI_UTILIZATION_COUNTER_FIRST, //!< Course Grain Graphic Activity + AMDSMI_COARSE_GRAIN_MEM_ACTIVITY, //!< Course Grain Memory Activity + AMDSMI_COARSE_DECODER_ACTIVITY, //!< Course Grain Decoder Activity + // Fine grain activity counters + AMDSMI_FINE_GRAIN_GFX_ACTIVITY = 100, //!< Fine Grain Graphic Activity + AMDSMI_FINE_GRAIN_MEM_ACTIVITY = 101, //!< Fine Grain Memory Activity + AMDSMI_FINE_DECODER_ACTIVITY = 102, //!< Fine Grain Decoder Activity AMDSMI_UTILIZATION_COUNTER_LAST = AMDSMI_FINE_DECODER_ACTIVITY -/** - * @brief The utilization counter type - * - * @cond @tag{gpu_bm_linux} @endcond - */ } amdsmi_utilization_counter_type_t; #define AMDSMI_MAX_UTILIZATION_VALUES 4 //!< The max number of values per counter type @@ -1597,9 +1588,9 @@ typedef struct { * @cond @tag{gpu_bm_linux} @endcond */ typedef struct { - amdsmi_bit_field_t available_profiles; //