EXWHTEC-262 - Implement tests for increment/decrement atomic operations #395

Change-Id: I4d3ff4beb9385abdebf59e3eac8783a5c625fdac


[ROCm/hip-tests commit: 8f244479cf]

projects/hip-tests/catch/unit/atomics/CMakeLists.txt

@@ -44,6 +44,8 @@ set(TEST_SRC
     safeAtomicAdd.cc
     atomicSub.cc
     atomicSub_system.cc
+    atomicInc.cc
+    atomicDec.cc
     atomicExch.cc
     atomicExch_system.cc
     __hip_atomic_fetch_and.cc
@@ -111,6 +113,15 @@ add_test(NAME Unit_atomicSub_Negative_Parameters
          COMMAND python3 ${CMAKE_CURRENT_SOURCE_DIR}/../compileAndCaptureOutput.py
          ${CMAKE_CURRENT_SOURCE_DIR} ${HIP_PLATFORM} ${HIP_PATH}
          atomicSub_negative_kernels.cc 48)
+add_test(NAME Unit_atomicInc_Negative_Parameters
+         COMMAND python3 ${CMAKE_CURRENT_SOURCE_DIR}/../compileAndCaptureOutput.py
+         ${CMAKE_CURRENT_SOURCE_DIR} ${HIP_PLATFORM} ${HIP_PATH}
+         atomicInc_negative_kernels.cc 8)
+
+add_test(NAME Unit_atomicDec_Negative_Parameters
+         COMMAND python3 ${CMAKE_CURRENT_SOURCE_DIR}/../compileAndCaptureOutput.py
+         ${CMAKE_CURRENT_SOURCE_DIR} ${HIP_PLATFORM} ${HIP_PATH}
+         atomicDec_negative_kernels.cc 8)
 
 # SWDEV-435667: Below 2 tests failed in stress test on 01/12/23
 #add_test(NAME Unit_atomicExch_Negative_Parameters

projects/hip-tests/catch/unit/atomics/atomicDec.cc

@@ -0,0 +1,164 @@
+/*
+Copyright (c) 2023 Advanced Micro Devices, Inc. All rights reserved.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+*/
+
+#include "arithmetic_common.hh"
+#include "atomicDec_negative_kernels_rtc.hh"
+
+#include <hip_test_common.hh>
+
+/**
+ * @addtogroup atomicDec atomicDec
+ * @{
+ * @ingroup AtomicsTest
+ */
+
+/**
+ * Test Description
+ * ------------------------
+ *    - Executes a single kernel on a single device wherein all threads will perform an atomic
+ * decrement on a target memory location. Each thread will decrement the memory location,
+ * storing the return value into a separate output array slot corresponding to it. Once complete,
+ * the output array and target memory is validated to contain all the expected values. Several
+ * memory access patterns are tested:
+ *      -# All threads decrement a single, compile time deducible, memory location
+ *      -# Each thread targets an array containing warp_size elements, using tid % warp_size
+ *         for indexing
+ *      -# Same as the above, but the elements are spread out by L1 cache line size bytes.
+ *
+ *    - The test is run for:
+ *      - All overloads of atomicDec
+ *      - hipMalloc, hipMallocManaged, hipHostMalloc and hipHostRegister allocated memory
+ *      - Shared memory
+ *      - Several grid and block dimension combinations (only one block is used for shared memory).
+ * Test source
+ * ------------------------
+ *    - unit/atomics/atomicDec.cc
+ * Test requirements
+ * ------------------------
+ *    - HIP_VERSION >= 5.2
+ */
+TEMPLATE_TEST_CASE("Unit_atomicDec_Positive", "", unsigned int) {
+  int warp_size = 0;
+  HIP_CHECK(hipDeviceGetAttribute(&warp_size, hipDeviceAttributeWarpSize, 0));
+  const auto cache_line_size = 128u;
+
+  for (auto current = 0; current < cmd_options.iterations; ++current) {
+    DYNAMIC_SECTION("Same address " << current) {
+      SingleDeviceSingleKernelTest<TestType, AtomicOperation::kDec>(1, sizeof(TestType));
+    }
+
+    DYNAMIC_SECTION("Adjacent addresses " << current) {
+      SingleDeviceSingleKernelTest<TestType, AtomicOperation::kDec>(warp_size, sizeof(TestType));
+    }
+
+    DYNAMIC_SECTION("Scattered addresses " << current) {
+      SingleDeviceSingleKernelTest<TestType, AtomicOperation::kDec>(warp_size, cache_line_size);
+    }
+  }
+}
+
+/**
+ * Test Description
+ * ------------------------
+ *    - Executes a kernel two times concurrently on a single device wherein all threads will perform
+ * an atomic decrement on a target memory location. Each thread will decrement the memory
+ * location, storing the return value into a separate output array slot corresponding to it. Once
+ * complete, the output array and target memory is validated to contain all the expected values.
+ * Several memory access patterns are tested:
+ *      -# All threads decrement a single, compile time deducible, memory location
+ *      -# Each thread targets an array containing warp_size elements, using tid % warp_size
+ *         for indexing
+ *      -# Same as the above, but the elements are spread out by L1 cache line size bytes.
+ *
+ *    - The test is run for:
+ *      - All overloads of atomicDec
+ *      - hipMalloc, hipMallocManaged, hipHostMalloc and hipHostRegister allocated memory
+ *      - Several grid and block dimension combinations.
+ * Test source
+ * ------------------------
+ *    - unit/atomics/atomicDec.cc
+ * Test requirements
+ * ------------------------
+ *    - HIP_VERSION >= 5.2
+ */
+TEMPLATE_TEST_CASE("Unit_atomicDec_Positive_Multi_Kernel", "", unsigned int) {
+  int warp_size = 0;
+  HIP_CHECK(hipDeviceGetAttribute(&warp_size, hipDeviceAttributeWarpSize, 0));
+  const auto cache_line_size = 128u;
+
+  for (auto current = 0; current < cmd_options.iterations; ++current) {
+    DYNAMIC_SECTION("Same address " << current) {
+      SingleDeviceMultipleKernelTest<TestType, AtomicOperation::kDec>(2, 1, sizeof(TestType));
+    }
+
+    DYNAMIC_SECTION("Adjacent addresses " << current) {
+      SingleDeviceMultipleKernelTest<TestType, AtomicOperation::kDec>(2, warp_size,
+                                                                      sizeof(TestType));
+    }
+
+    DYNAMIC_SECTION("Scattered addresses " << current) {
+      SingleDeviceMultipleKernelTest<TestType, AtomicOperation::kDec>(2, warp_size,
+                                                                      cache_line_size);
+    }
+  }
+}
+
+/**
+ * Test Description
+ * ------------------------
+ *    - RTCs kernels that pass combinations of arguments of invalid types for all overloads of
+ * atomicDec.
+ * Test source
+ * ------------------------
+ *    - unit/atomics/atomicDec.cc
+ * Test requirements
+ * ------------------------
+ *    - HIP_VERSION >= 5.2
+ */
+TEST_CASE("Unit_atomicDec_Negative_Parameters_RTC") {
+  hiprtcProgram program{};
+
+  const auto program_source = GENERATE(kAtomicDec_uint);
+  HIPRTC_CHECK(
+      hiprtcCreateProgram(&program, program_source, "atomicDec_negative.cc", 0, nullptr, nullptr));
+  hiprtcResult result{hiprtcCompileProgram(program, 0, nullptr)};
+
+  // Get the compile log and count compiler error messages
+  size_t log_size{};
+  HIPRTC_CHECK(hiprtcGetProgramLogSize(program, &log_size));
+  std::string log(log_size, ' ');
+  HIPRTC_CHECK(hiprtcGetProgramLog(program, log.data()));
+  int error_count{0};
+
+  int expected_error_count{8};
+  std::string error_message{"error:"};
+
+  size_t n_pos = log.find(error_message, 0);
+  while (n_pos != std::string::npos) {
+    ++error_count;
+    n_pos = log.find(error_message, n_pos + 1);
+  }
+
+  HIPRTC_CHECK(hiprtcDestroyProgram(&program));
+  HIPRTC_CHECK_ERROR(result, HIPRTC_ERROR_COMPILATION);
+  REQUIRE(error_count == expected_error_count);
+}

projects/hip-tests/catch/unit/atomics/atomicDec_negative_kernels.cc

@@ -0,0 +1,62 @@
+/*
+Copyright (c) 2023 Advanced Micro Devices, Inc. All rights reserved.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+*/
+
+#include <hip_test_common.hh>
+
+class Dummy {
+ public:
+  __device__ Dummy() {}
+  __device__ ~Dummy() {}
+};
+
+/* unsigned int atomicDec(unsigned int* address, unsigned int val) */
+__global__ void atomicDec_uint_v1(unsigned int* address, unsigned int* result) {
+  *result = atomicDec(&address, 1234);
+}
+
+__global__ void atomicDec_uint_v2(unsigned int* address, unsigned int* result) {
+  *result = atomicDec(address, address);
+}
+
+__global__ void atomicDec_uint_v3(unsigned int* address, unsigned int* result) {
+  *result = atomicDec(1234, 1234);
+}
+
+__global__ void atomicDec_uint_v4(Dummy* address, unsigned int* result) {
+  *result = atomicDec(address, 1234);
+}
+
+__global__ void atomicDec_uint_v5(char* address, unsigned int* result) {
+  *result = atomicDec(address, 1234);
+}
+
+__global__ void atomicDec_uint_v6(short* address, unsigned int* result) {
+  *result = atomicDec(address, 1234);
+}
+
+__global__ void atomicDec_uint_v7(long* address, unsigned int* result) {
+  *result = atomicDec(address, 1234);
+}
+
+__global__ void atomicDec_uint_v8(long long* address, unsigned int* result) {
+  *result = atomicDec(address, 1234);
+}

projects/hip-tests/catch/unit/atomics/atomicDec_negative_kernels_rtc.hh

@@ -0,0 +1,68 @@
+/*
+Copyright (c) 2023 Advanced Micro Devices, Inc. All rights reserved.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+*/
+
+#pragma once
+
+/*
+Negative kernels used for the atomics negative Test Cases that are using RTC.
+*/
+
+static constexpr auto kAtomicDec_uint{
+    R"(
+    __global__ void atomicDec_uint_v1(unsigned int* address, unsigned int* result) {
+      *result = atomicDec(&address, 1234);
+    }
+
+    __global__ void atomicDec_uint_v2(unsigned int* address, unsigned int* result) {
+      *result = atomicDec(address, address);
+    }
+
+    __global__ void atomicDec_uint_v3(unsigned int* address, unsigned int* result) {
+      *result = atomicDec(1234, 1234);
+    }
+
+    class Dummy {
+     public:
+      __device__ Dummy() {}
+      __device__ ~Dummy() {}
+    };
+
+    __global__ void atomicDec_uint_v4(Dummy* address, unsigned int* result) {
+      *result = atomicDec(address, 1234);
+    }
+
+    __global__ void atomicDec_uint_v5(char* address, unsigned int* result) {
+      *result = atomicDec(address, 1234);
+    }
+
+    __global__ void atomicDec_uint_v6(short* address, unsigned int* result) {
+      *result = atomicDec(address, 1234);
+    }
+
+    __global__ void atomicDec_uint_v7(long* address, unsigned int* result) {
+      *result = atomicDec(address, 1234);
+    }
+
+    __global__ void atomicDec_uint_v8(long long* address, unsigned int* result) {
+      *result = atomicDec(address, 1234);
+    }
+  )"};

projects/hip-tests/catch/unit/atomics/atomicInc.cc

@@ -0,0 +1,164 @@
+/*
+Copyright (c) 2023 Advanced Micro Devices, Inc. All rights reserved.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+*/
+
+#include "arithmetic_common.hh"
+#include "atomicInc_negative_kernels_rtc.hh"
+
+#include <hip_test_common.hh>
+
+/**
+ * @addtogroup atomicInc atomicInc
+ * @{
+ * @ingroup AtomicsTest
+ */
+
+/**
+ * Test Description
+ * ------------------------
+ *    - Executes a single kernel on a single device wherein all threads will perform an atomic
+ * increment on a target memory location. Each thread will increment the memory location,
+ * storing the return value into a separate output array slot corresponding to it. Once complete,
+ * the output array and target memory is validated to contain all the expected values. Several
+ * memory access patterns are tested:
+ *      -# All threads increment a single, compile time deducible, memory location
+ *      -# Each thread targets an array containing warp_size elements, using tid % warp_size
+ *         for indexing
+ *      -# Same as the above, but the elements are spread out by L1 cache line size bytes.
+ *
+ *    - The test is run for:
+ *      - All overloads of atomicInc
+ *      - hipMalloc, hipMallocManaged, hipHostMalloc and hipHostRegister allocated memory
+ *      - Shared memory
+ *      - Several grid and block dimension combinations (only one block is used for shared memory).
+ * Test source
+ * ------------------------
+ *    - unit/atomics/atomicInc.cc
+ * Test requirements
+ * ------------------------
+ *    - HIP_VERSION >= 5.2
+ */
+TEMPLATE_TEST_CASE("Unit_atomicInc_Positive", "", unsigned int) {
+  int warp_size = 0;
+  HIP_CHECK(hipDeviceGetAttribute(&warp_size, hipDeviceAttributeWarpSize, 0));
+  const auto cache_line_size = 128u;
+
+  for (auto current = 0; current < cmd_options.iterations; ++current) {
+    DYNAMIC_SECTION("Same address " << current) {
+      SingleDeviceSingleKernelTest<TestType, AtomicOperation::kInc>(1, sizeof(TestType));
+    }
+
+    DYNAMIC_SECTION("Adjacent addresses " << current) {
+      SingleDeviceSingleKernelTest<TestType, AtomicOperation::kInc>(warp_size, sizeof(TestType));
+    }
+
+    DYNAMIC_SECTION("Scattered addresses " << current) {
+      SingleDeviceSingleKernelTest<TestType, AtomicOperation::kInc>(warp_size, cache_line_size);
+    }
+  }
+}
+
+/**
+ * Test Description
+ * ------------------------
+ *    - Executes a kernel two times concurrently on a single device wherein all threads will
+ * perform an atomic increment on a target memory location. Each thread will increment the memory
+ * location, storing the return value into a separate output array slot corresponding to it. Once
+ * complete, the output array and target memory is validated to contain all the expected values.
+ * Several memory access patterns are tested:
+ *      -# All threads increment a single, compile time deducible, memory location
+ *      -# Each thread targets an array containing warp_size elements, using tid % warp_size
+ *         for indexing
+ *      -# Same as the above, but the elements are spread out by L1 cache line size bytes.
+ *
+ *    - The test is run for:
+ *      - All overloads of atomicInc
+ *      - hipMalloc, hipMallocManaged, hipHostMalloc and hipHostRegister allocated memory
+ *      - Several grid and block dimension combinations.
+ * Test source
+ * ------------------------
+ *    - unit/atomics/atomicInc.cc
+ * Test requirements
+ * ------------------------
+ *    - HIP_VERSION >= 5.2
+ */
+TEMPLATE_TEST_CASE("Unit_atomicInc_Positive_Multi_Kernel", "", unsigned int) {
+  int warp_size = 0;
+  HIP_CHECK(hipDeviceGetAttribute(&warp_size, hipDeviceAttributeWarpSize, 0));
+  const auto cache_line_size = 128u;
+
+  for (auto current = 0; current < cmd_options.iterations; ++current) {
+    DYNAMIC_SECTION("Same address " << current) {
+      SingleDeviceMultipleKernelTest<TestType, AtomicOperation::kInc>(2, 1, sizeof(TestType));
+    }
+
+    DYNAMIC_SECTION("Adjacent addresses " << current) {
+      SingleDeviceMultipleKernelTest<TestType, AtomicOperation::kInc>(2, warp_size,
+                                                                      sizeof(TestType));
+    }
+
+    DYNAMIC_SECTION("Scattered addresses " << current) {
+      SingleDeviceMultipleKernelTest<TestType, AtomicOperation::kInc>(2, warp_size,
+                                                                      cache_line_size);
+    }
+  }
+}
+
+/**
+ * Test Description
+ * ------------------------
+ *    - RTCs kernels that pass combinations of arguments of invalid types for all overloads of
+ * atomicInc.
+ * Test source
+ * ------------------------
+ *    - unit/atomics/atomicInc.cc
+ * Test requirements
+ * ------------------------
+ *    - HIP_VERSION >= 5.2
+ */
+TEST_CASE("Unit_atomicInc_Negative_Parameters_RTC") {
+  hiprtcProgram program{};
+
+  const auto program_source = GENERATE(kAtomicInc_uint);
+  HIPRTC_CHECK(
+      hiprtcCreateProgram(&program, program_source, "atomicInc_negative.cc", 0, nullptr, nullptr));
+  hiprtcResult result{hiprtcCompileProgram(program, 0, nullptr)};
+
+  // Get the compile log and count compiler error messages
+  size_t log_size{};
+  HIPRTC_CHECK(hiprtcGetProgramLogSize(program, &log_size));
+  std::string log(log_size, ' ');
+  HIPRTC_CHECK(hiprtcGetProgramLog(program, log.data()));
+  int error_count{0};
+
+  int expected_error_count{8};
+  std::string error_message{"error:"};
+
+  size_t n_pos = log.find(error_message, 0);
+  while (n_pos != std::string::npos) {
+    ++error_count;
+    n_pos = log.find(error_message, n_pos + 1);
+  }
+
+  HIPRTC_CHECK(hiprtcDestroyProgram(&program));
+  HIPRTC_CHECK_ERROR(result, HIPRTC_ERROR_COMPILATION);
+  REQUIRE(error_count == expected_error_count);
+}

projects/hip-tests/catch/unit/atomics/atomicInc_negative_kernels.cc

@@ -0,0 +1,62 @@
+/*
+Copyright (c) 2023 Advanced Micro Devices, Inc. All rights reserved.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+*/
+
+#include <hip_test_common.hh>
+
+class Dummy {
+ public:
+  __device__ Dummy() {}
+  __device__ ~Dummy() {}
+};
+
+/* unsigned int atomicInc(unsigned int* address, unsigned int val) */
+__global__ void atomicInc_uint_v1(unsigned int* address, unsigned int* result) {
+  *result = atomicInc(&address, 1234);
+}
+
+__global__ void atomicInc_uint_v2(unsigned int* address, unsigned int* result) {
+  *result = atomicInc(address, address);
+}
+
+__global__ void atomicInc_uint_v3(unsigned int* address, unsigned int* result) {
+  *result = atomicInc(1234, 1234);
+}
+
+__global__ void atomicInc_uint_v4(Dummy* address, unsigned int* result) {
+  *result = atomicInc(address, 1234);
+}
+
+__global__ void atomicInc_uint_v5(char* address, unsigned int* result) {
+  *result = atomicInc(address, 1234);
+}
+
+__global__ void atomicInc_uint_v6(short* address, unsigned int* result) {
+  *result = atomicInc(address, 1234);
+}
+
+__global__ void atomicInc_uint_v7(long* address, unsigned int* result) {
+  *result = atomicInc(address, 1234);
+}
+
+__global__ void atomicInc_uint_v8(long long* address, unsigned int* result) {
+  *result = atomicInc(address, 1234);
+}

projects/hip-tests/catch/unit/atomics/atomicInc_negative_kernels_rtc.hh

@@ -0,0 +1,68 @@
+/*
+Copyright (c) 2023 Advanced Micro Devices, Inc. All rights reserved.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+*/
+
+#pragma once
+
+/*
+Negative kernels used for the atomics negative Test Cases that are using RTC.
+*/
+
+static constexpr auto kAtomicInc_uint{
+    R"(
+    __global__ void atomicInc_uint_v1(unsigned int* address, unsigned int* result) {
+      *result = atomicInc(&address, 1234);
+    }
+
+    __global__ void atomicInc_uint_v2(unsigned int* address, unsigned int* result) {
+      *result = atomicInc(address, address);
+    }
+
+    __global__ void atomicInc_uint_v3(unsigned int* address, unsigned int* result) {
+      *result = atomicInc(1234, 1234);
+    }
+
+    class Dummy {
+     public:
+      __device__ Dummy() {}
+      __device__ ~Dummy() {}
+    };
+
+    __global__ void atomicInc_uint_v4(Dummy* address, unsigned int* result) {
+      *result = atomicInc(address, 1234);
+    }
+
+    __global__ void atomicInc_uint_v5(char* address, unsigned int* result) {
+      *result = atomicInc(address, 1234);
+    }
+
+    __global__ void atomicInc_uint_v6(short* address, unsigned int* result) {
+      *result = atomicInc(address, 1234);
+    }
+
+    __global__ void atomicInc_uint_v7(long* address, unsigned int* result) {
+      *result = atomicInc(address, 1234);
+    }
+
+    __global__ void atomicInc_uint_v8(long long* address, unsigned int* result) {
+      *result = atomicInc(address, 1234);
+    }
+  )"};