Benchmark copy of data from one pool to another pool either in
one or both directions. Users can enumerate the pools reported by system to specify which pools serve as source / destination Change-Id: I8e6d0adb3743b3328dd3ce9152762ca840ea613b
Cette révision appartient à :
Ramesh Errabolu
Fichier exécutable
+478
@@ -0,0 +1,478 @@
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#include "common.hpp"
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#include "rocm_async.hpp"
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#include <stdlib.h>
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#include <assert.h>
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#include <algorithm>
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#include <unistd.h>
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#include <cctype>
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#include <sstream>
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// The values are in megabytes at allocation time
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const uint32_t RocmAsync::SIZE_LIST[] = { 64, 128, 256, 512 };
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//const uint32_t RocmAsync::SIZE_LIST[] = { 2, 4, 8, 16, 32, 64, 128, 256, 512 };
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uint32_t RocmAsync::GetIterationNum() {
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return num_iteration_ * 1.2 + 1;
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}
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void RocmAsync::AcquireAccess(hsa_agent_t agent, void* ptr) {
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err_ = hsa_amd_agents_allow_access(1, &agent, NULL, ptr);
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ErrorCheck(err_);
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}
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void RocmAsync::AllocateHostBuffers(bool bidir, uint32_t size,
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void*& src_fwd, void*& dst_fwd,
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void* buf_src_fwd, void* buf_dst_fwd,
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hsa_agent_t src_agent_fwd, hsa_agent_t dst_agent_fwd,
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void*& src_rev, void*& dst_rev,
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void* buf_src_rev, void* buf_dst_rev,
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hsa_agent_t src_agent_rev, hsa_agent_t dst_agent_rev,
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hsa_signal_t& signal_fwd, hsa_signal_t& signal_rev) {
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// Allocate host buffers and setup accessibility for copy operation
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err_ = hsa_amd_memory_pool_allocate(sys_pool_, size, 0, (void**)&src_fwd);
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ErrorCheck(err_);
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AcquireAccess(src_agent_fwd, src_fwd);
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AcquireAccess(cpu_agent_, buf_src_fwd);
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err_ = hsa_amd_memory_pool_allocate(sys_pool_, size, 0, (void**)&dst_fwd);
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ErrorCheck(err_);
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AcquireAccess(dst_agent_fwd, dst_fwd);
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AcquireAccess(cpu_agent_, buf_dst_fwd);
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// Initialize host buffers to a determinate value
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memset(src_fwd, 0x23, size);
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memset(dst_fwd, 0x00, size);
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// Create a signal to wait on copy operation
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// @TODO: replace it with a signal pool call
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err_ = hsa_signal_create(1, 0, NULL, &signal_fwd);
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ErrorCheck(err_);
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if (bidir == false) {
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return;
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}
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err_ = hsa_amd_memory_pool_allocate(sys_pool_, size, 0, (void**)&src_rev);
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ErrorCheck(err_);
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AcquireAccess(src_agent_rev, src_rev);
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AcquireAccess(cpu_agent_, buf_src_rev);
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err_ = hsa_amd_memory_pool_allocate(sys_pool_, size, 0, (void**)&dst_rev);
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ErrorCheck(err_);
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AcquireAccess(dst_agent_rev, dst_rev);
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AcquireAccess(cpu_agent_, buf_dst_rev);
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// Initialize host buffers to a determinate value
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memset(src_rev, 0x23, size);
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memset(dst_rev, 0x00, size);
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err_ = hsa_signal_create(1, 0, NULL, &signal_rev);
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ErrorCheck(err_);
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}
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void RocmAsync::AllocateCopyBuffers(bool bidir, uint32_t size,
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void*& src_fwd, hsa_amd_memory_pool_t src_pool_fwd,
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void*& dst_fwd, hsa_amd_memory_pool_t dst_pool_fwd,
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hsa_agent_t src_agent_fwd, hsa_agent_t dst_agent_fwd,
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void*& src_rev, hsa_amd_memory_pool_t src_pool_rev,
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void*& dst_rev, hsa_amd_memory_pool_t dst_pool_rev,
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hsa_agent_t src_agent_rev, hsa_agent_t dst_agent_rev,
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hsa_signal_t& signal_fwd, hsa_signal_t& signal_rev) {
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// Allocate buffers in src and dst pools for forward copy
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err_ = hsa_amd_memory_pool_allocate(src_pool_fwd, size, 0, &src_fwd);
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ErrorCheck(err_);
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err_ = hsa_amd_memory_pool_allocate(dst_pool_fwd, size, 0, &dst_fwd);
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ErrorCheck(err_);
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// Allocate buffers in src and dst pools for reverse copy
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if (bidir) {
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err_ = hsa_amd_memory_pool_allocate(src_pool_rev, size, 0, &src_rev);
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ErrorCheck(err_);
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err_ = hsa_amd_memory_pool_allocate(dst_pool_rev, size, 0, &dst_rev);
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ErrorCheck(err_);
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}
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// Acquire access to src and dst buffers for forward copy
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AcquireAccess(src_agent_fwd, dst_fwd);
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AcquireAccess(dst_agent_fwd, src_fwd);
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// Acquire access to src and dst buffers for reverse copy
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if (bidir) {
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AcquireAccess(src_agent_rev, dst_rev);
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AcquireAccess(dst_agent_rev, src_rev);
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}
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// Create a signal to wait on copy operation
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// @TODO: replace it with a signal pool call
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err_ = hsa_signal_create(1, 0, NULL, &signal_fwd);
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ErrorCheck(err_);
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if (bidir) {
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err_ = hsa_signal_create(1, 0, NULL, &signal_rev);
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ErrorCheck(err_);
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}
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}
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void RocmAsync::ReleaseBuffers(bool bidir,
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void* src_fwd, void* src_rev,
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void* dst_fwd, void* dst_rev,
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hsa_signal_t signal_fwd,
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hsa_signal_t signal_rev) {
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// Free the src and dst buffers used in forward copy
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// including the signal used to wait
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err_ = hsa_amd_memory_pool_free(src_fwd);
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ErrorCheck(err_);
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err_ = hsa_amd_memory_pool_free(dst_fwd);
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ErrorCheck(err_);
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err_ = hsa_signal_destroy(signal_fwd);
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ErrorCheck(err_);
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// Free the src and dst buffers used in reverse copy
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// including the signal used to wait
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if (bidir) {
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err_ = hsa_amd_memory_pool_free(src_rev);
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ErrorCheck(err_);
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err_ = hsa_amd_memory_pool_free(dst_rev);
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ErrorCheck(err_);
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err_ = hsa_signal_destroy(signal_rev);
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ErrorCheck(err_);
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}
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}
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double RocmAsync::GetGpuCopyTime(bool bidir,
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hsa_signal_t signal_fwd,
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hsa_signal_t signal_rev) {
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// Obtain time taken for forward copy
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hsa_amd_profiling_async_copy_time_t async_time_fwd = {0};
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err_= hsa_amd_profiling_get_async_copy_time(signal_fwd, &async_time_fwd);
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ErrorCheck(err_);
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if (bidir == false) {
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return(async_time_fwd.end - async_time_fwd.start);
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}
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hsa_amd_profiling_async_copy_time_t async_time_rev = {0};
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err_= hsa_amd_profiling_get_async_copy_time(signal_rev, &async_time_rev);
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ErrorCheck(err_);
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double start = min(async_time_fwd.start, async_time_rev.start);
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double end = max(async_time_fwd.end, async_time_rev.end);
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return(end - start);
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}
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void RocmAsync::copy_buffer(void* dst, hsa_agent_t dst_agent,
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void* src, hsa_agent_t src_agent,
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size_t size, hsa_signal_t signal) {
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// Copy from src into dst buffer
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err_ = hsa_amd_memory_async_copy(dst, dst_agent,
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src, src_agent,
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size, 0, NULL, signal);
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ErrorCheck(err_);
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// Wait for the forward copy operation to complete
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while (hsa_signal_wait_acquire(signal, HSA_SIGNAL_CONDITION_LT, 1,
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uint64_t(-1), HSA_WAIT_STATE_ACTIVE));
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}
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void RocmAsync::RunCopyBenchmark(async_trans_t& trans) {
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// Bind if this transaction is bidirectional
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bool bidir = trans.copy.bidir_;
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// Initialize size of buffer to equal the largest element of allocation
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uint32_t size_len = size_list_.size();
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uint32_t max_size = size_list_.back() * 1024 * 1024;
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// Bind to resources such as pool and agents that are involved
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// in both forward and reverse copy operations
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void* buf_src_fwd;
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void* buf_dst_fwd;
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void* buf_src_rev;
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void* buf_dst_rev;
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void* host_src_fwd;
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void* host_dst_fwd;
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void* host_src_rev;
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void* host_dst_rev;
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hsa_signal_t signal_fwd;
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hsa_signal_t signal_rev;
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hsa_signal_t host_signal_fwd;
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hsa_signal_t host_signal_rev;
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hsa_amd_memory_pool_t src_pool_fwd = trans.copy.src_pool_;
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hsa_amd_memory_pool_t dst_pool_fwd = trans.copy.dst_pool_;
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hsa_amd_memory_pool_t src_pool_rev = dst_pool_fwd;
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hsa_amd_memory_pool_t dst_pool_rev = src_pool_fwd;
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hsa_agent_t src_agent_fwd = pool_list_[trans.copy.src_idx_].owner_agent_;
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hsa_agent_t dst_agent_fwd = pool_list_[trans.copy.dst_idx_].owner_agent_;
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hsa_agent_t src_agent_rev = dst_agent_fwd;
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hsa_agent_t dst_agent_rev = src_agent_fwd;
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// Allocate buffers and signal objects
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AllocateCopyBuffers(bidir, max_size,
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buf_src_fwd, src_pool_fwd,
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buf_dst_fwd, dst_pool_fwd,
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src_agent_fwd, dst_agent_fwd,
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buf_src_rev, src_pool_rev,
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buf_dst_rev, dst_pool_rev,
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src_agent_rev, dst_agent_rev,
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signal_fwd, signal_rev);
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if (verify_) {
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AllocateHostBuffers(bidir, max_size,
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host_src_fwd, host_dst_fwd,
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buf_src_fwd, buf_dst_fwd,
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src_agent_fwd, dst_agent_fwd,
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host_src_rev, host_dst_rev,
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buf_src_rev, buf_dst_rev,
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src_agent_rev, dst_agent_rev,
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host_signal_fwd, host_signal_rev);
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// Initialize source buffer with values from verification buffer
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copy_buffer(buf_src_fwd, src_agent_fwd,
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host_src_fwd, cpu_agent_,
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max_size, host_signal_fwd);
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ErrorCheck(err_);
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if (bidir) {
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copy_buffer(buf_src_rev, src_agent_rev,
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host_src_rev, cpu_agent_,
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max_size, host_signal_rev);
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ErrorCheck(err_);
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}
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}
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// Bind the number of iterations
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uint32_t iterations = GetIterationNum();
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// Iterate through the differnt buffer sizes to
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// compute the bandwidth as determined by copy
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for (uint32_t idx = 0; idx < size_len; idx++) {
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// This should not be happening
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uint32_t curr_size = size_list_[idx] * 1024 * 1024;
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if (curr_size > max_size) {
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break;
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}
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std::vector<double> cpu_time;
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std::vector<double> gpu_time;
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for (uint32_t it = 0; it < iterations; it++) {
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#if DEBUG
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printf(".");
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fflush(stdout);
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#endif
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hsa_signal_store_relaxed(signal_fwd, 1);
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if (bidir) {
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hsa_signal_store_relaxed(signal_rev, 1);
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}
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if (verify_) {
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AcquireAccess(src_agent_fwd, buf_dst_fwd);
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AcquireAccess(dst_agent_fwd, buf_src_fwd);
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if (bidir) {
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AcquireAccess(src_agent_rev, buf_dst_rev);
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AcquireAccess(dst_agent_rev, buf_src_rev);
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}
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}
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// Create a timer object and reset signals
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PerfTimer timer;
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uint32_t index = timer.CreateTimer();
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// Start the timer and launch forward copy operation
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timer.StartTimer(index);
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err_ = hsa_amd_memory_async_copy(buf_dst_fwd, dst_agent_fwd,
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buf_src_fwd, src_agent_fwd,
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curr_size, 0, NULL, signal_fwd);
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ErrorCheck(err_);
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// Launch reverse copy operation if it is bidirectional
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if (bidir) {
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err_ = hsa_amd_memory_async_copy(buf_dst_rev, dst_agent_rev,
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buf_src_rev, src_agent_rev,
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curr_size, 0, NULL, signal_rev);
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ErrorCheck(err_);
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}
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// Wait for the forward copy operation to complete
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while (hsa_signal_wait_acquire(signal_fwd, HSA_SIGNAL_CONDITION_LT, 1,
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uint64_t(-1), HSA_WAIT_STATE_ACTIVE));
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// Wait for the reverse copy operation to complete
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if (bidir) {
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while (hsa_signal_wait_acquire(signal_rev, HSA_SIGNAL_CONDITION_LT, 1,
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uint64_t(-1), HSA_WAIT_STATE_ACTIVE));
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}
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// Stop the timer object
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timer.StopTimer(index);
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// Push the time taken for copy into a vector of copy times
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cpu_time.push_back(timer.ReadTimer(index));
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// Collect time from the signal(s)
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if (trans.copy.uses_gpu_) {
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double temp = GetGpuCopyTime(bidir, signal_fwd, signal_rev);
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gpu_time.push_back(temp);
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}
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if (verify_) {
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// Re-Establish access to destination buffer and host buffer
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AcquireAccess(cpu_agent_, buf_dst_fwd);
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AcquireAccess(dst_agent_fwd, host_dst_fwd);
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// Init dst buffer with values from outbuffer of copy operation
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hsa_signal_store_relaxed(host_signal_fwd, 1);
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copy_buffer(host_dst_fwd, cpu_agent_,
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buf_dst_fwd, dst_agent_fwd,
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curr_size, host_signal_fwd);
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ErrorCheck(err_);
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// Compare output equals input
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err_ = (hsa_status_t)memcmp(host_src_fwd, host_dst_fwd, curr_size);
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ErrorCheck(err_);
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if (bidir) {
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// Re-Establish access to destination buffer and host buffer
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AcquireAccess(cpu_agent_, buf_dst_rev);
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AcquireAccess(dst_agent_rev, host_dst_rev);
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hsa_signal_store_relaxed(host_signal_rev, 1);
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copy_buffer(host_dst_rev, cpu_agent_,
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buf_dst_rev, dst_agent_rev,
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curr_size, host_signal_rev);
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ErrorCheck(err_);
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// Compare output equals input
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err_ = (hsa_status_t)memcmp(host_src_rev, host_dst_rev, curr_size);
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ErrorCheck(err_);
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}
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}
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}
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#if DEBUG
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std::cout << std::endl;
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#endif
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// Get Cpu min copy time
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trans.cpu_min_time_.push_back(GetMinTime(cpu_time));
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// Get Cpu mean copy time and store to the array
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trans.cpu_avg_time_.push_back(GetMeanTime(cpu_time));
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if (trans.copy.uses_gpu_) {
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// Get Gpu min copy time
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trans.gpu_min_time_.push_back(GetMinTime(gpu_time));
|
||||
// Get Gpu mean copy time and store to the array
|
||||
trans.gpu_avg_time_.push_back(GetMeanTime(gpu_time));
|
||||
}
|
||||
|
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// Clear the stack of cpu times
|
||||
cpu_time.clear();
|
||||
gpu_time.clear();
|
||||
}
|
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|
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// Free up buffers and signal objects used in copy operation
|
||||
ReleaseBuffers(bidir, buf_src_fwd, buf_src_rev,
|
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buf_dst_fwd, buf_dst_rev, signal_fwd, signal_rev);
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|
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if (verify_) {
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ReleaseBuffers(bidir, host_src_fwd, host_src_rev,
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host_dst_fwd, host_dst_rev, host_signal_fwd, host_signal_rev);
|
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}
|
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}
|
||||
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void RocmAsync::RunIOBenchmark(async_trans_t& trans) {
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||||
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std::cout << "Unsupported Request - Read / Write" << std::endl;
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exit(1);
|
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}
|
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|
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void RocmAsync::Run() {
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||||
|
||||
// Enable profiling of Async Copy Activity
|
||||
err_ = hsa_amd_profiling_async_copy_enable(true);
|
||||
ErrorCheck(err_);
|
||||
|
||||
// Iterate through the list of transactions and execute them
|
||||
uint32_t trans_size = trans_list_.size();
|
||||
for (uint32_t idx = 0; idx < trans_size; idx++) {
|
||||
async_trans_t& trans = trans_list_[idx];
|
||||
if ((trans.req_type_ == REQ_COPY_BIDIR) ||
|
||||
(trans.req_type_ == REQ_COPY_UNIDIR)) {
|
||||
RunCopyBenchmark(trans);
|
||||
}
|
||||
if ((trans.req_type_ == REQ_READ) ||
|
||||
(trans.req_type_ == REQ_WRITE)) {
|
||||
RunIOBenchmark(trans);
|
||||
}
|
||||
}
|
||||
|
||||
// Disable profiling of Async Copy Activity
|
||||
err_ = hsa_amd_profiling_async_copy_enable(false);
|
||||
ErrorCheck(err_);
|
||||
|
||||
}
|
||||
|
||||
void RocmAsync::Close() {
|
||||
hsa_status_t status = hsa_shut_down();
|
||||
ErrorCheck(status);
|
||||
return;
|
||||
}
|
||||
|
||||
// Sets up the bandwidth test object to enable running
|
||||
// the various test scenarios requested by user. The
|
||||
// things this proceedure takes care of are:
|
||||
//
|
||||
// Parse user arguments
|
||||
// Discover RocR Device Topology
|
||||
// Determine validity of requested test scenarios
|
||||
// Build the list of transactions to execute
|
||||
// Miscellaneous
|
||||
//
|
||||
void RocmAsync::SetUp() {
|
||||
|
||||
// Parse user arguments
|
||||
ParseArguments();
|
||||
|
||||
// Validate input parameters
|
||||
bool status = ValidateArguments();
|
||||
if (status == false) {
|
||||
PrintHelpScreen();
|
||||
exit(1);
|
||||
}
|
||||
|
||||
// Build list of transactions (copy, read, write) to execute
|
||||
status = BuildTransList();
|
||||
if (status == false) {
|
||||
PrintHelpScreen();
|
||||
exit(1);
|
||||
}
|
||||
|
||||
// Print Debug Info - List of Agents, Pool, Transactions
|
||||
char* print_debug = getenv("PRINT_DEBUG");
|
||||
if (print_debug) {
|
||||
//PrintAgentsList();
|
||||
//PrintPoolsList();
|
||||
PrintTransList();
|
||||
//PrintTopology();
|
||||
}
|
||||
}
|
||||
|
||||
RocmAsync::RocmAsync(int argc, char** argv) : BaseTest() {
|
||||
usr_argc_ = argc;
|
||||
usr_argv_ = argv;
|
||||
verify_ = false;
|
||||
pool_index_ = 0;
|
||||
agent_index_ = 0;
|
||||
req_read_ = REQ_INVALID;
|
||||
req_write_ = REQ_INVALID;
|
||||
req_copy_bidir_ = REQ_INVALID;
|
||||
req_copy_unidir_ = REQ_INVALID;
|
||||
}
|
||||
|
||||
RocmAsync::~RocmAsync() { }
|
||||
|
||||
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