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Fix miscellaneous warnings flagged by Clang

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Change-Id: I85a45cb3b44e4379b31bcc56af061fd1571f2af5
This commit is contained in:
Jay Cornwall
2016-10-26 19:24:48 -05:00
parent d5b4078072
commit c30c25bd30
11 changed files with 127 additions and 141 deletions
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runtime/hsa-runtime/core/inc/host_queue.h
+18 -19
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@@ -56,90 +56,89 @@ class HostQueue : public Queue {
~HostQueue();
hsa_status_t Inactivate() { return HSA_STATUS_SUCCESS; }
hsa_status_t Inactivate() override { return HSA_STATUS_SUCCESS; }
uint64_t LoadReadIndexAcquire() {
uint64_t LoadReadIndexAcquire() override {
return atomic::Load(&amd_queue_.read_dispatch_id,
std::memory_order_acquire);
}
uint64_t LoadReadIndexRelaxed() {
uint64_t LoadReadIndexRelaxed() override {
return atomic::Load(&amd_queue_.read_dispatch_id,
std::memory_order_relaxed);
}
uint64_t LoadWriteIndexAcquire() {
uint64_t LoadWriteIndexAcquire() override {
return atomic::Load(&amd_queue_.write_dispatch_id,
std::memory_order_acquire);
}
uint64_t LoadWriteIndexRelaxed() {
uint64_t LoadWriteIndexRelaxed() override {
return atomic::Load(&amd_queue_.write_dispatch_id,
std::memory_order_relaxed);
}
void StoreReadIndexRelaxed(uint64_t value) {
void StoreReadIndexRelaxed(uint64_t value) override {
atomic::Store(&amd_queue_.read_dispatch_id, value,
std::memory_order_relaxed);
}
void StoreReadIndexRelease(uint64_t value) {
void StoreReadIndexRelease(uint64_t value) override {
atomic::Store(&amd_queue_.read_dispatch_id, value,
std::memory_order_release);
}
void StoreWriteIndexRelaxed(uint64_t value) {
void StoreWriteIndexRelaxed(uint64_t value) override {
atomic::Store(&amd_queue_.write_dispatch_id, value,
std::memory_order_relaxed);
}
void StoreWriteIndexRelease(uint64_t value) {
void StoreWriteIndexRelease(uint64_t value) override {
atomic::Store(&amd_queue_.write_dispatch_id, value,
std::memory_order_release);
}
uint64_t CasWriteIndexAcqRel(uint64_t expected, uint64_t value) {
uint64_t CasWriteIndexAcqRel(uint64_t expected, uint64_t value) override {
return atomic::Cas(&amd_queue_.write_dispatch_id, value, expected,
std::memory_order_acq_rel);
}
uint64_t CasWriteIndexAcquire(uint64_t expected, uint64_t value) {
uint64_t CasWriteIndexAcquire(uint64_t expected, uint64_t value) override {
return atomic::Cas(&amd_queue_.write_dispatch_id, value, expected,
std::memory_order_acquire);
}
uint64_t CasWriteIndexRelaxed(uint64_t expected, uint64_t value) {
uint64_t CasWriteIndexRelaxed(uint64_t expected, uint64_t value) override {
return atomic::Cas(&amd_queue_.write_dispatch_id, value, expected,
std::memory_order_relaxed);
}
uint64_t CasWriteIndexRelease(uint64_t expected, uint64_t value) {
uint64_t CasWriteIndexRelease(uint64_t expected, uint64_t value) override {
return atomic::Cas(&amd_queue_.write_dispatch_id, value, expected,
std::memory_order_release);
}
uint64_t AddWriteIndexAcqRel(uint64_t value) {
uint64_t AddWriteIndexAcqRel(uint64_t value) override {
return atomic::Add(&amd_queue_.write_dispatch_id, value,
std::memory_order_acq_rel);
}
uint64_t AddWriteIndexAcquire(uint64_t value) {
uint64_t AddWriteIndexAcquire(uint64_t value) override {
return atomic::Add(&amd_queue_.write_dispatch_id, value,
std::memory_order_acquire);
}
uint64_t AddWriteIndexRelaxed(uint64_t value) {
uint64_t AddWriteIndexRelaxed(uint64_t value) override {
return atomic::Add(&amd_queue_.write_dispatch_id, value,
std::memory_order_relaxed);
}
uint64_t AddWriteIndexRelease(uint64_t value) {
uint64_t AddWriteIndexRelease(uint64_t value) override {
return atomic::Add(&amd_queue_.write_dispatch_id, value,
std::memory_order_release);
}
hsa_status_t SetCUMasking(const uint32_t num_cu_mask_count,
const uint32_t* cu_mask) {
hsa_status_t SetCUMasking(const uint32_t num_cu_mask_count, const uint32_t* cu_mask) override {
return HSA_STATUS_ERROR;
}