[gfx12] Finalize support for gfx12 new counter blocks (#81)
1. Move all new gfx12 block enums to aql_profile_v2.h. hsa_ven_amd_aqlprofile.h will be left untouched.
2. Re-org counter info in gfx12_block_info.h to be purely alphabetic-ordered for easy comparison between different IP versions. Also use auto-gen block name from IP header files whenever possible to reduce manual editing.
3. Remove unused counter info from graphics blocks.
4. Added UTCL2 and VML2 support
5. Added all gfx12 blocks to ctrl test
[ROCm/aqlprofile commit: b20803e95d]
This commit is contained in:
@@ -48,7 +48,7 @@ class Gfx10Factory : public Pm4Factory {
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// void ConstructTable(const AgentInfo* agent_info);
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void Init(const AgentInfo* agent_info);
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// void ConstructBuilders(const AgentInfo* agent_info);
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static const GpuBlockInfo* block_table_[HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER];
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static const GpuBlockInfo* block_table_[AQLPROFILE_BLOCKS_NUMBER];
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};
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// Gfx builders init
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@@ -81,7 +81,7 @@ void Gfx10Factory::Init(const AgentInfo* agent_info) {
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}
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// GFX10 block table
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const GpuBlockInfo* Gfx10Factory::block_table_[HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER] = {
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const GpuBlockInfo* Gfx10Factory::block_table_[AQLPROFILE_BLOCKS_NUMBER] = {
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&CpcCounterBlockInfo, &CpfCounterBlockInfo, &GdsCounterBlockInfo, &GrbmCounterBlockInfo,
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NULL /*&GrbmSeCounterBlockInfo*/, &SpiCounterBlockInfo, &SqCounterBlockInfo,
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NULL /*&SqCsCounterBlockInfo*/, NULL /*GFX8 SRBM*/, &SxCounterBlockInfo, &TaCounterBlockInfo,
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@@ -48,7 +48,7 @@ class Gfx11Factory : public Pm4Factory {
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// void ConstructTable(const AgentInfo* agent_info);
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void Init(const AgentInfo* agent_info);
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// void ConstructBuilders(const AgentInfo* agent_info);
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static const GpuBlockInfo* block_table_[HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER];
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static const GpuBlockInfo* block_table_[AQLPROFILE_BLOCKS_NUMBER];
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};
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// Gfx builders init
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@@ -81,7 +81,7 @@ void Gfx11Factory::Init(const AgentInfo* agent_info) {
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}
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// GFX11 block table
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const GpuBlockInfo* Gfx11Factory::block_table_[HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER] = {
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const GpuBlockInfo* Gfx11Factory::block_table_[AQLPROFILE_BLOCKS_NUMBER] = {
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&CpcCounterBlockInfo, &CpfCounterBlockInfo, &GdsCounterBlockInfo, &GrbmCounterBlockInfo,
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NULL /*&GrbmSeCounterBlockInfo*/, &SpiCounterBlockInfo, &SqCounterBlockInfo,
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NULL /*&SqCsCounterBlockInfo*/, NULL /*GFX8 SRBM*/, &SxCounterBlockInfo, &TaCounterBlockInfo,
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@@ -79,31 +79,35 @@ void Gfx12Factory::ConstructBuilders(const AgentInfo* agent_info) {
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void Gfx12Factory::ConstructTable(const AgentInfo* agent_info) {
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// Global blocks
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block_table_[__BLOCK_ID(CHA)] = &ChaCounterBlockInfo;
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block_table_[__BLOCK_ID(CHC)] = &ChcCounterBlockInfo;
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block_table_[__BLOCK_ID(CPC)] = &CpcCounterBlockInfo;
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block_table_[__BLOCK_ID(CPF)] = &CpfCounterBlockInfo;
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block_table_[__BLOCK_ID(CPG)] = &CpgCounterBlockInfo;
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block_table_[__BLOCK_ID(GCEA)] = &GceaCounterBlockInfo;
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block_table_[__BLOCK_ID(GCR)] = &GcrCounterBlockInfo;
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block_table_[__BLOCK_ID(GL2A)] = &Gl2aCounterBlockInfo;
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block_table_[__BLOCK_ID(GL2C)] = &Gl2cCounterBlockInfo;
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block_table_[__BLOCK_ID(GRBM)] = &GrbmCounterBlockInfo;
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block_table_[__BLOCK_ID(RLC)] = &RlcCounterBlockInfo;
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block_table_[__BLOCK_ID(SDMA_PM)] = &SdmaPmCounterBlockInfo;
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block_table_[__BLOCK_ID(CHA)] = &ChaCounterBlockInfo;
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block_table_[__BLOCK_ID(CHC)] = &ChcCounterBlockInfo;
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block_table_[__BLOCK_ID_HSA(CPC)] = &CpcCounterBlockInfo;
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block_table_[__BLOCK_ID_HSA(CPF)] = &CpfCounterBlockInfo;
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block_table_[__BLOCK_ID(CPG)] = &CpgCounterBlockInfo;
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block_table_[__BLOCK_ID(GC_UTCL2)] = &GcUtcl2CounterBlockInfo;
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block_table_[__BLOCK_ID(GC_VML2)] = &GcVml2CounterBlockInfo;
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block_table_[__BLOCK_ID(GC_VML2_SPM)] = &GcVml2SpmCounterBlockInfo;
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block_table_[__BLOCK_ID_HSA(GCEA)] = &GceaCounterBlockInfo;
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block_table_[__BLOCK_ID_HSA(GCR)] = &GcrCounterBlockInfo;
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block_table_[__BLOCK_ID_HSA(GL2A)] = &Gl2aCounterBlockInfo;
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block_table_[__BLOCK_ID_HSA(GL2C)] = &Gl2cCounterBlockInfo;
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block_table_[__BLOCK_ID_HSA(GRBM)] = &GrbmCounterBlockInfo;
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block_table_[__BLOCK_ID(RLC)] = &RlcCounterBlockInfo;
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block_table_[__BLOCK_ID_HSA(SDMA)] = &SdmaCounterBlockInfo;
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// SE blocks
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block_table_[__BLOCK_ID(GCEA_SE)] = &GceaSeCounterBlockInfo;
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block_table_[__BLOCK_ID(GRBMH)] = &GrbmhCounterBlockInfo;
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block_table_[__BLOCK_ID(SPI)] = &SpiCounterBlockInfo;
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block_table_[__BLOCK_ID(SQ)] = &SqcCounterBlockInfo;
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block_table_[__BLOCK_ID(GC_UTCL1)] = &GcUtcl1CounterBlockInfo;
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block_table_[__BLOCK_ID(GC_UTCL1)] = &GcUtcl1CounterBlockInfo;
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block_table_[__BLOCK_ID(GCEA_SE)] = &GceaSeCounterBlockInfo;
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block_table_[__BLOCK_ID(GRBMH)] = &GrbmhCounterBlockInfo;
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block_table_[__BLOCK_ID_HSA(SPI)] = &SpiCounterBlockInfo;
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block_table_[__BLOCK_ID(SQG)] = &SqgCounterBlockInfo;
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// SA blocks
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block_table_[__BLOCK_ID(GL1A)] = &Gl1aCounterBlockInfo;
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block_table_[__BLOCK_ID(GL1C)] = &Gl1cCounterBlockInfo;
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block_table_[__BLOCK_ID_HSA(GL1A)] = &Gl1aCounterBlockInfo;
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block_table_[__BLOCK_ID_HSA(GL1C)] = &Gl1cCounterBlockInfo;
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// WGP blocks
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block_table_[__BLOCK_ID(TA)] = &TaCounterBlockInfo;
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block_table_[__BLOCK_ID(TCP)] = &TcpCounterBlockInfo;
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block_table_[__BLOCK_ID(TD)] = &TdCounterBlockInfo;
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block_table_[__BLOCK_ID_HSA(SQ)] = &SqcCounterBlockInfo;
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block_table_[__BLOCK_ID_HSA(TA)] = &TaCounterBlockInfo;
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block_table_[__BLOCK_ID_HSA(TCP)] = &TcpCounterBlockInfo;
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block_table_[__BLOCK_ID_HSA(TD)] = &TdCounterBlockInfo;
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}
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// Pm4Factory create mathods
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@@ -28,11 +28,11 @@
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namespace aql_profile {
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const GpuBlockInfo* Mi100Factory::block_table_[HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER] = {};
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const GpuBlockInfo* Mi100Factory::block_table_[AQLPROFILE_BLOCKS_NUMBER] = {};
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Mi100Factory::Mi100Factory(const AgentInfo* agent_info)
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: Gfx9Factory(block_table_, sizeof(block_table_), agent_info) {
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for (unsigned i = 0; i < HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER; ++i) {
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for (unsigned i = 0; i < AQLPROFILE_BLOCKS_NUMBER; ++i) {
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const GpuBlockInfo* base_table_ptr = Gfx9Factory::block_table_[i];
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if (base_table_ptr == NULL) continue;
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GpuBlockInfo* block_info = nullptr;
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@@ -37,14 +37,14 @@ class Mi200Factory : public Gfx9Factory {
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virtual int GetAccumHiID() const override { return 185; };
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protected:
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static const GpuBlockInfo* block_table_[HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER];
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static const GpuBlockInfo* block_table_[AQLPROFILE_BLOCKS_NUMBER];
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};
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const GpuBlockInfo* Mi200Factory::block_table_[HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER] = {};
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const GpuBlockInfo* Mi200Factory::block_table_[AQLPROFILE_BLOCKS_NUMBER] = {};
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Mi200Factory::Mi200Factory(const AgentInfo* agent_info)
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: Gfx9Factory(block_table_, sizeof(block_table_), agent_info) {
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for (unsigned i = 0; i < HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER; ++i) {
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for (unsigned i = 0; i < AQLPROFILE_BLOCKS_NUMBER; ++i) {
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const GpuBlockInfo* base_table_ptr = Gfx9Factory::block_table_[i];
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if (base_table_ptr == NULL) continue;
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GpuBlockInfo* block_info = nullptr;
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@@ -31,7 +31,7 @@ namespace aql_profile {
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class Mi300Factory : public Mi100Factory {
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public:
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explicit Mi300Factory(const AgentInfo* agent_info) : Mi100Factory(agent_info) {
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for (unsigned blockname_id = 0; blockname_id < HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER;
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for (unsigned blockname_id = 0; blockname_id < AQLPROFILE_BLOCKS_NUMBER;
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++blockname_id) {
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const GpuBlockInfo* base_table_ptr = Gfx9Factory::block_table_[blockname_id];
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if (base_table_ptr == NULL) continue;
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@@ -76,7 +76,7 @@ void Gfx9Factory::Print(const GpuBlockInfo* block_info) {
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}
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// GFX9 block table
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const GpuBlockInfo* Gfx9Factory::block_table_[HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER] = {
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const GpuBlockInfo* Gfx9Factory::block_table_[AQLPROFILE_BLOCKS_NUMBER] = {
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&CpcCounterBlockInfo, &CpfCounterBlockInfo, &GdsCounterBlockInfo, &GrbmCounterBlockInfo,
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&GrbmSeCounterBlockInfo, &SpiCounterBlockInfo, &SqCounterBlockInfo, &SqCsCounterBlockInfo,
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NULL /*GFX? SRBM*/, &SxCounterBlockInfo, &TaCounterBlockInfo, &TcaCounterBlockInfo,
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@@ -42,7 +42,7 @@ class Gfx9Factory : public Pm4Factory {
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protected:
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void Init(const AgentInfo* agent_info);
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static const GpuBlockInfo* block_table_[HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER];
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static const GpuBlockInfo* block_table_[AQLPROFILE_BLOCKS_NUMBER];
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static void Print(const GpuBlockInfo* block_info);
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};
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@@ -53,7 +53,7 @@ class Mi100Factory : public Gfx9Factory {
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explicit Mi100Factory(const AgentInfo* agent_info);
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protected:
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static const GpuBlockInfo* block_table_[HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER];
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static const GpuBlockInfo* block_table_[AQLPROFILE_BLOCKS_NUMBER];
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};
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} // namespace aql_profile
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@@ -50,6 +50,49 @@ typedef enum {
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AQLPROFILE_AGENT_VERSION_LAST
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} aqlprofile_agent_version_t;
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/**
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* @brief Enums for counter blocks.
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* AQLPROFILE_BLOCK_NAME_RESERVED_X are blocks reserved for npi. Reserving them here can maintain
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* enum consistency between mainline and npi.
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* TODO: Move all counter blocks here from hsa_ven_amd_aqlprofile.h
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*/
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typedef enum {
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// Blocks reserved for NPI support
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AQLPROFILE_BLOCK_NAME_RESERVED_0 = HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER,
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AQLPROFILE_BLOCK_NAME_RESERVED_1,
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AQLPROFILE_BLOCK_NAME_RESERVED_2,
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AQLPROFILE_BLOCK_NAME_RESERVED_3,
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AQLPROFILE_BLOCK_NAME_RESERVED_4,
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AQLPROFILE_BLOCK_NAME_RESERVED_5,
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// Blocks available for most ASICs, but not currently in use
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AQLPROFILE_BLOCK_NAME_CPG,
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AQLPROFILE_BLOCK_NAME_RLC,
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// New blocks for gc_12_0_x
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AQLPROFILE_BLOCK_NAME_CHA,
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AQLPROFILE_BLOCK_NAME_CHC,
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AQLPROFILE_BLOCK_NAME_GC_CANE,
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AQLPROFILE_BLOCK_NAME_GC_FFBM,
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AQLPROFILE_BLOCK_NAME_GC_L2TLB,
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AQLPROFILE_BLOCK_NAME_GC_UTCL1,
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AQLPROFILE_BLOCK_NAME_GC_UTCL2,
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AQLPROFILE_BLOCK_NAME_GC_VML2,
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AQLPROFILE_BLOCK_NAME_GC_VML2_SPM,
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AQLPROFILE_BLOCK_NAME_GCEA_SE,
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AQLPROFILE_BLOCK_NAME_GRBMH,
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AQLPROFILE_BLOCK_NAME_SQG,
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// Blocks reserved for NPI support
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AQLPROFILE_BLOCK_NAME_RESERVED_6,
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AQLPROFILE_BLOCK_NAME_RESERVED_7,
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AQLPROFILE_BLOCK_NAME_RESERVED_8,
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AQLPROFILE_BLOCK_NAME_RESERVED_9,
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// Add new blocks above
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AQLPROFILE_BLOCKS_NUMBER
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} aqlprofile_block_name_t;
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/**
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* @brief Flags to describe which agents can access given buffer.
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*/
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@@ -285,9 +285,14 @@ class GpuPmcBuilder : public PmcBuilder, protected Primitives {
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// std::endl;
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// Set GRBM index to access proper block instance
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const uint32_t grbm_value = (block_info->instance_count > 1)
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//
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// TODO: In order to get different event for different instance with WGP counter blocks, we
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// need to loop through WGP instead of blindly broadcast instance. Fortunately, this
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// is not a common practice
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const uint32_t grbm_value = (block_info->instance_count > 1 && !(block_info->attr & CounterBlockWgpAttr))
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? Primitives::grbm_inst_index_value(block_des.index)
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: Primitives::grbm_broadcast_value();
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builder.BuildWriteUConfigRegPacket(cmd_buffer, Primitives::GRBM_GFX_INDEX_ADDR, grbm_value);
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// Reset counters
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if (block_info->attr & CounterBlockMcAttr) {
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@@ -602,9 +607,12 @@ class GpuPmcBuilder : public PmcBuilder, protected Primitives {
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else
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grbm_value = Primitives::grbm_se_sh_wgp_index_value(se_index, sarray, wgp);
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builder.BuildWriteUConfigRegPacket(cmd_buffer, Primitives::GRBM_GFX_INDEX_ADDR, grbm_value);
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uint32_t dw_mask = reg_info.register_addr_hi.offset ? 3 : 1;
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builder.BuildCopyCounterDataPacket(
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cmd_buffer, reg_info.register_addr_lo, reg_info.register_addr_hi,
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reinterpret_cast<uint32_t*>(data_buffer) + read_counter, 1);
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reinterpret_cast<uint32_t*>(data_buffer) + read_counter, dw_mask);
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if (data_buffer && (dw_mask == 1))
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*(reinterpret_cast<uint32_t*>(data_buffer) + read_counter + 1) = 0;
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read_counter += 2;
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}
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} else {
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