Check open source core runtime code into perforce. This includes license and README files.
[git-p4: depot-paths = "//depot/stg/hsa/drivers/hsa/runtime/": change = 1249136]
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James Edwards (xN/A) TX
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////////////////////////////////////////////////////////////////////////////////
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//
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// The University of Illinois/NCSA
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// Open Source License (NCSA)
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//
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// Copyright (c) 2014-2015, Advanced Micro Devices, Inc. All rights reserved.
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//
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// Developed by:
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//
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// AMD Research and AMD HSA Software Development
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//
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// Advanced Micro Devices, Inc.
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//
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// www.amd.com
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy
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// of this software and associated documentation files (the "Software"), to
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// deal with the Software without restriction, including without limitation
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// the rights to use, copy, modify, merge, publish, distribute, sublicense,
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// and/or sell copies of the Software, and to permit persons to whom the
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// Software is furnished to do so, subject to the following conditions:
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//
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// - Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimers.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimers in
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// the documentation and/or other materials provided with the distribution.
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// - Neither the names of Advanced Micro Devices, Inc,
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// nor the names of its contributors may be used to endorse or promote
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// products derived from this Software without specific prior written
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// permission.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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// THE CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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// OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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// ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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// DEALINGS WITH THE SOFTWARE.
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//
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////////////////////////////////////////////////////////////////////////////////
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// HSA runtime C++ interface file.
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#ifndef HSA_RUNTME_CORE_INC_COMMAND_QUEUE_H_
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#define HSA_RUNTME_CORE_INC_COMMAND_QUEUE_H_
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#include <sstream>
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#include "core/common/shared.h"
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#include "core/inc/runtime.h"
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#include "core/inc/checked.h"
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#include "core/util/utils.h"
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#include "inc/amd_hsa_queue.h"
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namespace core {
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struct AqlPacket {
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union {
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hsa_kernel_dispatch_packet_t dispatch;
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hsa_barrier_and_packet_t barrier_and;
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hsa_barrier_or_packet_t barrier_or;
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hsa_agent_dispatch_packet_t agent;
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};
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uint8_t type() {
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return ((dispatch.header >> HSA_PACKET_HEADER_TYPE) &
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((1 << HSA_PACKET_HEADER_WIDTH_TYPE) - 1));
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}
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bool IsValid() {
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const uint8_t packet_type = dispatch.header >> HSA_PACKET_HEADER_TYPE;
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return (packet_type > HSA_PACKET_TYPE_INVALID &&
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packet_type <= HSA_PACKET_TYPE_BARRIER_OR);
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}
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std::string string() const {
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std::stringstream string;
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uint8_t type = ((dispatch.header >> HSA_PACKET_HEADER_TYPE) &
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((1 << HSA_PACKET_HEADER_WIDTH_TYPE) - 1));
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const char* type_names[] = {
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"HSA_PACKET_TYPE_VENDOR_SPECIFIC", "HSA_PACKET_TYPE_INVALID",
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"HSA_PACKET_TYPE_KERNEL_DISPATCH", "HSA_PACKET_TYPE_BARRIER_AND",
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"HSA_PACKET_TYPE_AGENT_DISPATCH", "HSA_PACKET_TYPE_BARRIER_OR"};
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string << "type: " << type_names[type]
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<< "\nbarrier: " << ((dispatch.header >> HSA_PACKET_HEADER_BARRIER) &
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((1 << HSA_PACKET_HEADER_WIDTH_BARRIER) - 1))
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<< "\nacquire: "
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<< ((dispatch.header >> HSA_PACKET_HEADER_ACQUIRE_FENCE_SCOPE) &
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((1 << HSA_PACKET_HEADER_WIDTH_ACQUIRE_FENCE_SCOPE) - 1))
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<< "\nrelease: "
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<< ((dispatch.header >> HSA_PACKET_HEADER_RELEASE_FENCE_SCOPE) &
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((1 << HSA_PACKET_HEADER_WIDTH_RELEASE_FENCE_SCOPE) - 1));
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if (type == HSA_PACKET_TYPE_KERNEL_DISPATCH) {
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string << "\nDim: " << dispatch.setup
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<< "\nworkgroup_size: " << dispatch.workgroup_size_x << ", "
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<< dispatch.workgroup_size_y << ", " << dispatch.workgroup_size_z
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<< "\ngrid_size: " << dispatch.grid_size_x << ", "
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<< dispatch.grid_size_y << ", " << dispatch.grid_size_z
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<< "\nprivate_size: " << dispatch.private_segment_size
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<< "\ngroup_size: " << dispatch.group_segment_size
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<< "\nkernel_object: " << dispatch.kernel_object
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<< "\nkern_arg: " << dispatch.kernarg_address
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<< "\nsignal: " << dispatch.completion_signal.handle;
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}
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if ((type == HSA_PACKET_TYPE_BARRIER_AND) ||
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(type == HSA_PACKET_TYPE_BARRIER_OR)) {
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for (int i = 0; i < 5; i++)
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string << "\ndep[" << i << "]: " << barrier_and.dep_signal[i].handle;
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string << "\nsignal: " << barrier_and.completion_signal.handle;
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}
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return string.str();
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}
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};
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class Queue;
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/// @brief Helper structure to simplify conversion of amd_queue_t and
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/// core::Queue object.
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struct SharedQueue {
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amd_queue_t amd_queue;
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Queue* core_queue;
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};
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/// @brief Class Queue which encapsulate user mode queues and
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/// provides Api to access its Read, Write indices using Acquire,
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/// Release and Relaxed semantics.
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/*
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Queue is intended to be an pure interface class and may be wrapped or replaced
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by tools.
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All funtions other than Convert and public_handle must be virtual.
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*/
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class Queue : public Checked<0xFA3906A679F9DB49>,
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public Shared<SharedQueue, AMD_QUEUE_ALIGN_BYTES> {
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public:
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Queue() : Shared(), amd_queue_(shared_object()->amd_queue) {
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if (!Shared::IsSharedObjectAllocationValid()) {
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return;
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}
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shared_object()->core_queue = this;
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public_handle_ = Convert(this);
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}
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virtual ~Queue() {}
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/// @brief Returns the handle of Queue's public data type
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///
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/// @param queue Pointer to an instance of Queue implementation object
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///
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/// @return hsa_queue_t * Pointer to the public data type of a queue
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static __forceinline hsa_queue_t* Convert(Queue* queue) {
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return ((queue != NULL) && (queue->IsSharedObjectAllocationValid()))
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? &queue->amd_queue_.hsa_queue
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: NULL;
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}
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/// @brief Transform the public data type of a Queue's data type into an
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// instance of it Queue class object
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///
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/// @param queue Handle of public data type of a queue
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///
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/// @return Queue * Pointer to the Queue's implementation object
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static __forceinline Queue* Convert(const hsa_queue_t* queue) {
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return (queue != NULL)
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? reinterpret_cast<const SharedQueue*>(
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reinterpret_cast<uintptr_t>(queue) -
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(reinterpret_cast<uintptr_t>(
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&reinterpret_cast<SharedQueue*>(1234)
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->amd_queue.hsa_queue) -
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uintptr_t(1234)))->core_queue
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: NULL;
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}
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/// @brief Inactivate the queue object. Once inactivate a
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/// queue cannot be used anymore and must be destroyed
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///
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/// @return hsa_status_t Status of request
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virtual hsa_status_t Inactivate() = 0;
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/// @brief Reads the Read Index of Queue using Acquire semantics
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///
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/// @return uint64_t Value of Read index
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virtual uint64_t LoadReadIndexAcquire() = 0;
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/// @brief Reads the Read Index of Queue using Relaxed semantics
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///
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/// @return uint64_t Value of Read index
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virtual uint64_t LoadReadIndexRelaxed() = 0;
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/// @brief Reads the Write Index of Queue using Acquire semantics
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///
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/// @return uint64_t Value of Write index
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virtual uint64_t LoadWriteIndexAcquire() = 0;
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/// Reads the Write Index of Queue using Relaxed semantics
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///
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/// @return uint64_t Value of Write index
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virtual uint64_t LoadWriteIndexRelaxed() = 0;
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/// @brief Updates the Read Index of Queue using Relaxed semantics
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///
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/// @param value New value of Read index to update
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virtual void StoreReadIndexRelaxed(uint64_t value) = 0;
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/// @brief Updates the Read Index of Queue using Release semantics
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///
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/// @param value New value of Read index to update
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virtual void StoreReadIndexRelease(uint64_t value) = 0;
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/// @brief Updates the Write Index of Queue using Relaxed semantics
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///
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/// @param value New value of Write index to update
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virtual void StoreWriteIndexRelaxed(uint64_t value) = 0;
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/// @brief Updates the Write Index of Queue using Release semantics
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///
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/// @param value New value of Write index to update
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virtual void StoreWriteIndexRelease(uint64_t value) = 0;
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/// @brief Compares and swaps Write index using Acquire and Release semantics
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///
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/// @param expected Current value of write index
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///
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/// @param value Value of new write index
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///
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/// @return uint64_t Value of write index before the update
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virtual uint64_t CasWriteIndexAcqRel(uint64_t expected, uint64_t value) = 0;
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/// @brief Compares and swaps Write index using Acquire semantics
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///
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/// @param expected Current value of write index
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///
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/// @param value Value of new write index
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///
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/// @return uint64_t Value of write index before the update
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virtual uint64_t CasWriteIndexAcquire(uint64_t expected, uint64_t value) = 0;
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/// @brief Compares and swaps Write index using Relaxed semantics
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///
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/// @param expected Current value of write index
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///
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/// @param value Value of new write index
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///
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/// @return uint64_t Value of write index before the update
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virtual uint64_t CasWriteIndexRelaxed(uint64_t expected, uint64_t value) = 0;
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/// @brief Compares and swaps Write index using Release semantics
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///
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/// @param expected Current value of write index
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///
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/// @param value Value of new write index
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///
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/// @return uint64_t Value of write index before the update
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virtual uint64_t CasWriteIndexRelease(uint64_t expected, uint64_t value) = 0;
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/// @brief Updates the Write index using Acquire and Release semantics
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///
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/// @param value Value of new write index
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///
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/// @return uint64_t Value of write index before the update
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virtual uint64_t AddWriteIndexAcqRel(uint64_t value) = 0;
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/// @brief Updates the Write index using Acquire semantics
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///
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/// @param value Value of new write index
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///
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/// @return uint64_t Value of write index before the update
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virtual uint64_t AddWriteIndexAcquire(uint64_t value) = 0;
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/// @brief Updates the Write index using Relaxed semantics
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///
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/// @param value Value of new write index
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///
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/// @return uint64_t Value of write index before the update
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virtual uint64_t AddWriteIndexRelaxed(uint64_t value) = 0;
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/// @brief Updates the Write index using Release semantics
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///
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/// @param value Value of new write index
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///
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/// @return uint64_t Value of write index before the update
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virtual uint64_t AddWriteIndexRelease(uint64_t value) = 0;
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/// @brief Set CU Masking
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///
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/// @param num_cu_mask_count size of mask bit array
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///
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/// @param cu_mask pointer to cu mask
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///
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/// @return hsa_status_t
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virtual hsa_status_t SetCUMasking(const uint32_t num_cu_mask_count,
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const uint32_t* cu_mask) = 0;
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// Handle of AMD Queue struct
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amd_queue_t& amd_queue_;
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hsa_queue_t* public_handle() const { return public_handle_; }
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protected:
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static void set_public_handle(Queue* ptr, hsa_queue_t* handle) {
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ptr->do_set_public_handle(handle);
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}
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virtual void do_set_public_handle(hsa_queue_t* handle) {
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public_handle_ = handle;
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}
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hsa_queue_t* public_handle_;
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private:
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DISALLOW_COPY_AND_ASSIGN(Queue);
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};
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}
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#endif // header guard
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