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SWDEV-292525 - [vdi] Path to streamOps shaders

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Implementation to use a blit kernel to perform
a hipStreamWait/write instead of an AQL packet.

Change-Id: I462671ed5cec37144dfe97ff66439249196117c1
This commit is contained in:
Sourabh
2021-08-31 16:13:17 +00:00
committed by Sourabh Betigeri
parent 60295a9da9
commit cbb8d82bdb
6 changed files with 169 additions and 45 deletions
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rocclr/device/rocm/rocblit.cpp
+77
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@@ -2278,6 +2278,83 @@ bool KernelBlitManager::fillImage(device::Memory& memory, const void* pattern,
return result;
}
// ================================================================================================
bool KernelBlitManager::streamOpsWrite(device::Memory& memory, uint64_t value,
size_t sizeBytes) const {
amd::ScopedLock k(lockXferOps_);
bool result = false;
uint blitType = StreamOpsWrite;
size_t dim = 1;
size_t globalWorkOffset[1] = { 0 };
size_t globalWorkSize[1] = { 1 };
size_t localWorkSize[1] = { 1 };
// Program kernels arguments for the write operation
cl_mem mem = as_cl<amd::Memory>(memory.owner());
bool is32BitWrite = (sizeBytes == sizeof(uint32_t)) ? true : false;
// Program kernels arguments for the write operation
if (is32BitWrite) {
setArgument(kernels_[blitType], 0, sizeof(cl_mem), &mem);
setArgument(kernels_[blitType], 1, sizeof(cl_mem), nullptr);
setArgument(kernels_[blitType], 2, sizeof(uint32_t), &value);
} else {
setArgument(kernels_[blitType], 0, sizeof(cl_mem), nullptr);
setArgument(kernels_[blitType], 1, sizeof(cl_mem), &mem);
setArgument(kernels_[blitType], 2, sizeof(uint64_t), &value);
}
setArgument(kernels_[blitType], 3, sizeof(size_t), &sizeBytes);
// Create ND range object for the kernel's execution
amd::NDRangeContainer ndrange(dim, globalWorkOffset, globalWorkSize, localWorkSize);
// Execute the blit
address parameters = captureArguments(kernels_[blitType]);
result = gpu().submitKernelInternal(ndrange, *kernels_[blitType], parameters, nullptr);
releaseArguments(parameters);
synchronize();
return result;
}
// ================================================================================================
bool KernelBlitManager::streamOpsWait(device::Memory& memory, uint64_t value, size_t sizeBytes,
uint64_t flags, uint64_t mask) const {
amd::ScopedLock k(lockXferOps_);
bool result = false;
uint blitType = StreamOpsWait;
size_t dim = 1;
size_t globalWorkOffset[1] = { 0 };
size_t globalWorkSize[1] = { 1 };
size_t localWorkSize[1] = { 1 };
// Program kernels arguments for the wait operation
cl_mem mem = as_cl<amd::Memory>(memory.owner());
bool is32BitWait = (sizeBytes == sizeof(uint32_t)) ? true : false;
// Program kernels arguments for the wait operation
if (is32BitWait) {
setArgument(kernels_[blitType], 0, sizeof(cl_mem), &mem);
setArgument(kernels_[blitType], 1, sizeof(cl_mem), nullptr);
setArgument(kernels_[blitType], 2, sizeof(uint32_t), &value);
setArgument(kernels_[blitType], 3, sizeof(uint32_t), &flags);
setArgument(kernels_[blitType], 4, sizeof(uint32_t), &mask);
} else {
setArgument(kernels_[blitType], 0, sizeof(cl_mem), nullptr);
setArgument(kernels_[blitType], 1, sizeof(cl_mem), &mem);
setArgument(kernels_[blitType], 2, sizeof(uint64_t), &value);
setArgument(kernels_[blitType], 3, sizeof(uint64_t), &flags);
setArgument(kernels_[blitType], 4, sizeof(uint64_t), &mask);
}
// Create ND range object for the kernel's execution
amd::NDRangeContainer ndrange(dim, globalWorkOffset, globalWorkSize, localWorkSize);
// Execute the blit
address parameters = captureArguments(kernels_[blitType]);
result = gpu().submitKernelInternal(ndrange, *kernels_[blitType], parameters, nullptr);
releaseArguments(parameters);
synchronize();
return result;
}
// ================================================================================================
amd::Memory* DmaBlitManager::pinHostMemory(const void* hostMem, size_t pinSize,
size_t& partial) const {
size_t pinAllocSize;