From ccf86da3c976615491696d542e1b692646e2bc11 Mon Sep 17 00:00:00 2001 From: foreman Date: Wed, 16 Aug 2017 20:11:30 -0400 Subject: [PATCH] P4 to Git Change 1448201 by smekhano@stas-nova-hsa on 2017/08/16 19:58:09 SWDEV-121551 - Complib: fix ocltst ACLApi regression after CL 1448141 (HSAIL part) Affected files ... ... //depot/stg/opencl/drivers/opencl/compiler/lib/utils/v0_8/libUtils.cpp#25 edit ... //depot/stg/opencl/drivers/opencl/compiler/lib/utils/v0_8/target_mappings_amdil.h#47 edit ... //depot/stg/opencl/drivers/opencl/compiler/lib/utils/v0_8/target_mappings_amdil64.h#43 edit ... //depot/stg/opencl/drivers/opencl/compiler/lib/utils/v0_8/target_mappings_hsail.h#46 edit ... //depot/stg/opencl/drivers/opencl/compiler/lib/utils/v0_8/target_mappings_hsail64.h#41 edit [ROCm/clr commit: 6622762df50597e9dde047003a12c8b362805e66] --- projects/clr/rocclr/compiler/lib/utils/v0_8/libUtils.cpp | 2 ++ .../rocclr/compiler/lib/utils/v0_8/target_mappings_amdil.h | 4 ++-- .../rocclr/compiler/lib/utils/v0_8/target_mappings_amdil64.h | 4 ++-- .../rocclr/compiler/lib/utils/v0_8/target_mappings_hsail.h | 4 ++-- .../rocclr/compiler/lib/utils/v0_8/target_mappings_hsail64.h | 4 ++-- 5 files changed, 10 insertions(+), 8 deletions(-) diff --git a/projects/clr/rocclr/compiler/lib/utils/v0_8/libUtils.cpp b/projects/clr/rocclr/compiler/lib/utils/v0_8/libUtils.cpp index 5787b47c56..a6775d991f 100644 --- a/projects/clr/rocclr/compiler/lib/utils/v0_8/libUtils.cpp +++ b/projects/clr/rocclr/compiler/lib/utils/v0_8/libUtils.cpp @@ -566,7 +566,9 @@ int getIsaType(const aclTargetInfo *target) case VI_ICELAND_M_A0: return 800; case VI_FIJI_P_A0: case VI_BAFFIN_M_A0: + case VI_BAFFIN_M_A1: case VI_ELLESMERE_P_A0: + case VI_ELLESMERE_P_A1: case VI_LEXA_V_A0: case VI_POLARIS22_P_A0: #if defined(BUILD_HSA_TARGET) diff --git a/projects/clr/rocclr/compiler/lib/utils/v0_8/target_mappings_amdil.h b/projects/clr/rocclr/compiler/lib/utils/v0_8/target_mappings_amdil.h index d4f923aaee..f92add3ac1 100644 --- a/projects/clr/rocclr/compiler/lib/utils/v0_8/target_mappings_amdil.h +++ b/projects/clr/rocclr/compiler/lib/utils/v0_8/target_mappings_amdil.h @@ -98,9 +98,9 @@ static const TargetMapping AMDILTargetMapping_0_8[] = { { "CI", "Bonaire", "bonaire", amd::GPU_Library_CI, CI_BONAIRE_M_A1, F_SI_BASE, true, true, FAMILY_CI }, { "VI", "Fiji", "fiji", amd::GPU_Library_CI, VI_FIJI_P_A0, F_SI_BASE, true, true, FAMILY_VI }, { "CZ", "Stoney", "stoney", amd::GPU_Library_CI, STONEY_A0, F_SI_BASE, true, true, FAMILY_CZ }, - { "VI", "Baffin", "baffin", amd::GPU_Library_CI, VI_BAFFIN_M_A0, F_SI_BASE, true, true, FAMILY_VI }, + { "VI", "Baffin", "baffin", amd::GPU_Library_CI, VI_BAFFIN_M_A0, F_SI_BASE, true, false, FAMILY_VI }, { "VI", "Baffin", "baffin", amd::GPU_Library_CI, VI_BAFFIN_M_A1, F_SI_BASE, true, true, FAMILY_VI }, - { "VI", "Ellesmere", "ellesmere", amd::GPU_Library_CI, VI_ELLESMERE_P_A0, F_SI_BASE, true, true, FAMILY_VI }, + { "VI", "Ellesmere", "ellesmere", amd::GPU_Library_CI, VI_ELLESMERE_P_A0, F_SI_BASE, true, false, FAMILY_VI }, { "VI", "Ellesmere", "ellesmere", amd::GPU_Library_CI, VI_ELLESMERE_P_A1, F_SI_BASE, true, true, FAMILY_VI }, #ifndef BRAHMA { "VI", "gfx804", "gfx804", amd::GPU_Library_CI, VI_LEXA_V_A0, F_SI_BASE, true, true, FAMILY_VI }, diff --git a/projects/clr/rocclr/compiler/lib/utils/v0_8/target_mappings_amdil64.h b/projects/clr/rocclr/compiler/lib/utils/v0_8/target_mappings_amdil64.h index 8851ffcd75..7a264b083f 100644 --- a/projects/clr/rocclr/compiler/lib/utils/v0_8/target_mappings_amdil64.h +++ b/projects/clr/rocclr/compiler/lib/utils/v0_8/target_mappings_amdil64.h @@ -44,9 +44,9 @@ static const TargetMapping AMDIL64TargetMapping_0_8[] = { { "CI", "Bonaire", "bonaire", amd::GPU64_Library_CI, CI_BONAIRE_M_A0, F_SI_64BIT_PTR, true, true, FAMILY_CI }, { "VI", "Fiji", "fiji", amd::GPU64_Library_CI, VI_FIJI_P_A0, F_SI_64BIT_PTR, true, true, FAMILY_VI }, { "CZ", "Stoney", "stoney", amd::GPU64_Library_CI, STONEY_A0, F_SI_64BIT_PTR, true, true, FAMILY_CZ }, - { "VI", "Baffin", "baffin", amd::GPU64_Library_CI, VI_BAFFIN_M_A0, F_SI_64BIT_PTR, true, true, FAMILY_VI }, + { "VI", "Baffin", "baffin", amd::GPU64_Library_CI, VI_BAFFIN_M_A0, F_SI_64BIT_PTR, true, false, FAMILY_VI }, { "VI", "Baffin", "baffin", amd::GPU64_Library_CI, VI_BAFFIN_M_A1, F_SI_64BIT_PTR, true, true, FAMILY_VI }, - { "VI", "Ellesmere", "ellesmere", amd::GPU64_Library_CI, VI_ELLESMERE_P_A0, F_SI_64BIT_PTR, true, true, FAMILY_VI }, + { "VI", "Ellesmere", "ellesmere", amd::GPU64_Library_CI, VI_ELLESMERE_P_A0, F_SI_64BIT_PTR, true, false, FAMILY_VI }, { "VI", "Ellesmere", "ellesmere", amd::GPU64_Library_CI, VI_ELLESMERE_P_A1, F_SI_64BIT_PTR, true, true, FAMILY_VI }, #ifndef BRAHMA { "VI", "gfx804", "gfx804", amd::GPU64_Library_CI, VI_LEXA_V_A0, F_SI_64BIT_PTR, true, true, FAMILY_VI }, diff --git a/projects/clr/rocclr/compiler/lib/utils/v0_8/target_mappings_hsail.h b/projects/clr/rocclr/compiler/lib/utils/v0_8/target_mappings_hsail.h index 95969dc8e6..b7b6b5dff7 100644 --- a/projects/clr/rocclr/compiler/lib/utils/v0_8/target_mappings_hsail.h +++ b/projects/clr/rocclr/compiler/lib/utils/v0_8/target_mappings_hsail.h @@ -29,9 +29,9 @@ static const TargetMapping HSAILTargetMapping_0_8[] = { { "CZ", "Carrizo", "GFX8", amd::GPU_Library_HSAIL, CARRIZO_A0, F_VI_BASE, true, true, FAMILY_CZ }, { "VI", "Fiji", "GFX8", amd::GPU_Library_HSAIL, VI_FIJI_P_A0, F_VI_BASE, true, true, FAMILY_VI }, { "CZ", "Stoney", "GFX8", amd::GPU_Library_HSAIL, STONEY_A0, F_VI_BASE, true, true, FAMILY_CZ }, - { "VI", "Baffin", "GFX8", amd::GPU_Library_HSAIL, VI_BAFFIN_M_A0, F_VI_BASE, true, true, FAMILY_VI }, + { "VI", "Baffin", "GFX8", amd::GPU_Library_HSAIL, VI_BAFFIN_M_A0, F_VI_BASE, true, false, FAMILY_VI }, { "VI", "Baffin", "GFX8", amd::GPU_Library_HSAIL, VI_BAFFIN_M_A1, F_VI_BASE, true, true, FAMILY_VI }, - { "VI", "Ellesmere", "GFX8", amd::GPU_Library_HSAIL, VI_ELLESMERE_P_A0, F_VI_BASE, true, true, FAMILY_VI }, + { "VI", "Ellesmere", "GFX8", amd::GPU_Library_HSAIL, VI_ELLESMERE_P_A0, F_VI_BASE, true, false, FAMILY_VI }, { "VI", "Ellesmere", "GFX8", amd::GPU_Library_HSAIL, VI_ELLESMERE_P_A1, F_VI_BASE, true, true, FAMILY_VI }, #ifndef BRAHMA { "AI", "gfx900", "GFX9", amd::GPU_Library_HSAIL, AI_GREENLAND_P_A0, F_AI_BASE, true, true, FAMILY_AI }, diff --git a/projects/clr/rocclr/compiler/lib/utils/v0_8/target_mappings_hsail64.h b/projects/clr/rocclr/compiler/lib/utils/v0_8/target_mappings_hsail64.h index 25dcb75fc2..c45be57b0d 100644 --- a/projects/clr/rocclr/compiler/lib/utils/v0_8/target_mappings_hsail64.h +++ b/projects/clr/rocclr/compiler/lib/utils/v0_8/target_mappings_hsail64.h @@ -28,9 +28,9 @@ static const TargetMapping HSAIL64TargetMapping_0_8[] = { { "CZ", "Carrizo", "GFX8", amd::GPU_Library_HSAIL, CARRIZO_A0, F_VI_BASE, true, true, FAMILY_CZ }, { "VI", "Fiji", "GFX8", amd::GPU_Library_HSAIL, VI_FIJI_P_A0, F_VI_BASE, true, true, FAMILY_VI }, { "CZ", "Stoney", "GFX8", amd::GPU_Library_HSAIL, STONEY_A0, F_VI_BASE, true, true, FAMILY_CZ }, - { "VI", "Baffin", "GFX8", amd::GPU_Library_HSAIL, VI_BAFFIN_M_A0, F_VI_BASE, true, true, FAMILY_VI }, + { "VI", "Baffin", "GFX8", amd::GPU_Library_HSAIL, VI_BAFFIN_M_A0, F_VI_BASE, true, false, FAMILY_VI }, { "VI", "Baffin", "GFX8", amd::GPU_Library_HSAIL, VI_BAFFIN_M_A1, F_VI_BASE, true, true, FAMILY_VI }, - { "VI", "Ellesmere", "GFX8", amd::GPU_Library_HSAIL, VI_ELLESMERE_P_A0, F_VI_BASE, true, true, FAMILY_VI }, + { "VI", "Ellesmere", "GFX8", amd::GPU_Library_HSAIL, VI_ELLESMERE_P_A0, F_VI_BASE, true, false, FAMILY_VI }, { "VI", "Ellesmere", "GFX8", amd::GPU_Library_HSAIL, VI_ELLESMERE_P_A1, F_VI_BASE, true, true, FAMILY_VI }, #ifndef BRAHMA { "AI", "gfx900", "GFX9", amd::GPU_Library_HSAIL, AI_GREENLAND_P_A0, F_AI_BASE, true, true, FAMILY_AI },