diff --git a/projects/clr/rocclr/device/pal/paldevice.cpp b/projects/clr/rocclr/device/pal/paldevice.cpp index f11ef5b409..ecd382db40 100644 --- a/projects/clr/rocclr/device/pal/paldevice.cpp +++ b/projects/clr/rocclr/device/pal/paldevice.cpp @@ -2266,7 +2266,7 @@ void* Device::svmAlloc(amd::Context& context, size_t size, size_t alignment, cl_ constexpr bool kForceAllocation = true; alignment = std::max(alignment, static_cast(info_.memBaseAddrAlign_)); - if (amd::IS_HIP) { + if (amd::IS_HIP && PAL_HIP_IPC_FLAG) { //set interprocess for IPC memory support flags |= ROCCLR_MEM_INTERPROCESS; } diff --git a/projects/clr/rocclr/device/pal/palresource.cpp b/projects/clr/rocclr/device/pal/palresource.cpp index c5058bf56d..dae5c4f7aa 100644 --- a/projects/clr/rocclr/device/pal/palresource.cpp +++ b/projects/clr/rocclr/device/pal/palresource.cpp @@ -2057,7 +2057,7 @@ bool CoarseMemorySubAllocator::CreateChunk(const Pal::IGpuMemory* reserved_va) { createInfo.heaps[0] = Pal::GpuHeapInvisible; createInfo.heaps[1] = Pal::GpuHeapLocal; createInfo.mallPolicy = static_cast(device_->settings().mallPolicy_); - if (amd::IS_HIP) { + if (amd::IS_HIP && PAL_HIP_IPC_FLAG) { //set interprocess for IPC memory support createInfo.flags.interprocess = 1; } diff --git a/projects/clr/rocclr/utils/flags.hpp b/projects/clr/rocclr/utils/flags.hpp index 926d63bf0e..3fdd0b9765 100644 --- a/projects/clr/rocclr/utils/flags.hpp +++ b/projects/clr/rocclr/utils/flags.hpp @@ -253,6 +253,8 @@ release(bool, HIP_MEM_POOL_SUPPORT, false, \ "Enables memory pool support in HIP") \ release(bool, HIP_MEM_POOL_USE_VM, IS_WINDOWS, \ "Enables memory pool support in HIP") \ +release(bool, PAL_HIP_IPC_FLAG, false, \ + "Enable interprocess flag for device allocation in PAL HIP") \ release(uint, PAL_FORCE_ASIC_REVISION, 0, \ "Force a specific asic revision for all devices") \ release(bool, PAL_EMBED_KERNEL_MD, false, \