From d287c60246026ccb6db5208afccc895520fd24cf Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Fri, 26 Feb 2021 17:25:56 -0500 Subject: [PATCH] libhsakmt: New SRAM EDC support bit The old bit was deprecated, because old buggy user mode depends on it being always 0. The correct value is now reported in a new bit. New user mode handles the reported EDC setting correctly, so we can report the correct value in a new bit. Signed-off-by: Felix Kuehling Change-Id: Ib5d5ed2519810e650458c6b69c97670dab435ddb --- include/hsakmttypes.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/include/hsakmttypes.h b/include/hsakmttypes.h index a12c5c1200..0ae74d9400 100644 --- a/include/hsakmttypes.h +++ b/include/hsakmttypes.h @@ -209,11 +209,12 @@ typedef union unsigned int WaveLaunchTrapOverrideSupported: 1; // Indicates if Wave Launch Trap Override is supported on the node. unsigned int WaveLaunchModeSupported: 1; // Indicates if Wave Launch Mode is supported on the node. unsigned int PreciseMemoryOperationsSupported: 1; // Indicates if Precise Memory Operations are supported on the node. - unsigned int SRAM_EDCSupport: 1; // Indicates if GFX internal SRAM EDC/ECC functionality is active + unsigned int DEPRECATED_SRAM_EDCSupport: 1; // Old buggy user mode depends on this being 0 unsigned int Mem_EDCSupport: 1; // Indicates if GFX internal DRAM/HBM EDC/ECC functionality is active unsigned int RASEventNotify: 1; // Indicates if GFX extended RASFeatures and RAS EventNotify status is available unsigned int ASICRevision: 4; // Indicates the ASIC revision of the chip on this node. - unsigned int Reserved : 6; + unsigned int SRAM_EDCSupport: 1; // Indicates if GFX internal SRAM EDC/ECC functionality is active + unsigned int Reserved : 5; } ui32; } HSA_CAPABILITY;