Revise PCI BW numbers on Rome
此提交包含在:
+3
-3
@@ -21,9 +21,9 @@
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#define SKL_CPUPCI_WIDTH 12
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#define P9_WIDTH 32
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#define NET_WIDTH 12 // 100Gbit
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#define ROME_QPI_WIDTH 24
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#define ROME_PCI_WIDTH 24
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#define ROME_CPUPCI_WIDTH 24
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#define ROME_QPI_WIDTH 18
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#define ROME_PCI_WIDTH 18
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#define ROME_CPUPCI_WIDTH 18
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// Intel CPU convert GPU P2P traffic into 64B PCI TLPs, to GPU
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// to GPU traffic consumed more PCI bandwidth.
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