SWDEV-453301 - Remove the option to write multiple packets in dispatchGenericAqlPacket
Dispatching multiple packets with ring the doorbell once is not supported by the lower layers Change-Id: I7665a2dcdd4ef9e47dadfe410180fed64c5a4ee0
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Ioannis Assiouras committed
1 szülő
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commit
d7f352dbed
4 files changed
+35
-59
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@@ -832,13 +832,13 @@ static inline void packet_store_release(uint32_t* packet, uint16_t header, uint1
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// ================================================================================================
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template <typename AqlPacket>
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bool VirtualGPU::dispatchGenericAqlPacket(
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AqlPacket* packet, uint16_t header, uint16_t rest, bool blocking, size_t size) {
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AqlPacket* packet, uint16_t header, uint16_t rest, bool blocking) {
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const uint32_t queueSize = gpu_queue_->size;
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const uint32_t queueMask = queueSize - 1;
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const uint32_t sw_queue_size = queueMask;
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// Check for queue full and wait if needed.
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uint64_t index = hsa_queue_add_write_index_screlease(gpu_queue_, size);
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uint64_t index = hsa_queue_add_write_index_screlease(gpu_queue_, 1);
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uint64_t read = hsa_queue_load_read_index_relaxed(gpu_queue_);
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if (addSystemScope_) {
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header &= ~(HSA_FENCE_SCOPE_AGENT << HSA_PACKET_HEADER_SCACQUIRE_FENCE_SCOPE |
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@@ -887,43 +887,38 @@ bool VirtualGPU::dispatchGenericAqlPacket(
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blocking = true;
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}
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// Insert packet(s)
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// NOTE: need multiple packets to dispatch the performance counter
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// packet blob of the legacy devices (gfx8)
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for (uint i = 0; i < size; i++, index++, packet++) {
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AqlPacket* aql_loc = &((AqlPacket*)(gpu_queue_->base_address))[index & queueMask];
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*aql_loc = *packet;
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if (header != 0) {
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packet_store_release(reinterpret_cast<uint32_t*>(aql_loc), header, rest);
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}
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ClPrint(amd::LOG_DEBUG, amd::LOG_AQL,
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"SWq=0x%zx, HWq=0x%zx, id=%d, Dispatch Header = "
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"0x%x (type=%d, barrier=%d, acquire=%d, release=%d), "
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"setup=%d, grid=[%zu, %zu, %zu], workgroup=[%zu, %zu, %zu], private_seg_size=%zu, "
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"group_seg_size=%zu, kernel_obj=0x%zx, kernarg_address=0x%zx, completion_signal=0x%zx "
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"rptr=%u, wptr=%u",
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gpu_queue_, gpu_queue_->base_address, gpu_queue_->id, header,
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extractAqlBits(header, HSA_PACKET_HEADER_TYPE, HSA_PACKET_HEADER_WIDTH_TYPE),
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extractAqlBits(header, HSA_PACKET_HEADER_BARRIER, HSA_PACKET_HEADER_WIDTH_BARRIER),
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extractAqlBits(header, HSA_PACKET_HEADER_SCACQUIRE_FENCE_SCOPE,
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HSA_PACKET_HEADER_WIDTH_SCACQUIRE_FENCE_SCOPE),
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extractAqlBits(header, HSA_PACKET_HEADER_SCRELEASE_FENCE_SCOPE,
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HSA_PACKET_HEADER_WIDTH_SCRELEASE_FENCE_SCOPE),
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rest, reinterpret_cast<hsa_kernel_dispatch_packet_t*>(packet)->grid_size_x,
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reinterpret_cast<hsa_kernel_dispatch_packet_t*>(packet)->grid_size_y,
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reinterpret_cast<hsa_kernel_dispatch_packet_t*>(packet)->grid_size_z,
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reinterpret_cast<hsa_kernel_dispatch_packet_t*>(packet)->workgroup_size_x,
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reinterpret_cast<hsa_kernel_dispatch_packet_t*>(packet)->workgroup_size_y,
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reinterpret_cast<hsa_kernel_dispatch_packet_t*>(packet)->workgroup_size_z,
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reinterpret_cast<hsa_kernel_dispatch_packet_t*>(packet)->private_segment_size,
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reinterpret_cast<hsa_kernel_dispatch_packet_t*>(packet)->group_segment_size,
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reinterpret_cast<hsa_kernel_dispatch_packet_t*>(packet)->kernel_object,
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reinterpret_cast<hsa_kernel_dispatch_packet_t*>(packet)->kernarg_address,
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reinterpret_cast<hsa_kernel_dispatch_packet_t*>(packet)->completion_signal, read,
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index);
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AqlPacket* aql_loc = &((AqlPacket*)(gpu_queue_->base_address))[index & queueMask];
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*aql_loc = *packet;
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if (header != 0) {
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packet_store_release(reinterpret_cast<uint32_t*>(aql_loc), header, rest);
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}
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ClPrint(amd::LOG_DEBUG, amd::LOG_AQL,
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"SWq=0x%zx, HWq=0x%zx, id=%d, Dispatch Header = "
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"0x%x (type=%d, barrier=%d, acquire=%d, release=%d), "
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"setup=%d, grid=[%zu, %zu, %zu], workgroup=[%zu, %zu, %zu], private_seg_size=%zu, "
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"group_seg_size=%zu, kernel_obj=0x%zx, kernarg_address=0x%zx, completion_signal=0x%zx "
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"rptr=%u, wptr=%u",
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gpu_queue_, gpu_queue_->base_address, gpu_queue_->id, header,
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extractAqlBits(header, HSA_PACKET_HEADER_TYPE, HSA_PACKET_HEADER_WIDTH_TYPE),
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extractAqlBits(header, HSA_PACKET_HEADER_BARRIER, HSA_PACKET_HEADER_WIDTH_BARRIER),
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extractAqlBits(header, HSA_PACKET_HEADER_SCACQUIRE_FENCE_SCOPE,
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HSA_PACKET_HEADER_WIDTH_SCACQUIRE_FENCE_SCOPE),
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extractAqlBits(header, HSA_PACKET_HEADER_SCRELEASE_FENCE_SCOPE,
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HSA_PACKET_HEADER_WIDTH_SCRELEASE_FENCE_SCOPE),
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rest, reinterpret_cast<hsa_kernel_dispatch_packet_t*>(packet)->grid_size_x,
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reinterpret_cast<hsa_kernel_dispatch_packet_t*>(packet)->grid_size_y,
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reinterpret_cast<hsa_kernel_dispatch_packet_t*>(packet)->grid_size_z,
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reinterpret_cast<hsa_kernel_dispatch_packet_t*>(packet)->workgroup_size_x,
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reinterpret_cast<hsa_kernel_dispatch_packet_t*>(packet)->workgroup_size_y,
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reinterpret_cast<hsa_kernel_dispatch_packet_t*>(packet)->workgroup_size_z,
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reinterpret_cast<hsa_kernel_dispatch_packet_t*>(packet)->private_segment_size,
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reinterpret_cast<hsa_kernel_dispatch_packet_t*>(packet)->group_segment_size,
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reinterpret_cast<hsa_kernel_dispatch_packet_t*>(packet)->kernel_object,
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reinterpret_cast<hsa_kernel_dispatch_packet_t*>(packet)->kernarg_address,
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reinterpret_cast<hsa_kernel_dispatch_packet_t*>(packet)->completion_signal, read,
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index);
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hsa_signal_store_screlease(gpu_queue_->doorbell_signal, index - 1);
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hsa_signal_store_screlease(gpu_queue_->doorbell_signal, index);
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// Mark the flag indicating if a dispatch is outstanding.
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// We are not waiting after every dispatch.
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@@ -984,9 +979,8 @@ inline bool VirtualGPU::dispatchAqlPacket(uint8_t* aqlpacket, amd::AccumulateCom
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profilingBegin(*vcmd, true);
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}
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dispatchBlockingWait();
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constexpr size_t kPacketSize = 1;
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auto packet = reinterpret_cast<hsa_kernel_dispatch_packet_t*>(aqlpacket);
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dispatchGenericAqlPacket(packet, packet->header, packet->setup, false, kPacketSize);
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dispatchGenericAqlPacket(packet, packet->header, packet->setup, false);
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if (vcmd != nullptr) {
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profilingEnd(*vcmd);
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}
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@@ -1003,13 +997,6 @@ bool VirtualGPU::dispatchCounterAqlPacket(hsa_ext_amd_aql_pm4_packet_t* packet,
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// In GFX8 the PM4 IB packet blob is writing directly to AQL queue
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// In GFX9 the PM4 IB is submitting by AQL Vendor Specific packet and
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switch (gfxVersion) {
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case PerfCounter::ROC_GFX8:
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{ // Create legacy devices PM4 data
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hsa_ext_amd_aql_pm4_packet_t pm4Packet[SLOT_PM4_SIZE_AQLP];
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extApi->hsa_ven_amd_aqlprofile_legacy_get_pm4(packet, static_cast<void*>(&pm4Packet[0]));
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return dispatchGenericAqlPacket(&pm4Packet[0], 0, 0, blocking, SLOT_PM4_SIZE_AQLP);
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}
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break;
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case PerfCounter::ROC_GFX9:
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case PerfCounter::ROC_GFX10:
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{
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@@ -3468,9 +3455,8 @@ void VirtualGPU::submitAccumulate(amd::AccumulateCommand& vcmd) {
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uint8_t* aqlPacket = vcmd.getLastPacket();
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if (aqlPacket != nullptr) {
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dispatchBlockingWait();
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constexpr size_t kPacketSize = 1;
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auto packet = reinterpret_cast<hsa_kernel_dispatch_packet_t*>(aqlPacket);
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dispatchGenericAqlPacket(packet, packet->header, packet->setup, false, kPacketSize);
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dispatchGenericAqlPacket(packet, packet->header, packet->setup, false);
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// We need to set fence_dirty_ flag as we would use a dispatch packet with a completion signal
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// to track graph finish for the last. The sync logic assumes HW event to a barrier packet that
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// has a system scope release. This would cause isFenceDirty() check at top level to insert
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