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SWDEV-368235 - Revert "Remove obsolete env variables"

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This reverts commit dfa7790030.

Reason for revert: Deferred to a future release.

Change-Id: Ia66c37f0ab9734dee73c930d10d7469d5fd57254


[ROCm/clr commit: 5dc104b3ea]
This commit is contained in:
Maneesh Gupta
2023-02-15 07:23:23 +00:00
parent 24eec94928
commit d7fdd9fcb8
12 changed files with 273 additions and 106 deletions
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projects/clr/rocclr/device/device.cpp
+11
View File
@@ -798,6 +798,17 @@ Settings::Settings() : value_(0) {
commandQueues_ = 200; //!< Field value set to maximum number
//!< concurrent Virtual GPUs for default
overrideLclSet = (!flagIsDefault(GPU_MAX_WORKGROUP_SIZE)) ? 1 : 0;
overrideLclSet |=
(!flagIsDefault(GPU_MAX_WORKGROUP_SIZE_2D_X) || !flagIsDefault(GPU_MAX_WORKGROUP_SIZE_2D_Y))
? 2
: 0;
overrideLclSet |=
(!flagIsDefault(GPU_MAX_WORKGROUP_SIZE_3D_X) || !flagIsDefault(GPU_MAX_WORKGROUP_SIZE_3D_Y) ||
!flagIsDefault(GPU_MAX_WORKGROUP_SIZE_3D_Z))
? 4
: 0;
fenceScopeAgent_ = AMD_OPT_FLUSH;
if (amd::IS_HIP) {
if (flagIsDefault(GPU_SINGLE_ALLOC_PERCENT)) {
projects/clr/rocclr/device/device.hpp
+2 -1
View File
@@ -619,6 +619,7 @@ class Settings : public amd::HeapObject {
uint64_t extensions_; //!< Supported OCL extensions
union {
struct {
uint overrideLclSet : 3; //!< Bit mask to override the local size
uint apuSystem_ : 1; //!< Device is APU system with shared memory
uint supportRA_ : 1; //!< Support RA channel order format
uint waitCommand_ : 1; //!< Enables a wait for every submitted command
@@ -638,7 +639,7 @@ class Settings : public amd::HeapObject {
uint enableCoopMultiDeviceGroups_ : 1; //!< Enable cooperative groups multi device
uint fenceScopeAgent_ : 1; //!< Enable fence scope agent in AQL dispatch packet
uint rocr_backend_ : 1; //!< Device uses ROCr backend for submissions
uint reserved_ : 14;
uint reserved_ : 11;
};
uint value_;
};
projects/clr/rocclr/device/devkernel.cpp
+85 -65
View File
@@ -677,78 +677,98 @@ void Kernel::FindLocalWorkSize(size_t workDim, const amd::NDRange& gblWorkSize,
if (workGroupInfo()->compileSize_[0] == 0) {
// Find the default local workgroup size, if it wasn't specified
if (lclWorkSize[0] == 0) {
// Find threads per group
size_t thrPerGrp = workGroupInfo()->size_;
if ((device().settings().overrideLclSet & (1 << (workDim - 1))) == 0) {
// Find threads per group
size_t thrPerGrp = workGroupInfo()->size_;
// Check if kernel uses images
if (flags_.imageEna_ &&
// and thread group is a multiple value of wavefronts
((thrPerGrp % workGroupInfo()->wavefrontSize_) == 0) &&
// and it's 2 or 3-dimensional workload
(workDim > 1) && (((gblWorkSize[0] % 16) == 0) && ((gblWorkSize[1] % 16) == 0))) {
// Use 8x8 workgroup size if kernel has image writes
if (flags_.imageWriteEna_ || (thrPerGrp != device().info().preferredWorkGroupSize_)) {
lclWorkSize[0] = 8;
lclWorkSize[1] = 8;
// Check if kernel uses images
if (flags_.imageEna_ &&
// and thread group is a multiple value of wavefronts
((thrPerGrp % workGroupInfo()->wavefrontSize_) == 0) &&
// and it's 2 or 3-dimensional workload
(workDim > 1) && (((gblWorkSize[0] % 16) == 0) && ((gblWorkSize[1] % 16) == 0))) {
// Use 8x8 workgroup size if kernel has image writes
if (flags_.imageWriteEna_ || (thrPerGrp != device().info().preferredWorkGroupSize_)) {
lclWorkSize[0] = 8;
lclWorkSize[1] = 8;
}
else {
lclWorkSize[0] = 16;
lclWorkSize[1] = 16;
}
if (workDim == 3) {
lclWorkSize[2] = 1;
}
}
else {
lclWorkSize[0] = 16;
lclWorkSize[1] = 16;
}
if (workDim == 3) {
lclWorkSize[2] = 1;
size_t tmp = thrPerGrp;
// Split the local workgroup into the most efficient way
for (uint d = 0; d < workDim; ++d) {
size_t div = tmp;
for (; (gblWorkSize[d] % div) != 0; div--)
;
lclWorkSize[d] = div;
tmp /= div;
}
// Assuming DWORD access
const uint cacheLineMatch = device().info().globalMemCacheLineSize_ >> 2;
// Check if we couldn't find optimal workload
if (((lclWorkSize.product() % workGroupInfo()->wavefrontSize_) != 0) ||
// or size is too small for the cache line
(lclWorkSize[0] < cacheLineMatch)) {
size_t maxSize = 0;
size_t maxDim = 0;
for (uint d = 0; d < workDim; ++d) {
if (maxSize < gblWorkSize[d]) {
maxSize = gblWorkSize[d];
maxDim = d;
}
}
// Use X dimension as high priority. Runtime will assume that
// X dimension is more important for the address calculation
if ((maxDim != 0) && (gblWorkSize[0] >= (cacheLineMatch / 2))) {
lclWorkSize[0] = cacheLineMatch;
thrPerGrp /= cacheLineMatch;
lclWorkSize[maxDim] = thrPerGrp;
for (uint d = 1; d < workDim; ++d) {
if (d != maxDim) {
lclWorkSize[d] = 1;
}
}
}
else {
// Check if a local workgroup has the most optimal size
if (thrPerGrp > maxSize) {
thrPerGrp = maxSize;
}
lclWorkSize[maxDim] = thrPerGrp;
for (uint d = 0; d < workDim; ++d) {
if (d != maxDim) {
lclWorkSize[d] = 1;
}
}
}
}
}
}
else {
size_t tmp = thrPerGrp;
// Split the local workgroup into the most efficient way
for (uint d = 0; d < workDim; ++d) {
size_t div = tmp;
for (; (gblWorkSize[d] % div) != 0; div--)
;
lclWorkSize[d] = div;
tmp /= div;
// Use overrides when app doesn't provide workgroup dimensions
if (workDim == 1) {
lclWorkSize[0] = GPU_MAX_WORKGROUP_SIZE;
}
// Assuming DWORD access
const uint cacheLineMatch = device().info().globalMemCacheLineSize_ >> 2;
// Check if we couldn't find optimal workload
if (((lclWorkSize.product() % workGroupInfo()->wavefrontSize_) != 0) ||
// or size is too small for the cache line
(lclWorkSize[0] < cacheLineMatch)) {
size_t maxSize = 0;
size_t maxDim = 0;
for (uint d = 0; d < workDim; ++d) {
if (maxSize < gblWorkSize[d]) {
maxSize = gblWorkSize[d];
maxDim = d;
}
}
// Use X dimension as high priority. Runtime will assume that
// X dimension is more important for the address calculation
if ((maxDim != 0) && (gblWorkSize[0] >= (cacheLineMatch / 2))) {
lclWorkSize[0] = cacheLineMatch;
thrPerGrp /= cacheLineMatch;
lclWorkSize[maxDim] = thrPerGrp;
for (uint d = 1; d < workDim; ++d) {
if (d != maxDim) {
lclWorkSize[d] = 1;
}
}
}
else {
// Check if a local workgroup has the most optimal size
if (thrPerGrp > maxSize) {
thrPerGrp = maxSize;
}
lclWorkSize[maxDim] = thrPerGrp;
for (uint d = 0; d < workDim; ++d) {
if (d != maxDim) {
lclWorkSize[d] = 1;
}
}
}
else if (workDim == 2) {
lclWorkSize[0] = GPU_MAX_WORKGROUP_SIZE_2D_X;
lclWorkSize[1] = GPU_MAX_WORKGROUP_SIZE_2D_Y;
}
else if (workDim == 3) {
lclWorkSize[0] = GPU_MAX_WORKGROUP_SIZE_3D_X;
lclWorkSize[1] = GPU_MAX_WORKGROUP_SIZE_3D_Y;
lclWorkSize[2] = GPU_MAX_WORKGROUP_SIZE_3D_Z;
}
else {
assert(0 && "Invalid workDim!");
}
}
}
projects/clr/rocclr/device/pal/paldevice.cpp
+2 -2
View File
@@ -291,7 +291,7 @@ bool NullDevice::create(const char* palName, const amd::Isa& isa, Pal::GfxIpLeve
nullptr,
nullptr,
nullptr,
nullptr};
AMD_OCL_SC_LIB};
// Initialize the compiler handle
acl_error error;
compiler_ = amd::Hsail::CompilerInit(&opts, &error);
@@ -1013,7 +1013,7 @@ bool Device::create(Pal::IDevice* device) {
nullptr,
nullptr,
nullptr,
nullptr};
AMD_OCL_SC_LIB};
// Initialize the compiler handle
acl_error error;
compiler_ = amd::Hsail::CompilerInit(&opts, &error);
projects/clr/rocclr/device/pal/palsettings.cpp
+35 -4
View File
@@ -76,6 +76,8 @@ Settings::Settings() {
// Enable workload split by default (for 24 bit arithmetic or timeout)
workloadSplitSize_ = 1 << GPU_WORKLOAD_SPLIT;
// By default use host blit
blitEngine_ = BlitEngineHost;
pinnedXferSize_ = GPU_PINNED_MIN_XFER_SIZE * Mi;
pinnedMinXferSize_ = flagIsDefault(GPU_PINNED_MIN_XFER_SIZE)
? 128 * Mi : GPU_PINNED_MIN_XFER_SIZE * Mi;
@@ -121,6 +123,8 @@ Settings::Settings() {
//!@note IOL for Linux doesn't setup tiling aperture in CMM/QS
linearPersistentImage_ = false;
useSingleScratch_ = GPU_USE_SINGLE_SCRATCH;
// Device enqueuing settings
numDeviceEvents_ = 1024;
numWaitEvents_ = 8;
@@ -324,11 +328,16 @@ bool Settings::create(const Pal::DeviceProperties& palProp,
libSelector_ = amd::GPU_Library_CI;
if (LP64_SWITCH(false, true)) {
oclVersion_ = !reportAsOCL12Device
oclVersion_ = !reportAsOCL12Device /*&& calAttr.isOpenCL200Device*/
? XCONCAT(OpenCL, XCONCAT(OPENCL_MAJOR, OPENCL_MINOR))
: OpenCL12;
}
if (GPU_FORCE_OCL20_32BIT) {
force32BitOcl20_ = true;
oclVersion_ = !reportAsOCL12Device /*&& calAttr.isOpenCL200Device*/
? XCONCAT(OpenCL, XCONCAT(OPENCL_MAJOR, OPENCL_MINOR))
: OpenCL12;
}
if (OPENCL_VERSION < 200) {
oclVersion_ = OpenCL12;
}
@@ -337,13 +346,27 @@ bool Settings::create(const Pal::DeviceProperties& palProp,
// Cap at OpenCL20 for now
if (oclVersion_ > OpenCL20) oclVersion_ = OpenCL20;
use64BitPtr_ = LP64_SWITCH(false, true);
// This needs to be cleaned once 64bit addressing is stable
if (oclVersion_ < OpenCL20) {
use64BitPtr_ = flagIsDefault(GPU_FORCE_64BIT_PTR)
? LP64_SWITCH(false,
/*calAttr.isWorkstation ||*/ true)
: GPU_FORCE_64BIT_PTR;
} else {
if (GPU_FORCE_64BIT_PTR || LP64_SWITCH(false, true)) {
use64BitPtr_ = true;
}
}
if (oclVersion_ >= OpenCL20) {
supportDepthsRGB_ = true;
}
if (use64BitPtr_) {
maxAllocSize_ = 64ULL * Gi;
if (GPU_ENABLE_LARGE_ALLOCATION) {
maxAllocSize_ = 64ULL * Gi;
} else {
maxAllocSize_ = 4048 * Mi;
}
} else {
maxAllocSize_ = 3ULL * Gi;
}
@@ -424,6 +447,9 @@ bool Settings::create(const Pal::DeviceProperties& palProp,
imageSupport_ = true;
// Use kernels for blit if appropriate
blitEngine_ = BlitEngineKernel;
hostMemDirectAccess_ |= HostMemBuffer;
// HW doesn't support untiled image writes
// hostMemDirectAccess_ |= HostMemImage;
@@ -516,6 +542,11 @@ void Settings::override() {
preferredWorkGroupSize_ = GPU_MAX_WORKGROUP_SIZE;
}
// Override blit engine type
if (GPU_BLIT_ENGINE_TYPE != BlitEngineDefault) {
blitEngine_ = GPU_BLIT_ENGINE_TYPE;
}
if (!flagIsDefault(DEBUG_GPU_FLAGS)) {
debugFlags_ = DEBUG_GPU_FLAGS;
}
projects/clr/rocclr/device/pal/palsettings.hpp
+3 -1
View File
@@ -70,6 +70,7 @@ class Settings : public device::Settings {
uint gfx10Plus_ : 1; //!< gfx10 and post gfx10 features
uint threadTraceEnable_ : 1; //!< Thread trace enable
uint linearPersistentImage_ : 1; //!< Allocates linear images in persistent
uint useSingleScratch_ : 1; //!< Allocates single scratch per device
uint svmAtomics_ : 1; //!< SVM device atomics
uint svmFineGrainSystem_ : 1; //!< SVM fine grain system support
uint useDeviceQueue_ : 1; //!< Submit to separate device queue
@@ -81,7 +82,7 @@ class Settings : public device::Settings {
uint imageBufferWar_ : 1; //!< Image buffer workaround for Gfx10
uint disableSdma_ : 1; //!< Disable SDMA support
uint alwaysResident_ : 1; //!< Make resources resident at allocation time
uint reserved_ : 8;
uint reserved_ : 7;
};
uint value_;
};
@@ -94,6 +95,7 @@ class Settings : public device::Settings {
uint workloadSplitSize_; //!< Workload split size
uint minWorkloadTime_; //!< Minimal workload time in 0.1 ms
uint maxWorkloadTime_; //!< Maximum workload time in 0.1 ms
uint blitEngine_; //!< Blit engine type
uint cacheLineSize_; //!< Cache line size in bytes
uint cacheSize_; //!< L1 cache size in bytes
uint numComputeRings_; //!< 0 - disabled, 1 , 2,.. - the number of compute rings
projects/clr/rocclr/device/pal/palvirtual.cpp
+22 -3
View File
@@ -905,6 +905,11 @@ bool VirtualGPU::create(bool profiling, uint deviceQueueSize, uint rtCUs,
// because destructor calls eraseResourceList() even if create() failed
dev().resizeResoureList(index());
if (index() >= GPU_MAX_COMMAND_QUEUES) {
// Cap the maximum number of concurrent Virtual GPUs
return false;
}
// Virtual GPU will have profiling enabled
state_.profiling_ = profiling;
@@ -1015,7 +1020,18 @@ bool VirtualGPU::create(bool profiling, uint deviceQueueSize, uint rtCUs,
return false;
}
blitMgr_ = new KernelBlitManager(*this, blitSetup);
// Choose the appropriate class for blit engine
switch (dev().settings().blitEngine_) {
default:
// Fall through ...
case Settings::BlitEngineHost:
blitSetup.disableAll();
// Fall through ...
case Settings::BlitEngineCAL:
case Settings::BlitEngineKernel:
blitMgr_ = new KernelBlitManager(*this, blitSetup);
break;
}
if ((nullptr == blitMgr_) || !blitMgr_->create(gpuDevice_)) {
LogError("Could not create BlitManager!");
return false;
@@ -3253,8 +3269,11 @@ void VirtualGPU::waitEventLock(CommandBatch* cb) {
cb->lastTS_->value(&startTimeStampGPU, &endTimeStampGPU);
uint64_t endTimeStampCPU = amd::Os::timeNanos();
// Adjust the base time by the execution time
readjustTimeGPU_ = endTimeStampGPU - endTimeStampCPU;
// Make sure the command batch has a valid GPU TS
if (!GPU_RAW_TIMESTAMP) {
// Adjust the base time by the execution time
readjustTimeGPU_ = endTimeStampGPU - endTimeStampCPU;
}
}
}
}
projects/clr/rocclr/device/rocm/rocdevice.cpp
+30 -28
View File
@@ -894,35 +894,37 @@ hsa_status_t Device::iterateGpuMemoryPoolCallback(hsa_amd_memory_pool_t pool, vo
Device* dev = reinterpret_cast<Device*>(data);
switch (segment_type) {
case HSA_REGION_SEGMENT_GLOBAL: {
uint32_t global_flag = 0;
hsa_status_t stat =
hsa_amd_memory_pool_get_info(pool, HSA_AMD_MEMORY_POOL_INFO_GLOBAL_FLAGS, &global_flag);
if (stat != HSA_STATUS_SUCCESS) {
return stat;
}
if ((global_flag & HSA_REGION_GLOBAL_FLAG_FINE_GRAINED) != 0) {
dev->gpu_fine_grained_segment_ = pool;
} else if ((global_flag & HSA_REGION_GLOBAL_FLAG_COARSE_GRAINED) != 0) {
dev->gpuvm_segment_ = pool;
// If cpu agent cannot access this pool, the device does not support large bar.
hsa_amd_memory_pool_access_t tmp{};
hsa_amd_agent_memory_pool_get_info(
dev->cpu_agent_,
pool,
HSA_AMD_AGENT_MEMORY_POOL_INFO_ACCESS,
&tmp);
if (tmp == HSA_AMD_MEMORY_POOL_ACCESS_NEVER_ALLOWED) {
dev->info_.largeBar_ = false;
} else {
dev->info_.largeBar_ = ROC_ENABLE_LARGE_BAR;
if (dev->settings().enableLocalMemory_) {
uint32_t global_flag = 0;
hsa_status_t stat =
hsa_amd_memory_pool_get_info(pool, HSA_AMD_MEMORY_POOL_INFO_GLOBAL_FLAGS, &global_flag);
if (stat != HSA_STATUS_SUCCESS) {
return stat;
}
}
if (dev->gpuvm_segment_.handle == 0) {
dev->gpuvm_segment_ = pool;
if ((global_flag & HSA_REGION_GLOBAL_FLAG_FINE_GRAINED) != 0) {
dev->gpu_fine_grained_segment_ = pool;
} else if ((global_flag & HSA_REGION_GLOBAL_FLAG_COARSE_GRAINED) != 0) {
dev->gpuvm_segment_ = pool;
// If cpu agent cannot access this pool, the device does not support large bar.
hsa_amd_memory_pool_access_t tmp{};
hsa_amd_agent_memory_pool_get_info(
dev->cpu_agent_,
pool,
HSA_AMD_AGENT_MEMORY_POOL_INFO_ACCESS,
&tmp);
if (tmp == HSA_AMD_MEMORY_POOL_ACCESS_NEVER_ALLOWED) {
dev->info_.largeBar_ = false;
} else {
dev->info_.largeBar_ = ROC_ENABLE_LARGE_BAR;
}
}
if (dev->gpuvm_segment_.handle == 0) {
dev->gpuvm_segment_ = pool;
}
}
break;
}
@@ -1232,7 +1234,7 @@ bool Device::populateOCLDeviceConstants() {
info_.maxWorkItemDimensions_ = 3;
if (gpuvm_segment_.handle != 0) {
if (settings().enableLocalMemory_ && gpuvm_segment_.handle != 0) {
size_t global_segment_size = 0;
if (HSA_STATUS_SUCCESS != hsa_amd_memory_pool_get_info(gpuvm_segment_,
HSA_AMD_MEMORY_POOL_INFO_SIZE,
projects/clr/rocclr/device/rocm/rocdevice.hpp
+1 -1
View File
@@ -218,7 +218,7 @@ class NullDevice : public amd::Device {
//! Determine if we can use device memory for SVM
const bool forceFineGrain(amd::Memory* memory) const {
return (memory->getContext().devices().size() > 1);
return !settings().enableCoarseGrainSVM_ || (memory->getContext().devices().size() > 1);
}
virtual bool importExtSemaphore(void** extSemahore, const amd::Os::FileDesc& handle) {
projects/clr/rocclr/device/rocm/rocsettings.cpp
+26
View File
@@ -35,9 +35,18 @@ Settings::Settings() {
// Set this to true when we drop the flag
doublePrecision_ = ::CL_KHR_FP64;
enableLocalMemory_ = HSA_LOCAL_MEMORY_ENABLE;
enableCoarseGrainSVM_ = HSA_ENABLE_COARSE_GRAIN_SVM;
maxWorkGroupSize_ = 1024;
preferredWorkGroupSize_ = 256;
maxWorkGroupSize2DX_ = 16;
maxWorkGroupSize2DY_ = 16;
maxWorkGroupSize3DX_ = 4;
maxWorkGroupSize3DY_ = 4;
maxWorkGroupSize3DZ_ = 4;
kernargPoolSize_ = HSA_KERNARG_POOL_SIZE;
// Determine if user is requesting Non-Coherent mode
@@ -192,6 +201,23 @@ void Settings::override() {
preferredWorkGroupSize_ = GPU_MAX_WORKGROUP_SIZE;
}
if (GPU_MAX_WORKGROUP_SIZE_2D_X != 0) {
maxWorkGroupSize2DX_ = GPU_MAX_WORKGROUP_SIZE_2D_X;
}
if (GPU_MAX_WORKGROUP_SIZE_2D_Y != 0) {
maxWorkGroupSize2DY_ = GPU_MAX_WORKGROUP_SIZE_2D_Y;
}
if (GPU_MAX_WORKGROUP_SIZE_3D_X != 0) {
maxWorkGroupSize3DX_ = GPU_MAX_WORKGROUP_SIZE_3D_X;
}
if (GPU_MAX_WORKGROUP_SIZE_3D_Y != 0) {
maxWorkGroupSize3DY_ = GPU_MAX_WORKGROUP_SIZE_3D_Y;
}
if (GPU_MAX_WORKGROUP_SIZE_3D_Z != 0) {
maxWorkGroupSize3DZ_ = GPU_MAX_WORKGROUP_SIZE_3D_Z;
}
if (!flagIsDefault(GPU_XFER_BUFFER_SIZE)) {
xferBufSize_ = GPU_XFER_BUFFER_SIZE * Ki;
}
projects/clr/rocclr/device/rocm/rocsettings.hpp
+12 -1
View File
@@ -42,6 +42,8 @@ class Settings : public device::Settings {
union {
struct {
uint doublePrecision_ : 1; //!< Enables double precision support
uint enableLocalMemory_ : 1; //!< Enable GPUVM memory
uint enableCoarseGrainSVM_ : 1; //!< Enable device memory for coarse grain SVM allocations
uint enableNCMode_ : 1; //!< Enable Non Coherent mode for system memory
uint imageDMA_ : 1; //!< Enable direct image DMA transfers
uint stagedXferRead_ : 1; //!< Uses a staged buffer read
@@ -53,7 +55,7 @@ class Settings : public device::Settings {
uint fgs_kernel_arg_ : 1; //!< Use fine grain kernel arg segment
uint coop_sync_ : 1; //!< grid and multi-grid sync for gfx940+
uint barrier_value_packet_ : 1; //!< Barrier value packet functionality
uint reserved_ : 20;
uint reserved_ : 18;
};
uint value_;
};
@@ -64,6 +66,15 @@ class Settings : public device::Settings {
//! Preferred workgroup size
uint preferredWorkGroupSize_;
//! Default max workgroup sizes for 2D
int maxWorkGroupSize2DX_;
int maxWorkGroupSize2DY_;
//! Default max workgroup sizes for 3D
int maxWorkGroupSize3DX_;
int maxWorkGroupSize3DY_;
int maxWorkGroupSize3DZ_;
uint kernargPoolSize_;
uint numDeviceEvents_; //!< The number of device events
uint numWaitEvents_; //!< The number of wait events for device enqueue