2.24.3-1
Network user buffer support for collectives
* Leverage user buffer registration to achieve zero-copy
inter-node communications for Ring, NVLS and Collnet
Add RAS subsystem
* Create a RAS thread keeping track of all NCCL communicators.
* Add a ncclras tool contacting the RAS thread and getting a
report.
Add fp8 support
* Add support for e5m2 and e4m3 8-bit floating point operations.
* Use Tree/PAT algorithms when possible for better numerical
stability.
Add NIC fusion
* Add a NET API to ask the network plugin to fuse a set of
interfaces together.
* Fuse multiple NICs under the same PCI switch as a single,
larger NIC.
Socket connection failure retry
* Retry in case of socket connection failure (unreachable host)
* Avoid "Software caused connection abort" errors on retries
QP connection failure retry
* Retry in case of IB QP connection failure during ibv_modify_qp.
NET API improvements
* Allow plugins to force a flush in case data and completion
ordering is not guaranteed.
* Indicate when completion is not needed (e.g. for the LL128
protocol), allowing plugins to skip generating a completion.
* Allow for full offload of allgather operations when using one
GPU per node.
NCCL_ALGO/NCCL_PROTO strict enforcement
* Extend NCCL_ALGO/NCCL_PROTO syntax to be able to specify
ALGO/PROTO filters for each collective operation.
* Strictly enforce the ALGO/PROTO filters, no longer fall back
on the ring algorithm when the filtering leaves no option and
error out instead.
Enable CUMEM host allocations
* Use cumem functions for host memory allocation by default.
Improved profiler plugin API
* Avoid dependencies with NCCL includes.
* Add information on whether the buffer is registered or not
Adjust PAT tuning
* Improve transition between PAT and ring at scale.
Fix hangs when running with different CPU architectures
* Detect when we use a mix of GPU architectures
* Ensure Algo/Proto decisions are made based on that unified
state.
Fix FD leak in UDS
* Fix a leak when mapping buffers intra-node with cumem IPCs.
Fix crash when mixing buffer registration and graph buffer registration.
* Separate local and graph registration to avoid crashes when we free
buffers.
Fix user buffer registration with dmabuf
* Make ncclSend/ncclRecv communication with buffer registration functional
on network plugins relying on dmabuf for buffer registration.
Fix crash in IB code caused by uninitialized fields.
Fix non-blocking ncclSend/ncclRecv
* Fix case where ncclSend/ncclRecv would return ncclSuccess in non-blocking
mode even though the operation was not enqueued onto the stream.
* Issue #1495
Various compiler tweaks and fixes
* PR #758
Fix typo in ncclTopoPrintGraph
* Issue #1468
[ROCm/rccl commit: 6aae379278]
This commit is contained in:
@@ -88,24 +88,18 @@ static_assert(NCCL_LL_CLEAN_MASK % NCCL_STEPS == 0, "Invalid NCCL_LL_CLEAN_MASK
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#define NCCL_LL128_SHMEM_ELEMS_PER_THREAD 8
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#define NCCL_LL128_SHMEM_SIZE (NCCL_LL128_SHMEM_ELEMS_PER_THREAD*NCCL_LL128_MAX_NTHREADS)
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#define NCCL_DIRECT_WRITE 0x01
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#define NCCL_DIRECT_READ 0x02
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#define NCCL_P2P_WRITE 0x01
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#define NCCL_P2P_READ 0x02
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#define NCCL_DIRECT_NIC 0x04
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#define NCCL_IPC_WRITE 0x08
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#define NCCL_IPC_READ 0x10
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#define NCCL_NVLS_MIN_POLL 0x20
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#define NCCL_NVLS_MIN_POLL 0x80
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// Number of named barriers supported by CUDA
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#define NCCL_MAX_GROUPS 16
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#define NCCL_MAX_COLLNET_SIZE (1L << 29)
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enum ncclRegBufferType {
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NCCL_REGULAR_BUFFER = 0,
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NCCL_IPC_REG_BUFFER = 1,
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NCCL_NVLS_REG_BUFFER = 2,
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NCCL_COLLNET_REG_BUFFER = 3
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};
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#define NCCL_REGULAR_BUFFER 0x00
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#define NCCL_IPC_REG_BUFFER 0x01
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#define NCCL_NVLS_REG_BUFFER 0x02
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#define NCCL_NET_REG_BUFFER 0x04
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struct ncclConnInfo {
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// Regular comm mechanism
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@@ -143,8 +137,6 @@ struct ncclConnector {
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struct ncclTransportComm* transportComm;
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void* transportResources;
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struct ncclConnInfo conn;
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int sendMemSameProcess;
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int recvMemSameProcess;
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};
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struct ncclRing {
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@@ -228,7 +220,7 @@ struct alignas(16) ncclDevWorkP2p {
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uint8_t sendChunkSize_u32fp8, recvChunkSize_u32fp8;
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uint8_t sendProtoLL:1, recvProtoLL:1;
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uint8_t sendRegistered:1, recvRegistered:1;
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uint8_t sendNetReg:1, recvNetReg:1;
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uint8_t sendIpcReg:1, recvIpcReg:1;
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};
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@@ -267,7 +259,7 @@ struct alignas(16) ncclDevWorkColl {
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// nChannels == (channelHi - channelLo) + 1
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uint32_t channelLo:8, channelHi:8;
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uint32_t nWarps:8;
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uint32_t redOpArgIsPtr:1, regUsed:2, oneNode:1, direct:4;
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uint32_t redOpArgIsPtr:1, regUsed:1, netRegUsed:1, oneNode:1, direct:2, isOneRPN:1;
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uint32_t root;
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void* recvbuff;
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void* sendbuff;
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@@ -393,7 +385,7 @@ struct ncclDevComm {
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int nNodes;
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int buffSizes[NCCL_NUM_PROTOCOLS];
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int p2pChunkSize;
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int isNvlink;
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int isAllNvlink;
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// Work fifo return credits
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uint32_t* workConsumed/*[MAXCHANNELS]*/;
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@@ -525,9 +517,7 @@ inline bool ncclNvlsSupported(int devRedOp, int type) {
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case ncclInt64:
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case ncclUint64:
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case ncclFloat16:
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#if defined(__CUDA_BF16_TYPES_EXIST__)
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case ncclBfloat16:
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#endif
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return devRedOp == ncclDevSum || devRedOp == ncclDevMinMax;
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case ncclFloat:
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case ncclDouble:
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