Add GFX debug trap control code
Add initial support for the kfd debugger trap support for GFX9 chips. - Adding support for Enable/Disable trap support - Setting debug trap support data - Setting wave launch trap override - Setting wave launch mode Change-Id: If39f2395c4b6cf56249cf76f1c44cfcbdcef891c Signed-off-by: Philip Cox <Philip.Cox@amd.com>
Этот коммит содержится в:
Philip Cox
@@ -72,6 +72,8 @@ extern "C" {
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typedef void* HSA_HANDLE;
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typedef HSAuint64 HSA_QUEUEID;
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// An HSA_QUEUEID that is never a valid queue ID.
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#define INVALID_QUEUEID 0xFFFFFFFFFFFFFFFFULL
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// This is included in order to force the alignments to be 4 bytes so that
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// it avoids extra padding added by the compiler when a 64-bit binary is generated.
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@@ -97,13 +99,14 @@ typedef enum _HSAKMT_STATUS
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HSAKMT_STATUS_NOT_IMPLEMENTED = 10, // KFD function is not implemented for this set of paramters
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HSAKMT_STATUS_NOT_SUPPORTED = 11, // KFD function is not supported on this node
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HSAKMT_STATUS_UNAVAILABLE = 12, // KFD function is not available currently on this node (but
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// may be at a later time)
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// may be at a later time)
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HSAKMT_STATUS_OUT_OF_RESOURCES = 13, // KFD function request exceeds the resources currently available.
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HSAKMT_STATUS_KERNEL_IO_CHANNEL_NOT_OPENED = 20, // KFD driver path not opened
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HSAKMT_STATUS_KERNEL_COMMUNICATION_ERROR = 21, // user-kernel mode communication failure
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HSAKMT_STATUS_KERNEL_ALREADY_OPENED = 22, // KFD driver path already opened
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HSAKMT_STATUS_HSAMMU_UNAVAILABLE = 23, // ATS/PRI 1.1 (Address Translation Services) not available
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// (IOMMU driver not installed or not-available)
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// (IOMMU driver not installed or not-available)
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HSAKMT_STATUS_WAIT_FAILURE = 30, // The wait operation failed
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HSAKMT_STATUS_WAIT_TIMEOUT = 31, // The wait operation timed out
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@@ -190,13 +193,20 @@ typedef union
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unsigned int VALimit : 1; // This node GPU has limited VA range for platform
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// (typical 40bit). Affects shared VM use for 64bit apps
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unsigned int WatchPointsSupported: 1; // Indicates if Watchpoints are available on the node.
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unsigned int WatchPointsTotalBits: 4; // ld(Watchpoints) available. To determine the number use 2^value
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unsigned int WatchPointsTotalBits: 4; // Watchpoints available. To determine the number use 2^value
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unsigned int DoorbellType : 2; // 0: This node has pre-1.0 doorbell characteristic
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// 1: This node has 1.0 doorbell characteristic
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// 2,3: reserved for future use
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unsigned int AQLQueueDoubleMap : 1; // The unit needs a VA “double map”
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unsigned int Reserved : 17;
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unsigned int AQLQueueDoubleMap : 1; // The unit needs a VA “double map”
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unsigned int WatchAddrMaskLoBit : 4; // Only bits WatchAddrMaskLoBit..WatchAddrMaskHiBit of the
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unsigned int WatchAddrMaskHiBit : 6; // watch address mask are used. 0 is the least significant bit.
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unsigned int DebugTrapSupported : 1; // Indicates if Debug Trap is supported on the node.
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unsigned int TrapDataCount : 2; // Number of 32 bit TrapData registers supported.
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unsigned int WaveLaunchTrapOverrideSupported: 1; // Indicates if Wave Launch Trap Override is supported on the node.
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unsigned int WaveLaunchModeSupported: 1; // Indicates if Wave Launch Mode is supported on the node.
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unsigned int PreciseMemoryOperationsSupported: 1; // Indicates if Precise Memory Operations are supported on the node.
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unsigned int Reserved : 1;
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} ui32;
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} HSA_CAPABILITY;
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@@ -690,10 +700,44 @@ typedef enum _HSA_DBG_WATCH_MODE
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HSA_DBG_WATCH_NONREAD = 1, //Write or Atomic operations only
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HSA_DBG_WATCH_ATOMIC = 2, //Atomic Operations only
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HSA_DBG_WATCH_ALL = 3, //Read, Write or Atomic operations
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HSA_DBG_WATCH_NUM,
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HSA_DBG_WATCH_SIZE = 0xFFFFFFFF
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HSA_DBG_WATCH_NUM
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} HSA_DBG_WATCH_MODE;
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typedef enum _HSA_DBG_TRAP_OVERRIDE
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{
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HSA_DBG_TRAP_OVERRIDE_OR = 0, // Bitwise OR exception mask with HSA_DBG_TRAP_MASK
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HSA_DBG_TRAP_OVERRIDE_REPLACE = 1, // Replace exception mask with HSA_DBG_TRAP_MASK
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HSA_DBG_TRAP_OVERRIDE_NUM
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} HSA_DBG_TRAP_OVERRIDE;
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typedef enum _HSA_DBG_TRAP_MASK
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{
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HSA_DBG_TRAP_MASK_FP_INVALID = 1, // Floating point invalid operation
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HSA_DBG_TRAP_MASK_FP_INPUT_DENOMAL = 2, // Floating point input denormal
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HSA_DBG_TRAP_MASK_FP_DIVIDE_BY_ZERO = 4, // Floating point divide by zero
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HSA_DBG_TRAP_MASK_FP_OVERFLOW = 8, // Floating point overflow
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HSA_DBG_TRAP_MASK_FP_UNDERFLOW = 16, // Floating point underflow
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HSA_DBG_TRAP_MASK_FP_INEXACT = 32, // Floating point inexact
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HSA_DBG_TRAP_MASK_INT_DIVIDE_BY_ZERO = 64, // Integer divide by zero
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HSA_DBG_TRAP_MASK_DBG_ADDRESS_WATCH = 128, // Debug address watch
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HSA_DBG_TRAP_MASK_DBG_MEMORY_VIOLATION = 256 // Memory violation
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} HSA_DBG_TRAP_MASK;
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typedef enum _HSA_DBG_WAVE_LAUNCH_MODE
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{
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HSA_DBG_WAVE_LAUNCH_MODE_NORMAL = 0, // Wavefront launched normally.
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HSA_DBG_WAVE_LAUNCH_MODE_HALT = 1, // Wavefront launched in halted mode.
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HSA_DBG_WAVE_LAUNCH_MODE_KILL = 2, // Wavefront is launched but immediately
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// terminated before executing any instructions.
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HSA_DBG_WAVE_LAUNCH_MODE_SINGLE_STEP = 3, // Wavefront is launched in single step (debug)
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// mode. If debug trap is enabled by
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// hsaKmtDbgEnableDebugTrap() then causes a
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// trap after executing each instruction,
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// otherwise behaves the same as
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// HSA_DBG_WAVE_LAUNCH_MODE_NORMAL.
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HSA_DBG_WAVE_LAUNCH_MODE_DISABLE = 4, // Disable launching any new waves.
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HSA_DBG_WAVE_LAUNCH_MODE_NUM
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} HSA_DBG_WAVE_LAUNCH_MODE;
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//This structure is hardware specific and may change in the future
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typedef struct _HsaDbgWaveMsgAMDGen2
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